From de649b91943816149e28a49acb4718e41be2589f Mon Sep 17 00:00:00 2001
From: Kamil Rakoczy <krakoczy@antmicro.com>
Date: Fri, 10 Jul 2020 09:59:48 +0200
Subject: Revert "Revert PRs #2203 and #2244."

This reverts commit 9c120b89ace6c111aa4677616947d18d980b9c1a.
---
 tests/various/integer_range_bad_syntax.ys |  6 ++++++
 tests/various/integer_real_bad_syntax.ys  |  6 ++++++
 tests/various/logic_param_simple.ys       |  9 +++++++++
 tests/various/signed.ys                   | 28 ++++++++++++++++++++++++++++
 4 files changed, 49 insertions(+)
 create mode 100644 tests/various/integer_range_bad_syntax.ys
 create mode 100644 tests/various/integer_real_bad_syntax.ys
 create mode 100644 tests/various/logic_param_simple.ys
 create mode 100644 tests/various/signed.ys

(limited to 'tests')

diff --git a/tests/various/integer_range_bad_syntax.ys b/tests/various/integer_range_bad_syntax.ys
new file mode 100644
index 000000000..4f427211f
--- /dev/null
+++ b/tests/various/integer_range_bad_syntax.ys
@@ -0,0 +1,6 @@
+logger -expect error "syntax error, unexpected" 1
+read_verilog -sv <<EOT
+module test_integer_range();
+parameter integer [31:0] a = 0;
+endmodule
+EOT
diff --git a/tests/various/integer_real_bad_syntax.ys b/tests/various/integer_real_bad_syntax.ys
new file mode 100644
index 000000000..942d8de77
--- /dev/null
+++ b/tests/various/integer_real_bad_syntax.ys
@@ -0,0 +1,6 @@
+logger -expect error "syntax error, unexpected TOK_REAL" 1
+read_verilog -sv <<EOT
+module test_integer_real();
+parameter integer real a = 0;
+endmodule
+EOT
diff --git a/tests/various/logic_param_simple.ys b/tests/various/logic_param_simple.ys
new file mode 100644
index 000000000..968564080
--- /dev/null
+++ b/tests/various/logic_param_simple.ys
@@ -0,0 +1,9 @@
+read_verilog -sv <<EOT
+module test_logic_param();
+parameter logic                 a = 0;
+parameter logic [31:0]          e = 0;
+parameter logic signed          b = 0;
+parameter logic unsigned        c = 0;
+parameter logic unsigned [31:0] d = 0;
+endmodule
+EOT
diff --git a/tests/various/signed.ys b/tests/various/signed.ys
new file mode 100644
index 000000000..2319a5da1
--- /dev/null
+++ b/tests/various/signed.ys
@@ -0,0 +1,28 @@
+# SV LRM A2.2.1
+
+read_verilog -sv <<EOT
+module test_signed();
+parameter integer signed  a = 0;
+parameter integer unsigned  b = 0;
+
+endmodule
+EOT
+
+design -reset
+read_verilog -sv <<EOT
+module test_signed();
+parameter logic signed [7:0] a = 0;
+parameter logic unsigned [7:0] b = 0;
+
+endmodule
+EOT
+
+design -reset
+logger -expect error "syntax error, unexpected TOK_INTEGER" 1
+read_verilog -sv <<EOT
+module test_signed();
+parameter signed integer a = 0;
+parameter unsigned integer b = 0;
+
+endmodule
+EOT
-- 
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