From 55ad3fe6c701607ce6b184d03241be38e894c2fd Mon Sep 17 00:00:00 2001 From: Jannis Harder Date: Mon, 13 Feb 2023 16:50:27 +0100 Subject: xprop tests: Make iverilog invocation more portable --- tests/xprop/test.py | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'tests/xprop') diff --git a/tests/xprop/test.py b/tests/xprop/test.py index 507e4e9e2..a275b0d93 100644 --- a/tests/xprop/test.py +++ b/tests/xprop/test.py @@ -357,15 +357,15 @@ for mode in ["", "_xprop"]: "-DSIMLIB_FF", "-DSIMLIB_GLOBAL_CLOCK=top.gclk", f"-DDUMPFILE=\"vsim_{expr}.vcd\"", + "-o", + f"vsim_{expr}", "verilog_sim_tb.v", f"vsim_{expr}.v", *simlibs, - "-o", - f"vsim_{expr}", ] ) with open(f"vsim_{expr}.out", "w") as f: - subprocess.check_call([f"./vsim_{expr}"], stdout=f) + subprocess.check_call(["vvp", f"./vsim_{expr}"], stdout=f) for mode in ["", "_xprop"]: if f"sim{mode}" not in steps: -- cgit v1.2.3