From 2e911bc806d0a54e4d7e84ef2218ff088ea20b5f Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Mon, 4 May 2020 12:18:02 -0700
Subject: test: add failing test

---
 tests/verilog/upto.ys | 5 +++++
 1 file changed, 5 insertions(+)
 create mode 100644 tests/verilog/upto.ys

(limited to 'tests/verilog')

diff --git a/tests/verilog/upto.ys b/tests/verilog/upto.ys
new file mode 100644
index 000000000..d87f4424e
--- /dev/null
+++ b/tests/verilog/upto.ys
@@ -0,0 +1,5 @@
+read_verilog <<EOT
+module top(input [-128:-65] a);
+endmodule
+EOT
+dump
-- 
cgit v1.2.3


From 004999218f52cd5a1308023a474ee608b842a5b7 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Tue, 5 May 2020 08:01:27 -0700
Subject: techlibs/common: more robustness when *_WIDTH = 0

---
 tests/verilog/upto.ys | 1 -
 1 file changed, 1 deletion(-)

(limited to 'tests/verilog')

diff --git a/tests/verilog/upto.ys b/tests/verilog/upto.ys
index d87f4424e..2f3394761 100644
--- a/tests/verilog/upto.ys
+++ b/tests/verilog/upto.ys
@@ -2,4 +2,3 @@ read_verilog <<EOT
 module top(input [-128:-65] a);
 endmodule
 EOT
-dump
-- 
cgit v1.2.3