From cffec1f95f0ac4bad1deb24bf7f921bd93145a16 Mon Sep 17 00:00:00 2001
From: Jannis Harder <me@jix.one>
Date: Tue, 24 May 2022 14:32:14 +0200
Subject: verilog: fix signedness when removing unreachable cases

---
 tests/verilog/unreachable_case_sign.ys | 33 +++++++++++++++++++++++++++++++++
 1 file changed, 33 insertions(+)
 create mode 100644 tests/verilog/unreachable_case_sign.ys

(limited to 'tests/verilog')

diff --git a/tests/verilog/unreachable_case_sign.ys b/tests/verilog/unreachable_case_sign.ys
new file mode 100644
index 000000000..25bc0c6f0
--- /dev/null
+++ b/tests/verilog/unreachable_case_sign.ys
@@ -0,0 +1,33 @@
+logger -expect-no-warnings
+
+read_verilog -formal <<EOT
+module top(input clk);
+    reg good = 0;
+
+    always @(posedge clk) begin
+        case (4'sb1111) 15: good = 1; 4'b0000: ; endcase
+        assert (good);
+    end
+endmodule
+EOT
+
+prep -top top
+sim -n 3 -clock clk
+
+design -reset
+
+read_verilog -formal <<EOT
+module top(input clk);
+    reg good = 1;
+    reg signed [1:0] case_value = -1;
+
+    always @(posedge clk) begin
+        case (4'sb1111) 4'b0000: ; case_value: good = 0; endcase
+        assert (good);
+    end
+endmodule
+EOT
+
+prep -top top
+sim -n 3 -clock clk
+
-- 
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