From bf15dbd0f7cac8cfb572e137b9332016d0cc483d Mon Sep 17 00:00:00 2001
From: Zachary Snow <zach@zachjs.com>
Date: Tue, 22 Feb 2022 16:57:08 +0100
Subject: sv: fix always_comb auto nosync for nested and function blocks

---
 tests/verilog/always_comb_nolatch_5.ys | 15 +++++++++++++++
 tests/verilog/always_comb_nolatch_6.ys | 15 +++++++++++++++
 2 files changed, 30 insertions(+)
 create mode 100644 tests/verilog/always_comb_nolatch_5.ys
 create mode 100644 tests/verilog/always_comb_nolatch_6.ys

(limited to 'tests/verilog')

diff --git a/tests/verilog/always_comb_nolatch_5.ys b/tests/verilog/always_comb_nolatch_5.ys
new file mode 100644
index 000000000..132878626
--- /dev/null
+++ b/tests/verilog/always_comb_nolatch_5.ys
@@ -0,0 +1,15 @@
+read_verilog -sv <<EOF
+module top;
+logic [4:0] x;
+logic z;
+assign z = 1'b1;
+always_comb begin : foo
+    x = '0;
+    if (z) begin : bar
+        for (int i = 0; i < 5; i++)
+            x[i] = 1'b1;
+    end
+end
+endmodule
+EOF
+proc
diff --git a/tests/verilog/always_comb_nolatch_6.ys b/tests/verilog/always_comb_nolatch_6.ys
new file mode 100644
index 000000000..90ee78a68
--- /dev/null
+++ b/tests/verilog/always_comb_nolatch_6.ys
@@ -0,0 +1,15 @@
+read_verilog -sv <<EOF
+module top(input wire x, y, output reg z);
+function automatic f;
+    input inp;
+    for (int i = 0; i < 1; i++)
+        f = inp + 0;
+endfunction
+always_comb
+    if (y)
+        z = f(x);
+    else
+        z = 0;
+endmodule
+EOF
+proc
-- 
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