From b75fa62e9b2a9f4410084fb1c80ceb23ed9d9c48 Mon Sep 17 00:00:00 2001
From: Jannis Harder <me@jix.one>
Date: Tue, 24 May 2022 17:18:53 +0200
Subject: verilog: fix $past's signedness

---
 tests/verilog/past_signedness.ys | 35 +++++++++++++++++++++++++++++++++++
 1 file changed, 35 insertions(+)
 create mode 100644 tests/verilog/past_signedness.ys

(limited to 'tests/verilog')

diff --git a/tests/verilog/past_signedness.ys b/tests/verilog/past_signedness.ys
new file mode 100644
index 000000000..91f32328b
--- /dev/null
+++ b/tests/verilog/past_signedness.ys
@@ -0,0 +1,35 @@
+logger -expect-no-warnings
+
+read_verilog -formal <<EOT
+module top(input clk);
+    reg signed [3:0] value = -1;
+    reg ready = 0;
+
+    always @(posedge clk) begin
+        if (ready)
+            assert ($past(value) == -1);
+        ready <= 1;
+    end
+endmodule
+EOT
+
+prep -top top
+sim -n 3 -clock clk
+
+design -reset
+
+read_verilog -formal <<EOT
+module top(input clk);
+    reg signed [3:0] value = -1;
+    reg ready = 0;
+
+    always @(posedge clk) begin
+        if (ready)
+            assert ($past(value + 4'b0000) == 15);
+        ready <= 1;
+    end
+endmodule
+EOT
+
+prep -top top
+sim -n 3 -clock clk
-- 
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