From b6af90fe20bc92631061c48c328f3c6e4760e4df Mon Sep 17 00:00:00 2001 From: Zachary Snow Date: Sun, 21 Feb 2021 14:45:21 -0500 Subject: verilog: fix sizing of constant args for tasks/functions - Simplify synthetic localparams for normal calls to update their width - This step was inadvertently removed alongside `added_mod_children` - Support redeclaration of constant function arguments - `eval_const_function` never correctly handled this, but the issue was not exposed in the existing tests until the recent change to always attempt constant function evaluation when all-const args are used - Check asserts in const_arg_loop and const_func tests - Add coverage for width mismatch error cases --- tests/various/const_arg_loop.sv | 92 ++++++++++++++++++++++++++++++++++++++++ tests/various/const_arg_loop.v | 93 ----------------------------------------- tests/various/const_arg_loop.ys | 7 +++- tests/various/const_func.sv | 86 +++++++++++++++++++++++++++++++++++++ tests/various/const_func.v | 87 -------------------------------------- tests/various/const_func.ys | 8 +++- 6 files changed, 191 insertions(+), 182 deletions(-) create mode 100644 tests/various/const_arg_loop.sv delete mode 100644 tests/various/const_arg_loop.v create mode 100644 tests/various/const_func.sv delete mode 100644 tests/various/const_func.v (limited to 'tests/various') diff --git a/tests/various/const_arg_loop.sv b/tests/various/const_arg_loop.sv new file mode 100644 index 000000000..f28d06e68 --- /dev/null +++ b/tests/various/const_arg_loop.sv @@ -0,0 +1,92 @@ +module top; + function automatic [31:0] operation1; + input [4:0] rounds; + input integer num; + integer i; + begin + begin : shadow + integer rounds; + rounds = 0; + end + for (i = 0; i < rounds; i = i + 1) + num = num * 2; + operation1 = num; + end + endfunction + + function automatic [31:0] pass_through; + input [31:0] inp; + pass_through = inp; + endfunction + + function automatic [31:0] operation2; + input [4:0] inp; + input integer num; + begin + inp[0] = inp[0] ^ 1; + operation2 = num * inp; + end + endfunction + + function automatic [31:0] operation3; + input [4:0] rounds; + input integer num; + reg [4:0] rounds; + integer i; + begin + begin : shadow + integer rounds; + rounds = 0; + end + for (i = 0; i < rounds; i = i + 1) + num = num * 2; + operation3 = num; + end + endfunction + + function automatic [16:0] operation4; + input [15:0] a; + input b; + operation4 = {a, b}; + endfunction + + function automatic integer operation5; + input x; + integer x; + operation5 = x; + endfunction + + wire [31:0] a; + assign a = 2; + + parameter A = 3; + + wire [31:0] x1; + assign x1 = operation1(A, a); + + wire [31:0] x1b; + assign x1b = operation1(pass_through(A), a); + + wire [31:0] x2; + assign x2 = operation2(A, a); + + wire [31:0] x3; + assign x3 = operation3(A, a); + + wire [16:0] x4; + assign x4 = operation4(a[15:0], 0); + + wire [31:0] x5; + assign x5 = operation5(64); + + always_comb begin + assert(a == 2); + assert(A == 3); + assert(x1 == 16); + assert(x1b == 16); + assert(x2 == 4); + assert(x3 == 16); + assert(x4 == a << 1); + assert(x5 == 64); + end +endmodule diff --git a/tests/various/const_arg_loop.v b/tests/various/const_arg_loop.v deleted file mode 100644 index 358fb439a..000000000 --- a/tests/various/const_arg_loop.v +++ /dev/null @@ -1,93 +0,0 @@ -module top; - function automatic [31:0] operation1; - input [4:0] rounds; - input integer num; - integer i; - begin - begin : shadow - integer rounds; - rounds = 0; - end - for (i = 0; i < rounds; i = i + 1) - num = num * 2; - operation1 = num; - end - endfunction - - function automatic [31:0] pass_through; - input [31:0] inp; - pass_through = inp; - endfunction - - function automatic [31:0] operation2; - input [4:0] var; - input integer num; - begin - var[0] = var[0] ^ 1; - operation2 = num * var; - end - endfunction - - function automatic [31:0] operation3; - input [4:0] rounds; - input integer num; - reg [4:0] rounds; - integer i; - begin - begin : shadow - integer rounds; - rounds = 0; - end - for (i = 0; i < rounds; i = i + 1) - num = num * 2; - operation3 = num; - end - endfunction - - function automatic [16:0] operation4; - input [15:0] a; - input b; - operation4 = {a, b}; - endfunction - - function automatic integer operation5; - input x; - integer x; - operation5 = x; - endfunction - - wire [31:0] a; - assign a = 2; - - parameter A = 3; - - wire [31:0] x1; - assign x1 = operation1(A, a); - - wire [31:0] x1b; - assign x1b = operation1(pass_through(A), a); - - wire [31:0] x2; - assign x2 = operation2(A, a); - - wire [31:0] x3; - assign x3 = operation3(A, a); - - wire [16:0] x4; - assign x4 = operation4(a[15:0], 0); - - wire [31:0] x5; - assign x5 = operation5(64); - -// `define VERIFY -`ifdef VERIFY - assert property (a == 2); - assert property (A == 3); - assert property (x1 == 16); - assert property (x1b == 16); - assert property (x2 == 4); - assert property (x3 == 16); - assert property (x4 == a << 1); - assert property (x5 == 64); -`endif -endmodule diff --git a/tests/various/const_arg_loop.ys b/tests/various/const_arg_loop.ys index b039bda10..392532213 100644 --- a/tests/various/const_arg_loop.ys +++ b/tests/various/const_arg_loop.ys @@ -1 +1,6 @@ -read_verilog const_arg_loop.v +read_verilog -sv const_arg_loop.sv +hierarchy +proc +opt -full +select -module top +sat -verify -seq 1 -tempinduct -prove-asserts -show-all diff --git a/tests/various/const_func.sv b/tests/various/const_func.sv new file mode 100644 index 000000000..af65f5c73 --- /dev/null +++ b/tests/various/const_func.sv @@ -0,0 +1,86 @@ +module Example(outA, outB, outC, outD); + parameter OUTPUT = "FOO"; + output wire [23:0] outA; + output wire [23:0] outB; + output reg outC, outD; + function automatic [23:0] flip; + input [23:0] inp; + flip = ~inp; + endfunction + + generate + if (flip(OUTPUT) == flip("BAR")) + assign outA = OUTPUT; + else + assign outA = 0; + + case (flip(OUTPUT)) + flip("FOO"): assign outB = OUTPUT; + flip("BAR"): assign outB = 0; + flip("BAZ"): assign outB = "HI"; + endcase + + genvar i; + initial outC = 0; + for (i = 0; i != flip(flip(OUTPUT[15:8])); i = i + 1) + if (i + 1 == flip(flip("O"))) + initial outC = 1; + endgenerate + + integer j; + initial begin + outD = 1; + for (j = 0; j != flip(flip(OUTPUT[15:8])); j = j + 1) + if (j + 1 == flip(flip("O"))) + outD = 0; + end +endmodule + +module top(out); + wire [23:0] a1, a2, a3, a4; + wire [23:0] b1, b2, b3, b4; + wire c1, c2, c3, c4; + wire d1, d2, d3, d4; + Example e1(a1, b1, c1, d1); + Example #("FOO") e2(a2, b2, c2, d2); + Example #("BAR") e3(a3, b3, c3, d3); + Example #("BAZ") e4(a4, b4, c4, d4); + + output wire [24 * 8 - 1 + 4 :0] out; + assign out = { + a1, a2, a3, a4, + b1, b2, b3, b4, + c1, c2, c3, c4, + d1, d2, d3, d4}; + + function signed [31:0] negate; + input integer inp; + negate = ~inp; + endfunction + parameter W = 10; + parameter X = 3; + localparam signed Y = $floor(W / X); + localparam signed Z = negate($floor(W / X)); + + always_comb begin + assert(a1 == 0); + assert(a2 == 0); + assert(a3 == "BAR"); + assert(a4 == 0); + assert(b1 == "FOO"); + assert(b2 == "FOO"); + assert(b3 == 0); + assert(b4 == "HI"); + assert(c1 == 1); + assert(c2 == 1); + assert(c3 == 0); + assert(c4 == 0); + assert(d1 == 0); + assert(d2 == 0); + assert(d3 == 1); + assert(d4 == 1); + + assert(Y == 3); + assert(Z == ~3); + end +endmodule diff --git a/tests/various/const_func.v b/tests/various/const_func.v deleted file mode 100644 index 541e63b19..000000000 --- a/tests/various/const_func.v +++ /dev/null @@ -1,87 +0,0 @@ -module Example(outA, outB, outC, outD); - parameter OUTPUT = "FOO"; - output wire [23:0] outA; - output wire [23:0] outB; - output reg outC, outD; - function automatic [23:0] flip; - input [23:0] inp; - flip = ~inp; - endfunction - - generate - if (flip(OUTPUT) == flip("BAR")) - assign outA = OUTPUT; - else - assign outA = 0; - - case (flip(OUTPUT)) - flip("FOO"): assign outB = OUTPUT; - flip("BAR"): assign outB = 0; - flip("BAZ"): assign outB = "HI"; - endcase - - genvar i; - initial outC = 0; - for (i = 0; i != flip(flip(OUTPUT[15:8])); i = i + 1) - if (i + 1 == flip(flip("O"))) - initial outC = 1; - endgenerate - - integer j; - initial begin - outD = 1; - for (j = 0; j != flip(flip(OUTPUT[15:8])); j = j + 1) - if (j + 1 == flip(flip("O"))) - outD = 0; - end -endmodule - -module top(out); - wire [23:0] a1, a2, a3, a4; - wire [23:0] b1, b2, b3, b4; - wire c1, c2, c3, c4; - wire d1, d2, d3, d4; - Example e1(a1, b1, c1, d1); - Example #("FOO") e2(a2, b2, c2, d2); - Example #("BAR") e3(a3, b3, c3, d3); - Example #("BAZ") e4(a4, b4, c4, d4); - - output wire [24 * 8 - 1 + 4 :0] out; - assign out = { - a1, a2, a3, a4, - b1, b2, b3, b4, - c1, c2, c3, c4, - d1, d2, d3, d4}; - - function signed [31:0] negate; - input integer inp; - negate = ~inp; - endfunction - parameter W = 10; - parameter X = 3; - localparam signed Y = $floor(W / X); - localparam signed Z = negate($floor(W / X)); - -// `define VERIFY -`ifdef VERIFY - assert property (a1 == 0); - assert property (a2 == 0); - assert property (a3 == "BAR"); - assert property (a4 == 0); - assert property (b1 == "FOO"); - assert property (b2 == "FOO"); - assert property (b3 == 0); - assert property (b4 == "HI"); - assert property (c1 == 1); - assert property (c2 == 1); - assert property (c3 == 0); - assert property (c4 == 0); - assert property (d1 == 0); - assert property (d2 == 0); - assert property (d3 == 1); - assert property (d4 == 1); - - assert property (Y == 3); - assert property (Z == ~3); -`endif -endmodule diff --git a/tests/various/const_func.ys b/tests/various/const_func.ys index 5e3c04105..2f60acfe6 100644 --- a/tests/various/const_func.ys +++ b/tests/various/const_func.ys @@ -1 +1,7 @@ -read_verilog const_func.v +read_verilog -sv const_func.sv +hierarchy +proc +flatten +opt -full +select -module top +sat -verify -seq 1 -tempinduct -prove-asserts -show-all -- cgit v1.2.3