From 0f6e914ef63d06ae77b54d246b61118c19647f26 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Fri, 7 Jun 2019 08:34:58 -0700 Subject: Another muxpack test --- tests/various/muxpack.v | 17 +++++++++++++++++ tests/various/muxpack.ys | 15 +++++++++++++++ 2 files changed, 32 insertions(+) (limited to 'tests/various') diff --git a/tests/various/muxpack.v b/tests/various/muxpack.v index f1bd5ea8e..41dfed396 100644 --- a/tests/various/muxpack.v +++ b/tests/various/muxpack.v @@ -136,3 +136,20 @@ always @* else o <= i[7*W+:W]; endmodule + +module mux_if_bal_5_1 #(parameter N=5, parameter W=1) (input [N*W-1:0] i, input [$clog2(N)-1:0] s, output reg [W-1:0] o); +always @* + if (s[0] == 1'b0) + if (s[1] == 1'b0) + if (s[2] == 1'b0) + o <= i[0*W+:W]; + else + o <= i[1*W+:W]; + else + if (s[2] == 1'b0) + o <= i[2*W+:W]; + else + o <= i[3*W+:W]; + else + o <= i[4*W+:W]; +endmodule diff --git a/tests/various/muxpack.ys b/tests/various/muxpack.ys index 9ea743b9f..dd3c143d8 100644 --- a/tests/various/muxpack.ys +++ b/tests/various/muxpack.ys @@ -148,3 +148,18 @@ design -import gold -as gold design -import gate -as gate miter -equiv -flatten -make_assert -make_outputs gold gate miter sat -verify -prove-asserts -show-ports miter + +design -load read +hierarchy -top mux_if_bal_5_1 +prep +design -save gold +muxpack +opt +stat +select -assert-count 2 t:$mux +select -assert-count 1 t:$pmux +design -stash gate +design -import gold -as gold +design -import gate -as gate +miter -equiv -flatten -make_assert -make_outputs gold gate miter +sat -verify -prove-asserts -show-ports miter -- cgit v1.2.3 From e263bc249b905195120fbc074c6f80d03fb21cf8 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Fri, 7 Jun 2019 11:54:29 -0700 Subject: Add nonexclusive test from @cliffordwolf --- tests/various/muxpack.v | 13 +++++++++++++ tests/various/muxpack.ys | 15 +++++++++++++++ 2 files changed, 28 insertions(+) (limited to 'tests/various') diff --git a/tests/various/muxpack.v b/tests/various/muxpack.v index 41dfed396..f3c25db8d 100644 --- a/tests/various/muxpack.v +++ b/tests/various/muxpack.v @@ -153,3 +153,16 @@ always @* else o <= i[4*W+:W]; endmodule + +module cliffordwolf_nonexclusive_select ( + input wire x, y, z, + input wire a, b, c, d, + output reg o +); + always @* begin + o = a; + if (x) o = b; + if (y) o = c; + if (z) o = d; + end +endmodule diff --git a/tests/various/muxpack.ys b/tests/various/muxpack.ys index dd3c143d8..7c3fe5070 100644 --- a/tests/various/muxpack.ys +++ b/tests/various/muxpack.ys @@ -163,3 +163,18 @@ design -import gold -as gold design -import gate -as gate miter -equiv -flatten -make_assert -make_outputs gold gate miter sat -verify -prove-asserts -show-ports miter + +design -load read +hierarchy -top cliffordwolf_nonexclusive_select +prep +design -save gold +muxpack +opt +stat +select -assert-count 0 t:$mux +select -assert-count 1 t:$pmux +design -stash gate +design -import gold -as gold +design -import gate -as gate +miter -equiv -flatten -make_assert -make_outputs gold gate miter +sat -verify -prove-asserts -show-ports miter -- cgit v1.2.3 From 1da12c5071a738504d22e68d66cab7c5c5afb07e Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Fri, 7 Jun 2019 12:12:11 -0700 Subject: Add @cliffordwolf freduce testcase --- tests/various/muxpack.v | 13 +++++++++++++ tests/various/muxpack.ys | 17 +++++++++++++++++ 2 files changed, 30 insertions(+) (limited to 'tests/various') diff --git a/tests/various/muxpack.v b/tests/various/muxpack.v index f3c25db8d..d45ce4045 100644 --- a/tests/various/muxpack.v +++ b/tests/various/muxpack.v @@ -166,3 +166,16 @@ module cliffordwolf_nonexclusive_select ( if (z) o = d; end endmodule + +module cliffordwolf_freduce ( + input wire [1:0] s, + input wire a, b, c, d, + output reg [3:0] o +); + always @* begin + o = {4{a}}; + if (s == 0) o = {3{b}}; + if (s == 1) o = {2{c}}; + if (s == 2) o = d; + end +endmodule diff --git a/tests/various/muxpack.ys b/tests/various/muxpack.ys index 7c3fe5070..afdacdf30 100644 --- a/tests/various/muxpack.ys +++ b/tests/various/muxpack.ys @@ -178,3 +178,20 @@ design -import gold -as gold design -import gate -as gate miter -equiv -flatten -make_assert -make_outputs gold gate miter sat -verify -prove-asserts -show-ports miter + +design -load read +hierarchy -top cliffordwolf_freduce +prep +design -save gold +proc; opt; freduce; opt +write_verilog -noexpr -norename +muxpack +opt +stat +select -assert-count 0 t:$mux +select -assert-count 1 t:$pmux +design -stash gate +design -import gold -as gold +design -import gate -as gate +miter -equiv -flatten -make_assert -make_outputs gold gate miter +sat -verify -prove-asserts -show-ports miter -- cgit v1.2.3 From b959bf79c004fdf81ccc397d5aa774b67a09d6da Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Fri, 7 Jun 2019 15:35:15 -0700 Subject: Add nonexcl case test, comment out two others --- tests/various/muxpack.v | 18 ++++++++++++++ tests/various/muxpack.ys | 61 +++++++++++++++++++++++++++++++----------------- 2 files changed, 57 insertions(+), 22 deletions(-) (limited to 'tests/various') diff --git a/tests/various/muxpack.v b/tests/various/muxpack.v index d45ce4045..3a1086dbf 100644 --- a/tests/various/muxpack.v +++ b/tests/various/muxpack.v @@ -179,3 +179,21 @@ module cliffordwolf_freduce ( if (s == 2) o = d; end endmodule + +module case_nonexclusive_select ( + input wire [1:0] x, y, + input wire a, b, c, d, e, + output reg o +); + always @* begin + case (x) + 0, 2: o = b; + 1: o = c; + default: begin + o = a; + if (y == 0) o = d; + if (y == 1) o = e; + end + endcase + end +endmodule diff --git a/tests/various/muxpack.ys b/tests/various/muxpack.ys index afdacdf30..579dad8d3 100644 --- a/tests/various/muxpack.ys +++ b/tests/various/muxpack.ys @@ -1,5 +1,6 @@ read_verilog muxpack.v design -save read + hierarchy -top mux_if_unbal_4_1 prep design -save gold @@ -29,20 +30,21 @@ design -import gate -as gate miter -equiv -flatten -make_assert -make_outputs gold gate miter sat -verify -prove-asserts -show-ports miter -design -load read -hierarchy -top mux_if_unbal_5_3_invert -prep -design -save gold -muxpack -opt -stat -select -assert-count 0 t:$mux -select -assert-count 1 t:$pmux -design -stash gate -design -import gold -as gold -design -import gate -as gate -miter -equiv -flatten -make_assert -make_outputs gold gate miter -sat -verify -prove-asserts -show-ports miter +# TODO: Currently ExclusiveDatabase only analyses $eq cells +#design -load read +#hierarchy -top mux_if_unbal_5_3_invert +#prep +#design -save gold +#muxpack +#opt +#stat +#select -assert-count 0 t:$mux +#select -assert-count 1 t:$pmux +#design -stash gate +#design -import gold -as gold +#design -import gate -as gate +#miter -equiv -flatten -make_assert -make_outputs gold gate miter +#sat -verify -prove-asserts -show-ports miter design -load read hierarchy -top mux_if_unbal_5_3_width_mismatch @@ -156,8 +158,8 @@ design -save gold muxpack opt stat -select -assert-count 2 t:$mux -select -assert-count 1 t:$pmux +select -assert-count 4 t:$mux +select -assert-count 0 t:$pmux design -stash gate design -import gold -as gold design -import gate -as gate @@ -171,25 +173,40 @@ design -save gold muxpack opt stat -select -assert-count 0 t:$mux -select -assert-count 1 t:$pmux +select -assert-count 3 t:$mux +select -assert-count 0 t:$pmux design -stash gate design -import gold -as gold design -import gate -as gate miter -equiv -flatten -make_assert -make_outputs gold gate miter sat -verify -prove-asserts -show-ports miter +#design -load read +#hierarchy -top cliffordwolf_freduce +#prep +#design -save gold +#proc; opt; freduce; opt +#show +#muxpack +#opt +#stat +#select -assert-count 0 t:$mux +#select -assert-count 1 t:$pmux +#design -stash gate +#design -import gold -as gold +#design -import gate -as gate +#miter -equiv -flatten -make_assert -make_outputs gold gate miter +#sat -verify -prove-asserts -show-ports miter + design -load read -hierarchy -top cliffordwolf_freduce +hierarchy -top case_nonexclusive_select prep design -save gold -proc; opt; freduce; opt -write_verilog -noexpr -norename muxpack opt stat select -assert-count 0 t:$mux -select -assert-count 1 t:$pmux +select -assert-count 2 t:$pmux design -stash gate design -import gold -as gold design -import gate -as gate -- cgit v1.2.3 From 6ec816098153c733b97410ebc6aef166db8affd8 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Fri, 21 Jun 2019 11:45:53 -0700 Subject: Add more muxpack tests, with overlapping entries --- tests/various/muxpack.v | 55 +++++++++++++++++++++++++++++++++++++++++++++++- tests/various/muxpack.ys | 30 ++++++++++++++++++++++++++ 2 files changed, 84 insertions(+), 1 deletion(-) (limited to 'tests/various') diff --git a/tests/various/muxpack.v b/tests/various/muxpack.v index 3a1086dbf..7a658d754 100644 --- a/tests/various/muxpack.v +++ b/tests/various/muxpack.v @@ -187,7 +187,9 @@ module case_nonexclusive_select ( ); always @* begin case (x) - 0, 2: o = b; + //0, 2: o = b; + 0: o = b; + 2: o = b; 1: o = c; default: begin o = a; @@ -197,3 +199,54 @@ module case_nonexclusive_select ( endcase end endmodule + +module case_nonoverlap ( + input wire [2:0] x, + input wire a, b, c, d, e, f, g, + output reg o +); + always @* begin + case (x) + //0, 2: o = b; // Creates $reduce_or + //0: o = b; 2: o = b; // Creates $reduce_or + 0: o = b; + 2: o = f; + 1: o = c; + default: + case (x) + //3, 4: o = d; // Creates $reduce_or + //3: o = d; 4: o = d; // Creates $reduce_or + 3: o = d; + 4: o = g; + 5: o = e; + default: o = 1'b0; + endcase + endcase + end +endmodule + +module case_overlap ( + input wire [2:0] x, + input wire a, b, c, d, e, f, g, + output reg o +); + always @* begin + case (x) + //0, 2: o = b; // Creates $reduce_or + //0: o = b; 2: o = b; // Creates $reduce_or + 0: o = b; + 2: o = f; + 1: o = c; + default: + case (x) + //3, 4: o = d; // Creates $reduce_or + //3: o = d; 4: o = d; // Creates $reduce_or + 2: o = 1'b1; // Overlaps with previous $pmux + 3: o = d; + 4: o = g; + 5: o = e; + default: o = 1'b0; + endcase + endcase + end +endmodule diff --git a/tests/various/muxpack.ys b/tests/various/muxpack.ys index 579dad8d3..ef8a6dab9 100644 --- a/tests/various/muxpack.ys +++ b/tests/various/muxpack.ys @@ -212,3 +212,33 @@ design -import gold -as gold design -import gate -as gate miter -equiv -flatten -make_assert -make_outputs gold gate miter sat -verify -prove-asserts -show-ports miter + +design -load read +hierarchy -top case_nonoverlap +prep +design -save gold +muxpack +opt +stat +select -assert-count 0 t:$mux +select -assert-count 1 t:$pmux +design -stash gate +design -import gold -as gold +design -import gate -as gate +miter -equiv -flatten -make_assert -make_outputs gold gate miter +sat -verify -prove-asserts -show-ports miter + +design -load read +hierarchy -top case_overlap +prep +design -save gold +muxpack +#opt # Do not opt otherwise $pmux's overlapping entry will get removed +stat +select -assert-count 0 t:$mux +select -assert-count 1 t:$pmux +design -stash gate +design -import gold -as gold +design -import gate -as gate +miter -equiv -flatten -make_assert -make_outputs gold gate miter +sat -verify -prove-asserts -show-ports miter -- cgit v1.2.3 From ae8305ffcc0c812488163bcc35365d473ce1345d Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Fri, 21 Jun 2019 12:13:00 -0700 Subject: Fix testcase --- tests/various/muxpack.ys | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) (limited to 'tests/various') diff --git a/tests/various/muxpack.ys b/tests/various/muxpack.ys index ef8a6dab9..de5eec87f 100644 --- a/tests/various/muxpack.ys +++ b/tests/various/muxpack.ys @@ -230,13 +230,14 @@ sat -verify -prove-asserts -show-ports miter design -load read hierarchy -top case_overlap -prep +#prep # Do not prep otherwise $pmux's overlapping entry will get removed +proc design -save gold muxpack -#opt # Do not opt otherwise $pmux's overlapping entry will get removed +opt stat select -assert-count 0 t:$mux -select -assert-count 1 t:$pmux +select -assert-count 2 t:$pmux design -stash gate design -import gold -as gold design -import gate -as gate -- cgit v1.2.3 From 32f637ffdb0c0641b51227fad92bc80e284740d2 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Fri, 21 Jun 2019 12:31:04 -0700 Subject: Add more tests --- tests/various/muxpack.v | 47 +++++++++++++++++++++++++++-------------------- tests/various/muxpack.ys | 25 ++++++++++++++++++++++++- 2 files changed, 51 insertions(+), 21 deletions(-) (limited to 'tests/various') diff --git a/tests/various/muxpack.v b/tests/various/muxpack.v index 7a658d754..33ece1f16 100644 --- a/tests/various/muxpack.v +++ b/tests/various/muxpack.v @@ -187,7 +187,6 @@ module case_nonexclusive_select ( ); always @* begin case (x) - //0, 2: o = b; 0: o = b; 2: o = b; 1: o = c; @@ -202,22 +201,16 @@ endmodule module case_nonoverlap ( input wire [2:0] x, - input wire a, b, c, d, e, f, g, + input wire a, b, c, d, e, output reg o ); always @* begin case (x) - //0, 2: o = b; // Creates $reduce_or - //0: o = b; 2: o = b; // Creates $reduce_or - 0: o = b; - 2: o = f; + 0, 2: o = b; // Creates $reduce_or 1: o = c; default: case (x) - //3, 4: o = d; // Creates $reduce_or - //3: o = d; 4: o = d; // Creates $reduce_or - 3: o = d; - 4: o = g; + 3: o = d; 4: o = d; // Creates $reduce_or 5: o = e; default: o = 1'b0; endcase @@ -227,23 +220,37 @@ endmodule module case_overlap ( input wire [2:0] x, - input wire a, b, c, d, e, f, g, + input wire a, b, c, d, e, output reg o ); always @* begin case (x) - //0, 2: o = b; // Creates $reduce_or - //0: o = b; 2: o = b; // Creates $reduce_or - 0: o = b; - 2: o = f; + 0, 2: o = b; // Creates $reduce_or + 1: o = c; + default: + case (x) + 0: o = 1'b1; // OVERLAP! + 3, 4: o = d; // Creates $reduce_or + 5: o = e; + default: o = 1'b0; + endcase + endcase + end +endmodule + +module case_overlap2 ( + input wire [2:0] x, + input wire a, b, c, d, e, + output reg o +); + always @* begin + case (x) + 0: o = b; 2: o = b; // Creates $reduce_or 1: o = c; default: case (x) - //3, 4: o = d; // Creates $reduce_or - //3: o = d; 4: o = d; // Creates $reduce_or - 2: o = 1'b1; // Overlaps with previous $pmux - 3: o = d; - 4: o = g; + 0: o = d; 2: o = d; // Creates $reduce_or + 3: o = d; 4: o = d; // Creates $reduce_or 5: o = e; default: o = 1'b0; endcase diff --git a/tests/various/muxpack.ys b/tests/various/muxpack.ys index de5eec87f..af23fcec8 100644 --- a/tests/various/muxpack.ys +++ b/tests/various/muxpack.ys @@ -215,8 +215,11 @@ sat -verify -prove-asserts -show-ports miter design -load read hierarchy -top case_nonoverlap -prep +#prep # Do not prep otherwise $pmux's overlapping entry will get removed +proc design -save gold +opt -fast -mux_undef +select -assert-count 2 t:$pmux muxpack opt stat @@ -233,6 +236,26 @@ hierarchy -top case_overlap #prep # Do not prep otherwise $pmux's overlapping entry will get removed proc design -save gold +opt -fast -mux_undef +select -assert-count 2 t:$pmux +muxpack +opt +stat +select -assert-count 0 t:$mux +select -assert-count 2 t:$pmux +design -stash gate +design -import gold -as gold +design -import gate -as gate +miter -equiv -flatten -make_assert -make_outputs gold gate miter +sat -verify -prove-asserts -show-ports miter + +design -load read +hierarchy -top case_overlap2 +#prep # Do not prep otherwise $pmux's overlapping entry will get removed +proc +design -save gold +opt -fast -mux_undef +select -assert-count 2 t:$pmux muxpack opt stat -- cgit v1.2.3