From 48052ad813db3561a959a1921466d571bafa354c Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Thu, 16 Apr 2020 10:24:02 -0700
Subject: abc9: add flop boxes to basic $_DFF_P_ and $_DFF_N_ too

---
 tests/various/abc9.ys | 12 +++++++-----
 1 file changed, 7 insertions(+), 5 deletions(-)

(limited to 'tests/various')

diff --git a/tests/various/abc9.ys b/tests/various/abc9.ys
index 6e2415ad7..7a3a503e4 100644
--- a/tests/various/abc9.ys
+++ b/tests/various/abc9.ys
@@ -45,14 +45,16 @@ sat -seq 10 -verify -prove-asserts -show-ports miter
 design -reset
 read_verilog -icells <<EOT
 module abc9_test036(input clk, d, output q);
-(* keep *) reg w;
-$__ABC9_FF_ ff(.D(d), .Q(w));
-wire \ff.clock = clk;
-wire \ff.init = 1'b0;
+(* keep, init=1'b0 *) wire w;
+$_DFF_P_ ff(.C(clk), .D(d), .Q(w));
 assign q = w;
 endmodule
 EOT
-abc9 -lut 4 -dff
+equiv_opt abc9 -lut 4 -dff
+design -load postopt
+cd abc9_test036
+select -assert-count 1 t:$_DFF_P_
+select -assert-none t:* t:$_DFF_P_ %d
 
 
 design -reset
-- 
cgit v1.2.3


From 722540dbf942d2b8acbaf7372001c7d982eb2845 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Thu, 16 Apr 2020 12:08:59 -0700
Subject: abc9: not enough to techmap_fail on (* init=1 *), hide them using $__

---
 tests/various/abc9.ys | 23 +++++++++++++++++++++--
 1 file changed, 21 insertions(+), 2 deletions(-)

(limited to 'tests/various')

diff --git a/tests/various/abc9.ys b/tests/various/abc9.ys
index 7a3a503e4..9586091c4 100644
--- a/tests/various/abc9.ys
+++ b/tests/various/abc9.ys
@@ -50,7 +50,7 @@ $_DFF_P_ ff(.C(clk), .D(d), .Q(w));
 assign q = w;
 endmodule
 EOT
-equiv_opt abc9 -lut 4 -dff
+equiv_opt -assert abc9 -lut 4 -dff
 design -load postopt
 cd abc9_test036
 select -assert-count 1 t:$_DFF_P_
@@ -69,8 +69,27 @@ specify
 endspecify
 endmodule
 
-module top(input [1:0] i, output o);
+module abc9_test037(input [1:0] i, output o);
 LUT2 #(.mask(4'b0)) lut (.i(i), .o(o));
 endmodule
 EOT
 abc9
+
+
+design -reset
+read_verilog -icells <<EOT
+module abc9_test038(input clk, output w, x, y);
+(* init=1'b1 *) wire w;
+$_DFF_N_ ff1(.C(clk), .D(1'b1), .Q(w));
+(* init=1'bx *) wire x;
+$_DFF_N_ ff2(.C(clk), .D(1'b0), .Q(x));
+(* init=1'b0 *) wire y;
+$_DFF_N_ ff3(.C(clk), .D(1'b0), .Q(y));
+endmodule
+EOT
+simplemap
+equiv_opt abc9 -lut 4 -dff
+design -load postopt
+cd abc9_test038
+select -assert-count 2 t:$_DFF_N_
+select -assert-none c:ff1 c:ff2 %% c:* %D
-- 
cgit v1.2.3


From 13f9d65b6fc09af76330c02ab420324b50db61da Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Thu, 14 May 2020 00:29:45 -0700
Subject: abc9: preserve $_DFF_?_.Q's (* init *); rely on clean to remove it

---
 tests/various/abc9.ys | 11 ++++++++---
 1 file changed, 8 insertions(+), 3 deletions(-)

(limited to 'tests/various')

diff --git a/tests/various/abc9.ys b/tests/various/abc9.ys
index 9586091c4..ac714665f 100644
--- a/tests/various/abc9.ys
+++ b/tests/various/abc9.ys
@@ -78,18 +78,23 @@ abc9
 
 design -reset
 read_verilog -icells <<EOT
-module abc9_test038(input clk, output w, x, y);
+module abc9_test038(input clk, output w, x, y, z);
 (* init=1'b1 *) wire w;
 $_DFF_N_ ff1(.C(clk), .D(1'b1), .Q(w));
 (* init=1'bx *) wire x;
 $_DFF_N_ ff2(.C(clk), .D(1'b0), .Q(x));
 (* init=1'b0 *) wire y;
 $_DFF_N_ ff3(.C(clk), .D(1'b0), .Q(y));
+(* init=1'b0 *) wire z;
+$_DFF_N_ ff4(.C(clk), .D(1'b1), .Q(z));
 endmodule
 EOT
 simplemap
 equiv_opt abc9 -lut 4 -dff
 design -load postopt
 cd abc9_test038
-select -assert-count 2 t:$_DFF_N_
-select -assert-none c:ff1 c:ff2 %% c:* %D
+select -assert-count 3 t:$_DFF_N_
+select -assert-none c:ff1 c:ff2 c:ff4 %% c:* %D
+clean
+select -assert-count 2 a:init
+select -assert-none w:w w:z %% a:init %D
-- 
cgit v1.2.3