From a6d4ea74634826741f09793c36d596f2fa239f62 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Mon, 13 Jan 2020 19:21:11 -0800
Subject: abc9: respect (* keep *) on cells

---
 tests/techmap/abc9.ys | 15 +++++++++++++++
 1 file changed, 15 insertions(+)

(limited to 'tests/techmap')

diff --git a/tests/techmap/abc9.ys b/tests/techmap/abc9.ys
index 46b6f08d2..d5a63e1cb 100644
--- a/tests/techmap/abc9.ys
+++ b/tests/techmap/abc9.ys
@@ -51,3 +51,18 @@ simplemap
 equiv_opt -assert abc9 -lut 4
 design -load postopt
 select -assert-count 2 t:$lut
+
+design -reset
+read_verilog -icells <<EOT
+module top(input a, b, output o);
+wire w;
+(* keep *) $_AND_ gate (.Y(w), .A(a), .B(b));
+assign o = ~w;
+endmodule
+EOT
+
+simplemap
+equiv_opt -assert abc9 -lut 4
+design -load postopt
+select -assert-count 1 t:$lut
+select -assert-count 1 t:$_AND_
-- 
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