From c2bf11e42a6de3f028ad0b484eb24b70618c6fc7 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Marcin=20Ko=C5=9Bcielnicki?= Date: Mon, 23 Mar 2020 11:07:03 +0100 Subject: techmap: Fix cell names with _TECHMAP_REPLACE_.* Fixes #1804. --- tests/techmap/techmap_replace.ys | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) (limited to 'tests/techmap') diff --git a/tests/techmap/techmap_replace.ys b/tests/techmap/techmap_replace.ys index c2f42d50b..8403586bd 100644 --- a/tests/techmap/techmap_replace.ys +++ b/tests/techmap/techmap_replace.ys @@ -16,3 +16,21 @@ EOT techmap -map %techmap select -assert-any w:s0.asdf select -assert-any c:s0.blah + +read_verilog < Date: Mon, 30 Mar 2020 15:35:31 +0200 Subject: iopadmap: Fix z assignment to inout port Fixes #1841. --- tests/techmap/iopadmap.ys | 10 +++++++++- 1 file changed, 9 insertions(+), 1 deletion(-) (limited to 'tests/techmap') diff --git a/tests/techmap/iopadmap.ys b/tests/techmap/iopadmap.ys index 25ea94dfc..df029b3a0 100644 --- a/tests/techmap/iopadmap.ys +++ b/tests/techmap/iopadmap.ys @@ -55,13 +55,19 @@ obuf b (.i(i), .o(tmp)); assign o = tmp; endmodule +module k(inout o, o2); +assign o = 1'bz; +endmodule + EOT opt_clean tribuf simplemap -iopadmap -bits -inpad ibuf o:i -outpad obuf i:o -toutpad obuft oe:i:o -tinoutpad iobuf oe:o:i:io a b c d e f g h i j +iopadmap -bits -inpad ibuf o:i -outpad obuf i:o -toutpad obuft oe:i:o -tinoutpad iobuf oe:o:i:io a b c d e f g h i j k opt_clean +hierarchy -check +check select -assert-count 1 a/t:ibuf select -assert-count 1 a/t:obuf @@ -140,6 +146,8 @@ select -assert-count 0 i/t:obuf select -assert-count 1 j/t:ibuf select -assert-count 1 j/t:obuf +select -assert-count 2 k/t:iobuf + # Check that \init attributes get moved from output buffer # to buffer input -- cgit v1.2.3 From 9b6370067858aa37825e7a030cd204726f0b58f9 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Fri, 17 Jan 2020 10:51:27 -0800 Subject: techmap +/cmp2lcu.v for decomposing arithmetic compares to $lcu --- tests/techmap/cmp2lcu.ys | 24 ++++++++++++++++++++++++ 1 file changed, 24 insertions(+) create mode 100644 tests/techmap/cmp2lcu.ys (limited to 'tests/techmap') diff --git a/tests/techmap/cmp2lcu.ys b/tests/techmap/cmp2lcu.ys new file mode 100644 index 000000000..e7a422e2f --- /dev/null +++ b/tests/techmap/cmp2lcu.ys @@ -0,0 +1,24 @@ +read_verilog < b; +assign gts = $signed(a) > $signed(b); +assign ltu = a < b; +assign lts = $signed(a) < $signed(b); +assign geu = a >= b; +assign ges = $signed(a) >= $signed(b); +assign leu = a <= b; +assign les = $signed(a) <= $signed(b); +endmodule +EOT +proc + +equiv_opt -assert techmap -map +/cmp2lcu.v -D LUT_WIDTH=6 +design -load postopt +select -assert-count 8 t:$lcu +select -assert-none t:$gt t:$ge t:$lt t:$le + +design -load preopt +equiv_opt -assert techmap -map +/cmp2lcu.v -D LUT_WIDTH=4 +design -load postopt +select -assert-count 8 t:$lcu +select -assert-none t:$gt t:$ge t:$lt t:$le -- cgit v1.2.3 From f68d723cdccdb1a604077e2a3526de2a5198123c Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Mon, 20 Jan 2020 16:42:08 -0800 Subject: Refactor +/cmp2lcu.v into recursive techmap --- tests/techmap/cmp2lcu.ys | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'tests/techmap') diff --git a/tests/techmap/cmp2lcu.ys b/tests/techmap/cmp2lcu.ys index e7a422e2f..620996549 100644 --- a/tests/techmap/cmp2lcu.ys +++ b/tests/techmap/cmp2lcu.ys @@ -1,5 +1,5 @@ read_verilog < b; assign gts = $signed(a) > $signed(b); assign ltu = a < b; -- cgit v1.2.3 From 92d70cafec026fb25bf45b020c138e5244bb8cdc Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Mon, 20 Jan 2020 16:42:17 -0800 Subject: +/cmp2lcu.v to work efficiently for fully/partially constant inputs --- tests/techmap/cmp2lcu.ys | 34 +++++++++++++++++++++++++++++++--- 1 file changed, 31 insertions(+), 3 deletions(-) (limited to 'tests/techmap') diff --git a/tests/techmap/cmp2lcu.ys b/tests/techmap/cmp2lcu.ys index 620996549..7c8a63692 100644 --- a/tests/techmap/cmp2lcu.ys +++ b/tests/techmap/cmp2lcu.ys @@ -10,15 +10,43 @@ assign leu = a <= b; assign les = $signed(a) <= $signed(b); endmodule EOT -proc equiv_opt -assert techmap -map +/cmp2lcu.v -D LUT_WIDTH=6 design -load postopt -select -assert-count 8 t:$lcu +select -assert-count 8 t:$lcu r:WIDTH=5 %i select -assert-none t:$gt t:$ge t:$lt t:$le design -load preopt equiv_opt -assert techmap -map +/cmp2lcu.v -D LUT_WIDTH=4 design -load postopt -select -assert-count 8 t:$lcu +select -assert-count 8 t:$lcu r:WIDTH=7 %i +select -assert-none t:$gt t:$ge t:$lt t:$le + + +design -reset +read_verilog < d; +assign gts = $signed(c) > $signed(d); +assign ltu = c < d; +assign lts = $signed(c) < $signed(d); +assign geu = c >= d; +assign ges = $signed(c) >= $signed(d); +assign leu = c <= d; +assign les = $signed(c) <= $signed(d); +endmodule +EOT +design -save gold + +equiv_opt -assert techmap -map +/cmp2lcu.v -D LUT_WIDTH=5 +design -load postopt +select -assert-count 8 t:$lcu r:WIDTH=2 %i +select -assert-none t:$gt t:$ge t:$lt t:$le + +design -load preopt +equiv_opt -assert techmap -map +/cmp2lcu.v -D LUT_WIDTH=3 +design -load postopt +select -assert-count 8 t:$lcu r:WIDTH=4 %i select -assert-none t:$gt t:$ge t:$lt t:$le -- cgit v1.2.3