From 9ec948f3965eef214bee3af778b67fdd6ee86929 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Mon, 13 Jan 2020 19:07:55 -0800
Subject: write_xaiger: add support and test for (* keep *) on wires

---
 tests/techmap/abc9.ys | 13 +++++++++++++
 1 file changed, 13 insertions(+)

(limited to 'tests/techmap')

diff --git a/tests/techmap/abc9.ys b/tests/techmap/abc9.ys
index 20f263da8..46b6f08d2 100644
--- a/tests/techmap/abc9.ys
+++ b/tests/techmap/abc9.ys
@@ -38,3 +38,16 @@ abc9 -lut 4
 design -load gold
 scratchpad -copy abc9.script.flow3 abc9.script
 abc9 -lut 4
+
+design -reset
+read_verilog <<EOT
+module top(input a, b, output o);
+(* keep *) wire w = a & b;
+assign o = ~w;
+endmodule
+EOT
+
+simplemap
+equiv_opt -assert abc9 -lut 4
+design -load postopt
+select -assert-count 2 t:$lut
-- 
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