From 21baf48e04bfb75527a6c04f1e98b34e62b8eec4 Mon Sep 17 00:00:00 2001
From: Miodrag Milanovic <mmicko@gmail.com>
Date: Wed, 16 Feb 2022 13:58:51 +0100
Subject: test dlatchsr and adlatch

---
 tests/sim/tb/tb_dlatchsr.v | 65 ++++++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 65 insertions(+)
 create mode 100755 tests/sim/tb/tb_dlatchsr.v

(limited to 'tests/sim/tb')

diff --git a/tests/sim/tb/tb_dlatchsr.v b/tests/sim/tb/tb_dlatchsr.v
new file mode 100755
index 000000000..0105d3288
--- /dev/null
+++ b/tests/sim/tb/tb_dlatchsr.v
@@ -0,0 +1,65 @@
+`timescale 1ns/1ns 
+module tb_dlatchsr();
+	reg d = 0;
+	reg set = 0;
+	reg clr = 0;
+	wire q;
+
+	dlatchsr uut(.d(d),.set(set),.clr(clr),.q(q));
+
+	initial
+	begin
+		$dumpfile("tb_dlatchsr");
+		$dumpvars(0,tb_dlatchsr);
+		#10
+		d = 1;
+		#10
+		d = 0;
+		#10
+		d = 1;
+		#10
+		d = 0;
+		#10
+		clr = 1;
+		#10
+		d = 1;
+		#10
+		d = 0;
+		#10
+		d = 1;
+		#10
+		d = 0;
+		#10
+		clr = 0;
+		#10
+		d = 1;
+		#10
+		d = 0;
+		#10
+		d = 1;
+		#10
+		d = 0;
+		#10
+		set = 1;
+		#10
+		d = 1;
+		#10
+		d = 0;
+		#10
+		d = 1;
+		#10
+		d = 0;
+		#10
+		set = 0;
+		#10
+		d = 1;
+		#10
+		d = 0;
+		#10
+		d = 1;
+		#10
+		d = 0;
+		#10
+		$finish;
+	end
+endmodule
-- 
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