From 6f450d0224a3ad09c61c5a150e3e7b3b6241338d Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Sun, 20 Jul 2014 14:55:10 +0200 Subject: Added tests/share for testing "share" supercell creation --- tests/share/generate.py | 41 +++++++++++++++++++++++++++++++++++++++++ 1 file changed, 41 insertions(+) create mode 100644 tests/share/generate.py (limited to 'tests/share/generate.py') diff --git a/tests/share/generate.py b/tests/share/generate.py new file mode 100644 index 000000000..86be6b5ed --- /dev/null +++ b/tests/share/generate.py @@ -0,0 +1,41 @@ +#!/usr/bin/python + +from __future__ import division +from __future__ import print_function + +import sys +import random +from contextlib import contextmanager + +@contextmanager +def redirect_stdout(new_target): + old_target, sys.stdout = sys.stdout, new_target + try: + yield new_target + finally: + sys.stdout = old_target + +for idx in range(100): + with file('temp/uut_%05d.v' % idx, 'w') as f, redirect_stdout(f): + print('module uut_%05d(a, b, c, d, s, y);' % (idx)) + ac_signed = random.choice(['', ' signed']) + bd_signed = random.choice(['', ' signed']) + op = random.choice(['+', '-', '*', '/', '%', '<<', '>>', '<<<', '>>>']) + print(' input%s [%d:0] a;' % (ac_signed, random.randint(0, 8))) + print(' input%s [%d:0] b;' % (bd_signed, random.randint(0, 8))) + print(' input%s [%d:0] c;' % (ac_signed, random.randint(0, 8))) + print(' input%s [%d:0] d;' % (bd_signed, random.randint(0, 8))) + print(' input s;') + print(' output [%d:0] y;' % random.randint(0, 8)) + print(' assign y = s ? %s(a %s b) : %s(c %s d);' % (random.choice(['', '$signed', '$unsigned']), op, random.choice(['', '$signed', '$unsigned']), op)) + print('endmodule') + with file('temp/uut_%05d.ys' % idx, 'w') as f, redirect_stdout(f): + print('read_verilog temp/uut_%05d.v' % idx) + print('proc;;') + print('copy uut_%05d gold' % idx) + print('rename uut_%05d gate' % idx) + print('share -aggressive gate') + print('miter -equiv -ignore_gold_x -make_outputs -make_outcmp gold gate miter') + print('flatten miter') + print('sat -verify -prove trigger 0 -show-inputs -show-outputs miter') + -- cgit v1.2.3 From 4c38ec1cc81c95b79fbd717dafd9f79708c123e8 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Sun, 20 Jul 2014 15:23:08 +0200 Subject: Added "miter -equiv -flatten" --- tests/share/generate.py | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) (limited to 'tests/share/generate.py') diff --git a/tests/share/generate.py b/tests/share/generate.py index 86be6b5ed..07821b721 100644 --- a/tests/share/generate.py +++ b/tests/share/generate.py @@ -35,7 +35,6 @@ for idx in range(100): print('copy uut_%05d gold' % idx) print('rename uut_%05d gate' % idx) print('share -aggressive gate') - print('miter -equiv -ignore_gold_x -make_outputs -make_outcmp gold gate miter') - print('flatten miter') + print('miter -equiv -flatten -ignore_gold_x -make_outputs -make_outcmp gold gate miter') print('sat -verify -prove trigger 0 -show-inputs -show-outputs miter') -- cgit v1.2.3 From 7a6d578b81581f5217b717dcd601cfba2d4a4d0f Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Sun, 20 Jul 2014 17:06:57 +0200 Subject: Improved tests/share/generate.py --- tests/share/generate.py | 14 ++++++++++++-- 1 file changed, 12 insertions(+), 2 deletions(-) (limited to 'tests/share/generate.py') diff --git a/tests/share/generate.py b/tests/share/generate.py index 07821b721..fa17080f9 100644 --- a/tests/share/generate.py +++ b/tests/share/generate.py @@ -15,9 +15,15 @@ def redirect_stdout(new_target): finally: sys.stdout = old_target +def maybe_plus_e(expr): + if random.randint(0, 4) == 0: + return "(%s + e)" % expr + else: + return expr + for idx in range(100): with file('temp/uut_%05d.v' % idx, 'w') as f, redirect_stdout(f): - print('module uut_%05d(a, b, c, d, s, y);' % (idx)) + print('module uut_%05d(a, b, c, d, e, s, y);' % (idx)) ac_signed = random.choice(['', ' signed']) bd_signed = random.choice(['', ' signed']) op = random.choice(['+', '-', '*', '/', '%', '<<', '>>', '<<<', '>>>']) @@ -25,9 +31,13 @@ for idx in range(100): print(' input%s [%d:0] b;' % (bd_signed, random.randint(0, 8))) print(' input%s [%d:0] c;' % (ac_signed, random.randint(0, 8))) print(' input%s [%d:0] d;' % (bd_signed, random.randint(0, 8))) + print(' input signed [%d:0] e;' % random.randint(0, 8)) print(' input s;') print(' output [%d:0] y;' % random.randint(0, 8)) - print(' assign y = s ? %s(a %s b) : %s(c %s d);' % (random.choice(['', '$signed', '$unsigned']), op, random.choice(['', '$signed', '$unsigned']), op)) + print(' assign y = (s ? %s(%s %s %s) : %s(%s %s %s))%s;' % + (random.choice(['', '$signed', '$unsigned']), maybe_plus_e('a'), op, maybe_plus_e('b'), + random.choice(['', '$signed', '$unsigned']), maybe_plus_e('c'), op, maybe_plus_e('d'), + ' + e' if random.randint(0, 4) == 0 else '')) print('endmodule') with file('temp/uut_%05d.ys' % idx, 'w') as f, redirect_stdout(f): print('read_verilog temp/uut_%05d.v' % idx) -- cgit v1.2.3 From e9506bb2da9640cebc325e33a678d352d36a909e Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Sun, 20 Jul 2014 18:54:06 +0200 Subject: Supercell creation for $div/$mod worked all along, fixed test benches --- tests/share/generate.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'tests/share/generate.py') diff --git a/tests/share/generate.py b/tests/share/generate.py index fa17080f9..9e5bef7ae 100644 --- a/tests/share/generate.py +++ b/tests/share/generate.py @@ -46,5 +46,5 @@ for idx in range(100): print('rename uut_%05d gate' % idx) print('share -aggressive gate') print('miter -equiv -flatten -ignore_gold_x -make_outputs -make_outcmp gold gate miter') - print('sat -verify -prove trigger 0 -show-inputs -show-outputs miter') + print('sat -set-def-inputs -verify -prove trigger 0 -show-inputs -show-outputs miter') -- cgit v1.2.3 From 3cb61d03f8722fddfa14877accae1b3ca51e3926 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Mon, 21 Jul 2014 12:04:56 +0200 Subject: Wider range of cell types supported in "share" pass --- tests/share/generate.py | 60 +++++++++++++++++++++++++++++++++---------------- 1 file changed, 41 insertions(+), 19 deletions(-) (limited to 'tests/share/generate.py') diff --git a/tests/share/generate.py b/tests/share/generate.py index 9e5bef7ae..e3b4bc969 100644 --- a/tests/share/generate.py +++ b/tests/share/generate.py @@ -15,36 +15,58 @@ def redirect_stdout(new_target): finally: sys.stdout = old_target -def maybe_plus_e(expr): +def random_plus_x(): + return "%s x" % random.choice(['+', '+', '+', '-', '-', '|', '&', '^']) + +def maybe_plus_x(expr): if random.randint(0, 4) == 0: - return "(%s + e)" % expr + return "(%s %s)" % (expr, random_plus_x()) else: return expr for idx in range(100): with file('temp/uut_%05d.v' % idx, 'w') as f, redirect_stdout(f): - print('module uut_%05d(a, b, c, d, e, s, y);' % (idx)) - ac_signed = random.choice(['', ' signed']) - bd_signed = random.choice(['', ' signed']) - op = random.choice(['+', '-', '*', '/', '%', '<<', '>>', '<<<', '>>>']) - print(' input%s [%d:0] a;' % (ac_signed, random.randint(0, 8))) - print(' input%s [%d:0] b;' % (bd_signed, random.randint(0, 8))) - print(' input%s [%d:0] c;' % (ac_signed, random.randint(0, 8))) - print(' input%s [%d:0] d;' % (bd_signed, random.randint(0, 8))) - print(' input signed [%d:0] e;' % random.randint(0, 8)) - print(' input s;') - print(' output [%d:0] y;' % random.randint(0, 8)) - print(' assign y = (s ? %s(%s %s %s) : %s(%s %s %s))%s;' % - (random.choice(['', '$signed', '$unsigned']), maybe_plus_e('a'), op, maybe_plus_e('b'), - random.choice(['', '$signed', '$unsigned']), maybe_plus_e('c'), op, maybe_plus_e('d'), - ' + e' if random.randint(0, 4) == 0 else '')) - print('endmodule') + if random.choice(['bin', 'uni']) == 'bin': + print('module uut_%05d(a, b, c, d, x, s, y);' % (idx)) + op = random.choice([ + random.choice(['+', '-', '*', '/', '%']), + random.choice(['<', '<=', '==', '!=', '===', '!==', '>=', '>' ]), + random.choice(['<<', '>>', '<<<', '>>>']), + random.choice(['|', '&', '^', '~^', '||', '&&']), + ]) + print(' input%s [%d:0] a;' % (random.choice(['', ' signed']), random.randint(0, 8))) + print(' input%s [%d:0] b;' % (random.choice(['', ' signed']), random.randint(0, 8))) + print(' input%s [%d:0] c;' % (random.choice(['', ' signed']), random.randint(0, 8))) + print(' input%s [%d:0] d;' % (random.choice(['', ' signed']), random.randint(0, 8))) + print(' input%s [%d:0] x;' % (random.choice(['', ' signed']), random.randint(0, 8))) + print(' input s;') + print(' output [%d:0] y;' % random.randint(0, 8)) + print(' assign y = (s ? %s(%s %s %s) : %s(%s %s %s))%s;' % + (random.choice(['', '$signed', '$unsigned']), maybe_plus_x('a'), op, maybe_plus_x('b'), + random.choice(['', '$signed', '$unsigned']), maybe_plus_x('c'), op, maybe_plus_x('d'), + random_plus_x() if random.randint(0, 4) == 0 else '')) + print('endmodule') + else: + print('module uut_%05d(a, b, x, s, y);' % (idx)) + op = random.choice(['~', '-', '!']) + print(' input%s [%d:0] a;' % (random.choice(['', ' signed']), random.randint(0, 8))) + print(' input%s [%d:0] b;' % (random.choice(['', ' signed']), random.randint(0, 8))) + print(' input%s [%d:0] x;' % (random.choice(['', ' signed']), random.randint(0, 8))) + print(' input s;') + print(' output [%d:0] y;' % random.randint(0, 8)) + print(' assign y = (s ? %s(%s%s) : %s(%s%s))%s;' % + (random.choice(['', '$signed', '$unsigned']), op, maybe_plus_x('a'), + random.choice(['', '$signed', '$unsigned']), op, maybe_plus_x('b'), + random_plus_x() if random.randint(0, 4) == 0 else '')) + print('endmodule') with file('temp/uut_%05d.ys' % idx, 'w') as f, redirect_stdout(f): print('read_verilog temp/uut_%05d.v' % idx) print('proc;;') print('copy uut_%05d gold' % idx) print('rename uut_%05d gate' % idx) - print('share -aggressive gate') + print('tee -a temp/all_share_log.txt log') + print('tee -a temp/all_share_log.txt log #job# uut_%05d' % idx) + print('tee -a temp/all_share_log.txt share -aggressive gate') print('miter -equiv -flatten -ignore_gold_x -make_outputs -make_outcmp gold gate miter') print('sat -set-def-inputs -verify -prove trigger 0 -show-inputs -show-outputs miter') -- cgit v1.2.3 From 358bf70a2111d476d9d209f216fdd087356ec0d9 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Sun, 3 Aug 2014 20:03:16 +0200 Subject: Added "wreduce" to some of the standard test benches --- tests/share/generate.py | 1 + 1 file changed, 1 insertion(+) (limited to 'tests/share/generate.py') diff --git a/tests/share/generate.py b/tests/share/generate.py index e3b4bc969..a06a642d8 100644 --- a/tests/share/generate.py +++ b/tests/share/generate.py @@ -66,6 +66,7 @@ for idx in range(100): print('rename uut_%05d gate' % idx) print('tee -a temp/all_share_log.txt log') print('tee -a temp/all_share_log.txt log #job# uut_%05d' % idx) + print('tee -a temp/all_share_log.txt wreduce') print('tee -a temp/all_share_log.txt share -aggressive gate') print('miter -equiv -flatten -ignore_gold_x -make_outputs -make_outcmp gold gate miter') print('sat -set-def-inputs -verify -prove trigger 0 -show-inputs -show-outputs miter') -- cgit v1.2.3