From 07a657fb0ca08012af3de410520458af255b1097 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Marcelina=20Ko=C5=9Bcielnicka?= <mwk@0x04.net>
Date: Sat, 29 Jan 2022 01:01:21 +0100
Subject: opt_reduce: Add $bmux and $demux optimization patterns.

---
 tests/opt/opt_reduce_bmux.ys  | 117 ++++++++++++++++++++++++++++++++++++++++++
 tests/opt/opt_reduce_demux.ys |  91 ++++++++++++++++++++++++++++++++
 2 files changed, 208 insertions(+)
 create mode 100644 tests/opt/opt_reduce_bmux.ys
 create mode 100644 tests/opt/opt_reduce_demux.ys

(limited to 'tests/opt')

diff --git a/tests/opt/opt_reduce_bmux.ys b/tests/opt/opt_reduce_bmux.ys
new file mode 100644
index 000000000..55e0b6d4b
--- /dev/null
+++ b/tests/opt/opt_reduce_bmux.ys
@@ -0,0 +1,117 @@
+read_ilang << EOT
+
+module \top
+  wire width 12 input 0 \A
+  wire width 2 input 1 \S
+  wire width 6 output 2 \Y
+
+  cell $bmux $0
+    parameter \WIDTH 6
+    parameter \S_WIDTH 2
+    connect \A { \A [11:10] \A [3:2] \A [10:9] \A [7] \A [7] \A [8] \A [2] \A [7:6] \A [5] \A [5] \A [3:2] \A [5:4] \A [1] \A [1] \A [3:0] }
+    connect \S \S
+    connect \Y \Y
+  end
+end
+
+EOT
+
+equiv_opt -assert opt_reduce -fine
+opt_reduce -fine
+select -assert-count 1 t:$bmux r:WIDTH=4 %i
+
+design -reset
+
+read_ilang << EOT
+
+module \top
+  wire width 6 input 0 \A
+  wire width 2 input 1 \S
+  wire width 6 output 2 \Y
+
+  cell $bmux $0
+    parameter \WIDTH 6
+    parameter \S_WIDTH 2
+    connect \A { \A [5:0] \A [5:0] \A [5:0] \A [5:0] }
+    connect \S \S
+    connect \Y \Y
+  end
+end
+
+EOT
+
+equiv_opt -assert opt_reduce -fine
+opt_reduce -fine
+select -assert-count 0 t:$bmux
+
+design -reset
+
+read_ilang << EOT
+
+module \top
+  wire width 160 input 0 \A
+  wire width 2 input 1 \S
+  wire width 5 output 2 \Y
+
+  cell $bmux $0
+    parameter \WIDTH 5
+    parameter \S_WIDTH 5
+    connect \A \A
+    connect \S { \S [1] 1'1 \S [0] \S [1] 1'0 }
+    connect \Y \Y
+  end
+end
+
+EOT
+
+equiv_opt -assert opt_reduce -fine
+opt_reduce -fine
+select -assert-count 1 t:$bmux r:S_WIDTH=2 %i
+
+design -reset
+
+read_ilang << EOT
+
+module \top
+  wire width 10 input 0 \A
+  wire input 1 \S
+  wire width 5 output 2 \Y
+
+  cell $bmux $0
+    parameter \WIDTH 5
+    parameter \S_WIDTH 1
+    connect \A \A
+    connect \S \S
+    connect \Y \Y
+  end
+end
+
+EOT
+
+equiv_opt -assert opt_reduce -fine
+opt_reduce -fine
+select -assert-count 0 t:$bmux
+select -assert-count 1 t:$mux
+
+design -reset
+
+read_ilang << EOT
+
+module \top
+  wire width 5 input 0 \A
+  wire width 5 output 1 \Y
+
+  cell $bmux $0
+    parameter \WIDTH 5
+    parameter \S_WIDTH 0
+    connect \A \A
+    connect \S { }
+    connect \Y \Y
+  end
+end
+
+EOT
+
+equiv_opt -assert opt_reduce -fine
+opt_reduce -fine
+select -assert-count 0 t:$bmux
diff --git a/tests/opt/opt_reduce_demux.ys b/tests/opt/opt_reduce_demux.ys
new file mode 100644
index 000000000..3c5bd7d43
--- /dev/null
+++ b/tests/opt/opt_reduce_demux.ys
@@ -0,0 +1,91 @@
+read_ilang << EOT
+
+module \top
+  wire width 4 input 0 \A
+  wire width 2 input 1 \S
+  wire width 24 output 2 \Y
+
+  cell $demux $0
+    parameter \WIDTH 6
+    parameter \S_WIDTH 2
+    connect \A { \A [3] \A [1] 1'0 \A [2:0] }
+    connect \S \S
+    connect \Y \Y
+  end
+end
+
+EOT
+
+equiv_opt -assert opt_reduce -fine
+opt_reduce -fine
+select -assert-count 1 t:$demux r:WIDTH=4 %i
+
+design -reset
+
+read_ilang << EOT
+
+module \top
+  wire width 2 input 1 \S
+  wire width 24 output 2 \Y
+
+  cell $demux $0
+    parameter \WIDTH 6
+    parameter \S_WIDTH 2
+    connect \A 6'000000
+    connect \S \S
+    connect \Y \Y
+  end
+end
+
+EOT
+
+equiv_opt -assert opt_reduce -fine
+opt_reduce -fine
+select -assert-count 0 t:$demux
+
+design -reset
+
+read_ilang << EOT
+
+module \top
+  wire width 5 input 0 \A
+  wire width 2 input 1 \S
+  wire width 160 output 2 \Y
+
+  cell $demux $0
+    parameter \WIDTH 5
+    parameter \S_WIDTH 5
+    connect \A \A
+    connect \S { \S [0] \S [1] 1'1 \S [0] 1'0 }
+    connect \Y \Y
+  end
+end
+
+EOT
+
+equiv_opt -assert opt_reduce -fine
+opt_reduce -fine
+select -assert-count 1 t:$demux r:S_WIDTH=2 %i
+
+design -reset
+
+read_ilang << EOT
+
+module \top
+  wire width 5 input 0 \A
+  wire width 20 output 2 \Y
+
+  cell $demux $0
+    parameter \WIDTH 5
+    parameter \S_WIDTH 2
+    connect \A \A
+    connect \S { 2'10 }
+    connect \Y \Y
+  end
+end
+
+EOT
+
+equiv_opt -assert opt_reduce -fine
+opt_reduce -fine
+select -assert-count 0 t:$demux
-- 
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