From c2ec7ca7031e2e9c655723fcdb3ce3cb83cc74b1 Mon Sep 17 00:00:00 2001
From: Miodrag Milanovic <mmicko@gmail.com>
Date: Fri, 18 Oct 2019 11:06:12 +0200
Subject: Moved all tests in arch sub directory

---
 tests/ice40/.gitignore   |   4 --
 tests/ice40/add_sub.v    |  13 ------
 tests/ice40/add_sub.ys   |   9 -----
 tests/ice40/adffs.v      |  87 -----------------------------------------
 tests/ice40/adffs.ys     |  11 ------
 tests/ice40/alu.v        |  19 ---------
 tests/ice40/alu.ys       |  11 ------
 tests/ice40/counter.v    |  17 --------
 tests/ice40/counter.ys   |  11 ------
 tests/ice40/dffs.v       |  37 ------------------
 tests/ice40/dffs.ys      |  10 -----
 tests/ice40/div_mod.v    |  13 ------
 tests/ice40/div_mod.ys   |   9 -----
 tests/ice40/dpram.v      |  23 -----------
 tests/ice40/dpram.ys     |  15 -------
 tests/ice40/fsm.v        |  73 ----------------------------------
 tests/ice40/fsm.ys       |  13 ------
 tests/ice40/ice40_opt.ys |  26 ------------
 tests/ice40/latches.v    |  58 ---------------------------
 tests/ice40/latches.ys   |  12 ------
 tests/ice40/logic.v      |  18 ---------
 tests/ice40/logic.ys     |   7 ----
 tests/ice40/macc.v       |  47 ----------------------
 tests/ice40/macc.ys      |  25 ------------
 tests/ice40/memory.v     |  21 ----------
 tests/ice40/memory.ys    |  15 -------
 tests/ice40/mul.v        |  11 ------
 tests/ice40/mul.ys       |   7 ----
 tests/ice40/mux.v        | 100 -----------------------------------------------
 tests/ice40/mux.ys       |   8 ----
 tests/ice40/rom.v        |  18 ---------
 tests/ice40/rom.ys       |   8 ----
 tests/ice40/run-test.sh  |  20 ----------
 tests/ice40/shifter.v    |  22 -----------
 tests/ice40/shifter.ys   |   9 -----
 tests/ice40/tribuf.v     |  23 -----------
 tests/ice40/tribuf.ys    |   9 -----
 tests/ice40/wrapcarry.ys |  22 -----------
 38 files changed, 861 deletions(-)
 delete mode 100644 tests/ice40/.gitignore
 delete mode 100644 tests/ice40/add_sub.v
 delete mode 100644 tests/ice40/add_sub.ys
 delete mode 100644 tests/ice40/adffs.v
 delete mode 100644 tests/ice40/adffs.ys
 delete mode 100644 tests/ice40/alu.v
 delete mode 100644 tests/ice40/alu.ys
 delete mode 100644 tests/ice40/counter.v
 delete mode 100644 tests/ice40/counter.ys
 delete mode 100644 tests/ice40/dffs.v
 delete mode 100644 tests/ice40/dffs.ys
 delete mode 100644 tests/ice40/div_mod.v
 delete mode 100644 tests/ice40/div_mod.ys
 delete mode 100644 tests/ice40/dpram.v
 delete mode 100644 tests/ice40/dpram.ys
 delete mode 100644 tests/ice40/fsm.v
 delete mode 100644 tests/ice40/fsm.ys
 delete mode 100644 tests/ice40/ice40_opt.ys
 delete mode 100644 tests/ice40/latches.v
 delete mode 100644 tests/ice40/latches.ys
 delete mode 100644 tests/ice40/logic.v
 delete mode 100644 tests/ice40/logic.ys
 delete mode 100644 tests/ice40/macc.v
 delete mode 100644 tests/ice40/macc.ys
 delete mode 100644 tests/ice40/memory.v
 delete mode 100644 tests/ice40/memory.ys
 delete mode 100644 tests/ice40/mul.v
 delete mode 100644 tests/ice40/mul.ys
 delete mode 100644 tests/ice40/mux.v
 delete mode 100644 tests/ice40/mux.ys
 delete mode 100644 tests/ice40/rom.v
 delete mode 100644 tests/ice40/rom.ys
 delete mode 100755 tests/ice40/run-test.sh
 delete mode 100644 tests/ice40/shifter.v
 delete mode 100644 tests/ice40/shifter.ys
 delete mode 100644 tests/ice40/tribuf.v
 delete mode 100644 tests/ice40/tribuf.ys
 delete mode 100644 tests/ice40/wrapcarry.ys

(limited to 'tests/ice40')

diff --git a/tests/ice40/.gitignore b/tests/ice40/.gitignore
deleted file mode 100644
index 9a71dca69..000000000
--- a/tests/ice40/.gitignore
+++ /dev/null
@@ -1,4 +0,0 @@
-*.log
-/run-test.mk
-+*_synth.v
-+*_testbench
diff --git a/tests/ice40/add_sub.v b/tests/ice40/add_sub.v
deleted file mode 100644
index 177c32e30..000000000
--- a/tests/ice40/add_sub.v
+++ /dev/null
@@ -1,13 +0,0 @@
-module top
-(
- input [3:0] x,
- input [3:0] y,
-
- output [3:0] A,
- output [3:0] B
- );
-
-assign A =  x + y;
-assign B =  x - y;
-
-endmodule
diff --git a/tests/ice40/add_sub.ys b/tests/ice40/add_sub.ys
deleted file mode 100644
index 4a998d98d..000000000
--- a/tests/ice40/add_sub.ys
+++ /dev/null
@@ -1,9 +0,0 @@
-read_verilog add_sub.v
-hierarchy -top top
-equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 # equivalency check
-design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
-cd top # Constrain all select calls below inside the top module
-select -assert-count 11 t:SB_LUT4
-select -assert-count 6 t:SB_CARRY
-select -assert-none t:SB_LUT4 t:SB_CARRY %% t:* %D
-
diff --git a/tests/ice40/adffs.v b/tests/ice40/adffs.v
deleted file mode 100644
index 09dc36001..000000000
--- a/tests/ice40/adffs.v
+++ /dev/null
@@ -1,87 +0,0 @@
-module adff
-    ( input d, clk, clr, output reg q );
-    initial begin
-      q = 0;
-    end
-	always @( posedge clk, posedge clr )
-		if ( clr )
-			q <= 1'b0;
-		else
-            q <= d;
-endmodule
-
-module adffn
-    ( input d, clk, clr, output reg q );
-    initial begin
-      q = 0;
-    end
-	always @( posedge clk, negedge clr )
-		if ( !clr )
-			q <= 1'b0;
-		else
-            q <= d;
-endmodule
-
-module dffs
-    ( input d, clk, pre, clr, output reg q );
-    initial begin
-      q = 0;
-    end
-	always @( posedge clk, posedge pre )
-		if ( pre )
-			q <= 1'b1;
-		else
-            q <= d;
-endmodule
-
-module ndffnr
-    ( input d, clk, pre, clr, output reg q );
-    initial begin
-      q = 0;
-    end
-	always @( negedge clk, negedge pre )
-		if ( !pre )
-			q <= 1'b1;
-		else
-            q <= d;
-endmodule
-
-module top (
-input clk,
-input clr,
-input pre,
-input a,
-output b,b1,b2,b3
-);
-
-dffs u_dffs (
-        .clk (clk ),
-        .clr (clr),
-        .pre (pre),
-        .d (a ),
-        .q (b )
-    );
-
-ndffnr u_ndffnr (
-        .clk (clk ),
-        .clr (clr),
-        .pre (pre),
-        .d (a ),
-        .q (b1 )
-    );
-
-adff u_adff (
-        .clk (clk ),
-        .clr (clr),
-        .d (a ),
-        .q (b2 )
-    );
-
-adffn u_adffn (
-        .clk (clk ),
-        .clr (clr),
-        .d (a ),
-        .q (b3 )
-    );
-
-endmodule
diff --git a/tests/ice40/adffs.ys b/tests/ice40/adffs.ys
deleted file mode 100644
index 548060b66..000000000
--- a/tests/ice40/adffs.ys
+++ /dev/null
@@ -1,11 +0,0 @@
-read_verilog adffs.v
-proc
-flatten
-equiv_opt -multiclock -assert -map +/ice40/cells_sim.v synth_ice40 # equivalency check
-design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
-cd top # Constrain all select calls below inside the top module
-select -assert-count 1 t:SB_DFFNS
-select -assert-count 2 t:SB_DFFR
-select -assert-count 1 t:SB_DFFS
-select -assert-count 2 t:SB_LUT4
-select -assert-none t:SB_DFFNS t:SB_DFFR t:SB_DFFS t:SB_LUT4 %% t:* %D
diff --git a/tests/ice40/alu.v b/tests/ice40/alu.v
deleted file mode 100644
index f82cc2e21..000000000
--- a/tests/ice40/alu.v
+++ /dev/null
@@ -1,19 +0,0 @@
-module top (
-	input clock,
-	input [31:0] dinA, dinB,
-	input [2:0] opcode,
-	output reg [31:0] dout
-);
-	always @(posedge clock) begin
-		case (opcode)
-		0: dout <= dinA + dinB;
-		1: dout <= dinA - dinB;
-		2: dout <= dinA >> dinB;
-		3: dout <= $signed(dinA) >>> dinB;
-		4: dout <= dinA << dinB;
-		5: dout <= dinA & dinB;
-		6: dout <= dinA | dinB;
-		7: dout <= dinA ^ dinB;
-		endcase
-	end
-endmodule
diff --git a/tests/ice40/alu.ys b/tests/ice40/alu.ys
deleted file mode 100644
index bd859efc4..000000000
--- a/tests/ice40/alu.ys
+++ /dev/null
@@ -1,11 +0,0 @@
-read_verilog alu.v
-hierarchy -top top
-proc
-flatten
-equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 # equivalency check
-design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
-cd top # Constrain all select calls below inside the top module
-select -assert-count 62 t:SB_CARRY
-select -assert-count 32 t:SB_DFF
-select -assert-count 655 t:SB_LUT4
-select -assert-none t:SB_CARRY t:SB_DFF t:SB_LUT4 %% t:* %D
diff --git a/tests/ice40/counter.v b/tests/ice40/counter.v
deleted file mode 100644
index 52852f8ac..000000000
--- a/tests/ice40/counter.v
+++ /dev/null
@@ -1,17 +0,0 @@
-module top    (
-out,
-clk,
-reset
-);
-    output [7:0] out;
-    input clk, reset;
-    reg [7:0] out;
-
-    always @(posedge clk, posedge reset)
-		if (reset) begin
-			out <= 8'b0 ;
-		end else
-			out <= out + 1;
-
-
-endmodule
diff --git a/tests/ice40/counter.ys b/tests/ice40/counter.ys
deleted file mode 100644
index c65c21622..000000000
--- a/tests/ice40/counter.ys
+++ /dev/null
@@ -1,11 +0,0 @@
-read_verilog counter.v
-hierarchy -top top
-proc
-flatten
-equiv_opt -map +/ice40/cells_sim.v synth_ice40 # equivalency check
-design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
-cd top # Constrain all select calls below inside the top module
-select -assert-count 6 t:SB_CARRY
-select -assert-count 8 t:SB_DFFR
-select -assert-count 8 t:SB_LUT4
-select -assert-none t:SB_CARRY t:SB_DFFR t:SB_LUT4 %% t:* %D
diff --git a/tests/ice40/dffs.v b/tests/ice40/dffs.v
deleted file mode 100644
index d97840c43..000000000
--- a/tests/ice40/dffs.v
+++ /dev/null
@@ -1,37 +0,0 @@
-module dff
-    ( input d, clk, output reg q );
-	always @( posedge clk )
-            q <= d;
-endmodule
-
-module dffe
-    ( input d, clk, en, output reg q );
-    initial begin
-      q = 0;
-    end
-	always @( posedge clk )
-		if ( en )
-			q <= d;
-endmodule
-
-module top (
-input clk,
-input en,
-input a,
-output b,b1,
-);
-
-dff u_dff (
-        .clk (clk ),
-        .d (a ),
-        .q (b )
-    );
-
-dffe u_ndffe (
-        .clk (clk ),
-        .en (en),
-        .d (a ),
-        .q (b1 )
-    );
-
-endmodule
diff --git a/tests/ice40/dffs.ys b/tests/ice40/dffs.ys
deleted file mode 100644
index ee7f884b1..000000000
--- a/tests/ice40/dffs.ys
+++ /dev/null
@@ -1,10 +0,0 @@
-read_verilog dffs.v
-hierarchy -top top
-proc
-flatten
-equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 # equivalency check
-design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
-cd top # Constrain all select calls below inside the top module
-select -assert-count 1 t:SB_DFF
-select -assert-count 1 t:SB_DFFE
-select -assert-none t:SB_DFF t:SB_DFFE %% t:* %D
diff --git a/tests/ice40/div_mod.v b/tests/ice40/div_mod.v
deleted file mode 100644
index 64a36707d..000000000
--- a/tests/ice40/div_mod.v
+++ /dev/null
@@ -1,13 +0,0 @@
-module top
-(
- input [3:0] x,
- input [3:0] y,
-
- output [3:0] A,
- output [3:0] B
- );
-
-assign A =  x % y;
-assign B =  x / y;
-
-endmodule
diff --git a/tests/ice40/div_mod.ys b/tests/ice40/div_mod.ys
deleted file mode 100644
index 821d6c301..000000000
--- a/tests/ice40/div_mod.ys
+++ /dev/null
@@ -1,9 +0,0 @@
-read_verilog div_mod.v
-hierarchy -top top
-flatten
-equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 # equivalency check
-design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
-cd top # Constrain all select calls below inside the top module
-select -assert-count 59 t:SB_LUT4
-select -assert-count 41 t:SB_CARRY
-select -assert-none t:SB_LUT4 t:SB_CARRY %% t:* %D
diff --git a/tests/ice40/dpram.v b/tests/ice40/dpram.v
deleted file mode 100644
index 3ea4c1f27..000000000
--- a/tests/ice40/dpram.v
+++ /dev/null
@@ -1,23 +0,0 @@
-/*
-Example from: https://www.latticesemi.com/-/media/LatticeSemi/Documents/UserManuals/EI/iCEcube201701UserGuide.ashx?document_id=52071 [p. 72].
-*/
-module top (din, write_en, waddr, wclk, raddr, rclk, dout);
-parameter addr_width = 8;
-parameter data_width = 8;
-input [addr_width-1:0] waddr, raddr;
-input [data_width-1:0] din;
-input write_en, wclk, rclk;
-output [data_width-1:0] dout;
-reg [data_width-1:0] dout;
-reg [data_width-1:0] mem [(1<<addr_width)-1:0]
-/* synthesis syn_ramstyle = "no_rw_check" */ ;
-always @(posedge wclk) // Write memory.
-begin
-if (write_en)
-mem[waddr] <= din; // Using write address bus.
-end
-always @(posedge rclk) // Read memory.
-begin
-dout <= mem[raddr]; // Using read address bus.
-end
-endmodule
diff --git a/tests/ice40/dpram.ys b/tests/ice40/dpram.ys
deleted file mode 100644
index 4f6a253ea..000000000
--- a/tests/ice40/dpram.ys
+++ /dev/null
@@ -1,15 +0,0 @@
-read_verilog dpram.v
-hierarchy -top top
-proc
-memory -nomap
-equiv_opt -run :prove -map +/ice40/cells_sim.v synth_ice40
-memory
-opt -full
-
-miter -equiv -flatten -make_assert -make_outputs gold gate miter
-sat -verify -prove-asserts -seq 3 -set-init-zero -show-inputs -show-outputs miter
-
-design -load postopt
-cd top
-select -assert-count 1 t:SB_RAM40_4K
-select -assert-none t:SB_RAM40_4K %% t:* %D
diff --git a/tests/ice40/fsm.v b/tests/ice40/fsm.v
deleted file mode 100644
index 0605bd102..000000000
--- a/tests/ice40/fsm.v
+++ /dev/null
@@ -1,73 +0,0 @@
- module fsm (
- clock,
- reset,
- req_0,
- req_1,
- gnt_0,
- gnt_1
- );
- input   clock,reset,req_0,req_1;
- output  gnt_0,gnt_1;
- wire    clock,reset,req_0,req_1;
- reg     gnt_0,gnt_1;
-
- parameter SIZE = 3           ;
- parameter IDLE  = 3'b001,GNT0 = 3'b010,GNT1 = 3'b100,GNT2 = 3'b101 ;
-
- reg [SIZE-1:0] state;
- reg [SIZE-1:0] next_state;
-
- always @ (posedge clock)
- begin : FSM
- if (reset == 1'b1) begin
-   state <=  #1  IDLE;
-   gnt_0 <= 0;
-   gnt_1 <= 0;
- end else
-  case(state)
-    IDLE : if (req_0 == 1'b1) begin
-                 state <=  #1  GNT0;
-                 gnt_0 <= 1;
-               end else if (req_1 == 1'b1) begin
-                 gnt_1 <= 1;
-                 state <=  #1  GNT0;
-               end else begin
-                 state <=  #1  IDLE;
-               end
-    GNT0 : if (req_0 == 1'b1) begin
-                 state <=  #1  GNT0;
-               end else begin
-                 gnt_0 <= 0;
-                 state <=  #1  IDLE;
-               end
-    GNT1 : if (req_1 == 1'b1) begin
-                 state <=  #1  GNT2;
-				 gnt_1 <= req_0;
-               end
-    GNT2 : if (req_0 == 1'b1) begin
-                 state <=  #1  GNT1;
-				 gnt_1 <= req_1;
-               end
-    default : state <=  #1  IDLE;
- endcase
- end
-
- endmodule
-
- module top (
-input clk,
-input rst,
-input a,
-input b,
-output g0,
-output g1
-);
-
-fsm u_fsm ( .clock(clk),
-            .reset(rst),
-            .req_0(a),
-            .req_1(b),
-            .gnt_0(g0),
-            .gnt_1(g1));
-
-endmodule
diff --git a/tests/ice40/fsm.ys b/tests/ice40/fsm.ys
deleted file mode 100644
index 4cc8629d6..000000000
--- a/tests/ice40/fsm.ys
+++ /dev/null
@@ -1,13 +0,0 @@
-read_verilog fsm.v
-hierarchy -top top
-proc
-flatten
-equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 # equivalency check
-design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
-cd top # Constrain all select calls below inside the top module
-
-select -assert-count 2 t:SB_DFFESR
-select -assert-count 2 t:SB_DFFSR
-select -assert-count 1 t:SB_DFFSS
-select -assert-count 13 t:SB_LUT4
-select -assert-none t:SB_DFFESR t:SB_DFFSR t:SB_DFFSS t:SB_LUT4 %% t:* %D
diff --git a/tests/ice40/ice40_opt.ys b/tests/ice40/ice40_opt.ys
deleted file mode 100644
index b17c69c91..000000000
--- a/tests/ice40/ice40_opt.ys
+++ /dev/null
@@ -1,26 +0,0 @@
-read_verilog -icells -formal <<EOT
-module top(input CI, I0, output [1:0] CO, output O);
-    wire A = 1'b0, B = 1'b0;
-	\$__ICE40_CARRY_WRAPPER #(
-		//    A[0]: 1010 1010 1010 1010
-		//    A[1]: 1100 1100 1100 1100
-		//    A[2]: 1111 0000 1111 0000
-		//    A[3]: 1111 1111 0000 0000
-		.LUT(~16'b 0110_1001_1001_0110)
-	) u0 (
-		.A(A),
-		.B(B),
-		.CI(CI),
-		.I0(I0),
-		.I3(CI),
-		.CO(CO[0]),
-		.O(O)
-	);
-    SB_CARRY u1 (.I0(~A), .I1(~B), .CI(CI), .CO(CO[1]));
-endmodule
-EOT
-
-equiv_opt -assert -map +/ice40/cells_map.v -map +/ice40/cells_sim.v ice40_opt
-design -load postopt
-select -assert-count 1 t:*
-select -assert-count 1 t:$lut
diff --git a/tests/ice40/latches.v b/tests/ice40/latches.v
deleted file mode 100644
index 9dc43e4c2..000000000
--- a/tests/ice40/latches.v
+++ /dev/null
@@ -1,58 +0,0 @@
-module latchp
-    ( input d, clk, en, output reg q );
-	always @*
-		if ( en )
-			q <= d;
-endmodule
-
-module latchn
-    ( input d, clk, en, output reg q );
-	always @*
-		if ( !en )
-			q <= d;
-endmodule
-
-module latchsr
-    ( input d, clk, en, clr, pre, output reg q );
-	always @*
-		if ( clr )
-			q <= 1'b0;
-		else if ( pre )
-			q <= 1'b1;
-		else if ( en )
-			q <= d;
-endmodule
-
-
-module top (
-input clk,
-input clr,
-input pre,
-input a,
-output b,b1,b2
-);
-
-
-latchp u_latchp (
-        .en (clk ),
-        .d (a ),
-        .q (b )
-    );
-
-
-latchn u_latchn (
-        .en (clk ),
-        .d (a ),
-        .q (b1 )
-    );
-
-
-latchsr u_latchsr (
-        .en (clk ),
-        .clr (clr),
-        .pre (pre),
-        .d (a ),
-        .q (b2 )
-    );
-
-endmodule
diff --git a/tests/ice40/latches.ys b/tests/ice40/latches.ys
deleted file mode 100644
index 708734e44..000000000
--- a/tests/ice40/latches.ys
+++ /dev/null
@@ -1,12 +0,0 @@
-read_verilog latches.v
-
-proc
-flatten
-# Can't run any sort of equivalence check because latches are blown to LUTs
-#equiv_opt -async2sync -assert -map +/ice40/cells_sim.v synth_ice40 # equivalency check
-
-#design -load preopt
-synth_ice40
-cd top
-select -assert-count 4 t:SB_LUT4
-select -assert-none t:SB_LUT4 %% t:* %D
diff --git a/tests/ice40/logic.v b/tests/ice40/logic.v
deleted file mode 100644
index e5343cae0..000000000
--- a/tests/ice40/logic.v
+++ /dev/null
@@ -1,18 +0,0 @@
-module top
-(
- input [0:7] in,
- output B1,B2,B3,B4,B5,B6,B7,B8,B9,B10
- );
-
-   assign     B1 =  in[0] & in[1];
-   assign     B2 =  in[0] | in[1];
-   assign     B3 =  in[0] ~& in[1];
-   assign     B4 =  in[0] ~| in[1];
-   assign     B5 =  in[0] ^ in[1];
-   assign     B6 =  in[0] ~^ in[1];
-   assign     B7 =  ~in[0];
-   assign     B8 =  in[0];
-   assign     B9 =  in[0:1] && in [2:3];
-   assign     B10 =  in[0:1] || in [2:3];
-
-endmodule
diff --git a/tests/ice40/logic.ys b/tests/ice40/logic.ys
deleted file mode 100644
index fc5e5b1d8..000000000
--- a/tests/ice40/logic.ys
+++ /dev/null
@@ -1,7 +0,0 @@
-read_verilog logic.v
-hierarchy -top top
-equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 # equivalency check
-design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
-cd top # Constrain all select calls below inside the top module
-select -assert-count 9 t:SB_LUT4
-select -assert-none t:SB_LUT4 %% t:* %D
diff --git a/tests/ice40/macc.v b/tests/ice40/macc.v
deleted file mode 100644
index 6f68e7500..000000000
--- a/tests/ice40/macc.v
+++ /dev/null
@@ -1,47 +0,0 @@
-/*
-Example from: https://www.latticesemi.com/-/media/LatticeSemi/Documents/UserManuals/EI/iCEcube201701UserGuide.ashx?document_id=52071 [p. 77].
-*/
-module top(clk,a,b,c,set);
-parameter A_WIDTH = 6 /*4*/;
-parameter B_WIDTH = 6 /*3*/;
-input set;
-input clk;
-input signed [(A_WIDTH - 1):0] a;
-input signed [(B_WIDTH - 1):0] b;
-output signed [(A_WIDTH + B_WIDTH - 1):0] c;
-reg [(A_WIDTH + B_WIDTH - 1):0] reg_tmp_c;
-assign c = reg_tmp_c;
-always @(posedge clk)
-begin
-    if(set)
-    begin
-        reg_tmp_c <= 0;
-    end
-    else
-    begin
-        reg_tmp_c <= a * b + c;
-    end
-end
-endmodule
-
-module top2(clk,a,b,c,hold);
-parameter A_WIDTH = 6 /*4*/;
-parameter B_WIDTH = 6 /*3*/;
-input hold;
-input clk;
-input signed [(A_WIDTH - 1):0] a;
-input signed [(B_WIDTH - 1):0] b;
-output signed [(A_WIDTH + B_WIDTH - 1):0] c;
-reg signed [A_WIDTH-1:0] reg_a;
-reg signed [B_WIDTH-1:0] reg_b;
-reg [(A_WIDTH + B_WIDTH - 1):0] reg_tmp_c;
-assign c = reg_tmp_c;
-always @(posedge clk)
-begin
-    if (!hold) begin
-        reg_a <= a;
-        reg_b <= b;
-        reg_tmp_c <= reg_a * reg_b + c;
-    end
-end
-endmodule
diff --git a/tests/ice40/macc.ys b/tests/ice40/macc.ys
deleted file mode 100644
index fd30e79c5..000000000
--- a/tests/ice40/macc.ys
+++ /dev/null
@@ -1,25 +0,0 @@
-read_verilog macc.v
-proc
-design -save read
-
-hierarchy -top top
-equiv_opt -assert -multiclock -map +/ice40/cells_sim.v synth_ice40 -dsp # equivalency check
-design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
-cd top # Constrain all select calls below inside the top module
-select -assert-count 1 t:SB_MAC16
-select -assert-none t:SB_MAC16 %% t:* %D
-
-design -load read
-hierarchy -top top2
-
-#equiv_opt -multiclock -assert -map +/ice40/cells_sim.v synth_ice40 -dsp # equivalency check
-
-equiv_opt -run :prove -multiclock -assert -map +/ice40/cells_sim.v synth_ice40 -dsp # equivalency check
-clk2fflogic
-miter -equiv -flatten -make_assert -make_outputs gold gate miter
-sat -set-init-zero -seq 4 -verify -prove-asserts -show-ports miter
-
-design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
-cd top2 # Constrain all select calls below inside the top module
-select -assert-count 1 t:SB_MAC16
-select -assert-none t:SB_MAC16 %% t:* %D
diff --git a/tests/ice40/memory.v b/tests/ice40/memory.v
deleted file mode 100644
index cb7753f7b..000000000
--- a/tests/ice40/memory.v
+++ /dev/null
@@ -1,21 +0,0 @@
-module top
-(
-	input [7:0] data_a,
-	input [6:1] addr_a,
-	input we_a, clk,
-	output reg [7:0] q_a
-);
-	// Declare the RAM variable
-	reg [7:0] ram[63:0];
-
-	// Port A
-	always @ (posedge clk)
-	begin
-		if (we_a)
-		begin
-			ram[addr_a] <= data_a;
-			q_a <= data_a;
-		end
-		q_a <= ram[addr_a];
-	end
-endmodule
diff --git a/tests/ice40/memory.ys b/tests/ice40/memory.ys
deleted file mode 100644
index a66afbae6..000000000
--- a/tests/ice40/memory.ys
+++ /dev/null
@@ -1,15 +0,0 @@
-read_verilog memory.v
-hierarchy -top top
-proc
-memory -nomap
-equiv_opt -run :prove -map +/ice40/cells_sim.v synth_ice40
-memory
-opt -full
-
-miter -equiv -flatten -make_assert -make_outputs gold gate miter
-sat -verify -prove-asserts -seq 5 -set-init-zero -show-inputs -show-outputs miter
-
-design -load postopt
-cd top
-select -assert-count 1 t:SB_RAM40_4K
-select -assert-none t:SB_RAM40_4K %% t:* %D
diff --git a/tests/ice40/mul.v b/tests/ice40/mul.v
deleted file mode 100644
index d5b48b1d7..000000000
--- a/tests/ice40/mul.v
+++ /dev/null
@@ -1,11 +0,0 @@
-module top
-(
- input [5:0] x,
- input [5:0] y,
-
- output [11:0] A,
- );
-
-assign A =  x * y;
-
-endmodule
diff --git a/tests/ice40/mul.ys b/tests/ice40/mul.ys
deleted file mode 100644
index 8a0822a84..000000000
--- a/tests/ice40/mul.ys
+++ /dev/null
@@ -1,7 +0,0 @@
-read_verilog mul.v
-hierarchy -top top
-equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 -dsp # equivalency check
-design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
-cd top # Constrain all select calls below inside the top module
-select -assert-count 1 t:SB_MAC16
-select -assert-none t:SB_MAC16 %% t:* %D
diff --git a/tests/ice40/mux.v b/tests/ice40/mux.v
deleted file mode 100644
index 0814b733e..000000000
--- a/tests/ice40/mux.v
+++ /dev/null
@@ -1,100 +0,0 @@
-module mux2 (S,A,B,Y);
-    input S;
-    input A,B;
-    output reg Y;
-
-    always @(*)
-		Y = (S)? B : A;
-endmodule
-
-module mux4 ( S, D, Y );
-
-input[1:0] S;
-input[3:0] D;
-output Y;
-
-reg Y;
-wire[1:0] S;
-wire[3:0] D;
-
-always @*
-begin
-    case( S )
-       0 : Y = D[0];
-       1 : Y = D[1];
-       2 : Y = D[2];
-       3 : Y = D[3];
-   endcase
-end
-
-endmodule
-
-module mux8 ( S, D, Y );
-
-input[2:0] S;
-input[7:0] D;
-output Y;
-
-reg Y;
-wire[2:0] S;
-wire[7:0] D;
-
-always @*
-begin
-   case( S )
-       0 : Y = D[0];
-       1 : Y = D[1];
-       2 : Y = D[2];
-       3 : Y = D[3];
-       4 : Y = D[4];
-       5 : Y = D[5];
-       6 : Y = D[6];
-       7 : Y = D[7];
-   endcase
-end
-
-endmodule
-
-module mux16 (D, S, Y);
- 	input  [15:0] D;
- 	input  [3:0] S;
- 	output Y;
-
-assign Y = D[S];
-
-endmodule
-
-
-module top (
-input [3:0] S,
-input [15:0] D,
-output M2,M4,M8,M16
-);
-
-mux2 u_mux2 (
-        .S (S[0]),
-        .A (D[0]),
-        .B (D[1]),
-        .Y (M2)
-    );
-
-
-mux4 u_mux4 (
-        .S (S[1:0]),
-        .D (D[3:0]),
-        .Y (M4)
-    );
-
-mux8 u_mux8 (
-        .S (S[2:0]),
-        .D (D[7:0]),
-        .Y (M8)
-    );
-
-mux16 u_mux16 (
-        .S (S[3:0]),
-        .D (D[15:0]),
-        .Y (M16)
-    );
-
-endmodule
diff --git a/tests/ice40/mux.ys b/tests/ice40/mux.ys
deleted file mode 100644
index 182b49499..000000000
--- a/tests/ice40/mux.ys
+++ /dev/null
@@ -1,8 +0,0 @@
-read_verilog mux.v
-proc
-flatten
-equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 # equivalency check
-design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
-cd top # Constrain all select calls below inside the top module
-select -assert-count 19 t:SB_LUT4
-select -assert-none t:SB_LUT4 %% t:* %D
diff --git a/tests/ice40/rom.v b/tests/ice40/rom.v
deleted file mode 100644
index 0a0f41f37..000000000
--- a/tests/ice40/rom.v
+++ /dev/null
@@ -1,18 +0,0 @@
-/*
-Example from: https://www.latticesemi.com/-/media/LatticeSemi/Documents/UserManuals/EI/iCEcube201701UserGuide.ashx?document_id=52071 [p. 74].
-*/
-module top(data, addr);
-output [3:0] data;
-input [4:0] addr;
-always @(addr) begin
-case (addr)
-0 : data = 'h4;
-1 : data = 'h9;
-2 : data = 'h1;
-15 : data = 'h8;
-16 : data = 'h1;
-17 : data = 'h0;
-default : data = 'h0;
-endcase
-end
-endmodule
diff --git a/tests/ice40/rom.ys b/tests/ice40/rom.ys
deleted file mode 100644
index 41d214e2a..000000000
--- a/tests/ice40/rom.ys
+++ /dev/null
@@ -1,8 +0,0 @@
-read_verilog rom.v
-proc
-flatten
-equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 # equivalency check
-design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
-cd top # Constrain all select calls below inside the top module
-select -assert-count 5 t:SB_LUT4
-select -assert-none t:SB_LUT4 %% t:* %D
diff --git a/tests/ice40/run-test.sh b/tests/ice40/run-test.sh
deleted file mode 100755
index 46716f9a0..000000000
--- a/tests/ice40/run-test.sh
+++ /dev/null
@@ -1,20 +0,0 @@
-#!/usr/bin/env bash
-set -e
-{
-echo "all::"
-for x in *.ys; do
-	echo "all:: run-$x"
-	echo "run-$x:"
-	echo "	@echo 'Running $x..'"
-	echo "	@../../yosys -ql ${x%.ys}.log -w 'Yosys has only limited support for tri-state logic at the moment.' $x"
-done
-for s in *.sh; do
-	if [ "$s" != "run-test.sh" ]; then
-		echo "all:: run-$s"
-		echo "run-$s:"
-		echo "	@echo 'Running $s..'"
-		echo "	@bash $s"
-	fi
-done
-} > run-test.mk
-exec ${MAKE:-make} -f run-test.mk
diff --git a/tests/ice40/shifter.v b/tests/ice40/shifter.v
deleted file mode 100644
index c55632552..000000000
--- a/tests/ice40/shifter.v
+++ /dev/null
@@ -1,22 +0,0 @@
-module top    (
-out,
-clk,
-in
-);
-    output [7:0] out;
-    input signed clk, in;
-    reg signed [7:0] out = 0;
-
-    always @(posedge clk)
-	begin
-`ifndef BUG
-		out    <= out >> 1;
-		out[7] <= in;
-`else
-
-		out    <= out << 1;
-		out[7] <= in;
-`endif
-	end
-
-endmodule
diff --git a/tests/ice40/shifter.ys b/tests/ice40/shifter.ys
deleted file mode 100644
index 47d95d298..000000000
--- a/tests/ice40/shifter.ys
+++ /dev/null
@@ -1,9 +0,0 @@
-read_verilog shifter.v
-hierarchy -top top
-proc
-flatten
-equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 # equivalency check
-design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
-cd top # Constrain all select calls below inside the top module
-select -assert-count 8 t:SB_DFF
-select -assert-none t:SB_DFF %% t:* %D
diff --git a/tests/ice40/tribuf.v b/tests/ice40/tribuf.v
deleted file mode 100644
index 870a02584..000000000
--- a/tests/ice40/tribuf.v
+++ /dev/null
@@ -1,23 +0,0 @@
-module tristate (en, i, o);
-    input en;
-    input i;
-    output o;
-
-	assign o = en ? i : 1'bz;
-
-endmodule
-
-
-module top (
-input en,
-input a,
-output b
-);
-
-tristate u_tri (
-        .en (en ),
-        .i (a ),
-        .o (b )
-    );
-
-endmodule
diff --git a/tests/ice40/tribuf.ys b/tests/ice40/tribuf.ys
deleted file mode 100644
index d1e1b3108..000000000
--- a/tests/ice40/tribuf.ys
+++ /dev/null
@@ -1,9 +0,0 @@
-read_verilog tribuf.v
-hierarchy -top top
-proc
-flatten
-equiv_opt -assert -map +/ice40/cells_sim.v -map +/simcells.v synth_ice40 # equivalency check
-design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
-cd top # Constrain all select calls below inside the top module
-select -assert-count 1 t:$_TBUF_
-select -assert-none t:$_TBUF_ %% t:* %D
diff --git a/tests/ice40/wrapcarry.ys b/tests/ice40/wrapcarry.ys
deleted file mode 100644
index 10c029e68..000000000
--- a/tests/ice40/wrapcarry.ys
+++ /dev/null
@@ -1,22 +0,0 @@
-read_verilog <<EOT
-module top(input A, B, CI, output O, CO);
-	SB_CARRY carry (
-		.I0(A),
-		.I1(B),
-		.CI(CI),
-		.CO(CO)
-	);
-	SB_LUT4 #(
-		.LUT_INIT(16'b 0110_1001_1001_0110)
-	) adder (
-		.I0(1'b0),
-		.I1(A),
-		.I2(B),
-		.I3(1'b0),
-		.O(O)
-	);
-endmodule
-EOT
-
-ice40_wrapcarry
-select -assert-count 1 t:$__ICE40_CARRY_WRAPPER
-- 
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