From 536ae16c3abcf3fef1dd14df8733bf51fa1bce1a Mon Sep 17 00:00:00 2001
From: Udi Finkelstein <github@udifink.com>
Date: Thu, 25 Oct 2018 02:37:56 +0300
Subject: Rename the generic "Syntax error" message from the
 Verilog/SystemVerilog parser into unique, meaningful info on the error. Also
 add 13 compilation examples that triggers each of these messages.

---
 tests/errors/syntax_err12.v | 7 +++++++
 1 file changed, 7 insertions(+)
 create mode 100644 tests/errors/syntax_err12.v

(limited to 'tests/errors/syntax_err12.v')

diff --git a/tests/errors/syntax_err12.v b/tests/errors/syntax_err12.v
new file mode 100644
index 000000000..f9b5d5b0b
--- /dev/null
+++ b/tests/errors/syntax_err12.v
@@ -0,0 +1,7 @@
+interface iface;
+endinterface
+
+module a (
+  iface x = 1'b0
+);
+endmodule
-- 
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