From d6e4d3f1ba9191f0f3bbed2d47a9ef80b8614e77 Mon Sep 17 00:00:00 2001 From: Claire Xenia Wolf Date: Fri, 10 Dec 2021 00:22:37 +0100 Subject: Fix the tests we just broke Signed-off-by: Claire Xenia Wolf --- tests/bram/run-single.sh | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'tests/bram') diff --git a/tests/bram/run-single.sh b/tests/bram/run-single.sh index 98a45b613..429a79e3c 100644 --- a/tests/bram/run-single.sh +++ b/tests/bram/run-single.sh @@ -1,6 +1,6 @@ #!/bin/bash set -e -../../yosys -qq -p "proc; opt; memory -nomap -bram temp/brams_${2}.txt; opt -fast -full" \ +../../yosys -qq -f verilog -p "proc; opt; memory -nomap -bram temp/brams_${2}.txt; opt -fast -full" \ -l temp/synth_${1}_${2}.log -o temp/synth_${1}_${2}.v temp/brams_${1}.v iverilog -Dvcd_file=\"temp/tb_${1}_${2}.vcd\" -DSIMLIB_MEMDELAY=1 -o temp/tb_${1}_${2}.tb temp/brams_${1}_tb.v \ temp/brams_${1}_ref.v temp/synth_${1}_${2}.v temp/brams_${2}.v ../../techlibs/common/simlib.v -- cgit v1.2.3