From ea79e16bab7abf374f371626297e65c81e00a068 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Marcelina=20Ko=C5=9Bcielnicka?= <mwk@0x04.net>
Date: Mon, 25 Jan 2021 13:01:18 +0100
Subject: xilinx_dffopt: Don't crash on missing IS_*_INVERTED.

The presence of IS_*_INVERTED on FD* cells follows Vivado, which
apparently has been decided by a dice roll.  Just assume false if the
parameter doesn't exist.

Fixes #2559.
---
 tests/arch/xilinx/mux.ys           |  3 ++-
 tests/arch/xilinx/xilinx_dffopt.ys | 46 ++++++++++++++++++++++++++++++++++++++
 2 files changed, 48 insertions(+), 1 deletion(-)

(limited to 'tests/arch')

diff --git a/tests/arch/xilinx/mux.ys b/tests/arch/xilinx/mux.ys
index 1b2788448..c2a23de6d 100644
--- a/tests/arch/xilinx/mux.ys
+++ b/tests/arch/xilinx/mux.ys
@@ -40,10 +40,11 @@ proc
 equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx -noiopad # equivalency check
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
 cd mux16 # Constrain all select calls below inside the top module
+select -assert-max 2 t:LUT3
 select -assert-max 2 t:LUT4
 select -assert-min 4 t:LUT6
 select -assert-max 7 t:LUT6
 select -assert-max 2 t:MUXF7
 dump
 
-select -assert-none t:LUT6 t:LUT4 t:MUXF7 %% t:* %D
+select -assert-none t:LUT6 t:LUT4 t:LUT3 t:MUXF7 %% t:* %D
diff --git a/tests/arch/xilinx/xilinx_dffopt.ys b/tests/arch/xilinx/xilinx_dffopt.ys
index 2c729832e..c09699411 100644
--- a/tests/arch/xilinx/xilinx_dffopt.ys
+++ b/tests/arch/xilinx/xilinx_dffopt.ys
@@ -223,3 +223,49 @@ select -assert-count 1 t:LUT2
 select -assert-none t:FDRSE t:LUT4 t:LUT2 %% t:* %D
 
 design -reset
+
+
+read_verilog << EOT
+
+// FDSE_1, mergeable CE and S, but CE only not worth it.
+
+module t0 (...);
+input wire clk;
+input wire [7:0] i;
+output wire [7:0] o;
+
+wire [7:0] tmp ;
+
+LUT2 #(.INIT(4'h6)) lut0 (.I0(i[0]), .I1(i[1]), .O(tmp[0]));
+LUT2 #(.INIT(4'h6)) lut1 (.I0(i[1]), .I1(i[2]), .O(tmp[1]));
+
+FDSE_1 ff (.D(tmp[0]), .CE(i[7]), .S(tmp[1]), .Q(o[0]));
+
+endmodule
+
+EOT
+
+read_verilog -lib +/xilinx/cells_sim.v
+design -save t0
+
+equiv_opt -blacklist xilinx_dffopt_blacklist.txt -assert -map +/xilinx/cells_sim.v xilinx_dffopt
+design -load postopt
+clean
+
+cd t0
+select -assert-count 1 t:FDSE_1
+select -assert-count 1 t:LUT5
+select -assert-none t:FDSE_1 t:LUT5 %% t:* %D
+
+design -load t0
+
+equiv_opt -blacklist xilinx_dffopt_blacklist.txt -assert -map +/xilinx/cells_sim.v xilinx_dffopt -lut4
+design -load postopt
+clean
+
+cd t0
+select -assert-count 1 t:FDSE_1
+select -assert-count 2 t:LUT2
+select -assert-none t:FDSE_1 t:LUT2 %% t:* %D
+
+design -reset
-- 
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