From a59016b146e91311324bc87f9a9437d7ff31d9f2 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Tue, 31 Dec 2019 18:40:11 -0800
Subject: Fix warnings

---
 tests/arch/ice40/mul.ys | 2 +-
 tests/arch/ice40/rom.v  | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

(limited to 'tests/arch')

diff --git a/tests/arch/ice40/mul.ys b/tests/arch/ice40/mul.ys
index 9891b77d6..b8c3eb941 100644
--- a/tests/arch/ice40/mul.ys
+++ b/tests/arch/ice40/mul.ys
@@ -1,6 +1,6 @@
 read_verilog ../common/mul.v
 hierarchy -top top
-equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 -dsp # equivalency check
+equiv_opt -assert -multiclock -map +/ice40/cells_sim.v synth_ice40 -dsp # equivalency check
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
 cd top # Constrain all select calls below inside the top module
 select -assert-count 1 t:SB_MAC16
diff --git a/tests/arch/ice40/rom.v b/tests/arch/ice40/rom.v
index 0a0f41f37..c4c677c1e 100644
--- a/tests/arch/ice40/rom.v
+++ b/tests/arch/ice40/rom.v
@@ -2,7 +2,7 @@
 Example from: https://www.latticesemi.com/-/media/LatticeSemi/Documents/UserManuals/EI/iCEcube201701UserGuide.ashx?document_id=52071 [p. 74].
 */
 module top(data, addr);
-output [3:0] data;
+output reg [3:0] data;
 input [4:0] addr;
 always @(addr) begin
 case (addr)
-- 
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