From 87e21b0122bd682db8aeffae3e1ac503c9cea2d2 Mon Sep 17 00:00:00 2001 From: Diego H Date: Mon, 16 Dec 2019 10:23:45 -0600 Subject: Fixing compiler warning/issues. Moving test script to the correct place --- .../common/memory_attributes/attributes_test.ys | 47 ---------------------- tests/arch/xilinx/attributes_test.ys | 47 ++++++++++++++++++++++ 2 files changed, 47 insertions(+), 47 deletions(-) delete mode 100644 tests/arch/common/memory_attributes/attributes_test.ys create mode 100644 tests/arch/xilinx/attributes_test.ys (limited to 'tests/arch') diff --git a/tests/arch/common/memory_attributes/attributes_test.ys b/tests/arch/common/memory_attributes/attributes_test.ys deleted file mode 100644 index 4e06a35e7..000000000 --- a/tests/arch/common/memory_attributes/attributes_test.ys +++ /dev/null @@ -1,47 +0,0 @@ -# Check that blockram memory without parameters is not modified -read_verilog attributes_test.v -hierarchy -top block_ram -synth_xilinx -top block_ram -cd block_ram # Constrain all select calls below inside the top module -select -assert-count 1 t:RAMB18E1 - -# Check that distributed memory without parameters is not modified -design -reset -read_verilog attributes_test.v -hierarchy -top distributed_ram -synth_xilinx -top distributed_ram -cd distributed_ram # Constrain all select calls below inside the top module -select -assert-count 8 t:RAM32X1D - -# Set ram_style distributed to blockram memory; will be implemented as distributed -design -reset -read_verilog attributes_test.v -prep -setattr -mod -set ram_style "distributed" block_ram -synth_xilinx -top block_ram -cd block_ram # Constrain all select calls below inside the top module -select -assert-count 32 t:RAM128X1D - -# Set synthesis, logic_block to blockram memory; will be implemented as distributed -design -reset -read_verilog attributes_test.v -prep -setattr -mod -set logic_block 1 block_ram -synth_xilinx -top block_ram -cd block_ram # Constrain all select calls below inside the top module -select -assert-count 0 t:RAMB18E1 -select -assert-count 32 t:RAM128X1D - -# Set ram_style block to a distributed memory; will be implemented as blockram -design -reset -read_verilog attributes_test.v -synth_xilinx -top distributed_ram_manual -cd distributed_ram_manual # Constrain all select calls below inside the top module -select -assert-count 1 t:RAMB18E1 - -# Set synthesis, ram_block block to a distributed memory; will be implemented as blockram -design -reset -read_verilog attributes_test.v -synth_xilinx -top distributed_ram_manual_syn -cd distributed_ram_manual_syn # Constrain all select calls below inside the top module -select -assert-count 1 t:RAMB18E1 diff --git a/tests/arch/xilinx/attributes_test.ys b/tests/arch/xilinx/attributes_test.ys new file mode 100644 index 000000000..4c881b280 --- /dev/null +++ b/tests/arch/xilinx/attributes_test.ys @@ -0,0 +1,47 @@ +# Check that blockram memory without parameters is not modified +read_verilog ../common/memory_attributes/attributes_test.v +hierarchy -top block_ram +synth_xilinx -top block_ram +cd block_ram # Constrain all select calls below inside the top module +select -assert-count 1 t:RAMB18E1 + +# Check that distributed memory without parameters is not modified +design -reset +read_verilog ../common/memory_attributes/attributes_test.v +hierarchy -top distributed_ram +synth_xilinx -top distributed_ram +cd distributed_ram # Constrain all select calls below inside the top module +select -assert-count 8 t:RAM32X1D + +# Set ram_style distributed to blockram memory; will be implemented as distributed +design -reset +read_verilog ../common/memory_attributes/attributes_test.v +prep +setattr -mod -set ram_style "distributed" block_ram +synth_xilinx -top block_ram +cd block_ram # Constrain all select calls below inside the top module +select -assert-count 32 t:RAM128X1D + +# Set synthesis, logic_block to blockram memory; will be implemented as distributed +design -reset +read_verilog ../common/memory_attributes/attributes_test.v +prep +setattr -mod -set logic_block 1 block_ram +synth_xilinx -top block_ram +cd block_ram # Constrain all select calls below inside the top module +select -assert-count 0 t:RAMB18E1 +select -assert-count 32 t:RAM128X1D + +# Set ram_style block to a distributed memory; will be implemented as blockram +design -reset +read_verilog ../common/memory_attributes/attributes_test.v +synth_xilinx -top distributed_ram_manual +cd distributed_ram_manual # Constrain all select calls below inside the top module +select -assert-count 1 t:RAMB18E1 + +# Set synthesis, ram_block block to a distributed memory; will be implemented as blockram +design -reset +read_verilog ../common/memory_attributes/attributes_test.v +synth_xilinx -top distributed_ram_manual_syn +cd distributed_ram_manual_syn # Constrain all select calls below inside the top module +select -assert-count 1 t:RAMB18E1 -- cgit v1.2.3