From bdc316db50cd8b68ef096386a89c1b38793784e1 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Fri, 14 Oct 2016 15:24:03 +0200 Subject: Added $anyseq cell type --- techlibs/common/simlib.v | 12 ++++++++++++ 1 file changed, 12 insertions(+) (limited to 'techlibs') diff --git a/techlibs/common/simlib.v b/techlibs/common/simlib.v index b10c858f2..2c4db1ac6 100644 --- a/techlibs/common/simlib.v +++ b/techlibs/common/simlib.v @@ -1334,6 +1334,18 @@ endmodule // -------------------------------------------------------- +module \$anyseq (Y); + +parameter WIDTH = 0; + +output [WIDTH-1:0] Y; + +assign Y = 'bx; + +endmodule + +// -------------------------------------------------------- + module \$equiv (A, B, Y); input A, B; -- cgit v1.2.3