From 1ecf6aee9b331efebeca1bd95a3d5125abf8da50 Mon Sep 17 00:00:00 2001 From: Miodrag Milanovic Date: Wed, 21 Sep 2022 15:46:43 +0200 Subject: Test fixes for latest iverilog --- techlibs/achronix/speedster22i/cells_sim.v | 3 +-- techlibs/sf2/cells_sim.v | 2 +- 2 files changed, 2 insertions(+), 3 deletions(-) (limited to 'techlibs') diff --git a/techlibs/achronix/speedster22i/cells_sim.v b/techlibs/achronix/speedster22i/cells_sim.v index 6c87adb94..fc15e0966 100644 --- a/techlibs/achronix/speedster22i/cells_sim.v +++ b/techlibs/achronix/speedster22i/cells_sim.v @@ -68,9 +68,8 @@ end assign dout = combout_rt & 1'b1; endmodule -module DFF (output q, +module DFF (output reg q, input d, ck); - reg q; always @(posedge ck) q <= d; diff --git a/techlibs/sf2/cells_sim.v b/techlibs/sf2/cells_sim.v index 02335404b..b5438e44c 100644 --- a/techlibs/sf2/cells_sim.v +++ b/techlibs/sf2/cells_sim.v @@ -162,7 +162,7 @@ module ARI1 ( wire F1 = INIT[8 + Fsel]; wire Yout = A ? F1 : F0; assign Y = Yout; - wire S = FCI ^ Yout; + assign S = FCI ^ Yout; wire G = INIT[16] ? (INIT[17] ? F1 : F0) : INIT[17]; wire P = INIT[19] ? 1'b1 : (INIT[18] ? Yout : 1'b0); assign FCO = P ? FCI : G; -- cgit v1.2.3