From 3fc474aa73cb447f22e9ca35687b054102f4be32 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Tue, 9 Apr 2019 10:06:44 -0700
Subject: Add support for synth_xilinx -abc9 and ignore abc9 -dress opt

---
 techlibs/xilinx/synth_xilinx.cc | 10 +++++++++-
 1 file changed, 9 insertions(+), 1 deletion(-)

(limited to 'techlibs')

diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc
index 805ae8e6e..090bcce85 100644
--- a/techlibs/xilinx/synth_xilinx.cc
+++ b/techlibs/xilinx/synth_xilinx.cc
@@ -80,6 +80,9 @@ struct SynthXilinxPass : public Pass
 		log("    -retime\n");
 		log("        run 'abc' with -dff option\n");
 		log("\n");
+		log("    -abc9\n");
+		log("        use abc9 instead of abc\n");
+		log("\n");
 		log("\n");
 		log("The following commands are executed by this synthesis command:\n");
 		log("\n");
@@ -142,6 +145,7 @@ struct SynthXilinxPass : public Pass
 		std::string edif_file;
 		std::string blif_file;
 		std::string run_from, run_to;
+		std::string abc = "abc";
 		bool flatten = false;
 		bool retime = false;
 		bool vpr = false;
@@ -191,6 +195,10 @@ struct SynthXilinxPass : public Pass
 				nodram = true;
 				continue;
 			}
+			if (args[argidx] == "-abc9") {
+				abc = "abc9";
+				continue;
+			}
 			break;
 		}
 		extra_args(args, argidx, design);
@@ -267,7 +275,7 @@ struct SynthXilinxPass : public Pass
 
 		if (check_label(active, run_from, run_to, "map_luts"))
 		{
-			Pass::call(design, "abc -luts 2:2,3,6:5,10,20" + string(retime ? " -dff" : ""));
+			Pass::call(design, abc + " -luts 2:2,3,6:5,10,20" + string(retime ? " -dff" : ""));
 			Pass::call(design, "clean");
 			Pass::call(design, "techmap -map +/xilinx/lut_map.v");
 		}
-- 
cgit v1.2.3


From 2ae26b986cd550e4d3ce4dc5c4f7235144a6f83c Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Tue, 9 Apr 2019 10:58:58 -0700
Subject: Add techlibs/xilinx/cells.box

---
 techlibs/xilinx/Makefile.inc | 1 +
 techlibs/xilinx/cells.box    | 5 +++++
 2 files changed, 6 insertions(+)
 create mode 100644 techlibs/xilinx/cells.box

(limited to 'techlibs')

diff --git a/techlibs/xilinx/Makefile.inc b/techlibs/xilinx/Makefile.inc
index d68f03bb4..9937c0c9c 100644
--- a/techlibs/xilinx/Makefile.inc
+++ b/techlibs/xilinx/Makefile.inc
@@ -30,6 +30,7 @@ $(eval $(call add_share_file,share/xilinx,techlibs/xilinx/drams_map.v))
 $(eval $(call add_share_file,share/xilinx,techlibs/xilinx/arith_map.v))
 $(eval $(call add_share_file,share/xilinx,techlibs/xilinx/ff_map.v))
 $(eval $(call add_share_file,share/xilinx,techlibs/xilinx/lut_map.v))
+$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/cells.box))
 
 $(eval $(call add_gen_share_file,share/xilinx,techlibs/xilinx/brams_init_36.vh))
 $(eval $(call add_gen_share_file,share/xilinx,techlibs/xilinx/brams_init_32.vh))
diff --git a/techlibs/xilinx/cells.box b/techlibs/xilinx/cells.box
new file mode 100644
index 000000000..31ad4a656
--- /dev/null
+++ b/techlibs/xilinx/cells.box
@@ -0,0 +1,5 @@
+MUXF7 1 0 2 1
+1 1
+
+MUXF8 2 0 2 1
+1 1
-- 
cgit v1.2.3


From f2042fc7c43af9f43d42fdd2e8034963122ff5eb Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Tue, 9 Apr 2019 11:01:46 -0700
Subject: synth_xilinx with abc9 to use -box

---
 techlibs/xilinx/synth_xilinx.cc | 5 ++++-
 1 file changed, 4 insertions(+), 1 deletion(-)

(limited to 'techlibs')

diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc
index 090bcce85..eb37feb83 100644
--- a/techlibs/xilinx/synth_xilinx.cc
+++ b/techlibs/xilinx/synth_xilinx.cc
@@ -275,7 +275,10 @@ struct SynthXilinxPass : public Pass
 
 		if (check_label(active, run_from, run_to, "map_luts"))
 		{
-			Pass::call(design, abc + " -luts 2:2,3,6:5,10,20" + string(retime ? " -dff" : ""));
+			if (abc == "abc9")
+				Pass::call(design, abc + " -luts 2:2,3,6:5,10,20 -box +/xilinx/cells.box" + string(retime ? " -dff" : ""));
+			else
+				Pass::call(design, abc + " -luts 2:2,3,6:5,10,20" + string(retime ? " -dff" : ""));
 			Pass::call(design, "clean");
 			Pass::call(design, "techmap -map +/xilinx/lut_map.v");
 		}
-- 
cgit v1.2.3


From b9e19071b8596b8d06b99cbb653325c0c9dc330f Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Tue, 9 Apr 2019 14:32:10 -0700
Subject: Add delays to cells.box

---
 techlibs/xilinx/cells.box | 16 ++++++++++++----
 1 file changed, 12 insertions(+), 4 deletions(-)

(limited to 'techlibs')

diff --git a/techlibs/xilinx/cells.box b/techlibs/xilinx/cells.box
index 31ad4a656..c8092db6e 100644
--- a/techlibs/xilinx/cells.box
+++ b/techlibs/xilinx/cells.box
@@ -1,5 +1,13 @@
-MUXF7 1 0 2 1
-1 1
+# Max delays from https://pastebin.com/v2hrcksd
+# from https://github.com/SymbiFlow/prjxray/pull/706#issuecomment-479380321
 
-MUXF8 2 0 2 1
-1 1
+# F7BMUX slower than F7AMUX
+# Inputs: 0 1 S0
+# Outputs: OUT
+F7BMUX 1 0 3 1
+217 223 296
+
+# Inputs: 0 1 S0
+# Outputs: OUT
+MUXF8 2 0 3 1
+104 94 273
-- 
cgit v1.2.3


From fd88ab5c834a45f4828a03fe7722b321e5f7c032 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Tue, 9 Apr 2019 14:32:39 -0700
Subject: synth_xilinx to call abc with -lut +/xilinx/cells.lut

---
 techlibs/xilinx/synth_xilinx.cc | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

(limited to 'techlibs')

diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc
index eb37feb83..e2a2dfeeb 100644
--- a/techlibs/xilinx/synth_xilinx.cc
+++ b/techlibs/xilinx/synth_xilinx.cc
@@ -276,9 +276,9 @@ struct SynthXilinxPass : public Pass
 		if (check_label(active, run_from, run_to, "map_luts"))
 		{
 			if (abc == "abc9")
-				Pass::call(design, abc + " -luts 2:2,3,6:5,10,20 -box +/xilinx/cells.box" + string(retime ? " -dff" : ""));
+				Pass::call(design, abc + " -lut +/xilinx/cells.lut -box +/xilinx/cells.box" + string(retime ? " -dff" : ""));
 			else
-				Pass::call(design, abc + " -luts 2:2,3,6:5,10,20" + string(retime ? " -dff" : ""));
+				Pass::call(design, abc + " -lut +/xilinx/cells.lut" + string(retime ? " -dff" : ""));
 			Pass::call(design, "clean");
 			Pass::call(design, "techmap -map +/xilinx/lut_map.v");
 		}
-- 
cgit v1.2.3


From 3e368593eb22d16de60c44ea721ca146082d3472 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Tue, 9 Apr 2019 14:33:37 -0700
Subject: Add cells.lut to techlibs/xilinx/

---
 techlibs/xilinx/Makefile.inc |  1 +
 techlibs/xilinx/cells.lut    | 15 +++++++++++++++
 2 files changed, 16 insertions(+)
 create mode 100644 techlibs/xilinx/cells.lut

(limited to 'techlibs')

diff --git a/techlibs/xilinx/Makefile.inc b/techlibs/xilinx/Makefile.inc
index 9937c0c9c..432bb0770 100644
--- a/techlibs/xilinx/Makefile.inc
+++ b/techlibs/xilinx/Makefile.inc
@@ -31,6 +31,7 @@ $(eval $(call add_share_file,share/xilinx,techlibs/xilinx/arith_map.v))
 $(eval $(call add_share_file,share/xilinx,techlibs/xilinx/ff_map.v))
 $(eval $(call add_share_file,share/xilinx,techlibs/xilinx/lut_map.v))
 $(eval $(call add_share_file,share/xilinx,techlibs/xilinx/cells.box))
+$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/cells.lut))
 
 $(eval $(call add_gen_share_file,share/xilinx,techlibs/xilinx/brams_init_36.vh))
 $(eval $(call add_gen_share_file,share/xilinx,techlibs/xilinx/brams_init_32.vh))
diff --git a/techlibs/xilinx/cells.lut b/techlibs/xilinx/cells.lut
new file mode 100644
index 000000000..3f3b69a8e
--- /dev/null
+++ b/techlibs/xilinx/cells.lut
@@ -0,0 +1,15 @@
+# Max delays from https://pastebin.com/v2hrcksd 
+# from https://github.com/SymbiFlow/prjxray/pull/706#issuecomment-479380321
+
+# Since LUT delays are pushed onto the fabric as routing delays,
+# assume each input costs +100ps
+
+# K	area	delay
+1 	11	224
+2	12	224 324
+3	13	224 324 424
+4	14	224 324 424 524
+5	15	224 324 424 524 624
+6	20	224 324 424 524 624 724
+7	40	224 324 424 524 624 724 1020
+8	80	224 324 424 524 624 724 1020 1293
-- 
cgit v1.2.3


From 4dac9818bde02222f951c25ada5f3fd651ea4e36 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Wed, 10 Apr 2019 08:49:39 -0700
Subject: Update LUT delays

---
 techlibs/xilinx/cells.lut | 19 ++++++++-----------
 1 file changed, 8 insertions(+), 11 deletions(-)

(limited to 'techlibs')

diff --git a/techlibs/xilinx/cells.lut b/techlibs/xilinx/cells.lut
index 3f3b69a8e..a1d9b9c42 100644
--- a/techlibs/xilinx/cells.lut
+++ b/techlibs/xilinx/cells.lut
@@ -1,15 +1,12 @@
 # Max delays from https://pastebin.com/v2hrcksd 
 # from https://github.com/SymbiFlow/prjxray/pull/706#issuecomment-479380321
 
-# Since LUT delays are pushed onto the fabric as routing delays,
-# assume each input costs +100ps
-
 # K	area	delay
-1 	11	224
-2	12	224 324
-3	13	224 324 424
-4	14	224 324 424 524
-5	15	224 324 424 524 624
-6	20	224 324 424 524 624 724
-7	40	224 324 424 524 624 724 1020
-8	80	224 324 424 524 624 724 1020 1293
+1 	11	624
+2	12	624
+3	13	624
+4	14	624
+5	15	624
+6	20	724
+7	40	1020
+8	80	1293
-- 
cgit v1.2.3


From e0b46eb4cbadafa5f03a5337f761d0ede2b993fa Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Wed, 10 Apr 2019 08:49:55 -0700
Subject: WIP for $shiftx to wide mux

---
 techlibs/xilinx/cells_map.v | 64 ++++++++++++++++++++++++++++++++++++++++++++-
 1 file changed, 63 insertions(+), 1 deletion(-)

(limited to 'techlibs')

diff --git a/techlibs/xilinx/cells_map.v b/techlibs/xilinx/cells_map.v
index d5801c0fc..4f5c7ff18 100644
--- a/techlibs/xilinx/cells_map.v
+++ b/techlibs/xilinx/cells_map.v
@@ -17,4 +17,66 @@
  *
  */
 
-// Empty for now
+module \$shiftx (A, B, Y);
+  parameter A_SIGNED = 0;
+  parameter B_SIGNED = 0;
+  parameter A_WIDTH = 1;
+  parameter B_WIDTH = 1;
+  parameter Y_WIDTH = 1;
+
+  input [A_WIDTH-1:0] A;
+  input [B_WIDTH-1:0] B;
+  output [Y_WIDTH-1:0] Y;
+
+  generate
+    genvar i;
+    if (B_WIDTH < 3) begin
+      reg _TECHMAP_FAIL_;
+      assign _TECHMAP_FAIL_ = 1;
+    end
+    else if (B_WIDTH == 3) begin
+      localparam a_width0 = Y_WIDTH * (2 ** (B_WIDTH-1));
+      localparam a_widthN = A_WIDTH - a_width0;
+      wire [Y_WIDTH-1:0] T0, T1;
+      \$shiftx  #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(a_width0), .B_WIDTH(B_WIDTH-1),        .Y_WIDTH(Y_WIDTH)) fpga_shiftx      (.A(A[a_width0-1:0]),       .B(B[B_WIDTH-2:0]), .Y(T0));
+      \$shiftx  #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(a_widthN), .B_WIDTH($clog2(a_widthN)), .Y_WIDTH(Y_WIDTH)) fpga_shiftx_last (.A(A[A_WIDTH-1:a_width0]), .B(B[$clog2(a_widthN)-1:0]), .Y(T1));
+      //MUXF7 fpga_mux[Y_WIDTH-1:0] (.I0(T0), .I1(T1), .S(B[B_WIDTH-1]), .O(Y));
+      for (i = 0; i < Y_WIDTH; i++)
+        MUXF7 fpga_mux (.I0(T0[i]), .I1(T1[i]), .S(B[B_WIDTH-1]), .O(Y[i]));
+    end
+    else if (B_WIDTH == 4) begin
+      localparam a_width0 = Y_WIDTH * (2 ** (B_WIDTH-2));
+      localparam num_mux8 = A_WIDTH / a_width0;
+      localparam a_widthN = A_WIDTH - num_mux8*a_width0;
+      wire [Y_WIDTH*B_WIDTH-1:0] T;
+      wire [Y_WIDTH-1:0] T0, T1;
+      for (i = 0; i < B_WIDTH; i++)
+	if (i < num_mux8)
+          \$shiftx  #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(a_width0), .B_WIDTH(B_WIDTH-2),        .Y_WIDTH(Y_WIDTH)) fpga_shiftx      (.A(A[(i+1)*a_width0-1:i*a_width0]), .B(B[B_WIDTH-3:0]),          .Y(T[(i+1)*Y_WIDTH-1:i*Y_WIDTH]));
+        else if (i == num_mux8 && A_WIDTH > i*a_width0)
+	  \$shiftx  #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(a_widthN), .B_WIDTH($clog2(a_widthN)), .Y_WIDTH(Y_WIDTH)) fpga_shiftx_last (.A(A[A_WIDTH-1:i*a_width0]),        .B(B[$clog2(a_widthN)-1:0]), .Y(T[(i+1)*Y_WIDTH-1:i*Y_WIDTH]));
+        else
+	  assign T[(i+1)*Y_WIDTH-1:i*Y_WIDTH] = {Y_WIDTH{1'bx}};
+      for (i = 0; i < Y_WIDTH; i++) begin
+        MUXF7 fpga_mux_0 (.I0(T[i*B_WIDTH+0]), .I1(T[i*B_WIDTH+1]), .S(B[B_WIDTH-2]), .O(T0[i]));
+        MUXF7 fpga_mux_1 (.I0(T[i*B_WIDTH+2]), .I1(T[i*B_WIDTH+3]), .S(B[B_WIDTH-2]), .O(T1[i]));
+        MUXF8 fpga_mux_2 (.I0(T0[i]), .I1(T1[i]), .S(B[B_WIDTH-1]), .O(Y[i]));
+      end
+    end
+    else begin
+      localparam a_width0 = Y_WIDTH * (2 ** 4);
+      localparam num_mux16 = A_WIDTH / a_width0;
+      localparam a_widthN = A_WIDTH - num_mux16*a_width0;
+      wire [Y_WIDTH*(2**(B_WIDTH-4))-1:0] T;
+      for (i = 0; i < 2 ** (B_WIDTH-4); i++)
+	if (i < num_mux16)
+          \$shiftx  #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(a_width0), .B_WIDTH(4),                .Y_WIDTH(Y_WIDTH)) fpga_shiftx      (.A(A[(i+1)*a_width0-1:i*a_width0]), .B(B[4-1:0]),                .Y(T[(i+1)*Y_WIDTH-1:i*Y_WIDTH]));
+        else if (i == num_mux16 && a_widthN > 0) begin
+	  \$shiftx  #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(a_widthN), .B_WIDTH($clog2(a_widthN)), .Y_WIDTH(Y_WIDTH)) fpga_shiftx_last (.A(A[A_WIDTH-1:i*a_width0]),        .B(B[$clog2(a_widthN)-1:0]), .Y(T[(i+1)*Y_WIDTH-1:i*Y_WIDTH]));
+        end
+        else
+	  assign T[(i+1)*Y_WIDTH-1:i*Y_WIDTH] = {Y_WIDTH{1'bx}};
+      \$shiftx  #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(Y_WIDTH*(2**(B_WIDTH-4))), .B_WIDTH(B_WIDTH-4), .Y_WIDTH(Y_WIDTH)) fpga_shiftx (.A(T), .B(B[B_WIDTH-1:4]), .Y(Y));
+    end
+  endgenerate
+endmodule
-- 
cgit v1.2.3


From 526aef9c2a9d61721add1c5ef1f85d439bfbb61e Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Wed, 10 Apr 2019 08:50:31 -0700
Subject: Move map_cells to before map_luts

---
 techlibs/xilinx/synth_xilinx.cc | 23 ++++++++++++-----------
 1 file changed, 12 insertions(+), 11 deletions(-)

(limited to 'techlibs')

diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc
index e2a2dfeeb..6d3999ae0 100644
--- a/techlibs/xilinx/synth_xilinx.cc
+++ b/techlibs/xilinx/synth_xilinx.cc
@@ -264,33 +264,34 @@ struct SynthXilinxPass : public Pass
 			Pass::call(design, "opt -full");
 
 			if (vpr) {
-				Pass::call(design, "techmap -map +/techmap.v -map +/xilinx/arith_map.v -map +/xilinx/ff_map.v -D _EXPLICIT_CARRY");
+				Pass::call(design, "techmap -map +/xilinx/arith_map.v -map +/xilinx/ff_map.v -D _EXPLICIT_CARRY");
 			} else {
-				Pass::call(design, "techmap -map +/techmap.v -map +/xilinx/arith_map.v -map +/xilinx/ff_map.v");
+				Pass::call(design, "techmap -map +/xilinx/arith_map.v -map +/xilinx/ff_map.v");
 			}
 
 			Pass::call(design, "hierarchy -check");
 			Pass::call(design, "opt -fast");
 		}
 
+		if (check_label(active, run_from, run_to, "map_cells"))
+		{
+			Pass::call(design, "techmap -map +/xilinx/cells_map.v");
+			Pass::call(design, "dffinit -ff FDRE Q INIT -ff FDCE Q INIT -ff FDPE Q INIT -ff FDSE Q INIT "
+					"-ff FDRE_1 Q INIT -ff FDCE_1 Q INIT -ff FDPE_1 Q INIT -ff FDSE_1 Q INIT");
+			Pass::call(design, "clean");
+		}
+
 		if (check_label(active, run_from, run_to, "map_luts"))
 		{
+			Pass::call(design, "techmap -map +/techmap.v");
 			if (abc == "abc9")
 				Pass::call(design, abc + " -lut +/xilinx/cells.lut -box +/xilinx/cells.box" + string(retime ? " -dff" : ""));
 			else
-				Pass::call(design, abc + " -lut +/xilinx/cells.lut" + string(retime ? " -dff" : ""));
+				Pass::call(design, abc + " -luts 2:2,3,6:5,10,20" + string(retime ? " -dff" : ""));
 			Pass::call(design, "clean");
 			Pass::call(design, "techmap -map +/xilinx/lut_map.v");
 		}
 
-		if (check_label(active, run_from, run_to, "map_cells"))
-		{
-			Pass::call(design, "techmap -map +/xilinx/cells_map.v");
-			Pass::call(design, "dffinit -ff FDRE Q INIT -ff FDCE Q INIT -ff FDPE Q INIT -ff FDSE Q INIT "
-					"-ff FDRE_1 Q INIT -ff FDCE_1 Q INIT -ff FDPE_1 Q INIT -ff FDSE_1 Q INIT");
-			Pass::call(design, "clean");
-		}
-
 		if (check_label(active, run_from, run_to, "check"))
 		{
 			Pass::call(design, "hierarchy -check");
-- 
cgit v1.2.3


From 1ec949d5edfb6b13b8bf412763ae272a47fec894 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Wed, 10 Apr 2019 09:02:42 -0700
Subject: Tidy up

---
 techlibs/xilinx/cells_map.v | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'techlibs')

diff --git a/techlibs/xilinx/cells_map.v b/techlibs/xilinx/cells_map.v
index 4f5c7ff18..ff33cf8ff 100644
--- a/techlibs/xilinx/cells_map.v
+++ b/techlibs/xilinx/cells_map.v
@@ -53,7 +53,7 @@ module \$shiftx (A, B, Y);
       for (i = 0; i < B_WIDTH; i++)
 	if (i < num_mux8)
           \$shiftx  #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(a_width0), .B_WIDTH(B_WIDTH-2),        .Y_WIDTH(Y_WIDTH)) fpga_shiftx      (.A(A[(i+1)*a_width0-1:i*a_width0]), .B(B[B_WIDTH-3:0]),          .Y(T[(i+1)*Y_WIDTH-1:i*Y_WIDTH]));
-        else if (i == num_mux8 && A_WIDTH > i*a_width0)
+        else if (i == num_mux8 && a_widthN > 0)
 	  \$shiftx  #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(a_widthN), .B_WIDTH($clog2(a_widthN)), .Y_WIDTH(Y_WIDTH)) fpga_shiftx_last (.A(A[A_WIDTH-1:i*a_width0]),        .B(B[$clog2(a_widthN)-1:0]), .Y(T[(i+1)*Y_WIDTH-1:i*Y_WIDTH]));
         else
 	  assign T[(i+1)*Y_WIDTH-1:i*Y_WIDTH] = {Y_WIDTH{1'bx}};
-- 
cgit v1.2.3


From 17a02df05cb04bf9c597564b130e556f186154f3 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Wed, 10 Apr 2019 12:36:06 -0700
Subject: ff_map.v after abc

---
 techlibs/xilinx/synth_xilinx.cc | 10 +++++-----
 1 file changed, 5 insertions(+), 5 deletions(-)

(limited to 'techlibs')

diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc
index 6d3999ae0..9178182fb 100644
--- a/techlibs/xilinx/synth_xilinx.cc
+++ b/techlibs/xilinx/synth_xilinx.cc
@@ -264,9 +264,9 @@ struct SynthXilinxPass : public Pass
 			Pass::call(design, "opt -full");
 
 			if (vpr) {
-				Pass::call(design, "techmap -map +/xilinx/arith_map.v -map +/xilinx/ff_map.v -D _EXPLICIT_CARRY");
+				Pass::call(design, "techmap -map +/xilinx/arith_map.v -D _EXPLICIT_CARRY");
 			} else {
-				Pass::call(design, "techmap -map +/xilinx/arith_map.v -map +/xilinx/ff_map.v");
+				Pass::call(design, "techmap -map +/xilinx/arith_map.v");
 			}
 
 			Pass::call(design, "hierarchy -check");
@@ -276,8 +276,6 @@ struct SynthXilinxPass : public Pass
 		if (check_label(active, run_from, run_to, "map_cells"))
 		{
 			Pass::call(design, "techmap -map +/xilinx/cells_map.v");
-			Pass::call(design, "dffinit -ff FDRE Q INIT -ff FDCE Q INIT -ff FDPE Q INIT -ff FDSE Q INIT "
-					"-ff FDRE_1 Q INIT -ff FDCE_1 Q INIT -ff FDPE_1 Q INIT -ff FDSE_1 Q INIT");
 			Pass::call(design, "clean");
 		}
 
@@ -289,7 +287,9 @@ struct SynthXilinxPass : public Pass
 			else
 				Pass::call(design, abc + " -luts 2:2,3,6:5,10,20" + string(retime ? " -dff" : ""));
 			Pass::call(design, "clean");
-			Pass::call(design, "techmap -map +/xilinx/lut_map.v");
+			Pass::call(design, "techmap -map +/xilinx/lut_map.v -map +/xilinx/ff_map.v");
+			Pass::call(design, "dffinit -ff FDRE Q INIT -ff FDCE Q INIT -ff FDPE Q INIT -ff FDSE Q INIT "
+					"-ff FDRE_1 Q INIT -ff FDCE_1 Q INIT -ff FDPE_1 Q INIT -ff FDSE_1 Q INIT");
 		}
 
 		if (check_label(active, run_from, run_to, "check"))
-- 
cgit v1.2.3


From 32561332b21b7b072fa6619f0bbb29a69cb30f33 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Wed, 10 Apr 2019 14:48:58 -0700
Subject: Update doc for synth_xilinx

---
 techlibs/xilinx/synth_xilinx.cc | 15 ++++++++-------
 1 file changed, 8 insertions(+), 7 deletions(-)

(limited to 'techlibs')

diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc
index 9178182fb..10902a560 100644
--- a/techlibs/xilinx/synth_xilinx.cc
+++ b/techlibs/xilinx/synth_xilinx.cc
@@ -113,19 +113,20 @@ struct SynthXilinxPass : public Pass
 		log("        dffsr2dff\n");
 		log("        dff2dffe\n");
 		log("        opt -full\n");
-		log("        techmap -map +/techmap.v -map +/xilinx/arith_map.v -map +/xilinx/ff_map.v\n");
+		log("        techmap -map +/xilinx/arith_map.v\n");
 		log("        opt -fast\n");
 		log("\n");
-		log("    map_luts:\n");
-		log("        abc -luts 2:2,3,6:5,10,20 [-dff] (without '-vpr' only!)\n");
-		log("        abc -lut 5 [-dff] (with '-vpr' only!)\n");
-		log("        clean\n");
-		log("\n");
 		log("    map_cells:\n");
 		log("        techmap -map +/xilinx/cells_map.v\n");
+		log("        clean\n");
+		log("\n");
+		log("    map_luts:\n");
+		log("        techmap -map +/techmap.v\n");
+		log("        abc -luts 2:2,3,6:5,10,20 [-dff]\n");
+		log("        clean\n");
+		log("        techmap -map +/xilinx/lut_map.v -map +/xilinx/ff_map.v\n");
 		log("        dffinit -ff FDRE   Q INIT -ff FDCE   Q INIT -ff FDPE   Q INIT -ff FDSE   Q INIT \\\n");
 		log("                -ff FDRE_1 Q INIT -ff FDCE_1 Q INIT -ff FDPE_1 Q INIT -ff FDSE_1 Q INIT\n");
-		log("        clean\n");
 		log("\n");
 		log("    check:\n");
 		log("        hierarchy -check\n");
-- 
cgit v1.2.3


From 3f5dab0d09f881d78fca73c54c20118c52b2e563 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Wed, 10 Apr 2019 14:51:10 -0700
Subject: Fix for when B_SIGNED = 1

---
 techlibs/xilinx/cells_map.v | 9 ++++++++-
 1 file changed, 8 insertions(+), 1 deletion(-)

(limited to 'techlibs')

diff --git a/techlibs/xilinx/cells_map.v b/techlibs/xilinx/cells_map.v
index ff33cf8ff..758d2ade3 100644
--- a/techlibs/xilinx/cells_map.v
+++ b/techlibs/xilinx/cells_map.v
@@ -28,12 +28,19 @@ module \$shiftx (A, B, Y);
   input [B_WIDTH-1:0] B;
   output [Y_WIDTH-1:0] Y;
 
+  parameter [B_WIDTH-1:0] _TECHMAP_CONSTMSK_B_ = 0;
+  parameter [B_WIDTH-1:0] _TECHMAP_CONSTVAL_B_ = 0;
+
   generate
     genvar i;
     if (B_WIDTH < 3) begin
-      reg _TECHMAP_FAIL_;
+      wire _TECHMAP_FAIL_;
       assign _TECHMAP_FAIL_ = 1;
     end
+    // Optimisation to remove B_SIGNED if sign bit of B is constant-0
+    else if (B_SIGNED && _TECHMAP_CONSTMSK_B_[B_WIDTH-1] && _TECHMAP_CONSTVAL_B_[B_WIDTH-1] == 1'b0) begin
+      \$shiftx  #(.A_SIGNED(A_SIGNED), .B_SIGNED(0), .A_WIDTH(A_WIDTH), .B_WIDTH(B_WIDTH-1), .Y_WIDTH(Y_WIDTH)) _TECHMAP_REPLACE_ (.A(A), .B(B[B_WIDTH-2:0]), .Y(Y));
+    end
     else if (B_WIDTH == 3) begin
       localparam a_width0 = Y_WIDTH * (2 ** (B_WIDTH-1));
       localparam a_widthN = A_WIDTH - a_width0;
-- 
cgit v1.2.3


From 3d577586fde783829aae213fac4d1480ce1b8c53 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Wed, 10 Apr 2019 16:15:23 -0700
Subject: Try splitting $shiftx with Y_WIDTH > 1 into Y_WIDTH = 1

---
 techlibs/xilinx/cells_map.v | 69 +++++++++++++++++++++++++--------------------
 1 file changed, 38 insertions(+), 31 deletions(-)

(limited to 'techlibs')

diff --git a/techlibs/xilinx/cells_map.v b/techlibs/xilinx/cells_map.v
index 758d2ade3..253678028 100644
--- a/techlibs/xilinx/cells_map.v
+++ b/techlibs/xilinx/cells_map.v
@@ -32,58 +32,65 @@ module \$shiftx (A, B, Y);
   parameter [B_WIDTH-1:0] _TECHMAP_CONSTVAL_B_ = 0;
 
   generate
-    genvar i;
-    if (B_WIDTH < 3) begin
-      wire _TECHMAP_FAIL_;
-      assign _TECHMAP_FAIL_ = 1;
+    genvar i, j;
+    if (B_SIGNED) begin
+      if (_TECHMAP_CONSTMSK_B_[B_WIDTH-1] && _TECHMAP_CONSTVAL_B_[B_WIDTH-1] == 1'b0)
+        // Optimisation to remove B_SIGNED if sign bit of B is constant-0
+        \$shiftx  #(.A_SIGNED(A_SIGNED), .B_SIGNED(0), .A_WIDTH(A_WIDTH), .B_WIDTH(B_WIDTH-1), .Y_WIDTH(Y_WIDTH)) _TECHMAP_REPLACE_ (.A(A), .B(B[B_WIDTH-2:0]), .Y(Y));
+      else
+        wire _TECHMAP_FAIL_ = 1;
     end
-    // Optimisation to remove B_SIGNED if sign bit of B is constant-0
-    else if (B_SIGNED && _TECHMAP_CONSTMSK_B_[B_WIDTH-1] && _TECHMAP_CONSTVAL_B_[B_WIDTH-1] == 1'b0) begin
-      \$shiftx  #(.A_SIGNED(A_SIGNED), .B_SIGNED(0), .A_WIDTH(A_WIDTH), .B_WIDTH(B_WIDTH-1), .Y_WIDTH(Y_WIDTH)) _TECHMAP_REPLACE_ (.A(A), .B(B[B_WIDTH-2:0]), .Y(Y));
+    else if (Y_WIDTH > 1) begin
+      for (i = 0; i < Y_WIDTH; i++) begin
+        wire [A_WIDTH/Y_WIDTH-1:0] A_i;
+        for (j = 0; j < A_WIDTH/Y_WIDTH; j++)
+          assign A_i[j] = A[i*Y_WIDTH+j];
+        wire [$clog2(A_WIDTH/Y_WIDTH)-1:0] B_i = B/Y_WIDTH;
+        \$shiftx  #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(A_WIDTH/Y_WIDTH), .B_WIDTH($clog2(A_WIDTH/Y_WIDTH)), .Y_WIDTH(1)) bitblast (.A(A_i), .B(B_i), .Y(Y[i]));
+      end
+    end
+    else if (B_WIDTH < 3) begin
+      wire _TECHMAP_FAIL_ = 1;
     end
     else if (B_WIDTH == 3) begin
-      localparam a_width0 = Y_WIDTH * (2 ** (B_WIDTH-1));
+      localparam a_width0 = 2 ** 2;
       localparam a_widthN = A_WIDTH - a_width0;
-      wire [Y_WIDTH-1:0] T0, T1;
+      wire T0, T1;
       \$shiftx  #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(a_width0), .B_WIDTH(B_WIDTH-1),        .Y_WIDTH(Y_WIDTH)) fpga_shiftx      (.A(A[a_width0-1:0]),       .B(B[B_WIDTH-2:0]), .Y(T0));
       \$shiftx  #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(a_widthN), .B_WIDTH($clog2(a_widthN)), .Y_WIDTH(Y_WIDTH)) fpga_shiftx_last (.A(A[A_WIDTH-1:a_width0]), .B(B[$clog2(a_widthN)-1:0]), .Y(T1));
-      //MUXF7 fpga_mux[Y_WIDTH-1:0] (.I0(T0), .I1(T1), .S(B[B_WIDTH-1]), .O(Y));
-      for (i = 0; i < Y_WIDTH; i++)
-        MUXF7 fpga_mux (.I0(T0[i]), .I1(T1[i]), .S(B[B_WIDTH-1]), .O(Y[i]));
+      MUXF7 fpga_mux (.I0(T0[i]), .I1(T1[i]), .S(B[B_WIDTH-1]), .O(Y[i]));
     end
     else if (B_WIDTH == 4) begin
-      localparam a_width0 = Y_WIDTH * (2 ** (B_WIDTH-2));
+      localparam a_width0 = 2 ** 3;
       localparam num_mux8 = A_WIDTH / a_width0;
       localparam a_widthN = A_WIDTH - num_mux8*a_width0;
-      wire [Y_WIDTH*B_WIDTH-1:0] T;
-      wire [Y_WIDTH-1:0] T0, T1;
+      wire [B_WIDTH-1:0] T;
+      wire T0, T1;
       for (i = 0; i < B_WIDTH; i++)
-	if (i < num_mux8)
-          \$shiftx  #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(a_width0), .B_WIDTH(B_WIDTH-2),        .Y_WIDTH(Y_WIDTH)) fpga_shiftx      (.A(A[(i+1)*a_width0-1:i*a_width0]), .B(B[B_WIDTH-3:0]),          .Y(T[(i+1)*Y_WIDTH-1:i*Y_WIDTH]));
+        if (i < num_mux8)
+          \$shiftx  #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(a_width0), .B_WIDTH(B_WIDTH-2),        .Y_WIDTH(Y_WIDTH)) fpga_shiftx      (.A(A[(i+1)*a_width0-1:i*a_width0]), .B(B[B_WIDTH-3:0]),          .Y(T[i]));
         else if (i == num_mux8 && a_widthN > 0)
-	  \$shiftx  #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(a_widthN), .B_WIDTH($clog2(a_widthN)), .Y_WIDTH(Y_WIDTH)) fpga_shiftx_last (.A(A[A_WIDTH-1:i*a_width0]),        .B(B[$clog2(a_widthN)-1:0]), .Y(T[(i+1)*Y_WIDTH-1:i*Y_WIDTH]));
+          \$shiftx  #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(a_widthN), .B_WIDTH($clog2(a_widthN)), .Y_WIDTH(Y_WIDTH)) fpga_shiftx_last (.A(A[A_WIDTH-1:i*a_width0]),        .B(B[$clog2(a_widthN)-1:0]), .Y(T[i]));
         else
-	  assign T[(i+1)*Y_WIDTH-1:i*Y_WIDTH] = {Y_WIDTH{1'bx}};
-      for (i = 0; i < Y_WIDTH; i++) begin
-        MUXF7 fpga_mux_0 (.I0(T[i*B_WIDTH+0]), .I1(T[i*B_WIDTH+1]), .S(B[B_WIDTH-2]), .O(T0[i]));
-        MUXF7 fpga_mux_1 (.I0(T[i*B_WIDTH+2]), .I1(T[i*B_WIDTH+3]), .S(B[B_WIDTH-2]), .O(T1[i]));
-        MUXF8 fpga_mux_2 (.I0(T0[i]), .I1(T1[i]), .S(B[B_WIDTH-1]), .O(Y[i]));
-      end
+          assign T[i] = 1'bx;
+      MUXF7 fpga_mux_0 (.I0(T[0]), .I1(T[1]), .S(B[B_WIDTH-2]), .O(T0));
+      MUXF7 fpga_mux_1 (.I0(T[2]), .I1(T[3]), .S(B[B_WIDTH-2]), .O(T1));
+      MUXF8 fpga_mux_2 (.I0(T0),   .I1(T1),   .S(B[B_WIDTH-1]), .O(Y));
     end
     else begin
-      localparam a_width0 = Y_WIDTH * (2 ** 4);
+      localparam a_width0 = 2 ** 4;
       localparam num_mux16 = A_WIDTH / a_width0;
       localparam a_widthN = A_WIDTH - num_mux16*a_width0;
-      wire [Y_WIDTH*(2**(B_WIDTH-4))-1:0] T;
+      wire [(2**(B_WIDTH-4))-1:0] T;
       for (i = 0; i < 2 ** (B_WIDTH-4); i++)
-	if (i < num_mux16)
-          \$shiftx  #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(a_width0), .B_WIDTH(4),                .Y_WIDTH(Y_WIDTH)) fpga_shiftx      (.A(A[(i+1)*a_width0-1:i*a_width0]), .B(B[4-1:0]),                .Y(T[(i+1)*Y_WIDTH-1:i*Y_WIDTH]));
+        if (i < num_mux16)
+          \$shiftx  #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(a_width0), .B_WIDTH(4),                .Y_WIDTH(Y_WIDTH)) fpga_shiftx      (.A(A[(i+1)*a_width0-1:i*a_width0]), .B(B[4-1:0]),                .Y(T[i]));
         else if (i == num_mux16 && a_widthN > 0) begin
-	  \$shiftx  #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(a_widthN), .B_WIDTH($clog2(a_widthN)), .Y_WIDTH(Y_WIDTH)) fpga_shiftx_last (.A(A[A_WIDTH-1:i*a_width0]),        .B(B[$clog2(a_widthN)-1:0]), .Y(T[(i+1)*Y_WIDTH-1:i*Y_WIDTH]));
+          \$shiftx  #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(a_widthN), .B_WIDTH($clog2(a_widthN)), .Y_WIDTH(Y_WIDTH)) fpga_shiftx_last (.A(A[A_WIDTH-1:i*a_width0]),        .B(B[$clog2(a_widthN)-1:0]), .Y(T[i]));
         end
         else
-	  assign T[(i+1)*Y_WIDTH-1:i*Y_WIDTH] = {Y_WIDTH{1'bx}};
-      \$shiftx  #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(Y_WIDTH*(2**(B_WIDTH-4))), .B_WIDTH(B_WIDTH-4), .Y_WIDTH(Y_WIDTH)) fpga_shiftx (.A(T), .B(B[B_WIDTH-1:4]), .Y(Y));
+          assign T[i] = 1'bx;
+      \$shiftx  #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(2**(B_WIDTH-4)), .B_WIDTH(B_WIDTH-4), .Y_WIDTH(Y_WIDTH)) fpga_shiftx (.A(T), .B(B[B_WIDTH-1:4]), .Y(Y));
     end
   endgenerate
 endmodule
-- 
cgit v1.2.3


From cd7b2de27f4ffd097af7662a0390a5c86e5532a3 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Wed, 10 Apr 2019 18:05:09 -0700
Subject: WIP for cells_map.v -- maybe working?

---
 techlibs/xilinx/cells_map.v | 59 +++++++++++++++++++++------------------------
 1 file changed, 27 insertions(+), 32 deletions(-)

(limited to 'techlibs')

diff --git a/techlibs/xilinx/cells_map.v b/techlibs/xilinx/cells_map.v
index 253678028..93d60f60b 100644
--- a/techlibs/xilinx/cells_map.v
+++ b/techlibs/xilinx/cells_map.v
@@ -31,6 +31,7 @@ module \$shiftx (A, B, Y);
   parameter [B_WIDTH-1:0] _TECHMAP_CONSTMSK_B_ = 0;
   parameter [B_WIDTH-1:0] _TECHMAP_CONSTVAL_B_ = 0;
 
+  localparam NUM = A_WIDTH/Y_WIDTH;
   generate
     genvar i, j;
     if (B_SIGNED) begin
@@ -40,57 +41,51 @@ module \$shiftx (A, B, Y);
       else
         wire _TECHMAP_FAIL_ = 1;
     end
-    else if (Y_WIDTH > 1) begin
-      for (i = 0; i < Y_WIDTH; i++) begin
-        wire [A_WIDTH/Y_WIDTH-1:0] A_i;
-        for (j = 0; j < A_WIDTH/Y_WIDTH; j++)
-          assign A_i[j] = A[i*Y_WIDTH+j];
-        wire [$clog2(A_WIDTH/Y_WIDTH)-1:0] B_i = B/Y_WIDTH;
-        \$shiftx  #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(A_WIDTH/Y_WIDTH), .B_WIDTH($clog2(A_WIDTH/Y_WIDTH)), .Y_WIDTH(1)) bitblast (.A(A_i), .B(B_i), .Y(Y[i]));
-      end
-    end
-    else if (B_WIDTH < 3) begin
+    else if (NUM <= 4) begin
       wire _TECHMAP_FAIL_ = 1;
     end
-    else if (B_WIDTH == 3) begin
-      localparam a_width0 = 2 ** 2;
+    else if (NUM <= 8) begin
+      localparam a_width0 = Y_WIDTH * 4;
       localparam a_widthN = A_WIDTH - a_width0;
-      wire T0, T1;
+      wire [Y_WIDTH-1:0] T0, T1;
       \$shiftx  #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(a_width0), .B_WIDTH(B_WIDTH-1),        .Y_WIDTH(Y_WIDTH)) fpga_shiftx      (.A(A[a_width0-1:0]),       .B(B[B_WIDTH-2:0]), .Y(T0));
       \$shiftx  #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(a_widthN), .B_WIDTH($clog2(a_widthN)), .Y_WIDTH(Y_WIDTH)) fpga_shiftx_last (.A(A[A_WIDTH-1:a_width0]), .B(B[$clog2(a_widthN)-1:0]), .Y(T1));
-      MUXF7 fpga_mux (.I0(T0[i]), .I1(T1[i]), .S(B[B_WIDTH-1]), .O(Y[i]));
+      for (i = 0; i < Y_WIDTH; i++)
+        MUXF7 fpga_mux (.I0(T0[i]), .I1(T1[i]), .S(B[B_WIDTH-1]), .O(Y[i]));
     end
-    else if (B_WIDTH == 4) begin
-      localparam a_width0 = 2 ** 3;
+    else if (NUM <= 16) begin
+      localparam a_width0 = Y_WIDTH * 4;
       localparam num_mux8 = A_WIDTH / a_width0;
       localparam a_widthN = A_WIDTH - num_mux8*a_width0;
-      wire [B_WIDTH-1:0] T;
-      wire T0, T1;
-      for (i = 0; i < B_WIDTH; i++)
+      wire [Y_WIDTH*4-1:0] T;
+      wire [Y_WIDTH-1:0] T0, T1;
+      for (i = 0; i < 4; i++)
         if (i < num_mux8)
-          \$shiftx  #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(a_width0), .B_WIDTH(B_WIDTH-2),        .Y_WIDTH(Y_WIDTH)) fpga_shiftx      (.A(A[(i+1)*a_width0-1:i*a_width0]), .B(B[B_WIDTH-3:0]),          .Y(T[i]));
+          \$shiftx  #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(a_width0), .B_WIDTH(B_WIDTH-2), .Y_WIDTH(Y_WIDTH)) fpga_shiftx      (.A(A[(i+1)*a_width0-1:i*a_width0]), .B(B[B_WIDTH-3:0]), .Y(T[(i+1)*Y_WIDTH-1:i*Y_WIDTH]));
         else if (i == num_mux8 && a_widthN > 0)
-          \$shiftx  #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(a_widthN), .B_WIDTH($clog2(a_widthN)), .Y_WIDTH(Y_WIDTH)) fpga_shiftx_last (.A(A[A_WIDTH-1:i*a_width0]),        .B(B[$clog2(a_widthN)-1:0]), .Y(T[i]));
+          \$shiftx  #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(a_widthN), .B_WIDTH(B_WIDTH-2), .Y_WIDTH(Y_WIDTH)) fpga_shiftx_last (.A(A[A_WIDTH-1:i*a_width0]),        .B(B[B_WIDTH-3:0]), .Y(T[(i+1)*Y_WIDTH-1:i*Y_WIDTH]));
         else
-          assign T[i] = 1'bx;
-      MUXF7 fpga_mux_0 (.I0(T[0]), .I1(T[1]), .S(B[B_WIDTH-2]), .O(T0));
-      MUXF7 fpga_mux_1 (.I0(T[2]), .I1(T[3]), .S(B[B_WIDTH-2]), .O(T1));
-      MUXF8 fpga_mux_2 (.I0(T0),   .I1(T1),   .S(B[B_WIDTH-1]), .O(Y));
+          assign T[(i+1)*Y_WIDTH-1:i*Y_WIDTH] = {Y_WIDTH{1'bx}};
+      for (i = 0; i < Y_WIDTH; i++) begin
+        MUXF7 fpga_mux_0 (.I0(T[0*Y_WIDTH+i]), .I1(T[1*Y_WIDTH+i]), .S(B[B_WIDTH-2]), .O(T0[i]));
+        MUXF7 fpga_mux_1 (.I0(T[2*Y_WIDTH+i]), .I1(T[3*Y_WIDTH+i]), .S(B[B_WIDTH-2]), .O(T1[i]));
+        MUXF8 fpga_mux_2 (.I0(T0[i]),          .I1(T1[i]),          .S(B[B_WIDTH-1]), .O(Y[i]));
+      end
     end
     else begin
-      localparam a_width0 = 2 ** 4;
+      localparam a_width0 = Y_WIDTH * 16;
       localparam num_mux16 = A_WIDTH / a_width0;
       localparam a_widthN = A_WIDTH - num_mux16*a_width0;
-      wire [(2**(B_WIDTH-4))-1:0] T;
-      for (i = 0; i < 2 ** (B_WIDTH-4); i++)
+      wire [Y_WIDTH * (2 ** ($clog2(NUM)-4))-1:0] T;
+      for (i = 0; i < 2 ** ($clog2(NUM)-4); i++)
         if (i < num_mux16)
-          \$shiftx  #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(a_width0), .B_WIDTH(4),                .Y_WIDTH(Y_WIDTH)) fpga_shiftx      (.A(A[(i+1)*a_width0-1:i*a_width0]), .B(B[4-1:0]),                .Y(T[i]));
+          \$shiftx  #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(a_width0), .B_WIDTH($clog2(a_width0)), .Y_WIDTH(Y_WIDTH)) fpga_shiftx      (.A(A[(i+1)*a_width0-1:i*a_width0]), .B(B[$clog2(a_width0)-1:0]), .Y(T[(i+1)*Y_WIDTH-1:i*Y_WIDTH]));
         else if (i == num_mux16 && a_widthN > 0) begin
-          \$shiftx  #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(a_widthN), .B_WIDTH($clog2(a_widthN)), .Y_WIDTH(Y_WIDTH)) fpga_shiftx_last (.A(A[A_WIDTH-1:i*a_width0]),        .B(B[$clog2(a_widthN)-1:0]), .Y(T[i]));
+          \$shiftx  #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(a_widthN), .B_WIDTH($clog2(a_width0)), .Y_WIDTH(Y_WIDTH)) fpga_shiftx_last (.A(A[A_WIDTH-1:i*a_width0]),        .B(B[$clog2(a_width0)-1:0]), .Y(T[(i+1)*Y_WIDTH-1:i*Y_WIDTH]));
         end
         else
-          assign T[i] = 1'bx;
-      \$shiftx  #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(2**(B_WIDTH-4)), .B_WIDTH(B_WIDTH-4), .Y_WIDTH(Y_WIDTH)) fpga_shiftx (.A(T), .B(B[B_WIDTH-1:4]), .Y(Y));
+          assign T[(i+1)*Y_WIDTH-1:i*Y_WIDTH] = {Y_WIDTH{1'bx}};
+      \$shiftx  #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(Y_WIDTH * (2 ** ($clog2(NUM)-4))), .B_WIDTH(B_WIDTH-$clog2(a_width0)), .Y_WIDTH(Y_WIDTH)) fpga_shiftx (.A(T), .B(B[B_WIDTH-1:$clog2(a_width0)]), .Y(Y));
     end
   endgenerate
 endmodule
-- 
cgit v1.2.3


From 87b8d29a900eef6ec84c87ea7cd87f9a0b744fac Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Thu, 11 Apr 2019 09:13:39 -0700
Subject: Juggle opt calls in synth_xilinx

---
 techlibs/xilinx/cells_map.v     | 59 ++++++++++++++++++++++-------------------
 techlibs/xilinx/synth_xilinx.cc |  6 ++---
 2 files changed, 35 insertions(+), 30 deletions(-)

(limited to 'techlibs')

diff --git a/techlibs/xilinx/cells_map.v b/techlibs/xilinx/cells_map.v
index 93d60f60b..253678028 100644
--- a/techlibs/xilinx/cells_map.v
+++ b/techlibs/xilinx/cells_map.v
@@ -31,7 +31,6 @@ module \$shiftx (A, B, Y);
   parameter [B_WIDTH-1:0] _TECHMAP_CONSTMSK_B_ = 0;
   parameter [B_WIDTH-1:0] _TECHMAP_CONSTVAL_B_ = 0;
 
-  localparam NUM = A_WIDTH/Y_WIDTH;
   generate
     genvar i, j;
     if (B_SIGNED) begin
@@ -41,51 +40,57 @@ module \$shiftx (A, B, Y);
       else
         wire _TECHMAP_FAIL_ = 1;
     end
-    else if (NUM <= 4) begin
+    else if (Y_WIDTH > 1) begin
+      for (i = 0; i < Y_WIDTH; i++) begin
+        wire [A_WIDTH/Y_WIDTH-1:0] A_i;
+        for (j = 0; j < A_WIDTH/Y_WIDTH; j++)
+          assign A_i[j] = A[i*Y_WIDTH+j];
+        wire [$clog2(A_WIDTH/Y_WIDTH)-1:0] B_i = B/Y_WIDTH;
+        \$shiftx  #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(A_WIDTH/Y_WIDTH), .B_WIDTH($clog2(A_WIDTH/Y_WIDTH)), .Y_WIDTH(1)) bitblast (.A(A_i), .B(B_i), .Y(Y[i]));
+      end
+    end
+    else if (B_WIDTH < 3) begin
       wire _TECHMAP_FAIL_ = 1;
     end
-    else if (NUM <= 8) begin
-      localparam a_width0 = Y_WIDTH * 4;
+    else if (B_WIDTH == 3) begin
+      localparam a_width0 = 2 ** 2;
       localparam a_widthN = A_WIDTH - a_width0;
-      wire [Y_WIDTH-1:0] T0, T1;
+      wire T0, T1;
       \$shiftx  #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(a_width0), .B_WIDTH(B_WIDTH-1),        .Y_WIDTH(Y_WIDTH)) fpga_shiftx      (.A(A[a_width0-1:0]),       .B(B[B_WIDTH-2:0]), .Y(T0));
       \$shiftx  #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(a_widthN), .B_WIDTH($clog2(a_widthN)), .Y_WIDTH(Y_WIDTH)) fpga_shiftx_last (.A(A[A_WIDTH-1:a_width0]), .B(B[$clog2(a_widthN)-1:0]), .Y(T1));
-      for (i = 0; i < Y_WIDTH; i++)
-        MUXF7 fpga_mux (.I0(T0[i]), .I1(T1[i]), .S(B[B_WIDTH-1]), .O(Y[i]));
+      MUXF7 fpga_mux (.I0(T0[i]), .I1(T1[i]), .S(B[B_WIDTH-1]), .O(Y[i]));
     end
-    else if (NUM <= 16) begin
-      localparam a_width0 = Y_WIDTH * 4;
+    else if (B_WIDTH == 4) begin
+      localparam a_width0 = 2 ** 3;
       localparam num_mux8 = A_WIDTH / a_width0;
       localparam a_widthN = A_WIDTH - num_mux8*a_width0;
-      wire [Y_WIDTH*4-1:0] T;
-      wire [Y_WIDTH-1:0] T0, T1;
-      for (i = 0; i < 4; i++)
+      wire [B_WIDTH-1:0] T;
+      wire T0, T1;
+      for (i = 0; i < B_WIDTH; i++)
         if (i < num_mux8)
-          \$shiftx  #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(a_width0), .B_WIDTH(B_WIDTH-2), .Y_WIDTH(Y_WIDTH)) fpga_shiftx      (.A(A[(i+1)*a_width0-1:i*a_width0]), .B(B[B_WIDTH-3:0]), .Y(T[(i+1)*Y_WIDTH-1:i*Y_WIDTH]));
+          \$shiftx  #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(a_width0), .B_WIDTH(B_WIDTH-2),        .Y_WIDTH(Y_WIDTH)) fpga_shiftx      (.A(A[(i+1)*a_width0-1:i*a_width0]), .B(B[B_WIDTH-3:0]),          .Y(T[i]));
         else if (i == num_mux8 && a_widthN > 0)
-          \$shiftx  #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(a_widthN), .B_WIDTH(B_WIDTH-2), .Y_WIDTH(Y_WIDTH)) fpga_shiftx_last (.A(A[A_WIDTH-1:i*a_width0]),        .B(B[B_WIDTH-3:0]), .Y(T[(i+1)*Y_WIDTH-1:i*Y_WIDTH]));
+          \$shiftx  #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(a_widthN), .B_WIDTH($clog2(a_widthN)), .Y_WIDTH(Y_WIDTH)) fpga_shiftx_last (.A(A[A_WIDTH-1:i*a_width0]),        .B(B[$clog2(a_widthN)-1:0]), .Y(T[i]));
         else
-          assign T[(i+1)*Y_WIDTH-1:i*Y_WIDTH] = {Y_WIDTH{1'bx}};
-      for (i = 0; i < Y_WIDTH; i++) begin
-        MUXF7 fpga_mux_0 (.I0(T[0*Y_WIDTH+i]), .I1(T[1*Y_WIDTH+i]), .S(B[B_WIDTH-2]), .O(T0[i]));
-        MUXF7 fpga_mux_1 (.I0(T[2*Y_WIDTH+i]), .I1(T[3*Y_WIDTH+i]), .S(B[B_WIDTH-2]), .O(T1[i]));
-        MUXF8 fpga_mux_2 (.I0(T0[i]),          .I1(T1[i]),          .S(B[B_WIDTH-1]), .O(Y[i]));
-      end
+          assign T[i] = 1'bx;
+      MUXF7 fpga_mux_0 (.I0(T[0]), .I1(T[1]), .S(B[B_WIDTH-2]), .O(T0));
+      MUXF7 fpga_mux_1 (.I0(T[2]), .I1(T[3]), .S(B[B_WIDTH-2]), .O(T1));
+      MUXF8 fpga_mux_2 (.I0(T0),   .I1(T1),   .S(B[B_WIDTH-1]), .O(Y));
     end
     else begin
-      localparam a_width0 = Y_WIDTH * 16;
+      localparam a_width0 = 2 ** 4;
       localparam num_mux16 = A_WIDTH / a_width0;
       localparam a_widthN = A_WIDTH - num_mux16*a_width0;
-      wire [Y_WIDTH * (2 ** ($clog2(NUM)-4))-1:0] T;
-      for (i = 0; i < 2 ** ($clog2(NUM)-4); i++)
+      wire [(2**(B_WIDTH-4))-1:0] T;
+      for (i = 0; i < 2 ** (B_WIDTH-4); i++)
         if (i < num_mux16)
-          \$shiftx  #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(a_width0), .B_WIDTH($clog2(a_width0)), .Y_WIDTH(Y_WIDTH)) fpga_shiftx      (.A(A[(i+1)*a_width0-1:i*a_width0]), .B(B[$clog2(a_width0)-1:0]), .Y(T[(i+1)*Y_WIDTH-1:i*Y_WIDTH]));
+          \$shiftx  #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(a_width0), .B_WIDTH(4),                .Y_WIDTH(Y_WIDTH)) fpga_shiftx      (.A(A[(i+1)*a_width0-1:i*a_width0]), .B(B[4-1:0]),                .Y(T[i]));
         else if (i == num_mux16 && a_widthN > 0) begin
-          \$shiftx  #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(a_widthN), .B_WIDTH($clog2(a_width0)), .Y_WIDTH(Y_WIDTH)) fpga_shiftx_last (.A(A[A_WIDTH-1:i*a_width0]),        .B(B[$clog2(a_width0)-1:0]), .Y(T[(i+1)*Y_WIDTH-1:i*Y_WIDTH]));
+          \$shiftx  #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(a_widthN), .B_WIDTH($clog2(a_widthN)), .Y_WIDTH(Y_WIDTH)) fpga_shiftx_last (.A(A[A_WIDTH-1:i*a_width0]),        .B(B[$clog2(a_widthN)-1:0]), .Y(T[i]));
         end
         else
-          assign T[(i+1)*Y_WIDTH-1:i*Y_WIDTH] = {Y_WIDTH{1'bx}};
-      \$shiftx  #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(Y_WIDTH * (2 ** ($clog2(NUM)-4))), .B_WIDTH(B_WIDTH-$clog2(a_width0)), .Y_WIDTH(Y_WIDTH)) fpga_shiftx (.A(T), .B(B[B_WIDTH-1:$clog2(a_width0)]), .Y(Y));
+          assign T[i] = 1'bx;
+      \$shiftx  #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(2**(B_WIDTH-4)), .B_WIDTH(B_WIDTH-4), .Y_WIDTH(Y_WIDTH)) fpga_shiftx (.A(T), .B(B[B_WIDTH-1:4]), .Y(Y));
     end
   endgenerate
 endmodule
diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc
index 10902a560..0058f626f 100644
--- a/techlibs/xilinx/synth_xilinx.cc
+++ b/techlibs/xilinx/synth_xilinx.cc
@@ -118,7 +118,7 @@ struct SynthXilinxPass : public Pass
 		log("\n");
 		log("    map_cells:\n");
 		log("        techmap -map +/xilinx/cells_map.v\n");
-		log("        clean\n");
+		log("        opt -fast\n");
 		log("\n");
 		log("    map_luts:\n");
 		log("        techmap -map +/techmap.v\n");
@@ -258,11 +258,10 @@ struct SynthXilinxPass : public Pass
 
 		if (check_label(active, run_from, run_to, "fine"))
 		{
-			Pass::call(design, "opt -fast -full");
+			Pass::call(design, "opt -fast");
 			Pass::call(design, "memory_map");
 			Pass::call(design, "dffsr2dff");
 			Pass::call(design, "dff2dffe");
-			Pass::call(design, "opt -full");
 
 			if (vpr) {
 				Pass::call(design, "techmap -map +/xilinx/arith_map.v -D _EXPLICIT_CARRY");
@@ -282,6 +281,7 @@ struct SynthXilinxPass : public Pass
 
 		if (check_label(active, run_from, run_to, "map_luts"))
 		{
+			Pass::call(design, "opt -full");
 			Pass::call(design, "techmap -map +/techmap.v");
 			if (abc == "abc9")
 				Pass::call(design, abc + " -lut +/xilinx/cells.lut -box +/xilinx/cells.box" + string(retime ? " -dff" : ""));
-- 
cgit v1.2.3


From bca37796578ee3a259a8327d881d5ac1264c3ac9 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Thu, 11 Apr 2019 09:25:19 -0700
Subject: Fix typo

---
 techlibs/xilinx/cells_map.v | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'techlibs')

diff --git a/techlibs/xilinx/cells_map.v b/techlibs/xilinx/cells_map.v
index 253678028..8bf0a28b5 100644
--- a/techlibs/xilinx/cells_map.v
+++ b/techlibs/xilinx/cells_map.v
@@ -58,7 +58,7 @@ module \$shiftx (A, B, Y);
       wire T0, T1;
       \$shiftx  #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(a_width0), .B_WIDTH(B_WIDTH-1),        .Y_WIDTH(Y_WIDTH)) fpga_shiftx      (.A(A[a_width0-1:0]),       .B(B[B_WIDTH-2:0]), .Y(T0));
       \$shiftx  #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(a_widthN), .B_WIDTH($clog2(a_widthN)), .Y_WIDTH(Y_WIDTH)) fpga_shiftx_last (.A(A[A_WIDTH-1:a_width0]), .B(B[$clog2(a_widthN)-1:0]), .Y(T1));
-      MUXF7 fpga_mux (.I0(T0[i]), .I1(T1[i]), .S(B[B_WIDTH-1]), .O(Y[i]));
+      MUXF7 fpga_mux (.I0(T0), .I1(T1), .S(B[B_WIDTH-1]), .O(Y));
     end
     else if (B_WIDTH == 4) begin
       localparam a_width0 = 2 ** 3;
-- 
cgit v1.2.3


From 0ec85640993e0eeb089334efbcd486a254d32786 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Thu, 11 Apr 2019 10:04:58 -0700
Subject: Fix cells_map.v

---
 techlibs/xilinx/cells_map.v | 14 +++++++-------
 1 file changed, 7 insertions(+), 7 deletions(-)

(limited to 'techlibs')

diff --git a/techlibs/xilinx/cells_map.v b/techlibs/xilinx/cells_map.v
index 8bf0a28b5..f1ea8f6df 100644
--- a/techlibs/xilinx/cells_map.v
+++ b/techlibs/xilinx/cells_map.v
@@ -41,12 +41,12 @@ module \$shiftx (A, B, Y);
         wire _TECHMAP_FAIL_ = 1;
     end
     else if (Y_WIDTH > 1) begin
+      wire [$clog2(A_WIDTH/Y_WIDTH)-1:0] B_bitty = B/Y_WIDTH;
       for (i = 0; i < Y_WIDTH; i++) begin
         wire [A_WIDTH/Y_WIDTH-1:0] A_i;
         for (j = 0; j < A_WIDTH/Y_WIDTH; j++)
-          assign A_i[j] = A[i*Y_WIDTH+j];
-        wire [$clog2(A_WIDTH/Y_WIDTH)-1:0] B_i = B/Y_WIDTH;
-        \$shiftx  #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(A_WIDTH/Y_WIDTH), .B_WIDTH($clog2(A_WIDTH/Y_WIDTH)), .Y_WIDTH(1)) bitblast (.A(A_i), .B(B_i), .Y(Y[i]));
+          assign A_i[j] = A[j*Y_WIDTH+i];
+        \$shiftx  #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(A_WIDTH/Y_WIDTH), .B_WIDTH($clog2(A_WIDTH/Y_WIDTH)), .Y_WIDTH(1)) bitblast (.A(A_i), .B(B_bitty), .Y(Y[i]));
       end
     end
     else if (B_WIDTH < 3) begin
@@ -68,9 +68,9 @@ module \$shiftx (A, B, Y);
       wire T0, T1;
       for (i = 0; i < B_WIDTH; i++)
         if (i < num_mux8)
-          \$shiftx  #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(a_width0), .B_WIDTH(B_WIDTH-2),        .Y_WIDTH(Y_WIDTH)) fpga_shiftx      (.A(A[(i+1)*a_width0-1:i*a_width0]), .B(B[B_WIDTH-3:0]),          .Y(T[i]));
+          \$shiftx  #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(a_width0), .B_WIDTH(B_WIDTH-2),        .Y_WIDTH(Y_WIDTH)) fpga_shiftx      (.A(A[i*a_width0+:a_width0]), .B(B[B_WIDTH-3:0]),          .Y(T[i]));
         else if (i == num_mux8 && a_widthN > 0)
-          \$shiftx  #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(a_widthN), .B_WIDTH($clog2(a_widthN)), .Y_WIDTH(Y_WIDTH)) fpga_shiftx_last (.A(A[A_WIDTH-1:i*a_width0]),        .B(B[$clog2(a_widthN)-1:0]), .Y(T[i]));
+          \$shiftx  #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(a_widthN), .B_WIDTH($clog2(a_widthN)), .Y_WIDTH(Y_WIDTH)) fpga_shiftx_last (.A(A[A_WIDTH-1:i*a_width0]), .B(B[$clog2(a_widthN)-1:0]), .Y(T[i]));
         else
           assign T[i] = 1'bx;
       MUXF7 fpga_mux_0 (.I0(T[0]), .I1(T[1]), .S(B[B_WIDTH-2]), .O(T0));
@@ -84,9 +84,9 @@ module \$shiftx (A, B, Y);
       wire [(2**(B_WIDTH-4))-1:0] T;
       for (i = 0; i < 2 ** (B_WIDTH-4); i++)
         if (i < num_mux16)
-          \$shiftx  #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(a_width0), .B_WIDTH(4),                .Y_WIDTH(Y_WIDTH)) fpga_shiftx      (.A(A[(i+1)*a_width0-1:i*a_width0]), .B(B[4-1:0]),                .Y(T[i]));
+          \$shiftx  #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(a_width0), .B_WIDTH(4),                .Y_WIDTH(Y_WIDTH)) fpga_shiftx      (.A(A[i*a_width0+:a_width0]), .B(B[4-1:0]),                .Y(T[i]));
         else if (i == num_mux16 && a_widthN > 0) begin
-          \$shiftx  #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(a_widthN), .B_WIDTH($clog2(a_widthN)), .Y_WIDTH(Y_WIDTH)) fpga_shiftx_last (.A(A[A_WIDTH-1:i*a_width0]),        .B(B[$clog2(a_widthN)-1:0]), .Y(T[i]));
+          \$shiftx  #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(a_widthN), .B_WIDTH($clog2(a_widthN)), .Y_WIDTH(Y_WIDTH)) fpga_shiftx_last (.A(A[A_WIDTH-1:i*a_width0]), .B(B[$clog2(a_widthN)-1:0]), .Y(T[i]));
         end
         else
           assign T[i] = 1'bx;
-- 
cgit v1.2.3


From 8658b56a08737cef6040015b192c11da3e6b4eb4 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Thu, 11 Apr 2019 10:08:05 -0700
Subject: More fine tuning

---
 techlibs/xilinx/cells_map.v | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

(limited to 'techlibs')

diff --git a/techlibs/xilinx/cells_map.v b/techlibs/xilinx/cells_map.v
index f1ea8f6df..071014d47 100644
--- a/techlibs/xilinx/cells_map.v
+++ b/techlibs/xilinx/cells_map.v
@@ -56,7 +56,7 @@ module \$shiftx (A, B, Y);
       localparam a_width0 = 2 ** 2;
       localparam a_widthN = A_WIDTH - a_width0;
       wire T0, T1;
-      \$shiftx  #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(a_width0), .B_WIDTH(B_WIDTH-1),        .Y_WIDTH(Y_WIDTH)) fpga_shiftx      (.A(A[a_width0-1:0]),       .B(B[B_WIDTH-2:0]), .Y(T0));
+      \$shiftx  #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(a_width0), .B_WIDTH(2),                .Y_WIDTH(Y_WIDTH)) fpga_shiftx      (.A(A[a_width0-1:0]),       .B(B[2-1:0]),                .Y(T0));
       \$shiftx  #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(a_widthN), .B_WIDTH($clog2(a_widthN)), .Y_WIDTH(Y_WIDTH)) fpga_shiftx_last (.A(A[A_WIDTH-1:a_width0]), .B(B[$clog2(a_widthN)-1:0]), .Y(T1));
       MUXF7 fpga_mux (.I0(T0), .I1(T1), .S(B[B_WIDTH-1]), .O(Y));
     end
@@ -68,7 +68,7 @@ module \$shiftx (A, B, Y);
       wire T0, T1;
       for (i = 0; i < B_WIDTH; i++)
         if (i < num_mux8)
-          \$shiftx  #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(a_width0), .B_WIDTH(B_WIDTH-2),        .Y_WIDTH(Y_WIDTH)) fpga_shiftx      (.A(A[i*a_width0+:a_width0]), .B(B[B_WIDTH-3:0]),          .Y(T[i]));
+          \$shiftx  #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(a_width0), .B_WIDTH(3),                .Y_WIDTH(Y_WIDTH)) fpga_shiftx      (.A(A[i*a_width0+:a_width0]), .B(B[3-1:0]),                .Y(T[i]));
         else if (i == num_mux8 && a_widthN > 0)
           \$shiftx  #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(a_widthN), .B_WIDTH($clog2(a_widthN)), .Y_WIDTH(Y_WIDTH)) fpga_shiftx_last (.A(A[A_WIDTH-1:i*a_width0]), .B(B[$clog2(a_widthN)-1:0]), .Y(T[i]));
         else
-- 
cgit v1.2.3


From 233edf00fec32c8acd7ed442323e0cd515f0e681 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Thu, 11 Apr 2019 10:48:14 -0700
Subject: Fix cells_map.v some more

---
 techlibs/xilinx/cells_map.v | 14 +++++++-------
 1 file changed, 7 insertions(+), 7 deletions(-)

(limited to 'techlibs')

diff --git a/techlibs/xilinx/cells_map.v b/techlibs/xilinx/cells_map.v
index 071014d47..2981f89f6 100644
--- a/techlibs/xilinx/cells_map.v
+++ b/techlibs/xilinx/cells_map.v
@@ -61,21 +61,21 @@ module \$shiftx (A, B, Y);
       MUXF7 fpga_mux (.I0(T0), .I1(T1), .S(B[B_WIDTH-1]), .O(Y));
     end
     else if (B_WIDTH == 4) begin
-      localparam a_width0 = 2 ** 3;
+      localparam a_width0 = 2 ** 2;
       localparam num_mux8 = A_WIDTH / a_width0;
       localparam a_widthN = A_WIDTH - num_mux8*a_width0;
-      wire [B_WIDTH-1:0] T;
+      wire [4-1:0] T;
       wire T0, T1;
-      for (i = 0; i < B_WIDTH; i++)
+      for (i = 0; i < 4; i++)
         if (i < num_mux8)
-          \$shiftx  #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(a_width0), .B_WIDTH(3),                .Y_WIDTH(Y_WIDTH)) fpga_shiftx      (.A(A[i*a_width0+:a_width0]), .B(B[3-1:0]),                .Y(T[i]));
+          \$shiftx  #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(a_width0), .B_WIDTH(2),                .Y_WIDTH(Y_WIDTH)) fpga_shiftx      (.A(A[i*a_width0+:a_width0]), .B(B[2-1:0]),                .Y(T[i]));
         else if (i == num_mux8 && a_widthN > 0)
           \$shiftx  #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(a_widthN), .B_WIDTH($clog2(a_widthN)), .Y_WIDTH(Y_WIDTH)) fpga_shiftx_last (.A(A[A_WIDTH-1:i*a_width0]), .B(B[$clog2(a_widthN)-1:0]), .Y(T[i]));
         else
           assign T[i] = 1'bx;
-      MUXF7 fpga_mux_0 (.I0(T[0]), .I1(T[1]), .S(B[B_WIDTH-2]), .O(T0));
-      MUXF7 fpga_mux_1 (.I0(T[2]), .I1(T[3]), .S(B[B_WIDTH-2]), .O(T1));
-      MUXF8 fpga_mux_2 (.I0(T0),   .I1(T1),   .S(B[B_WIDTH-1]), .O(Y));
+      MUXF7 fpga_mux_0 (.I0(T[0]), .I1(T[1]), .S(B[2]), .O(T0));
+      MUXF7 fpga_mux_1 (.I0(T[2]), .I1(T[3]), .S(B[2]), .O(T1));
+      MUXF8 fpga_mux_2 (.I0(T0),   .I1(T1),   .S(B[3]), .O(Y));
     end
     else begin
       localparam a_width0 = 2 ** 4;
-- 
cgit v1.2.3


From 8fbbd9b129697152c93c35831c1d50982702a3ec Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Mon, 15 Apr 2019 22:25:09 -0700
Subject: Add abc_box_id attribute to MUXF7/F8 cells

---
 techlibs/xilinx/cells_sim.v | 2 ++
 1 file changed, 2 insertions(+)

(limited to 'techlibs')

diff --git a/techlibs/xilinx/cells_sim.v b/techlibs/xilinx/cells_sim.v
index 0c8f282a4..05dd9229f 100644
--- a/techlibs/xilinx/cells_sim.v
+++ b/techlibs/xilinx/cells_sim.v
@@ -159,10 +159,12 @@ module MUXCY(output O, input CI, DI, S);
   assign O = S ? CI : DI;
 endmodule
 
+(* abc_box_id = 1 *)
 module MUXF7(output O, input I0, I1, S);
   assign O = S ? I1 : I0;
 endmodule
 
+(* abc_box_id = 2 *)
 module MUXF8(output O, input I0, I1, S);
   assign O = S ? I1 : I0;
 endmodule
-- 
cgit v1.2.3


From 8c6cf07acff290ab2132c1a7d262bf195fa85b8b Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Tue, 16 Apr 2019 11:14:59 -0700
Subject: Revert "Add abc_box_id attribute to MUXF7/F8 cells"

This reverts commit 8fbbd9b129697152c93c35831c1d50982702a3ec.
---
 techlibs/xilinx/cells_sim.v | 2 --
 1 file changed, 2 deletions(-)

(limited to 'techlibs')

diff --git a/techlibs/xilinx/cells_sim.v b/techlibs/xilinx/cells_sim.v
index 05dd9229f..0c8f282a4 100644
--- a/techlibs/xilinx/cells_sim.v
+++ b/techlibs/xilinx/cells_sim.v
@@ -159,12 +159,10 @@ module MUXCY(output O, input CI, DI, S);
   assign O = S ? CI : DI;
 endmodule
 
-(* abc_box_id = 1 *)
 module MUXF7(output O, input I0, I1, S);
   assign O = S ? I1 : I0;
 endmodule
 
-(* abc_box_id = 2 *)
 module MUXF8(output O, input I0, I1, S);
   assign O = S ? I1 : I0;
 endmodule
-- 
cgit v1.2.3


From 3ac4977b70a373cdabaa72e5f08050f49a3d4046 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Tue, 16 Apr 2019 11:21:03 -0700
Subject: Add +/xilinx/cells_box.v containing models for ABC boxes

---
 techlibs/xilinx/Makefile.inc |  1 +
 techlibs/xilinx/cells_box.v  | 10 ++++++++++
 2 files changed, 11 insertions(+)
 create mode 100644 techlibs/xilinx/cells_box.v

(limited to 'techlibs')

diff --git a/techlibs/xilinx/Makefile.inc b/techlibs/xilinx/Makefile.inc
index 432bb0770..43be55d51 100644
--- a/techlibs/xilinx/Makefile.inc
+++ b/techlibs/xilinx/Makefile.inc
@@ -31,6 +31,7 @@ $(eval $(call add_share_file,share/xilinx,techlibs/xilinx/arith_map.v))
 $(eval $(call add_share_file,share/xilinx,techlibs/xilinx/ff_map.v))
 $(eval $(call add_share_file,share/xilinx,techlibs/xilinx/lut_map.v))
 $(eval $(call add_share_file,share/xilinx,techlibs/xilinx/cells.box))
+$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/cells_box.v))
 $(eval $(call add_share_file,share/xilinx,techlibs/xilinx/cells.lut))
 
 $(eval $(call add_gen_share_file,share/xilinx,techlibs/xilinx/brams_init_36.vh))
diff --git a/techlibs/xilinx/cells_box.v b/techlibs/xilinx/cells_box.v
new file mode 100644
index 000000000..7805e6306
--- /dev/null
+++ b/techlibs/xilinx/cells_box.v
@@ -0,0 +1,10 @@
+(* abc_box_id = 1 *)
+module MUXF7(output O, input I0, I1, S);
+  assign O = S ? I1 : I0;
+endmodule
+
+(* abc_box_id = 2 *)
+module MUXF8(output O, input I0, I1, S);
+  assign O = S ? I1 : I0;
+endmodule
+
-- 
cgit v1.2.3


From d259e6dc14dadf9101116c622569f5b961adde69 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Tue, 16 Apr 2019 11:21:46 -0700
Subject: synth_xilinx: before abc read +/xilinx/cells_box.v

---
 techlibs/xilinx/synth_xilinx.cc | 1 +
 1 file changed, 1 insertion(+)

(limited to 'techlibs')

diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc
index 0058f626f..c10e42532 100644
--- a/techlibs/xilinx/synth_xilinx.cc
+++ b/techlibs/xilinx/synth_xilinx.cc
@@ -283,6 +283,7 @@ struct SynthXilinxPass : public Pass
 		{
 			Pass::call(design, "opt -full");
 			Pass::call(design, "techmap -map +/techmap.v");
+			Pass::call(design, "read_verilog +/xilinx/cells_box.v");
 			if (abc == "abc9")
 				Pass::call(design, abc + " -lut +/xilinx/cells.lut -box +/xilinx/cells.box" + string(retime ? " -dff" : ""));
 			else
-- 
cgit v1.2.3


From 51896953626ddf7cffdbddfe64e8d85264d968a8 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Tue, 16 Apr 2019 12:41:56 -0700
Subject: read_verilog cells_box.v before techmap

---
 techlibs/xilinx/synth_xilinx.cc | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'techlibs')

diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc
index c10e42532..d5e9b80c8 100644
--- a/techlibs/xilinx/synth_xilinx.cc
+++ b/techlibs/xilinx/synth_xilinx.cc
@@ -282,8 +282,8 @@ struct SynthXilinxPass : public Pass
 		if (check_label(active, run_from, run_to, "map_luts"))
 		{
 			Pass::call(design, "opt -full");
-			Pass::call(design, "techmap -map +/techmap.v");
 			Pass::call(design, "read_verilog +/xilinx/cells_box.v");
+			Pass::call(design, "techmap -map +/techmap.v");
 			if (abc == "abc9")
 				Pass::call(design, abc + " -lut +/xilinx/cells.lut -box +/xilinx/cells.box" + string(retime ? " -dff" : ""));
 			else
-- 
cgit v1.2.3


From 53b19ab1f5631bcfc6c3def14f5d44ecc05c1cbc Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Tue, 16 Apr 2019 12:43:14 -0700
Subject: Make cells.box whiteboxes not blackboxes

---
 techlibs/xilinx/cells.box | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

(limited to 'techlibs')

diff --git a/techlibs/xilinx/cells.box b/techlibs/xilinx/cells.box
index c8092db6e..c236d3c90 100644
--- a/techlibs/xilinx/cells.box
+++ b/techlibs/xilinx/cells.box
@@ -4,10 +4,10 @@
 # F7BMUX slower than F7AMUX
 # Inputs: 0 1 S0
 # Outputs: OUT
-F7BMUX 1 0 3 1
+F7BMUX 1 1 3 1
 217 223 296
 
 # Inputs: 0 1 S0
 # Outputs: OUT
-MUXF8 2 0 3 1
+MUXF8 2 1 3 1
 104 94 273
-- 
cgit v1.2.3


From aece97024de574fd765e18e31f685e9ffb0a13c6 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Tue, 16 Apr 2019 13:16:20 -0700
Subject: Fix spacing

---
 techlibs/xilinx/cells.lut | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'techlibs')

diff --git a/techlibs/xilinx/cells.lut b/techlibs/xilinx/cells.lut
index a1d9b9c42..c6bc7b1f7 100644
--- a/techlibs/xilinx/cells.lut
+++ b/techlibs/xilinx/cells.lut
@@ -1,4 +1,4 @@
-# Max delays from https://pastebin.com/v2hrcksd 
+# Max delays from https://pastebin.com/v2hrcksd
 # from https://github.com/SymbiFlow/prjxray/pull/706#issuecomment-479380321
 
 # K	area	delay
-- 
cgit v1.2.3


From cbb85e40e87fbfb1602bb934ed76a97efb9e55c6 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Tue, 16 Apr 2019 14:53:28 -0700
Subject: Add MUXCY and XORCY to cells_box.v

---
 techlibs/xilinx/cells.box   | 6 ++++++
 techlibs/xilinx/cells_box.v | 9 +++++++++
 2 files changed, 15 insertions(+)

(limited to 'techlibs')

diff --git a/techlibs/xilinx/cells.box b/techlibs/xilinx/cells.box
index c236d3c90..5ad284f47 100644
--- a/techlibs/xilinx/cells.box
+++ b/techlibs/xilinx/cells.box
@@ -11,3 +11,9 @@ F7BMUX 1 1 3 1
 # Outputs: OUT
 MUXF8 2 1 3 1
 104 94 273
+
+MUXCY 3 1 3 1
+1 1 1
+
+XORCY 4 1 2 1
+1 1
diff --git a/techlibs/xilinx/cells_box.v b/techlibs/xilinx/cells_box.v
index 7805e6306..ef6f81d27 100644
--- a/techlibs/xilinx/cells_box.v
+++ b/techlibs/xilinx/cells_box.v
@@ -8,3 +8,12 @@ module MUXF8(output O, input I0, I1, S);
   assign O = S ? I1 : I0;
 endmodule
 
+(* abc_box_id = 3 *)
+module MUXCY(output O, input CI, DI, S);
+  assign O = S ? CI : DI;
+endmodule
+
+(* abc_box_id = 4 *)
+module XORCY(output O, input CI, LI);
+  assign O = CI ^ LI;
+endmodule
-- 
cgit v1.2.3


From 79fb291dbedbb6cf582925329e8140cbc7e502a9 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Mon, 22 Apr 2019 12:14:37 -0700
Subject: Cleanup, call pmux2shiftx even without -nosrl

---
 techlibs/xilinx/Makefile.inc    |  5 ++---
 techlibs/xilinx/abc.box         | 19 +++++++++++++++++++
 techlibs/xilinx/abc.lut         | 12 ++++++++++++
 techlibs/xilinx/cells.box       | 19 -------------------
 techlibs/xilinx/cells.lut       | 12 ------------
 techlibs/xilinx/cells_box.v     | 19 -------------------
 techlibs/xilinx/cells_sim.v     | 28 ++++++++++++++++------------
 techlibs/xilinx/synth_xilinx.cc | 15 ++++++++-------
 8 files changed, 57 insertions(+), 72 deletions(-)
 create mode 100644 techlibs/xilinx/abc.box
 create mode 100644 techlibs/xilinx/abc.lut
 delete mode 100644 techlibs/xilinx/cells.box
 delete mode 100644 techlibs/xilinx/cells.lut
 delete mode 100644 techlibs/xilinx/cells_box.v

(limited to 'techlibs')

diff --git a/techlibs/xilinx/Makefile.inc b/techlibs/xilinx/Makefile.inc
index 43be55d51..296edace9 100644
--- a/techlibs/xilinx/Makefile.inc
+++ b/techlibs/xilinx/Makefile.inc
@@ -30,9 +30,8 @@ $(eval $(call add_share_file,share/xilinx,techlibs/xilinx/drams_map.v))
 $(eval $(call add_share_file,share/xilinx,techlibs/xilinx/arith_map.v))
 $(eval $(call add_share_file,share/xilinx,techlibs/xilinx/ff_map.v))
 $(eval $(call add_share_file,share/xilinx,techlibs/xilinx/lut_map.v))
-$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/cells.box))
-$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/cells_box.v))
-$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/cells.lut))
+$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/abc.box))
+$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/abc.lut))
 
 $(eval $(call add_gen_share_file,share/xilinx,techlibs/xilinx/brams_init_36.vh))
 $(eval $(call add_gen_share_file,share/xilinx,techlibs/xilinx/brams_init_32.vh))
diff --git a/techlibs/xilinx/abc.box b/techlibs/xilinx/abc.box
new file mode 100644
index 000000000..d572817df
--- /dev/null
+++ b/techlibs/xilinx/abc.box
@@ -0,0 +1,19 @@
+# Max delays from https://pastebin.com/v2hrcksd
+# from https://github.com/SymbiFlow/prjxray/pull/706#issuecomment-479380321
+
+# F7BMUX slower than F7AMUX
+# Inputs: I0 I1 S0
+# Outputs: O
+F7BMUX 1 1 3 1
+217 223 296
+
+# Inputs: I0 I1 S0
+# Outputs: O
+MUXF8 2 1 3 1
+104 94 273
+
+MUXCY 3 1 3 1
+1 1 1
+
+XORCY 4 1 2 1
+1 1
diff --git a/techlibs/xilinx/abc.lut b/techlibs/xilinx/abc.lut
new file mode 100644
index 000000000..c6bc7b1f7
--- /dev/null
+++ b/techlibs/xilinx/abc.lut
@@ -0,0 +1,12 @@
+# Max delays from https://pastebin.com/v2hrcksd
+# from https://github.com/SymbiFlow/prjxray/pull/706#issuecomment-479380321
+
+# K	area	delay
+1 	11	624
+2	12	624
+3	13	624
+4	14	624
+5	15	624
+6	20	724
+7	40	1020
+8	80	1293
diff --git a/techlibs/xilinx/cells.box b/techlibs/xilinx/cells.box
deleted file mode 100644
index 5ad284f47..000000000
--- a/techlibs/xilinx/cells.box
+++ /dev/null
@@ -1,19 +0,0 @@
-# Max delays from https://pastebin.com/v2hrcksd
-# from https://github.com/SymbiFlow/prjxray/pull/706#issuecomment-479380321
-
-# F7BMUX slower than F7AMUX
-# Inputs: 0 1 S0
-# Outputs: OUT
-F7BMUX 1 1 3 1
-217 223 296
-
-# Inputs: 0 1 S0
-# Outputs: OUT
-MUXF8 2 1 3 1
-104 94 273
-
-MUXCY 3 1 3 1
-1 1 1
-
-XORCY 4 1 2 1
-1 1
diff --git a/techlibs/xilinx/cells.lut b/techlibs/xilinx/cells.lut
deleted file mode 100644
index c6bc7b1f7..000000000
--- a/techlibs/xilinx/cells.lut
+++ /dev/null
@@ -1,12 +0,0 @@
-# Max delays from https://pastebin.com/v2hrcksd
-# from https://github.com/SymbiFlow/prjxray/pull/706#issuecomment-479380321
-
-# K	area	delay
-1 	11	624
-2	12	624
-3	13	624
-4	14	624
-5	15	624
-6	20	724
-7	40	1020
-8	80	1293
diff --git a/techlibs/xilinx/cells_box.v b/techlibs/xilinx/cells_box.v
deleted file mode 100644
index ef6f81d27..000000000
--- a/techlibs/xilinx/cells_box.v
+++ /dev/null
@@ -1,19 +0,0 @@
-(* abc_box_id = 1 *)
-module MUXF7(output O, input I0, I1, S);
-  assign O = S ? I1 : I0;
-endmodule
-
-(* abc_box_id = 2 *)
-module MUXF8(output O, input I0, I1, S);
-  assign O = S ? I1 : I0;
-endmodule
-
-(* abc_box_id = 3 *)
-module MUXCY(output O, input CI, DI, S);
-  assign O = S ? CI : DI;
-endmodule
-
-(* abc_box_id = 4 *)
-module XORCY(output O, input CI, LI);
-  assign O = CI ^ LI;
-endmodule
diff --git a/techlibs/xilinx/cells_sim.v b/techlibs/xilinx/cells_sim.v
index 3a4540b83..8b231480f 100644
--- a/techlibs/xilinx/cells_sim.v
+++ b/techlibs/xilinx/cells_sim.v
@@ -155,18 +155,22 @@ module LUT6_2(output O6, output O5, input I0, I1, I2, I3, I4, I5);
   assign O5 = I0 ? s5_1[1] : s5_1[0];
 endmodule
 
+(* abc_box_id = 3, lib_whitebox *)
 module MUXCY(output O, input CI, DI, S);
   assign O = S ? CI : DI;
 endmodule
 
+(* abc_box_id = 1, lib_whitebox *)
 module MUXF7(output O, input I0, I1, S);
   assign O = S ? I1 : I0;
 endmodule
 
+(* abc_box_id = 2, lib_whitebox *)
 module MUXF8(output O, input I0, I1, S);
   assign O = S ? I1 : I0;
 endmodule
 
+(* abc_box_id = 4, lib_whitebox *)
 module XORCY(output O, input CI, LI);
   assign O = CI ^ LI;
 endmodule
@@ -202,7 +206,7 @@ endmodule
 
 `endif
 
-module FDRE (output reg Q, input C, CE, D, R);
+module FDRE ((* abc_flop_q *) output reg Q, input C, CE, input D, R);
   parameter [0:0] INIT = 1'b0;
   parameter [0:0] IS_C_INVERTED = 1'b0;
   parameter [0:0] IS_D_INVERTED = 1'b0;
@@ -214,7 +218,7 @@ module FDRE (output reg Q, input C, CE, D, R);
   endcase endgenerate
 endmodule
 
-module FDSE (output reg Q, input C, CE, D, S);
+module FDSE ((* abc_flop_q *) output reg Q, input C, CE, D, S);
   parameter [0:0] INIT = 1'b0;
   parameter [0:0] IS_C_INVERTED = 1'b0;
   parameter [0:0] IS_D_INVERTED = 1'b0;
@@ -226,7 +230,7 @@ module FDSE (output reg Q, input C, CE, D, S);
   endcase endgenerate
 endmodule
 
-module FDCE (output reg Q, input C, CE, D, CLR);
+module FDCE ((* abc_flop_q *) output reg Q, input C, CE, D, CLR);
   parameter [0:0] INIT = 1'b0;
   parameter [0:0] IS_C_INVERTED = 1'b0;
   parameter [0:0] IS_D_INVERTED = 1'b0;
@@ -240,7 +244,7 @@ module FDCE (output reg Q, input C, CE, D, CLR);
   endcase endgenerate
 endmodule
 
-module FDPE (output reg Q, input C, CE, D, PRE);
+module FDPE ((* abc_flop_q *) output reg Q, input C, CE, D, PRE);
   parameter [0:0] INIT = 1'b0;
   parameter [0:0] IS_C_INVERTED = 1'b0;
   parameter [0:0] IS_D_INVERTED = 1'b0;
@@ -254,32 +258,32 @@ module FDPE (output reg Q, input C, CE, D, PRE);
   endcase endgenerate
 endmodule
 
-module FDRE_1 (output reg Q, input C, CE, D, R);
+module FDRE_1 ((* abc_flop_q *) output reg Q, input C, CE, D, R);
   parameter [0:0] INIT = 1'b0;
   initial Q <= INIT;
   always @(negedge C) if (R) Q <= 1'b0; else if(CE) Q <= D;
 endmodule
 
-module FDSE_1 (output reg Q, input C, CE, D, S);
+module FDSE_1 ((* abc_flop_q *) output reg Q, input C, CE, D, S);
   parameter [0:0] INIT = 1'b1;
   initial Q <= INIT;
   always @(negedge C) if (S) Q <= 1'b1; else if(CE) Q <= D;
 endmodule
 
-module FDCE_1 (output reg Q, input C, CE, D, CLR);
+module FDCE_1 ((* abc_flop_q *) output reg Q, input C, CE, D, CLR);
   parameter [0:0] INIT = 1'b0;
   initial Q <= INIT;
   always @(negedge C, posedge CLR) if (CLR) Q <= 1'b0; else if (CE) Q <= D;
 endmodule
 
-module FDPE_1 (output reg Q, input C, CE, D, PRE);
+module FDPE_1 ((* abc_flop_q *) output reg Q, input C, CE, D, PRE);
   parameter [0:0] INIT = 1'b1;
   initial Q <= INIT;
   always @(negedge C, posedge PRE) if (PRE) Q <= 1'b1; else if (CE) Q <= D;
 endmodule
 
 module RAM64X1D (
-  output DPO, SPO,
+  (* abc_flop_q *) output DPO, SPO,
   input  D, WCLK, WE,
   input  A0, A1, A2, A3, A4, A5,
   input  DPRA0, DPRA1, DPRA2, DPRA3, DPRA4, DPRA5
@@ -296,7 +300,7 @@ module RAM64X1D (
 endmodule
 
 module RAM128X1D (
-  output       DPO, SPO,
+  (* abc_flop_q *) output       DPO, SPO,
   input        D, WCLK, WE,
   input  [6:0] A, DPRA
 );
@@ -310,7 +314,7 @@ module RAM128X1D (
 endmodule
 
 module SRL16E (
-  output Q,
+  (* abc_flop_q *) output Q,
   input A0, A1, A2, A3, CE, CLK, D
 );
   parameter [15:0] INIT = 16'h0000;
@@ -328,7 +332,7 @@ module SRL16E (
 endmodule
 
 module SRLC32E (
-  output Q,
+  (* abc_flop_q *) output Q,
   output Q31,
   input [4:0] A,
   input CE, CLK, D
diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc
index fa87a3ad6..5de2803e9 100644
--- a/techlibs/xilinx/synth_xilinx.cc
+++ b/techlibs/xilinx/synth_xilinx.cc
@@ -119,8 +119,8 @@ struct SynthXilinxPass : public Pass
 		log("        opt -fast\n");
 		log("\n");
 		log("    map_cells:\n");
+		log("        pmux2shiftx\n");
 		log("        simplemap t:$dff t:$dffe (without '-nosrl' only)\n");
-		log("        pmux2shiftx (without '-nosrl' only)\n");
 		log("        opt_expr -mux_undef (without '-nosrl' only)\n");
 		log("        shregmap -tech xilinx -minlen 3 (without '-nosrl' only)\n");
 		log("        techmap -map +/xilinx/cells_map.v\n");
@@ -288,14 +288,16 @@ struct SynthXilinxPass : public Pass
 
 		if (check_label(active, run_from, run_to, "map_cells"))
 		{
+			// shregmap -tech xilinx can cope with $shiftx and $mux
+			//   cells for identifying variable-length shift registers,
+			//   so attempt to convert $pmux-es to the former
+			// Also: wide multiplexers inference benefits from this too
+			Pass::call(design, "pmux2shiftx");
+
 			if (!nosrl) {
 				// shregmap operates on bit-level flops, not word-level,
 				//   so break those down here
 				Pass::call(design, "simplemap t:$dff t:$dffe");
-				// shregmap -tech xilinx can cope with $shiftx and $mux
-				//   cells for identifiying variable-length shift registers,
-				//   so attempt to convert $pmux-es to the former
-				Pass::call(design, "pmux2shiftx");
 				// pmux2shiftx can leave behind a $pmux with a single entry
 				//   -- need this to clean that up before shregmap
 				Pass::call(design, "opt_expr -mux_undef");
@@ -311,9 +313,8 @@ struct SynthXilinxPass : public Pass
 		{
 			Pass::call(design, "opt -full");
 			Pass::call(design, "techmap -map +/techmap.v -D _NO_POS_SR -map +/xilinx/ff_map.v");
-			Pass::call(design, "read_verilog +/xilinx/cells_box.v");
 			if (abc == "abc9")
-				Pass::call(design, abc + " -lut +/xilinx/cells.lut -box +/xilinx/cells.box" + string(retime ? " -dff" : ""));
+				Pass::call(design, abc + " -lut +/xilinx/abc.lut -box +/xilinx/abc.box" + string(retime ? " -dff" : ""));
 			else
 				Pass::call(design, abc + " -luts 2:2,3,6:5,10,20" + string(retime ? " -dff" : ""));
 			Pass::call(design, "clean");
-- 
cgit v1.2.3


From 75b96b1afff6062c936624c8d7ac19970299cd34 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Mon, 22 Apr 2019 12:36:15 -0700
Subject: Add synth_xilinx -nomux option

---
 techlibs/xilinx/cells_map.v     |  2 ++
 techlibs/xilinx/synth_xilinx.cc | 20 ++++++++++++++++----
 2 files changed, 18 insertions(+), 4 deletions(-)

(limited to 'techlibs')

diff --git a/techlibs/xilinx/cells_map.v b/techlibs/xilinx/cells_map.v
index 3c4d8f4cd..e71d4bafb 100644
--- a/techlibs/xilinx/cells_map.v
+++ b/techlibs/xilinx/cells_map.v
@@ -142,6 +142,7 @@ module \$__XILINX_SHREG_ (input C, input D, input [31:0] L, input E, output Q, o
   endgenerate
 endmodule
 
+`ifndef NO_MUXFN
 module \$shiftx (A, B, Y);
   parameter A_SIGNED = 0;
   parameter B_SIGNED = 0;
@@ -219,3 +220,4 @@ module \$shiftx (A, B, Y);
     end
   endgenerate
 endmodule
+`endif // NO_MUXFN
diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc
index 5de2803e9..04b0dabca 100644
--- a/techlibs/xilinx/synth_xilinx.cc
+++ b/techlibs/xilinx/synth_xilinx.cc
@@ -72,6 +72,9 @@ struct SynthXilinxPass : public Pass
 		log("    -nosrl\n");
 		log("        disable inference of shift registers\n");
 		log("\n");
+		log("    -nomux\n");
+		log("        disable inference of wide multiplexers\n");
+		log("\n");
 		log("    -run <from_label>:<to_label>\n");
 		log("        only run the commands between the labels (see below). an empty\n");
 		log("        from label is synonymous to 'begin', and empty to label is\n");
@@ -119,7 +122,7 @@ struct SynthXilinxPass : public Pass
 		log("        opt -fast\n");
 		log("\n");
 		log("    map_cells:\n");
-		log("        pmux2shiftx\n");
+		log("        pmux2shiftx (without '-nosrl' and '-nomux' only)\n");
 		log("        simplemap t:$dff t:$dffe (without '-nosrl' only)\n");
 		log("        opt_expr -mux_undef (without '-nosrl' only)\n");
 		log("        shregmap -tech xilinx -minlen 3 (without '-nosrl' only)\n");
@@ -161,6 +164,7 @@ struct SynthXilinxPass : public Pass
 		bool nobram = false;
 		bool nodram = false;
 		bool nosrl = false;
+		bool nomux = false;
 
 		size_t argidx;
 		for (argidx = 1; argidx < args.size(); argidx++)
@@ -209,6 +213,10 @@ struct SynthXilinxPass : public Pass
 				nosrl = true;
                 continue;
             }
+			if (args[argidx] == "-nomux") {
+				nomux = true;
+				continue;
+			}
 			if (args[argidx] == "-abc9") {
 				abc = "abc9";
 				continue;
@@ -291,8 +299,9 @@ struct SynthXilinxPass : public Pass
 			// shregmap -tech xilinx can cope with $shiftx and $mux
 			//   cells for identifying variable-length shift registers,
 			//   so attempt to convert $pmux-es to the former
-			// Also: wide multiplexers inference benefits from this too
-			Pass::call(design, "pmux2shiftx");
+			// Also: wide multiplexer inference benefits from this too
+			if (!nosrl || !nomux)
+				Pass::call(design, "pmux2shiftx");
 
 			if (!nosrl) {
 				// shregmap operates on bit-level flops, not word-level,
@@ -305,7 +314,10 @@ struct SynthXilinxPass : public Pass
 				Pass::call(design, "shregmap -tech xilinx -minlen 3");
 			}
 
-			Pass::call(design, "techmap -map +/xilinx/cells_map.v");
+			std::string define;
+			if (nomux)
+				define += " -D NO_MUXFN";
+			Pass::call(design, "techmap" + define + " -map +/xilinx/cells_map.v");
 			Pass::call(design, "clean");
 		}
 
-- 
cgit v1.2.3


From ac1e13819e9241eea0e047ecf396f3f4cd822a5b Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Mon, 22 Apr 2019 14:26:13 -0700
Subject: Fix for non-pow2 width muxes

---
 techlibs/xilinx/cells_map.v | 27 ++++++++++++++++++---------
 1 file changed, 18 insertions(+), 9 deletions(-)

(limited to 'techlibs')

diff --git a/techlibs/xilinx/cells_map.v b/techlibs/xilinx/cells_map.v
index e71d4bafb..87a14c961 100644
--- a/techlibs/xilinx/cells_map.v
+++ b/techlibs/xilinx/cells_map.v
@@ -78,7 +78,7 @@ module \$__XILINX_SHREG_ (input C, input D, input [31:0] L, input E, output Q, o
     end else
     if (DEPTH > 65 && DEPTH <= 96) begin
       wire T0, T1, T2, T3, T4, T5, T6;
-      SRLC32E #(.INIT(INIT_R[32-1:0]), .IS_CLK_INVERTED(~CLKPOL[0])) fpga_srl_0 (.A(L[4:0]), .CE(CE), .CLK(C), .D(D), .Q(T0), .Q31(T1));
+      SRLC32E #(.INIT(INIT_R[32-1: 0]), .IS_CLK_INVERTED(~CLKPOL[0])) fpga_srl_0 (.A(L[4:0]), .CE(CE), .CLK(C), .D( D), .Q(T0), .Q31(T1));
       SRLC32E #(.INIT(INIT_R[64-1:32]), .IS_CLK_INVERTED(~CLKPOL[0])) fpga_srl_1 (.A(L[4:0]), .CE(CE), .CLK(C), .D(T1), .Q(T2), .Q31(T3));
       \$__XILINX_SHREG_ #(.DEPTH(DEPTH-64), .INIT(INIT[DEPTH-64-1:0]), .CLKPOL(CLKPOL), .ENPOL(ENPOL)) fpga_srl_2 (.C(C), .D(T3), .L(L[4:0]), .E(E), .Q(T4));
       if (&_TECHMAP_CONSTMSK_L_)
@@ -91,7 +91,7 @@ module \$__XILINX_SHREG_ (input C, input D, input [31:0] L, input E, output Q, o
     end else
     if (DEPTH > 97 && DEPTH < 128) begin
       wire T0, T1, T2, T3, T4, T5, T6, T7, T8;
-      SRLC32E #(.INIT(INIT_R[32-1:0]), .IS_CLK_INVERTED(~CLKPOL[0])) fpga_srl_0 (.A(L[4:0]), .CE(CE), .CLK(C), .D(D), .Q(T0), .Q31(T1));
+      SRLC32E #(.INIT(INIT_R[32-1: 0]), .IS_CLK_INVERTED(~CLKPOL[0])) fpga_srl_0 (.A(L[4:0]), .CE(CE), .CLK(C), .D( D), .Q(T0), .Q31(T1));
       SRLC32E #(.INIT(INIT_R[64-1:32]), .IS_CLK_INVERTED(~CLKPOL[0])) fpga_srl_1 (.A(L[4:0]), .CE(CE), .CLK(C), .D(T1), .Q(T2), .Q31(T3));
       SRLC32E #(.INIT(INIT_R[96-1:64]), .IS_CLK_INVERTED(~CLKPOL[0])) fpga_srl_2 (.A(L[4:0]), .CE(CE), .CLK(C), .D(T3), .Q(T4), .Q31(T5));
       \$__XILINX_SHREG_ #(.DEPTH(DEPTH-96), .INIT(INIT[DEPTH-96-1:0]), .CLKPOL(CLKPOL), .ENPOL(ENPOL)) fpga_srl_3 (.C(C), .D(T5), .L(L[4:0]), .E(E), .Q(T6));
@@ -105,9 +105,9 @@ module \$__XILINX_SHREG_ (input C, input D, input [31:0] L, input E, output Q, o
     end
     else if (DEPTH == 128) begin
       wire T0, T1, T2, T3, T4, T5, T6;
-      SRLC32E #(.INIT(INIT_R[32-1:0]), .IS_CLK_INVERTED(~CLKPOL[0])) fpga_srl_0 (.A(L[4:0]), .CE(CE), .CLK(C), .D(D), .Q(T0), .Q31(T1));
-      SRLC32E #(.INIT(INIT_R[64-1:32]), .IS_CLK_INVERTED(~CLKPOL[0])) fpga_srl_1 (.A(L[4:0]), .CE(CE), .CLK(C), .D(T1), .Q(T2), .Q31(T3));
-      SRLC32E #(.INIT(INIT_R[96-1:64]), .IS_CLK_INVERTED(~CLKPOL[0])) fpga_srl_2 (.A(L[4:0]), .CE(CE), .CLK(C), .D(T3), .Q(T4), .Q31(T5));
+      SRLC32E #(.INIT(INIT_R[ 32-1: 0]), .IS_CLK_INVERTED(~CLKPOL[0])) fpga_srl_0 (.A(L[4:0]), .CE(CE), .CLK(C), .D( D), .Q(T0), .Q31(T1));
+      SRLC32E #(.INIT(INIT_R[ 64-1:32]), .IS_CLK_INVERTED(~CLKPOL[0])) fpga_srl_1 (.A(L[4:0]), .CE(CE), .CLK(C), .D(T1), .Q(T2), .Q31(T3));
+      SRLC32E #(.INIT(INIT_R[ 96-1:64]), .IS_CLK_INVERTED(~CLKPOL[0])) fpga_srl_2 (.A(L[4:0]), .CE(CE), .CLK(C), .D(T3), .Q(T4), .Q31(T5));
       SRLC32E #(.INIT(INIT_R[128-1:96]), .IS_CLK_INVERTED(~CLKPOL[0])) fpga_srl_3 (.A(L[4:0]), .CE(CE), .CLK(C), .D(T5), .Q(T6), .Q31(SO));
       if (&_TECHMAP_CONSTMSK_L_)
         assign Q = T6;
@@ -157,6 +157,15 @@ module \$shiftx (A, B, Y);
   parameter [B_WIDTH-1:0] _TECHMAP_CONSTMSK_B_ = 0;
   parameter [B_WIDTH-1:0] _TECHMAP_CONSTVAL_B_ = 0;
 
+  function integer first_B_nonzero;
+    integer i;
+    begin
+      for (i = B_WIDTH-1; i >= 0; i--)
+        if (_TECHMAP_CONSTMSK_B_[i] == 1'b0 || _TECHMAP_CONSTVAL_B_ != 1'b0)
+          first_B_nonzero = i;
+    end
+  endfunction
+
   generate
     genvar i, j;
     if (B_SIGNED) begin
@@ -167,12 +176,12 @@ module \$shiftx (A, B, Y);
         wire _TECHMAP_FAIL_ = 1;
     end
     else if (Y_WIDTH > 1) begin
-      wire [$clog2(A_WIDTH/Y_WIDTH)-1:0] B_bitty = B/Y_WIDTH;
+      localparam inc = first_B_nonzero();
       for (i = 0; i < Y_WIDTH; i++) begin
         wire [A_WIDTH/Y_WIDTH-1:0] A_i;
-        for (j = 0; j < A_WIDTH/Y_WIDTH; j++)
-          assign A_i[j] = A[j*Y_WIDTH+i];
-        \$shiftx  #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(A_WIDTH/Y_WIDTH), .B_WIDTH($clog2(A_WIDTH/Y_WIDTH)), .Y_WIDTH(1)) bitblast (.A(A_i), .B(B_bitty), .Y(Y[i]));
+        for (j = 0; j*(1<<inc)+i < A_WIDTH; j++)
+          assign A_i[j] = A[j*(1<<inc)+i];
+        \$shiftx  #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(A_WIDTH/Y_WIDTH), .B_WIDTH(B_WIDTH-inc), .Y_WIDTH(1'b1)) bitblast (.A(A_i), .B(B[B_WIDTH-1:inc]), .Y(Y[i]));
       end
     end
     else if (B_WIDTH < 3) begin
-- 
cgit v1.2.3


From 61161faefc731bfbb5b68b2458fbf7e087b16d78 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Mon, 22 Apr 2019 16:56:18 -0700
Subject: Fix for mux_case_* mappings

---
 techlibs/xilinx/cells_map.v | 26 +++++++++-----------------
 1 file changed, 9 insertions(+), 17 deletions(-)

(limited to 'techlibs')

diff --git a/techlibs/xilinx/cells_map.v b/techlibs/xilinx/cells_map.v
index 87a14c961..1def7b973 100644
--- a/techlibs/xilinx/cells_map.v
+++ b/techlibs/xilinx/cells_map.v
@@ -157,32 +157,24 @@ module \$shiftx (A, B, Y);
   parameter [B_WIDTH-1:0] _TECHMAP_CONSTMSK_B_ = 0;
   parameter [B_WIDTH-1:0] _TECHMAP_CONSTVAL_B_ = 0;
 
-  function integer first_B_nonzero;
-    integer i;
-    begin
-      for (i = B_WIDTH-1; i >= 0; i--)
-        if (_TECHMAP_CONSTMSK_B_[i] == 1'b0 || _TECHMAP_CONSTVAL_B_ != 1'b0)
-          first_B_nonzero = i;
-    end
-  endfunction
-
   generate
     genvar i, j;
     if (B_SIGNED) begin
       if (_TECHMAP_CONSTMSK_B_[B_WIDTH-1] && _TECHMAP_CONSTVAL_B_[B_WIDTH-1] == 1'b0)
         // Optimisation to remove B_SIGNED if sign bit of B is constant-0
-        \$shiftx  #(.A_SIGNED(A_SIGNED), .B_SIGNED(0), .A_WIDTH(A_WIDTH), .B_WIDTH(B_WIDTH-1), .Y_WIDTH(Y_WIDTH)) _TECHMAP_REPLACE_ (.A(A), .B(B[B_WIDTH-2:0]), .Y(Y));
+        \$shiftx  #(.A_SIGNED(A_SIGNED), .B_SIGNED(0), .A_WIDTH(A_WIDTH), .B_WIDTH(B_WIDTH-1'd1), .Y_WIDTH(Y_WIDTH)) _TECHMAP_REPLACE_ (.A(A), .B(B[B_WIDTH-2:0]), .Y(Y));
       else
         wire _TECHMAP_FAIL_ = 1;
     end
     else if (Y_WIDTH > 1) begin
-      localparam inc = first_B_nonzero();
-      for (i = 0; i < Y_WIDTH; i++) begin
-        wire [A_WIDTH/Y_WIDTH-1:0] A_i;
-        for (j = 0; j*(1<<inc)+i < A_WIDTH; j++)
-          assign A_i[j] = A[j*(1<<inc)+i];
-        \$shiftx  #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(A_WIDTH/Y_WIDTH), .B_WIDTH(B_WIDTH-inc), .Y_WIDTH(1'b1)) bitblast (.A(A_i), .B(B[B_WIDTH-1:inc]), .Y(Y[i]));
-      end
+      for (i = 0; i < Y_WIDTH; i++)
+        \$shiftx  #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(A_WIDTH), .B_WIDTH(B_WIDTH), .Y_WIDTH(1'd1)) bitblast (.A({{i{1'bx}}, A[A_WIDTH-1:i]}), .B(B), .Y(Y[i]));
+    end
+    else if (_TECHMAP_CONSTMSK_B_[0] && !_TECHMAP_CONSTVAL_B_[0]) begin
+      wire [(A_WIDTH+1)/2-1:0] A_i;
+      for (i = 0; i < (A_WIDTH+1)/2; i++)
+        assign A_i[i] = A[i*2];
+      \$shiftx  #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH((A_WIDTH+1'd1)/2'd2), .B_WIDTH(B_WIDTH-1'd1), .Y_WIDTH(Y_WIDTH)) _TECHMAP_REPLACE_ (.A(A_i), .B(B[B_WIDTH-1:1]), .Y(Y));
     end
     else if (B_WIDTH < 3) begin
       wire _TECHMAP_FAIL_ = 1;
-- 
cgit v1.2.3


From 69863f7698853d502f6d9bf810fcfda8fce87e6e Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Mon, 22 Apr 2019 16:58:44 -0700
Subject: Add comment

---
 techlibs/xilinx/cells_map.v | 3 +++
 1 file changed, 3 insertions(+)

(limited to 'techlibs')

diff --git a/techlibs/xilinx/cells_map.v b/techlibs/xilinx/cells_map.v
index 1def7b973..38c8a49e7 100644
--- a/techlibs/xilinx/cells_map.v
+++ b/techlibs/xilinx/cells_map.v
@@ -170,6 +170,9 @@ module \$shiftx (A, B, Y);
       for (i = 0; i < Y_WIDTH; i++)
         \$shiftx  #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(A_WIDTH), .B_WIDTH(B_WIDTH), .Y_WIDTH(1'd1)) bitblast (.A({{i{1'bx}}, A[A_WIDTH-1:i]}), .B(B), .Y(Y[i]));
     end
+    // If the LSB of B is constant zero (and Y_WIDTH is 1) then
+    //   we can optimise by removing every other entry from A
+    //   and popping the constant zero from B
     else if (_TECHMAP_CONSTMSK_B_[0] && !_TECHMAP_CONSTVAL_B_[0]) begin
       wire [(A_WIDTH+1)/2-1:0] A_i;
       for (i = 0; i < (A_WIDTH+1)/2; i++)
-- 
cgit v1.2.3


From 1fa2c36fbd98ff8d748a70c4cb352fa1c6070dae Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Mon, 22 Apr 2019 17:14:11 -0700
Subject: Trim A_WIDTH by Y_WIDTH-1

---
 techlibs/xilinx/cells_map.v | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'techlibs')

diff --git a/techlibs/xilinx/cells_map.v b/techlibs/xilinx/cells_map.v
index 38c8a49e7..60bc08b48 100644
--- a/techlibs/xilinx/cells_map.v
+++ b/techlibs/xilinx/cells_map.v
@@ -168,7 +168,7 @@ module \$shiftx (A, B, Y);
     end
     else if (Y_WIDTH > 1) begin
       for (i = 0; i < Y_WIDTH; i++)
-        \$shiftx  #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(A_WIDTH), .B_WIDTH(B_WIDTH), .Y_WIDTH(1'd1)) bitblast (.A({{i{1'bx}}, A[A_WIDTH-1:i]}), .B(B), .Y(Y[i]));
+        \$shiftx  #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(A_WIDTH-Y_WIDTH+1), .B_WIDTH(B_WIDTH), .Y_WIDTH(1'd1)) bitblast (.A(A[A_WIDTH-Y_WIDTH+i:i]), .B(B), .Y(Y[i]));
     end
     // If the LSB of B is constant zero (and Y_WIDTH is 1) then
     //   we can optimise by removing every other entry from A
-- 
cgit v1.2.3


From 26e461f47da12b79e5b6682f692d81e2721ca0c0 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Mon, 22 Apr 2019 17:58:28 -0700
Subject: Fix for A_WIDTH == 2 but B_WIDTH==3

---
 techlibs/xilinx/cells_map.v | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'techlibs')

diff --git a/techlibs/xilinx/cells_map.v b/techlibs/xilinx/cells_map.v
index 60bc08b48..10dbb8b9a 100644
--- a/techlibs/xilinx/cells_map.v
+++ b/techlibs/xilinx/cells_map.v
@@ -179,7 +179,7 @@ module \$shiftx (A, B, Y);
         assign A_i[i] = A[i*2];
       \$shiftx  #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH((A_WIDTH+1'd1)/2'd2), .B_WIDTH(B_WIDTH-1'd1), .Y_WIDTH(Y_WIDTH)) _TECHMAP_REPLACE_ (.A(A_i), .B(B[B_WIDTH-1:1]), .Y(Y));
     end
-    else if (B_WIDTH < 3) begin
+    else if (B_WIDTH < 3 || A_WIDTH == 2**2) begin
       wire _TECHMAP_FAIL_ = 1;
     end
     else if (B_WIDTH == 3) begin
-- 
cgit v1.2.3


From 60026842b20e04affe60a7871fd14bb544add37b Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Mon, 22 Apr 2019 17:59:56 -0700
Subject: Tweak

---
 techlibs/xilinx/cells_map.v | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'techlibs')

diff --git a/techlibs/xilinx/cells_map.v b/techlibs/xilinx/cells_map.v
index 10dbb8b9a..4275c03e6 100644
--- a/techlibs/xilinx/cells_map.v
+++ b/techlibs/xilinx/cells_map.v
@@ -179,7 +179,7 @@ module \$shiftx (A, B, Y);
         assign A_i[i] = A[i*2];
       \$shiftx  #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH((A_WIDTH+1'd1)/2'd2), .B_WIDTH(B_WIDTH-1'd1), .Y_WIDTH(Y_WIDTH)) _TECHMAP_REPLACE_ (.A(A_i), .B(B[B_WIDTH-1:1]), .Y(Y));
     end
-    else if (B_WIDTH < 3 || A_WIDTH == 2**2) begin
+    else if (B_WIDTH < 3 || A_WIDTH <= 4) begin
       wire _TECHMAP_FAIL_ = 1;
     end
     else if (B_WIDTH == 3) begin
-- 
cgit v1.2.3


From f96d82a5f1982ea86cf02182b33abe91c015b10d Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Wed, 24 Apr 2019 16:46:41 -0700
Subject: Add -nocarry option to synth_xilinx

---
 techlibs/xilinx/synth_xilinx.cc | 19 ++++++++++++++-----
 1 file changed, 14 insertions(+), 5 deletions(-)

(limited to 'techlibs')

diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc
index 04b0dabca..9e4a86a84 100644
--- a/techlibs/xilinx/synth_xilinx.cc
+++ b/techlibs/xilinx/synth_xilinx.cc
@@ -63,6 +63,9 @@ struct SynthXilinxPass : public Pass
 		log("        generate an output netlist (and BLIF file) suitable for VPR\n");
 		log("        (this feature is experimental and incomplete)\n");
 		log("\n");
+		log("    -nocarry\n");
+		log("        disable inference of carry chains\n");
+		log("\n");
 		log("    -nobram\n");
 		log("        disable inference of block rams\n");
 		log("\n");
@@ -118,7 +121,7 @@ struct SynthXilinxPass : public Pass
 		log("        memory_map\n");
 		log("        dffsr2dff\n");
 		log("        dff2dffe\n");
-		log("        techmap -map +/xilinx/arith_map.v\n");
+		log("        techmap -map +/xilinx/arith_map.v (without '-nocarry' only)\n");
 		log("        opt -fast\n");
 		log("\n");
 		log("    map_cells:\n");
@@ -161,6 +164,7 @@ struct SynthXilinxPass : public Pass
 		bool flatten = false;
 		bool retime = false;
 		bool vpr = false;
+		bool nocarry = false;
 		bool nobram = false;
 		bool nodram = false;
 		bool nosrl = false;
@@ -201,6 +205,10 @@ struct SynthXilinxPass : public Pass
 				vpr = true;
 				continue;
 			}
+			if (args[argidx] == "-nocarry") {
+				nocarry = true;
+				continue;
+			}
 			if (args[argidx] == "-nobram") {
 				nobram = true;
 				continue;
@@ -284,10 +292,11 @@ struct SynthXilinxPass : public Pass
 			Pass::call(design, "dffsr2dff");
 			Pass::call(design, "dff2dffe");
 
-			if (vpr) {
-				Pass::call(design, "techmap -map +/xilinx/arith_map.v -D _EXPLICIT_CARRY");
-			} else {
-				Pass::call(design, "techmap -map +/xilinx/arith_map.v");
+			if (!nocarry) {
+				if (vpr)
+					Pass::call(design, "techmap -map +/xilinx/arith_map.v -D _EXPLICIT_CARRY");
+				else
+					Pass::call(design, "techmap -map +/xilinx/arith_map.v");
 			}
 
 			Pass::call(design, "hierarchy -check");
-- 
cgit v1.2.3


From feff9764540cbf1152459cb377fc68d8e10c7153 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Thu, 25 Apr 2019 17:11:18 -0700
Subject: synth_xilinx to call bitblast_shiftx

---
 techlibs/xilinx/synth_xilinx.cc | 5 ++++-
 1 file changed, 4 insertions(+), 1 deletion(-)

(limited to 'techlibs')

diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc
index 9e4a86a84..d787687aa 100644
--- a/techlibs/xilinx/synth_xilinx.cc
+++ b/techlibs/xilinx/synth_xilinx.cc
@@ -126,6 +126,7 @@ struct SynthXilinxPass : public Pass
 		log("\n");
 		log("    map_cells:\n");
 		log("        pmux2shiftx (without '-nosrl' and '-nomux' only)\n");
+		log("        bitblast_shiftx (without '-nosrl' and '-nomux' only)\n");
 		log("        simplemap t:$dff t:$dffe (without '-nosrl' only)\n");
 		log("        opt_expr -mux_undef (without '-nosrl' only)\n");
 		log("        shregmap -tech xilinx -minlen 3 (without '-nosrl' only)\n");
@@ -309,8 +310,10 @@ struct SynthXilinxPass : public Pass
 			//   cells for identifying variable-length shift registers,
 			//   so attempt to convert $pmux-es to the former
 			// Also: wide multiplexer inference benefits from this too
-			if (!nosrl || !nomux)
+			if (!nosrl || !nomux) {
 				Pass::call(design, "pmux2shiftx");
+				Pass::call(design, "bitblast_shiftx");
+			}
 
 			if (!nosrl) {
 				// shregmap operates on bit-level flops, not word-level,
-- 
cgit v1.2.3


From 019c48b5083f065d3485b5c9e5c8d4b4554f3af3 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Thu, 25 Apr 2019 19:38:35 -0700
Subject: bitblast_shiftx -> split_shiftx

---
 techlibs/xilinx/synth_xilinx.cc | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

(limited to 'techlibs')

diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc
index d787687aa..f65ae87f5 100644
--- a/techlibs/xilinx/synth_xilinx.cc
+++ b/techlibs/xilinx/synth_xilinx.cc
@@ -126,7 +126,7 @@ struct SynthXilinxPass : public Pass
 		log("\n");
 		log("    map_cells:\n");
 		log("        pmux2shiftx (without '-nosrl' and '-nomux' only)\n");
-		log("        bitblast_shiftx (without '-nosrl' and '-nomux' only)\n");
+		log("        split_shiftx (without '-nosrl' and '-nomux' only)\n");
 		log("        simplemap t:$dff t:$dffe (without '-nosrl' only)\n");
 		log("        opt_expr -mux_undef (without '-nosrl' only)\n");
 		log("        shregmap -tech xilinx -minlen 3 (without '-nosrl' only)\n");
@@ -312,7 +312,7 @@ struct SynthXilinxPass : public Pass
 			// Also: wide multiplexer inference benefits from this too
 			if (!nosrl || !nomux) {
 				Pass::call(design, "pmux2shiftx");
-				Pass::call(design, "bitblast_shiftx");
+				Pass::call(design, "split_shiftx");
 			}
 
 			if (!nosrl) {
-- 
cgit v1.2.3


From f14d7f0df65c6892b911c74e1674a94ad3e556db Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Thu, 25 Apr 2019 19:43:41 -0700
Subject: Cleanup superseded

---
 techlibs/xilinx/cells_map.v | 12 +-----------
 1 file changed, 1 insertion(+), 11 deletions(-)

(limited to 'techlibs')

diff --git a/techlibs/xilinx/cells_map.v b/techlibs/xilinx/cells_map.v
index 4275c03e6..c814f3a96 100644
--- a/techlibs/xilinx/cells_map.v
+++ b/techlibs/xilinx/cells_map.v
@@ -167,17 +167,7 @@ module \$shiftx (A, B, Y);
         wire _TECHMAP_FAIL_ = 1;
     end
     else if (Y_WIDTH > 1) begin
-      for (i = 0; i < Y_WIDTH; i++)
-        \$shiftx  #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(A_WIDTH-Y_WIDTH+1), .B_WIDTH(B_WIDTH), .Y_WIDTH(1'd1)) bitblast (.A(A[A_WIDTH-Y_WIDTH+i:i]), .B(B), .Y(Y[i]));
-    end
-    // If the LSB of B is constant zero (and Y_WIDTH is 1) then
-    //   we can optimise by removing every other entry from A
-    //   and popping the constant zero from B
-    else if (_TECHMAP_CONSTMSK_B_[0] && !_TECHMAP_CONSTVAL_B_[0]) begin
-      wire [(A_WIDTH+1)/2-1:0] A_i;
-      for (i = 0; i < (A_WIDTH+1)/2; i++)
-        assign A_i[i] = A[i*2];
-      \$shiftx  #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH((A_WIDTH+1'd1)/2'd2), .B_WIDTH(B_WIDTH-1'd1), .Y_WIDTH(Y_WIDTH)) _TECHMAP_REPLACE_ (.A(A_i), .B(B[B_WIDTH-1:1]), .Y(Y));
+      wire _TECHMAP_FAIL_ = 1;
     end
     else if (B_WIDTH < 3 || A_WIDTH <= 4) begin
       wire _TECHMAP_FAIL_ = 1;
-- 
cgit v1.2.3


From 8469d9fe9ff0a819c6b67aa6121cfd01cd1d0665 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Fri, 26 Apr 2019 14:51:37 -0700
Subject: Missing newline

---
 techlibs/xilinx/synth_xilinx.cc | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'techlibs')

diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc
index f65ae87f5..b6b22284c 100644
--- a/techlibs/xilinx/synth_xilinx.cc
+++ b/techlibs/xilinx/synth_xilinx.cc
@@ -139,7 +139,7 @@ struct SynthXilinxPass : public Pass
 		log("        abc -luts 2:2,3,6:5,10,20 [-dff]\n");
 		log("        clean\n");
 		log("        shregmap -minlen 3 -init -params -enpol any_or_none (without '-nosrl' only)\n");
-		log("        techmap -map +/xilinx/lut_map.v -map +/xilinx/ff_map.v -map +/xilinx/cells_map.v");
+		log("        techmap -map +/xilinx/lut_map.v -map +/xilinx/ff_map.v -map +/xilinx/cells_map.v\n");
 		log("        dffinit -ff FDRE   Q INIT -ff FDCE   Q INIT -ff FDPE   Q INIT -ff FDSE   Q INIT \\\n");
 		log("                -ff FDRE_1 Q INIT -ff FDCE_1 Q INIT -ff FDPE_1 Q INIT -ff FDSE_1 Q INIT\n");
 		log("\n");
-- 
cgit v1.2.3


From 6b9ca7cd6d14ac5e3ebf8354849a5c31d9a3a49b Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Fri, 26 Apr 2019 15:32:58 -0700
Subject: Remove split_shiftx call

---
 techlibs/xilinx/synth_xilinx.cc | 5 +----
 1 file changed, 1 insertion(+), 4 deletions(-)

(limited to 'techlibs')

diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc
index b6b22284c..1320673e5 100644
--- a/techlibs/xilinx/synth_xilinx.cc
+++ b/techlibs/xilinx/synth_xilinx.cc
@@ -126,7 +126,6 @@ struct SynthXilinxPass : public Pass
 		log("\n");
 		log("    map_cells:\n");
 		log("        pmux2shiftx (without '-nosrl' and '-nomux' only)\n");
-		log("        split_shiftx (without '-nosrl' and '-nomux' only)\n");
 		log("        simplemap t:$dff t:$dffe (without '-nosrl' only)\n");
 		log("        opt_expr -mux_undef (without '-nosrl' only)\n");
 		log("        shregmap -tech xilinx -minlen 3 (without '-nosrl' only)\n");
@@ -310,10 +309,8 @@ struct SynthXilinxPass : public Pass
 			//   cells for identifying variable-length shift registers,
 			//   so attempt to convert $pmux-es to the former
 			// Also: wide multiplexer inference benefits from this too
-			if (!nosrl || !nomux) {
+			if (!nosrl || !nomux)
 				Pass::call(design, "pmux2shiftx");
-				Pass::call(design, "split_shiftx");
-			}
 
 			if (!nosrl) {
 				// shregmap operates on bit-level flops, not word-level,
-- 
cgit v1.2.3


From e31e21766d3bf323ce61754a28ac58ec7118b9c0 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Fri, 26 Apr 2019 16:09:54 -0700
Subject: Try a different approach with 'muxcover'

---
 techlibs/xilinx/cells_map.v     | 82 ++++++++---------------------------------
 techlibs/xilinx/synth_xilinx.cc | 42 ++++++++++-----------
 2 files changed, 36 insertions(+), 88 deletions(-)

(limited to 'techlibs')

diff --git a/techlibs/xilinx/cells_map.v b/techlibs/xilinx/cells_map.v
index c814f3a96..258b6c3de 100644
--- a/techlibs/xilinx/cells_map.v
+++ b/techlibs/xilinx/cells_map.v
@@ -143,75 +143,23 @@ module \$__XILINX_SHREG_ (input C, input D, input [31:0] L, input E, output Q, o
 endmodule
 
 `ifndef NO_MUXFN
-module \$shiftx (A, B, Y);
-  parameter A_SIGNED = 0;
-  parameter B_SIGNED = 0;
-  parameter A_WIDTH = 1;
-  parameter B_WIDTH = 1;
-  parameter Y_WIDTH = 1;
+module \$_MUX8_ (A, B, C, D, E, F, G, H, S, T, U, Y);
+    input A, B, C, D, E, F, G, H, S, T, U;
+    output Y;
 
-  input [A_WIDTH-1:0] A;
-  input [B_WIDTH-1:0] B;
-  output [Y_WIDTH-1:0] Y;
+	wire [1:0] Z;
+    assign Z = T ? (S ? {D,H} : {C,G}) :
+                   (S ? {B,F} : {A,E});
+    MUXF7 fpga_muxf7 (.I0(Z[0]), .I1(Z[1]), .S(U), .O(Y));
+endmodule
 
-  parameter [B_WIDTH-1:0] _TECHMAP_CONSTMSK_B_ = 0;
-  parameter [B_WIDTH-1:0] _TECHMAP_CONSTVAL_B_ = 0;
+module \$_MUX16_ (A, B, C, D, E, F, G, H, I, J, K, L, M, N, O, P, S, T, U, V, Y);
+    input A, B, C, D, E, F, G, H, I, J, K, L, M, N, O, P, S, T, U, V;
+    output Y;
 
-  generate
-    genvar i, j;
-    if (B_SIGNED) begin
-      if (_TECHMAP_CONSTMSK_B_[B_WIDTH-1] && _TECHMAP_CONSTVAL_B_[B_WIDTH-1] == 1'b0)
-        // Optimisation to remove B_SIGNED if sign bit of B is constant-0
-        \$shiftx  #(.A_SIGNED(A_SIGNED), .B_SIGNED(0), .A_WIDTH(A_WIDTH), .B_WIDTH(B_WIDTH-1'd1), .Y_WIDTH(Y_WIDTH)) _TECHMAP_REPLACE_ (.A(A), .B(B[B_WIDTH-2:0]), .Y(Y));
-      else
-        wire _TECHMAP_FAIL_ = 1;
-    end
-    else if (Y_WIDTH > 1) begin
-      wire _TECHMAP_FAIL_ = 1;
-    end
-    else if (B_WIDTH < 3 || A_WIDTH <= 4) begin
-      wire _TECHMAP_FAIL_ = 1;
-    end
-    else if (B_WIDTH == 3) begin
-      localparam a_width0 = 2 ** 2;
-      localparam a_widthN = A_WIDTH - a_width0;
-      wire T0, T1;
-      \$shiftx  #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(a_width0), .B_WIDTH(2),                .Y_WIDTH(Y_WIDTH)) fpga_shiftx      (.A(A[a_width0-1:0]),       .B(B[2-1:0]),                .Y(T0));
-      \$shiftx  #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(a_widthN), .B_WIDTH($clog2(a_widthN)), .Y_WIDTH(Y_WIDTH)) fpga_shiftx_last (.A(A[A_WIDTH-1:a_width0]), .B(B[$clog2(a_widthN)-1:0]), .Y(T1));
-      MUXF7 fpga_mux (.I0(T0), .I1(T1), .S(B[B_WIDTH-1]), .O(Y));
-    end
-    else if (B_WIDTH == 4) begin
-      localparam a_width0 = 2 ** 2;
-      localparam num_mux8 = A_WIDTH / a_width0;
-      localparam a_widthN = A_WIDTH - num_mux8*a_width0;
-      wire [4-1:0] T;
-      wire T0, T1;
-      for (i = 0; i < 4; i++)
-        if (i < num_mux8)
-          \$shiftx  #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(a_width0), .B_WIDTH(2),                .Y_WIDTH(Y_WIDTH)) fpga_shiftx      (.A(A[i*a_width0+:a_width0]), .B(B[2-1:0]),                .Y(T[i]));
-        else if (i == num_mux8 && a_widthN > 0)
-          \$shiftx  #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(a_widthN), .B_WIDTH($clog2(a_widthN)), .Y_WIDTH(Y_WIDTH)) fpga_shiftx_last (.A(A[A_WIDTH-1:i*a_width0]), .B(B[$clog2(a_widthN)-1:0]), .Y(T[i]));
-        else
-          assign T[i] = 1'bx;
-      MUXF7 fpga_mux_0 (.I0(T[0]), .I1(T[1]), .S(B[2]), .O(T0));
-      MUXF7 fpga_mux_1 (.I0(T[2]), .I1(T[3]), .S(B[2]), .O(T1));
-      MUXF8 fpga_mux_2 (.I0(T0),   .I1(T1),   .S(B[3]), .O(Y));
-    end
-    else begin
-      localparam a_width0 = 2 ** 4;
-      localparam num_mux16 = A_WIDTH / a_width0;
-      localparam a_widthN = A_WIDTH - num_mux16*a_width0;
-      wire [(2**(B_WIDTH-4))-1:0] T;
-      for (i = 0; i < 2 ** (B_WIDTH-4); i++)
-        if (i < num_mux16)
-          \$shiftx  #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(a_width0), .B_WIDTH(4),                .Y_WIDTH(Y_WIDTH)) fpga_shiftx      (.A(A[i*a_width0+:a_width0]), .B(B[4-1:0]),                .Y(T[i]));
-        else if (i == num_mux16 && a_widthN > 0) begin
-          \$shiftx  #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(a_widthN), .B_WIDTH($clog2(a_widthN)), .Y_WIDTH(Y_WIDTH)) fpga_shiftx_last (.A(A[A_WIDTH-1:i*a_width0]), .B(B[$clog2(a_widthN)-1:0]), .Y(T[i]));
-        end
-        else
-          assign T[i] = 1'bx;
-      \$shiftx  #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(2**(B_WIDTH-4)), .B_WIDTH(B_WIDTH-4), .Y_WIDTH(Y_WIDTH)) fpga_shiftx (.A(T), .B(B[B_WIDTH-1:4]), .Y(Y));
-    end
-  endgenerate
+	wire [1:0] Z;
+	\$_MUX8_ fpga_mux8_0 (.A(A), .B(B), .C(C), .D(D), .E(E), .F(F), .G(G), .H(H), .S(S), .T(T), .U(U), .Y(Z[0]));
+	\$_MUX8_ fpga_mux8_1 (.A(I), .B(J), .C(K), .D(L), .E(M), .F(N), .G(O), .H(P), .S(S), .T(T), .U(U), .Y(Z[1]));
+    MUXF8 fpga_muxf8 (.I0(Z[0]), .I1(Z[1]), .S(V), .O(Y));
 endmodule
 `endif // NO_MUXFN
diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc
index 524c54d3b..5652806f7 100644
--- a/techlibs/xilinx/synth_xilinx.cc
+++ b/techlibs/xilinx/synth_xilinx.cc
@@ -292,36 +292,37 @@ struct SynthXilinxPass : public Pass
 			Pass::call(design, "dffsr2dff");
 			Pass::call(design, "dff2dffe");
 
+			// shregmap -tech xilinx can cope with $shiftx and $mux
+			//   cells for identifying variable-length shift registers,
+			//   so attempt to convert $pmux-es to the former
+			// Also: wide multiplexer inference benefits from this too
+			if (!nosrl || !nomux)
+				Pass::call(design, "pmux2shiftx");
+
+			Pass::call(design, "opt -full");
 			if (!nocarry) {
 				if (vpr)
-					Pass::call(design, "techmap -map +/xilinx/arith_map.v -D _EXPLICIT_CARRY");
+					Pass::call(design, "techmap -map +/techmap.v  -D _EXPLICIT_CARRY -map +/xilinx/arith_map.v");
 				else
-					Pass::call(design, "techmap -map +/xilinx/arith_map.v");
+					Pass::call(design, "techmap -map +/techmap.v -map +/xilinx/arith_map.v");
+			}
+			else  {
+				Pass::call(design, "techmap");
 			}
+			Pass::call(design, "opt -fast");
+
+			// shregmap with '-tech xilinx' infers variable length shift regs
+			if (!nosrl)
+				Pass::call(design, "shregmap -tech xilinx -minlen 3");
+
+			if (!nomux)
+				Pass::call(design, "muxcover -mux8 -mux16");
 
 			Pass::call(design, "opt -fast");
 		}
 
 		if (check_label(active, run_from, run_to, "map_cells"))
 		{
-			// shregmap -tech xilinx can cope with $shiftx and $mux
-			//   cells for identifying variable-length shift registers,
-			//   so attempt to convert $pmux-es to the former
-			// Also: wide multiplexer inference benefits from this too
-			if (!nosrl || !nomux)
-				Pass::call(design, "pmux2shiftx");
-
-			if (!nosrl) {
-				// shregmap operates on bit-level flops, not word-level,
-				//   so break those down here
-				Pass::call(design, "simplemap t:$dff t:$dffe");
-				// pmux2shiftx can leave behind a $pmux with a single entry
-				//   -- need this to clean that up before shregmap
-				Pass::call(design, "opt_expr -mux_undef");
-				// shregmap with '-tech xilinx' infers variable length shift regs
-				Pass::call(design, "shregmap -tech xilinx -minlen 3");
-			}
-
 			std::string define;
 			if (nomux)
 				define += " -D NO_MUXFN";
@@ -331,7 +332,6 @@ struct SynthXilinxPass : public Pass
 
 		if (check_label(active, run_from, run_to, "map_luts"))
 		{
-			Pass::call(design, "opt -full");
 			Pass::call(design, "techmap -map +/techmap.v -D _NO_POS_SR -map +/xilinx/ff_map.v");
 			if (abc == "abc9")
 				Pass::call(design, abc + " -lut +/xilinx/abc.lut -box +/xilinx/abc.box" + string(retime ? " -dff" : ""));
-- 
cgit v1.2.3


From ccc283737d99cb0f4d5742692d5d86c4ad9396c6 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Fri, 26 Apr 2019 16:28:48 -0700
Subject: Apparently, this reduces number of MUXCY/XORCY

---
 techlibs/xilinx/synth_xilinx.cc | 19 +++++++++----------
 1 file changed, 9 insertions(+), 10 deletions(-)

(limited to 'techlibs')

diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc
index 5652806f7..4ec115bec 100644
--- a/techlibs/xilinx/synth_xilinx.cc
+++ b/techlibs/xilinx/synth_xilinx.cc
@@ -287,11 +287,18 @@ struct SynthXilinxPass : public Pass
 
 		if (check_label(active, run_from, run_to, "fine"))
 		{
-			Pass::call(design, "opt -fast");
+			Pass::call(design, "opt -fast -full");
 			Pass::call(design, "memory_map");
 			Pass::call(design, "dffsr2dff");
 			Pass::call(design, "dff2dffe");
 
+			if (!nocarry) {
+				if (vpr)
+					Pass::call(design, "techmap -D _EXPLICIT_CARRY -map +/xilinx/arith_map.v");
+				else
+					Pass::call(design, "techmap -map +/xilinx/arith_map.v");
+			}
+
 			// shregmap -tech xilinx can cope with $shiftx and $mux
 			//   cells for identifying variable-length shift registers,
 			//   so attempt to convert $pmux-es to the former
@@ -300,15 +307,7 @@ struct SynthXilinxPass : public Pass
 				Pass::call(design, "pmux2shiftx");
 
 			Pass::call(design, "opt -full");
-			if (!nocarry) {
-				if (vpr)
-					Pass::call(design, "techmap -map +/techmap.v  -D _EXPLICIT_CARRY -map +/xilinx/arith_map.v");
-				else
-					Pass::call(design, "techmap -map +/techmap.v -map +/xilinx/arith_map.v");
-			}
-			else  {
-				Pass::call(design, "techmap");
-			}
+			Pass::call(design, "techmap");
 			Pass::call(design, "opt -fast");
 
 			// shregmap with '-tech xilinx' infers variable length shift regs
-- 
cgit v1.2.3


From 4aca928033874e8e35ecc4a18f22475c00bebad9 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Fri, 26 Apr 2019 19:46:34 -0700
Subject: Fix spacing

---
 techlibs/xilinx/cells_map.v | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

(limited to 'techlibs')

diff --git a/techlibs/xilinx/cells_map.v b/techlibs/xilinx/cells_map.v
index 258b6c3de..6c280e0f1 100644
--- a/techlibs/xilinx/cells_map.v
+++ b/techlibs/xilinx/cells_map.v
@@ -147,7 +147,7 @@ module \$_MUX8_ (A, B, C, D, E, F, G, H, S, T, U, Y);
     input A, B, C, D, E, F, G, H, S, T, U;
     output Y;
 
-	wire [1:0] Z;
+    wire [1:0] Z;
     assign Z = T ? (S ? {D,H} : {C,G}) :
                    (S ? {B,F} : {A,E});
     MUXF7 fpga_muxf7 (.I0(Z[0]), .I1(Z[1]), .S(U), .O(Y));
@@ -157,9 +157,9 @@ module \$_MUX16_ (A, B, C, D, E, F, G, H, I, J, K, L, M, N, O, P, S, T, U, V, Y)
     input A, B, C, D, E, F, G, H, I, J, K, L, M, N, O, P, S, T, U, V;
     output Y;
 
-	wire [1:0] Z;
-	\$_MUX8_ fpga_mux8_0 (.A(A), .B(B), .C(C), .D(D), .E(E), .F(F), .G(G), .H(H), .S(S), .T(T), .U(U), .Y(Z[0]));
-	\$_MUX8_ fpga_mux8_1 (.A(I), .B(J), .C(K), .D(L), .E(M), .F(N), .G(O), .H(P), .S(S), .T(T), .U(U), .Y(Z[1]));
+    wire [1:0] Z;
+    \$_MUX8_ fpga_mux8_0 (.A(A), .B(B), .C(C), .D(D), .E(E), .F(F), .G(G), .H(H), .S(S), .T(T), .U(U), .Y(Z[0]));
+    \$_MUX8_ fpga_mux8_1 (.A(I), .B(J), .C(K), .D(L), .E(M), .F(N), .G(O), .H(P), .S(S), .T(T), .U(U), .Y(Z[1]));
     MUXF8 fpga_muxf8 (.I0(Z[0]), .I1(Z[1]), .S(V), .O(Y));
 endmodule
 `endif // NO_MUXFN
-- 
cgit v1.2.3


From 3b5e8c86a4516c202e877ee5ca154062682e15b9 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Thu, 2 May 2019 11:00:49 -0700
Subject: Fix -nocarry

---
 techlibs/xilinx/synth_xilinx.cc | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

(limited to 'techlibs')

diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc
index bde95c638..a0e77021a 100644
--- a/techlibs/xilinx/synth_xilinx.cc
+++ b/techlibs/xilinx/synth_xilinx.cc
@@ -241,10 +241,10 @@ struct SynthXilinxPass : public ScriptPass
 			run("dff2dffe");
 			run("opt -full");
 
-			if (!vpr || help_mode)
-				run("techmap -map +/xilinx/arith_map.v");
-			else
+			if (vpr && !nocarry && !help_mode)
 				run("techmap -map +/xilinx/arith_map.v -D _EXPLICIT_CARRY");
+			else if (!nocarry || help_mode)
+				run("techmap -map +/xilinx/arith_map.v", "(skip if '-nocarry')");
 
 			if (!nosrl || help_mode) {
 				// shregmap operates on bit-level flops, not word-level,
-- 
cgit v1.2.3


From d05ac7257e437466db0ce7f4c3264d8ad8e18fcd Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Thu, 2 May 2019 11:14:28 -0700
Subject: Missing help_mode

---
 techlibs/xilinx/synth_xilinx.cc | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'techlibs')

diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc
index a0e77021a..dd8b51818 100644
--- a/techlibs/xilinx/synth_xilinx.cc
+++ b/techlibs/xilinx/synth_xilinx.cc
@@ -232,7 +232,7 @@ struct SynthXilinxPass : public ScriptPass
 			//   cells for identifying variable-length shift registers,
 			//   so attempt to convert $pmux-es to the former
 			// Also: wide multiplexer inference benefits from this too
-			if (!nosrl || !nomux)
+			if (!nosrl || !nomux || help_mode)
 				run("pmux2shiftx", "(skip if '-nosrl' and '-nomux')");
 
 			run("opt -fast -full");
-- 
cgit v1.2.3


From 95867109ea4201d77a95a22f51cd3c4309ff8240 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Thu, 2 May 2019 11:25:10 -0700
Subject: Revert to pre-muxcover approach

---
 techlibs/xilinx/cells_map.v     | 94 +++++++++++++++++++++++++++++++++--------
 techlibs/xilinx/synth_xilinx.cc | 13 +++---
 2 files changed, 82 insertions(+), 25 deletions(-)

(limited to 'techlibs')

diff --git a/techlibs/xilinx/cells_map.v b/techlibs/xilinx/cells_map.v
index a80988480..0ec72b6a4 100644
--- a/techlibs/xilinx/cells_map.v
+++ b/techlibs/xilinx/cells_map.v
@@ -150,24 +150,84 @@ module \$__XILINX_SHREG_ (input C, input D, input [31:0] L, input E, output Q, o
   endgenerate
 endmodule
 
-`ifndef NO_MUXFN
-module \$_MUX8_ (A, B, C, D, E, F, G, H, S, T, U, Y);
-    input A, B, C, D, E, F, G, H, S, T, U;
-    output Y;
+module \$shiftx (A, B, Y);
+  parameter A_SIGNED = 0;
+  parameter B_SIGNED = 0;
+  parameter A_WIDTH = 1;
+  parameter B_WIDTH = 1;
+  parameter Y_WIDTH = 1;
 
-    wire [1:0] Z;
-    assign Z = T ? (S ? {D,H} : {C,G}) :
-                   (S ? {B,F} : {A,E});
-    MUXF7 fpga_muxf7 (.I0(Z[0]), .I1(Z[1]), .S(U), .O(Y));
-endmodule
+  input [A_WIDTH-1:0] A;
+  input [B_WIDTH-1:0] B;
+  output [Y_WIDTH-1:0] Y;
 
-module \$_MUX16_ (A, B, C, D, E, F, G, H, I, J, K, L, M, N, O, P, S, T, U, V, Y);
-    input A, B, C, D, E, F, G, H, I, J, K, L, M, N, O, P, S, T, U, V;
-    output Y;
+  parameter [B_WIDTH-1:0] _TECHMAP_CONSTMSK_B_ = 0;
+  parameter [B_WIDTH-1:0] _TECHMAP_CONSTVAL_B_ = 0;
 
-    wire [1:0] Z;
-    \$_MUX8_ fpga_mux8_0 (.A(A), .B(B), .C(C), .D(D), .E(E), .F(F), .G(G), .H(H), .S(S), .T(T), .U(U), .Y(Z[0]));
-    \$_MUX8_ fpga_mux8_1 (.A(I), .B(J), .C(K), .D(L), .E(M), .F(N), .G(O), .H(P), .S(S), .T(T), .U(U), .Y(Z[1]));
-    MUXF8 fpga_muxf8 (.I0(Z[0]), .I1(Z[1]), .S(V), .O(Y));
+  generate
+    genvar i, j;
+    if (B_SIGNED) begin
+      if (_TECHMAP_CONSTMSK_B_[B_WIDTH-1] && _TECHMAP_CONSTVAL_B_[B_WIDTH-1] == 1'b0)
+        // Optimisation to remove B_SIGNED if sign bit of B is constant-0
+        \$shiftx  #(.A_SIGNED(A_SIGNED), .B_SIGNED(0), .A_WIDTH(A_WIDTH), .B_WIDTH(B_WIDTH-1'd1), .Y_WIDTH(Y_WIDTH)) _TECHMAP_REPLACE_ (.A(A), .B(B[B_WIDTH-2:0]), .Y(Y));
+      else
+        wire _TECHMAP_FAIL_ = 1;
+    end
+    else if (Y_WIDTH > 1) begin
+      for (i = 0; i < Y_WIDTH; i++)
+        \$shiftx  #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(A_WIDTH-Y_WIDTH+1), .B_WIDTH(B_WIDTH), .Y_WIDTH(1'd1)) bitblast (.A(A[A_WIDTH-Y_WIDTH+i:i]), .B(B), .Y(Y[i]));
+    end
+    // If the LSB of B is constant zero (and Y_WIDTH is 1) then
+    //   we can optimise by removing every other entry from A
+    //   and popping the constant zero from B
+    else if (_TECHMAP_CONSTMSK_B_[0] && !_TECHMAP_CONSTVAL_B_[0]) begin
+      wire [(A_WIDTH+1)/2-1:0] A_i;
+      for (i = 0; i < (A_WIDTH+1)/2; i++)
+        assign A_i[i] = A[i*2];
+      \$shiftx  #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH((A_WIDTH+1'd1)/2'd2), .B_WIDTH(B_WIDTH-1'd1), .Y_WIDTH(Y_WIDTH)) _TECHMAP_REPLACE_ (.A(A_i), .B(B[B_WIDTH-1:1]), .Y(Y));
+    end
+    else if (B_WIDTH < 3 || A_WIDTH <= 4) begin
+      wire _TECHMAP_FAIL_ = 1;
+    end
+    else if (B_WIDTH == 3) begin
+      localparam a_width0 = 2 ** 2;
+      localparam a_widthN = A_WIDTH - a_width0;
+      wire T0, T1;
+      \$shiftx  #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(a_width0), .B_WIDTH(2),                .Y_WIDTH(Y_WIDTH)) fpga_shiftx      (.A(A[a_width0-1:0]),       .B(B[2-1:0]),                .Y(T0));
+      \$shiftx  #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(a_widthN), .B_WIDTH($clog2(a_widthN)), .Y_WIDTH(Y_WIDTH)) fpga_shiftx_last (.A(A[A_WIDTH-1:a_width0]), .B(B[$clog2(a_widthN)-1:0]), .Y(T1));
+      MUXF7 fpga_mux (.I0(T0), .I1(T1), .S(B[B_WIDTH-1]), .O(Y));
+    end
+    else if (B_WIDTH == 4) begin
+      localparam a_width0 = 2 ** 2;
+      localparam num_mux8 = A_WIDTH / a_width0;
+      localparam a_widthN = A_WIDTH - num_mux8*a_width0;
+      wire [4-1:0] T;
+      wire T0, T1;
+      for (i = 0; i < 4; i++)
+        if (i < num_mux8)
+          \$shiftx  #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(a_width0), .B_WIDTH(2),                .Y_WIDTH(Y_WIDTH)) fpga_shiftx      (.A(A[i*a_width0+:a_width0]), .B(B[2-1:0]),                .Y(T[i]));
+        else if (i == num_mux8 && a_widthN > 0)
+          \$shiftx  #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(a_widthN), .B_WIDTH($clog2(a_widthN)), .Y_WIDTH(Y_WIDTH)) fpga_shiftx_last (.A(A[A_WIDTH-1:i*a_width0]), .B(B[$clog2(a_widthN)-1:0]), .Y(T[i]));
+        else
+          assign T[i] = 1'bx;
+      MUXF7 fpga_mux_0 (.I0(T[0]), .I1(T[1]), .S(B[2]), .O(T0));
+      MUXF7 fpga_mux_1 (.I0(T[2]), .I1(T[3]), .S(B[2]), .O(T1));
+      MUXF8 fpga_mux_2 (.I0(T0),   .I1(T1),   .S(B[3]), .O(Y));
+    end
+    else begin
+      localparam a_width0 = 2 ** 4;
+      localparam num_mux16 = A_WIDTH / a_width0;
+      localparam a_widthN = A_WIDTH - num_mux16*a_width0;
+      wire [(2**(B_WIDTH-4))-1:0] T;
+      for (i = 0; i < 2 ** (B_WIDTH-4); i++)
+        if (i < num_mux16)
+          \$shiftx  #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(a_width0), .B_WIDTH(4),                .Y_WIDTH(Y_WIDTH)) fpga_shiftx      (.A(A[i*a_width0+:a_width0]), .B(B[4-1:0]),                .Y(T[i]));
+        else if (i == num_mux16 && a_widthN > 0) begin
+          \$shiftx  #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(a_widthN), .B_WIDTH($clog2(a_widthN)), .Y_WIDTH(Y_WIDTH)) fpga_shiftx_last (.A(A[A_WIDTH-1:i*a_width0]), .B(B[$clog2(a_widthN)-1:0]), .Y(T[i]));
+        end
+        else
+          assign T[i] = 1'bx;
+      \$shiftx  #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(2**(B_WIDTH-4)), .B_WIDTH(B_WIDTH-4), .Y_WIDTH(Y_WIDTH)) fpga_shiftx (.A(T), .B(B[B_WIDTH-1:4]), .Y(Y));
+    end
+  endgenerate
 endmodule
-`endif // NO_MUXFN
diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc
index dd8b51818..7d7a05616 100644
--- a/techlibs/xilinx/synth_xilinx.cc
+++ b/techlibs/xilinx/synth_xilinx.cc
@@ -232,7 +232,7 @@ struct SynthXilinxPass : public ScriptPass
 			//   cells for identifying variable-length shift registers,
 			//   so attempt to convert $pmux-es to the former
 			// Also: wide multiplexer inference benefits from this too
-			if (!nosrl || !nomux || help_mode)
+			if ((!nosrl && !nomux) || help_mode)
 				run("pmux2shiftx", "(skip if '-nosrl' and '-nomux')");
 
 			run("opt -fast -full");
@@ -254,18 +254,15 @@ struct SynthXilinxPass : public ScriptPass
 				run("shregmap -tech xilinx -minlen 3", "(skip if '-nosrl')");
 			}
 
+			if (!nomux || help_mode)
+				run("techmap -map +/xilinx/cells_map.v");
+
 			run("techmap");
 			run("opt -fast");
-
-			if (!nomux || help_mode)
-				run("muxcover -mux8 -mux16");
 		}
 
 		if (check_label("map_cells")) {
-			std::string define;
-			if (nomux)
-				define += " -D NO_MUXFN";
-			run("techmap -map +/techmap.v -map +/xilinx/cells_map.v" + define);
+			run("techmap -map +/techmap.v -map +/xilinx/cells_map.v");
 			run("clean");
 		}
 
-- 
cgit v1.2.3


From d80445e0492c67b63435880b3bca4ccbf6f3db43 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Thu, 2 May 2019 11:35:57 -0700
Subject: Use new peepopt from #969

---
 techlibs/xilinx/synth_xilinx.cc | 25 +++++++++++++++----------
 1 file changed, 15 insertions(+), 10 deletions(-)

(limited to 'techlibs')

diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc
index 7d7a05616..a1c4acf7e 100644
--- a/techlibs/xilinx/synth_xilinx.cc
+++ b/techlibs/xilinx/synth_xilinx.cc
@@ -211,6 +211,18 @@ struct SynthXilinxPass : public ScriptPass
 
 		if (check_label("coarse")) {
 			run("synth -run coarse");
+
+			// shregmap -tech xilinx can cope with $shiftx and $mux
+			//   cells for identifying variable-length shift registers,
+			//   so attempt to convert $pmux-es to the former
+			// Also: wide multiplexer inference benefits from this too
+			if ((!nosrl && !nomux) || help_mode)
+				run("pmux2shiftx", "(skip if '-nosrl' and '-nomux')");
+
+			// Run a number of peephole optimisations, including one
+			//   that optimises $mul cells driving $shiftx's B input
+			//   and that aids wide mux analysis
+			run("peepopt");
 		}
 
 		if (check_label("bram", "(skip if '-nobram')")) {
@@ -228,13 +240,6 @@ struct SynthXilinxPass : public ScriptPass
 		}
 
 		if (check_label("fine")) {
-			// shregmap -tech xilinx can cope with $shiftx and $mux
-			//   cells for identifying variable-length shift registers,
-			//   so attempt to convert $pmux-es to the former
-			// Also: wide multiplexer inference benefits from this too
-			if ((!nosrl && !nomux) || help_mode)
-				run("pmux2shiftx", "(skip if '-nosrl' and '-nomux')");
-
 			run("opt -fast -full");
 			run("memory_map");
 			run("dffsr2dff");
@@ -246,6 +251,9 @@ struct SynthXilinxPass : public ScriptPass
 			else if (!nocarry || help_mode)
 				run("techmap -map +/xilinx/arith_map.v", "(skip if '-nocarry')");
 
+			if (!nomux || help_mode)
+				run("techmap -map +/xilinx/cells_map.v");
+
 			if (!nosrl || help_mode) {
 				// shregmap operates on bit-level flops, not word-level,
 				//   so break those down here
@@ -254,9 +262,6 @@ struct SynthXilinxPass : public ScriptPass
 				run("shregmap -tech xilinx -minlen 3", "(skip if '-nosrl')");
 			}
 
-			if (!nomux || help_mode)
-				run("techmap -map +/xilinx/cells_map.v");
-
 			run("techmap");
 			run("opt -fast");
 		}
-- 
cgit v1.2.3


From fc72f07efdfbc1b87c4838af6138cdaa3cfd97ff Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Thu, 2 May 2019 15:01:37 -0700
Subject: Add don't care optimisation

---
 techlibs/xilinx/cells_map.v | 11 +++++++++++
 1 file changed, 11 insertions(+)

(limited to 'techlibs')

diff --git a/techlibs/xilinx/cells_map.v b/techlibs/xilinx/cells_map.v
index 0ec72b6a4..ecfbe2555 100644
--- a/techlibs/xilinx/cells_map.v
+++ b/techlibs/xilinx/cells_map.v
@@ -161,11 +161,14 @@ module \$shiftx (A, B, Y);
   input [B_WIDTH-1:0] B;
   output [Y_WIDTH-1:0] Y;
 
+  parameter [A_WIDTH-1:0] _TECHMAP_CONSTMSK_A_ = 0;
+  parameter [A_WIDTH-1:0] _TECHMAP_CONSTVAL_A_ = 0;
   parameter [B_WIDTH-1:0] _TECHMAP_CONSTMSK_B_ = 0;
   parameter [B_WIDTH-1:0] _TECHMAP_CONSTVAL_B_ = 0;
 
   generate
     genvar i, j;
+    // TODO: Check if this opt still necessary
     if (B_SIGNED) begin
       if (_TECHMAP_CONSTMSK_B_[B_WIDTH-1] && _TECHMAP_CONSTVAL_B_[B_WIDTH-1] == 1'b0)
         // Optimisation to remove B_SIGNED if sign bit of B is constant-0
@@ -186,6 +189,14 @@ module \$shiftx (A, B, Y);
         assign A_i[i] = A[i*2];
       \$shiftx  #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH((A_WIDTH+1'd1)/2'd2), .B_WIDTH(B_WIDTH-1'd1), .Y_WIDTH(Y_WIDTH)) _TECHMAP_REPLACE_ (.A(A_i), .B(B[B_WIDTH-1:1]), .Y(Y));
     end
+    // If upper half of A input is all constant 1'bx then
+    //   chop this $shiftx in half
+    else if (_TECHMAP_CONSTMSK_A_[A_WIDTH-1:2**(B_WIDTH-1)] == {A_WIDTH-2**(B_WIDTH-1){1'b1}} && _TECHMAP_CONSTVAL_A_[A_WIDTH-1:2**(B_WIDTH-1)] === {A_WIDTH-2**(B_WIDTH-1){1'bx}}) begin
+      if (B_WIDTH > 1)
+        \$shiftx  #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(2**(B_WIDTH-1)), .B_WIDTH(B_WIDTH-1'd1), .Y_WIDTH(Y_WIDTH)) _TECHMAP_REPLACE_ (.A(A[2**(B_WIDTH-1)-1:0]), .B(B[B_WIDTH-2:0]), .Y(Y));
+      else
+	assign Y = A[0];
+    end
     else if (B_WIDTH < 3 || A_WIDTH <= 4) begin
       wire _TECHMAP_FAIL_ = 1;
     end
-- 
cgit v1.2.3


From 283e33ba5aad3a66bd14c30e1f52361c5f4c9789 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Thu, 2 May 2019 16:02:37 -0700
Subject: Trim off leading 1'bx in A

---
 techlibs/xilinx/cells_map.v | 27 ++++++++++++++++++++-------
 1 file changed, 20 insertions(+), 7 deletions(-)

(limited to 'techlibs')

diff --git a/techlibs/xilinx/cells_map.v b/techlibs/xilinx/cells_map.v
index ecfbe2555..729cda139 100644
--- a/techlibs/xilinx/cells_map.v
+++ b/techlibs/xilinx/cells_map.v
@@ -166,6 +166,20 @@ module \$shiftx (A, B, Y);
   parameter [B_WIDTH-1:0] _TECHMAP_CONSTMSK_B_ = 0;
   parameter [B_WIDTH-1:0] _TECHMAP_CONSTVAL_B_ = 0;
 
+  function integer compute_num_leading_X_in_A;
+    integer i, c;
+  begin
+    compute_num_leading_X_in_A = 0;
+    c = 1;
+    for (i = A_WIDTH-1; i >= 0; i=i-1) begin
+      if (!_TECHMAP_CONSTMSK_A_[i] || _TECHMAP_CONSTVAL_A_[i] !== 1'bx)
+        c = 0;
+      compute_num_leading_X_in_A = compute_num_leading_X_in_A + c;
+    end
+  end
+  endfunction
+  localparam num_leading_X_in_A = compute_num_leading_X_in_A();
+
   generate
     genvar i, j;
     // TODO: Check if this opt still necessary
@@ -176,6 +190,7 @@ module \$shiftx (A, B, Y);
       else
         wire _TECHMAP_FAIL_ = 1;
     end
+    // Bit-blast
     else if (Y_WIDTH > 1) begin
       for (i = 0; i < Y_WIDTH; i++)
         \$shiftx  #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(A_WIDTH-Y_WIDTH+1), .B_WIDTH(B_WIDTH), .Y_WIDTH(1'd1)) bitblast (.A(A[A_WIDTH-Y_WIDTH+i:i]), .B(B), .Y(Y[i]));
@@ -189,13 +204,11 @@ module \$shiftx (A, B, Y);
         assign A_i[i] = A[i*2];
       \$shiftx  #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH((A_WIDTH+1'd1)/2'd2), .B_WIDTH(B_WIDTH-1'd1), .Y_WIDTH(Y_WIDTH)) _TECHMAP_REPLACE_ (.A(A_i), .B(B[B_WIDTH-1:1]), .Y(Y));
     end
-    // If upper half of A input is all constant 1'bx then
-    //   chop this $shiftx in half
-    else if (_TECHMAP_CONSTMSK_A_[A_WIDTH-1:2**(B_WIDTH-1)] == {A_WIDTH-2**(B_WIDTH-1){1'b1}} && _TECHMAP_CONSTVAL_A_[A_WIDTH-1:2**(B_WIDTH-1)] === {A_WIDTH-2**(B_WIDTH-1){1'bx}}) begin
-      if (B_WIDTH > 1)
-        \$shiftx  #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(2**(B_WIDTH-1)), .B_WIDTH(B_WIDTH-1'd1), .Y_WIDTH(Y_WIDTH)) _TECHMAP_REPLACE_ (.A(A[2**(B_WIDTH-1)-1:0]), .B(B[B_WIDTH-2:0]), .Y(Y));
-      else
-	assign Y = A[0];
+    // Trim off any leading 1'bx -es in A, and resize B accordingly
+    else if (num_leading_X_in_A > 0) begin
+      localparam A_WIDTH_new = A_WIDTH - num_leading_X_in_A;
+      localparam B_WIDTH_new = $clog2(A_WIDTH_new);
+      \$shiftx  #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(A_WIDTH_new), .B_WIDTH(B_WIDTH_new), .Y_WIDTH(Y_WIDTH)) _TECHMAP_REPLACE_ (.A(A[A_WIDTH_new-1:0]), .B(B[B_WIDTH_new-1:0]), .Y(Y));
     end
     else if (B_WIDTH < 3 || A_WIDTH <= 4) begin
       wire _TECHMAP_FAIL_ = 1;
-- 
cgit v1.2.3


From 36a219063ad7b4e70581bf83a00365db764737bf Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Tue, 21 May 2019 14:31:19 -0700
Subject: Modify LUT area cost to be same as old abc

---
 techlibs/xilinx/abc.lut | 19 +++++++++----------
 1 file changed, 9 insertions(+), 10 deletions(-)

(limited to 'techlibs')

diff --git a/techlibs/xilinx/abc.lut b/techlibs/xilinx/abc.lut
index c6bc7b1f7..c53cd50a1 100644
--- a/techlibs/xilinx/abc.lut
+++ b/techlibs/xilinx/abc.lut
@@ -1,12 +1,11 @@
-# Max delays from https://pastebin.com/v2hrcksd
-# from https://github.com/SymbiFlow/prjxray/pull/706#issuecomment-479380321
+# Max delays from https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLL_L.sdf
 
 # K	area	delay
-1 	11	624
-2	12	624
-3	13	624
-4	14	624
-5	15	624
-6	20	724
-7	40	1020
-8	80	1293
+1 	1	624
+2	2	624
+3	3	624
+4	3	624
+5	3	624
+6	5	724
+7	10	1020
+8	20	1293
-- 
cgit v1.2.3


From ee8435b820bbea4a4ceb2c46a81de9d03d4aa44c Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Tue, 21 May 2019 16:19:45 -0700
Subject: Instead of MUXCY/XORCY use CARRY4 (with timing)

---
 techlibs/xilinx/abc.box         | 22 +++++++++++++++-------
 techlibs/xilinx/arith_map.v     |  4 ++--
 techlibs/xilinx/cells_sim.v     |  3 +--
 techlibs/xilinx/synth_xilinx.cc |  2 ++
 4 files changed, 20 insertions(+), 11 deletions(-)

(limited to 'techlibs')

diff --git a/techlibs/xilinx/abc.box b/techlibs/xilinx/abc.box
index d572817df..57ea1670c 100644
--- a/techlibs/xilinx/abc.box
+++ b/techlibs/xilinx/abc.box
@@ -1,5 +1,4 @@
-# Max delays from https://pastebin.com/v2hrcksd
-# from https://github.com/SymbiFlow/prjxray/pull/706#issuecomment-479380321
+# Max delays from https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLL_L.sdf
 
 # F7BMUX slower than F7AMUX
 # Inputs: I0 I1 S0
@@ -12,8 +11,17 @@ F7BMUX 1 1 3 1
 MUXF8 2 1 3 1
 104 94 273
 
-MUXCY 3 1 3 1
-1 1 1
-
-XORCY 4 1 2 1
-1 1
+# CARRY4 + CARRY4_[ABCD]X
+# Inputs: CI CYINIT DI0 DI1 DI2 DI3 S0 S1 S2 S3
+# Outputs: CO0 CO1 CO2 CO3 O0 O1 O2 O3
+CARRY4 3 1 10 8
+271 157 228 114 222 334 239 313
+536 494 592 580 482 598 584 642
+379 465 540 526 -   407 556 615
+-   445 520 507 -   -   537 596
+-   -   356 398 -   -   -   438
+-   -   -   385 -   -   -   -
+340 433 512 508 223 400 523 582
+-   469 548 528 -   205 558 618
+-   -   292 376 -   -   226 330
+-   -   -   380 -   -   -   227
diff --git a/techlibs/xilinx/arith_map.v b/techlibs/xilinx/arith_map.v
index 09a5f07e8..5c848d4e6 100644
--- a/techlibs/xilinx/arith_map.v
+++ b/techlibs/xilinx/arith_map.v
@@ -180,7 +180,7 @@ module _80_xilinx_alu (A, B, CI, BI, X, Y, CO);
 
 			// First one
 			if (i == 0) begin
-				CARRY4 #(.IS_INITIALIZED(1'd1)) carry4_1st_part
+				CARRY4 carry4_1st_part
 				(
 				.CYINIT(CI),
 				.CI    (1'd0),
@@ -207,7 +207,7 @@ module _80_xilinx_alu (A, B, CI, BI, X, Y, CO);
 
 			// First one
 			if (i == 0) begin
-				CARRY4 #(.IS_INITIALIZED(1'd1)) carry4_1st_full
+				CARRY4 carry4_1st_full
 				(
 				.CYINIT(CI),
 				.CI    (1'd0),
diff --git a/techlibs/xilinx/cells_sim.v b/techlibs/xilinx/cells_sim.v
index 8b231480f..9db52b67a 100644
--- a/techlibs/xilinx/cells_sim.v
+++ b/techlibs/xilinx/cells_sim.v
@@ -155,7 +155,6 @@ module LUT6_2(output O6, output O5, input I0, I1, I2, I3, I4, I5);
   assign O5 = I0 ? s5_1[1] : s5_1[0];
 endmodule
 
-(* abc_box_id = 3, lib_whitebox *)
 module MUXCY(output O, input CI, DI, S);
   assign O = S ? CI : DI;
 endmodule
@@ -170,11 +169,11 @@ module MUXF8(output O, input I0, I1, S);
   assign O = S ? I1 : I0;
 endmodule
 
-(* abc_box_id = 4, lib_whitebox *)
 module XORCY(output O, input CI, LI);
   assign O = CI ^ LI;
 endmodule
 
+(* abc_box_id = 3, lib_whitebox *)
 module CARRY4(output [3:0] CO, O, input CI, CYINIT, input [3:0] DI, S);
   assign O = S ^ {CO[2:0], CI | CYINIT};
   assign CO[0] = S[0] ? CI | CYINIT : DI[0];
diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc
index e9a3b53a0..ec7768ffe 100644
--- a/techlibs/xilinx/synth_xilinx.cc
+++ b/techlibs/xilinx/synth_xilinx.cc
@@ -261,6 +261,8 @@ struct SynthXilinxPass : public ScriptPass
 
 			if (vpr && !nocarry && !help_mode)
 				run("techmap -map +/xilinx/arith_map.v -D _EXPLICIT_CARRY");
+			else if (abc == "abc9" && !nocarry && !help_mode)
+				run("techmap -map +/xilinx/arith_map.v -D _CLB_CARRY", "(skip if '-nocarry')");
 			else if (!nocarry || help_mode)
 				run("techmap -map +/xilinx/arith_map.v", "(skip if '-nocarry')");
 
-- 
cgit v1.2.3


From 9b1078b9bde70141514488acd01bb32b5422f9bd Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Tue, 21 May 2019 18:50:02 -0700
Subject: Fix/workaround symptom unveiled by #1023

---
 techlibs/xilinx/cells_map.v | 18 ++++++++++++++----
 1 file changed, 14 insertions(+), 4 deletions(-)

(limited to 'techlibs')

diff --git a/techlibs/xilinx/cells_map.v b/techlibs/xilinx/cells_map.v
index f566a8584..af6414667 100644
--- a/techlibs/xilinx/cells_map.v
+++ b/techlibs/xilinx/cells_map.v
@@ -220,7 +220,10 @@ module \$shiftx (A, B, Y);
       localparam a_widthN = A_WIDTH - a_width0;
       wire T0, T1;
       \$shiftx  #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(a_width0), .B_WIDTH(2),                .Y_WIDTH(Y_WIDTH)) fpga_shiftx      (.A(A[a_width0-1:0]),       .B(B[2-1:0]),                .Y(T0));
-      \$shiftx  #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(a_widthN), .B_WIDTH($clog2(a_widthN)), .Y_WIDTH(Y_WIDTH)) fpga_shiftx_last (.A(A[A_WIDTH-1:a_width0]), .B(B[$clog2(a_widthN)-1:0]), .Y(T1));
+      if (a_widthN > 1)
+        \$shiftx  #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(a_widthN), .B_WIDTH($clog2(a_widthN)), .Y_WIDTH(Y_WIDTH)) fpga_shiftx_last (.A(A[A_WIDTH-1:a_width0]), .B(B[$clog2(a_widthN)-1:0]), .Y(T1));
+      else
+        assign T1 = A[A_WIDTH-1];
       MUXF7 fpga_mux (.I0(T0), .I1(T1), .S(B[B_WIDTH-1]), .O(Y));
     end
     else if (B_WIDTH == 4) begin
@@ -232,8 +235,12 @@ module \$shiftx (A, B, Y);
       for (i = 0; i < 4; i++)
         if (i < num_mux8)
           \$shiftx  #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(a_width0), .B_WIDTH(2),                .Y_WIDTH(Y_WIDTH)) fpga_shiftx      (.A(A[i*a_width0+:a_width0]), .B(B[2-1:0]),                .Y(T[i]));
-        else if (i == num_mux8 && a_widthN > 0)
-          \$shiftx  #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(a_widthN), .B_WIDTH($clog2(a_widthN)), .Y_WIDTH(Y_WIDTH)) fpga_shiftx_last (.A(A[A_WIDTH-1:i*a_width0]), .B(B[$clog2(a_widthN)-1:0]), .Y(T[i]));
+        else if (i == num_mux8 && a_widthN > 0) begin
+          if (a_widthN > 1)
+            \$shiftx  #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(a_widthN), .B_WIDTH($clog2(a_widthN)), .Y_WIDTH(Y_WIDTH)) fpga_shiftx_last (.A(A[A_WIDTH-1:i*a_width0]), .B(B[$clog2(a_widthN)-1:0]), .Y(T[i]));
+          else
+            assign T[i] = A[A_WIDTH-1];
+        end
         else
           assign T[i] = 1'bx;
       MUXF7 fpga_mux_0 (.I0(T[0]), .I1(T[1]), .S(B[2]), .O(T0));
@@ -249,7 +256,10 @@ module \$shiftx (A, B, Y);
         if (i < num_mux16)
           \$shiftx  #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(a_width0), .B_WIDTH(4),                .Y_WIDTH(Y_WIDTH)) fpga_shiftx      (.A(A[i*a_width0+:a_width0]), .B(B[4-1:0]),                .Y(T[i]));
         else if (i == num_mux16 && a_widthN > 0) begin
-          \$shiftx  #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(a_widthN), .B_WIDTH($clog2(a_widthN)), .Y_WIDTH(Y_WIDTH)) fpga_shiftx_last (.A(A[A_WIDTH-1:i*a_width0]), .B(B[$clog2(a_widthN)-1:0]), .Y(T[i]));
+          if (a_widthN > 1)
+            \$shiftx  #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(a_widthN), .B_WIDTH($clog2(a_widthN)), .Y_WIDTH(Y_WIDTH)) fpga_shiftx_last (.A(A[A_WIDTH-1:i*a_width0]), .B(B[$clog2(a_widthN)-1:0]), .Y(T[i]));
+          else
+            assign T[i] = A[A_WIDTH-1];
         end
         else
           assign T[i] = 1'bx;
-- 
cgit v1.2.3


From 4f44e3399ba6c959c830943c44c4ad728be895fa Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Wed, 22 May 2019 02:36:28 -0700
Subject: shift register inference before mux

---
 techlibs/xilinx/synth_xilinx.cc | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

(limited to 'techlibs')

diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc
index ec7768ffe..3cee81a7b 100644
--- a/techlibs/xilinx/synth_xilinx.cc
+++ b/techlibs/xilinx/synth_xilinx.cc
@@ -266,9 +266,6 @@ struct SynthXilinxPass : public ScriptPass
 			else if (!nocarry || help_mode)
 				run("techmap -map +/xilinx/arith_map.v", "(skip if '-nocarry')");
 
-			if (!nomux || help_mode)
-				run("techmap -map +/xilinx/cells_map.v");
-
 			if (!nosrl || help_mode) {
 				// shregmap operates on bit-level flops, not word-level,
 				//   so break those down here
@@ -277,6 +274,9 @@ struct SynthXilinxPass : public ScriptPass
 				run("shregmap -tech xilinx -minlen 3", "(skip if '-nosrl')");
 			}
 
+			if (!nomux || help_mode)
+				run("techmap -map +/xilinx/cells_map.v");
+
 			run("techmap");
 			run("opt -fast");
 		}
-- 
cgit v1.2.3


From ae89e6ab26d2d87a604e20ebc14dcda8c9901585 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Thu, 23 May 2019 08:58:57 -0700
Subject: Add whitebox support to DRAM

---
 techlibs/xilinx/abc.box         | 14 ++++++++++++++
 techlibs/xilinx/cells_sim.v     | 10 ++++++++--
 techlibs/xilinx/cells_xtra.sh   |  4 ++--
 techlibs/xilinx/cells_xtra.v    | 18 ------------------
 techlibs/xilinx/synth_xilinx.cc |  4 ++--
 5 files changed, 26 insertions(+), 24 deletions(-)

(limited to 'techlibs')

diff --git a/techlibs/xilinx/abc.box b/techlibs/xilinx/abc.box
index 57ea1670c..92ea5537b 100644
--- a/techlibs/xilinx/abc.box
+++ b/techlibs/xilinx/abc.box
@@ -25,3 +25,17 @@ CARRY4 3 1 10 8
 -   469 548 528 -   205 558 618
 -   -   292 376 -   -   226 330
 -   -   -   380 -   -   -   227
+
+# SLICEM/A6LUT
+# Inputs: A0 A1 A2 A3 A4 A5 D DPRA0 DPRA1 DPRA2 DPRA3 DPRA4 DPRA5 WCLK WE
+# Outputs: DPO SPO
+RAM64X1D 4 1 15 2
+-   -   -   -   -   -   - 124 124 124 124 124 124 - -
+124 124 124 124 124 124 - -   -   -   -   -   124 - -
+
+# SLICEM/A6LUT + F7[AB]MUX
+# Inputs: A0 A1 A2 A3 A4 A5 A6 D DPRA0 DPRA1 DPRA2 DPRA3 DPRA4 DPRA5 DPRA6 WCLK WE
+# Outputs: DPO SPO
+RAM128X1D 5 1 17 2
+-   -   -   -   -   -   -   - 314 314 314 314 314 314 292 - -
+347 347 347 347 347 347 296 - -   -   -   -   -   -   -   - -
diff --git a/techlibs/xilinx/cells_sim.v b/techlibs/xilinx/cells_sim.v
index 9db52b67a..29c79f689 100644
--- a/techlibs/xilinx/cells_sim.v
+++ b/techlibs/xilinx/cells_sim.v
@@ -281,8 +281,9 @@ module FDPE_1 ((* abc_flop_q *) output reg Q, input C, CE, D, PRE);
   always @(negedge C, posedge PRE) if (PRE) Q <= 1'b1; else if (CE) Q <= D;
 endmodule
 
+(* abc_box_id = 4, lib_whitebox *)
 module RAM64X1D (
-  (* abc_flop_q *) output DPO, SPO,
+  output DPO, SPO,
   input  D, WCLK, WE,
   input  A0, A1, A2, A3, A4, A5,
   input  DPRA0, DPRA1, DPRA2, DPRA3, DPRA4, DPRA5
@@ -294,12 +295,15 @@ module RAM64X1D (
   reg [63:0] mem = INIT;
   assign SPO = mem[a];
   assign DPO = mem[dpra];
+`ifndef _ABC
   wire clk = WCLK ^ IS_WCLK_INVERTED;
   always @(posedge clk) if (WE) mem[a] <= D;
+`endif
 endmodule
 
+(* abc_box_id = 5, lib_whitebox *)
 module RAM128X1D (
-  (* abc_flop_q *) output       DPO, SPO,
+  output       DPO, SPO,
   input        D, WCLK, WE,
   input  [6:0] A, DPRA
 );
@@ -308,8 +312,10 @@ module RAM128X1D (
   reg [127:0] mem = INIT;
   assign SPO = mem[A];
   assign DPO = mem[DPRA];
+`ifndef _ABC
   wire clk = WCLK ^ IS_WCLK_INVERTED;
   always @(posedge clk) if (WE) mem[A] <= D;
+`endif
 endmodule
 
 module SRL16E (
diff --git a/techlibs/xilinx/cells_xtra.sh b/techlibs/xilinx/cells_xtra.sh
index 8e39b440d..e3b847c36 100644
--- a/techlibs/xilinx/cells_xtra.sh
+++ b/techlibs/xilinx/cells_xtra.sh
@@ -116,7 +116,7 @@ function xtract_cell_decl()
 	xtract_cell_decl PS7 "(* keep *)"
 	xtract_cell_decl PULLDOWN
 	xtract_cell_decl PULLUP
-	xtract_cell_decl RAM128X1D
+	#xtract_cell_decl RAM128X1D
 	xtract_cell_decl RAM128X1S
 	xtract_cell_decl RAM256X1S
 	xtract_cell_decl RAM32M
@@ -125,7 +125,7 @@ function xtract_cell_decl()
 	xtract_cell_decl RAM32X1S_1
 	xtract_cell_decl RAM32X2S
 	xtract_cell_decl RAM64M
-	xtract_cell_decl RAM64X1D
+	x#tract_cell_decl RAM64X1D
 	xtract_cell_decl RAM64X1S
 	xtract_cell_decl RAM64X1S_1
 	xtract_cell_decl RAM64X2S
diff --git a/techlibs/xilinx/cells_xtra.v b/techlibs/xilinx/cells_xtra.v
index fbcc74682..0ec3d0df0 100644
--- a/techlibs/xilinx/cells_xtra.v
+++ b/techlibs/xilinx/cells_xtra.v
@@ -3655,17 +3655,6 @@ module PULLUP (...);
     output O;
 endmodule
 
-module RAM128X1D (...);
-    parameter [127:0] INIT = 128'h00000000000000000000000000000000;
-    parameter [0:0] IS_WCLK_INVERTED = 1'b0;
-    output DPO, SPO;
-    input [6:0] A;
-    input [6:0] DPRA;
-    input D;
-    input WCLK;
-    input WE;
-endmodule
-
 module RAM128X1S (...);
     parameter [127:0] INIT = 128'h00000000000000000000000000000000;
     parameter [0:0] IS_WCLK_INVERTED = 1'b0;
@@ -3756,13 +3745,6 @@ module RAM64M (...);
     input WE;
 endmodule
 
-module RAM64X1D (...);
-    parameter [63:0] INIT = 64'h0000000000000000;
-    parameter [0:0] IS_WCLK_INVERTED = 1'b0;
-    output DPO, SPO;
-    input A0, A1, A2, A3, A4, A5, D, DPRA0, DPRA1, DPRA2, DPRA3, DPRA4, DPRA5, WCLK, WE;
-endmodule
-
 module RAM64X1S (...);
     parameter [63:0] INIT = 64'h0000000000000000;
     parameter [0:0] IS_WCLK_INVERTED = 1'b0;
diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc
index 3cee81a7b..ecfb94610 100644
--- a/techlibs/xilinx/synth_xilinx.cc
+++ b/techlibs/xilinx/synth_xilinx.cc
@@ -203,9 +203,9 @@ struct SynthXilinxPass : public ScriptPass
 	{
 		if (check_label("begin")) {
 			if (vpr)
-				run("read_verilog -lib -D_EXPLICIT_CARRY +/xilinx/cells_sim.v");
+				run("read_verilog -lib -D_ABC -D_EXPLICIT_CARRY +/xilinx/cells_sim.v");
 			else
-				run("read_verilog -lib +/xilinx/cells_sim.v");
+				run("read_verilog -lib -D_ABC +/xilinx/cells_sim.v");
 
 			run("read_verilog -lib +/xilinx/cells_xtra.v");
 
-- 
cgit v1.2.3


From 60af2ca94de482f09aaaa7d6eed66c299248f8f1 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Fri, 24 May 2019 14:09:15 -0700
Subject: Transpose CARRY4 delays

---
 techlibs/xilinx/abc.box | 18 ++++++++----------
 1 file changed, 8 insertions(+), 10 deletions(-)

(limited to 'techlibs')

diff --git a/techlibs/xilinx/abc.box b/techlibs/xilinx/abc.box
index 92ea5537b..9653fe5b8 100644
--- a/techlibs/xilinx/abc.box
+++ b/techlibs/xilinx/abc.box
@@ -15,16 +15,14 @@ MUXF8 2 1 3 1
 # Inputs: CI CYINIT DI0 DI1 DI2 DI3 S0 S1 S2 S3
 # Outputs: CO0 CO1 CO2 CO3 O0 O1 O2 O3
 CARRY4 3 1 10 8
-271 157 228 114 222 334 239 313
-536 494 592 580 482 598 584 642
-379 465 540 526 -   407 556 615
--   445 520 507 -   -   537 596
--   -   356 398 -   -   -   438
--   -   -   385 -   -   -   -
-340 433 512 508 223 400 523 582
--   469 548 528 -   205 558 618
--   -   292 376 -   -   226 330
--   -   -   380 -   -   -   227
+271 536 379 -   -   -   340 -   -   -
+157 494 465 445 -   -   433 469 -   -
+228 592 540 520 356 -   512 548 292 -
+114 580 526 507 398 385 508 528 378 380
+222 482 -   -   -   -   223 -   -   -
+334 598 407 -   -   -   400 205 -   -
+239 584 556 537 -   -   523 558 226 -
+313 642 615 596 438 -   582 618 330 227
 
 # SLICEM/A6LUT
 # Inputs: A0 A1 A2 A3 A4 A5 D DPRA0 DPRA1 DPRA2 DPRA3 DPRA4 DPRA5 WCLK WE
-- 
cgit v1.2.3


From ca5774ed40db8dafe3696deb9fe9827d7196d7bf Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Fri, 24 May 2019 20:39:55 -0700
Subject: Try new LUT delays

---
 techlibs/xilinx/abc.lut | 19 +++++++++++--------
 1 file changed, 11 insertions(+), 8 deletions(-)

(limited to 'techlibs')

diff --git a/techlibs/xilinx/abc.lut b/techlibs/xilinx/abc.lut
index c53cd50a1..438ed0368 100644
--- a/techlibs/xilinx/abc.lut
+++ b/techlibs/xilinx/abc.lut
@@ -1,11 +1,14 @@
 # Max delays from https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLL_L.sdf
 
 # K	area	delay
-1 	1	624
-2	2	624
-3	3	624
-4	3	624
-5	3	624
-6	5	724
-7	10	1020
-8	20	1293
+1 	1	248
+2	2	248 372
+3	3	248 372 496
+4	3	248 372 496 620
+5	3	248 372 496 620 744
+6	5	124 248 372 496 620 744
+                # F7BMUX
+7	10	296 420 544 668 792 916 1040
+                # F8MUX
+                    # F8MUX+F7BMUX
+8	20	273 569 693 817 941 1065 1189 1313
-- 
cgit v1.2.3


From 66701c5fcc399d83e736e83064a39466361763ba Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Sun, 26 May 2019 02:52:48 -0700
Subject: Muck about with LUT delays some more

---
 techlibs/xilinx/abc.lut | 10 +++++-----
 1 file changed, 5 insertions(+), 5 deletions(-)

(limited to 'techlibs')

diff --git a/techlibs/xilinx/abc.lut b/techlibs/xilinx/abc.lut
index 438ed0368..5550a4039 100644
--- a/techlibs/xilinx/abc.lut
+++ b/techlibs/xilinx/abc.lut
@@ -1,11 +1,11 @@
 # Max delays from https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLL_L.sdf
 
 # K	area	delay
-1 	1	248
-2	2	248 372
-3	3	248 372 496
-4	3	248 372 496 620
-5	3	248 372 496 620 744
+1 	1	124
+2	2	124 248
+3	3	124 248 372
+4	3	124 248 372 496
+5	3	124 248 372 496 620
 6	5	124 248 372 496 620 744
                 # F7BMUX
 7	10	296 420 544 668 792 916 1040
-- 
cgit v1.2.3


From 4311b9b583488817aaae0019f6ebc47deb030644 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Sun, 26 May 2019 11:32:02 -0700
Subject: Blackboxes

---
 techlibs/xilinx/abc.box     | 10 +++++-----
 techlibs/xilinx/cells_sim.v | 10 +++++-----
 2 files changed, 10 insertions(+), 10 deletions(-)

(limited to 'techlibs')

diff --git a/techlibs/xilinx/abc.box b/techlibs/xilinx/abc.box
index 9653fe5b8..4d907c7e2 100644
--- a/techlibs/xilinx/abc.box
+++ b/techlibs/xilinx/abc.box
@@ -3,18 +3,18 @@
 # F7BMUX slower than F7AMUX
 # Inputs: I0 I1 S0
 # Outputs: O
-F7BMUX 1 1 3 1
+F7BMUX 1 0 3 1
 217 223 296
 
 # Inputs: I0 I1 S0
 # Outputs: O
-MUXF8 2 1 3 1
+MUXF8 2 0 3 1
 104 94 273
 
 # CARRY4 + CARRY4_[ABCD]X
 # Inputs: CI CYINIT DI0 DI1 DI2 DI3 S0 S1 S2 S3
 # Outputs: CO0 CO1 CO2 CO3 O0 O1 O2 O3
-CARRY4 3 1 10 8
+CARRY4 3 0 10 8
 271 536 379 -   -   -   340 -   -   -
 157 494 465 445 -   -   433 469 -   -
 228 592 540 520 356 -   512 548 292 -
@@ -27,13 +27,13 @@ CARRY4 3 1 10 8
 # SLICEM/A6LUT
 # Inputs: A0 A1 A2 A3 A4 A5 D DPRA0 DPRA1 DPRA2 DPRA3 DPRA4 DPRA5 WCLK WE
 # Outputs: DPO SPO
-RAM64X1D 4 1 15 2
+RAM64X1D 4 0 15 2
 -   -   -   -   -   -   - 124 124 124 124 124 124 - -
 124 124 124 124 124 124 - -   -   -   -   -   124 - -
 
 # SLICEM/A6LUT + F7[AB]MUX
 # Inputs: A0 A1 A2 A3 A4 A5 A6 D DPRA0 DPRA1 DPRA2 DPRA3 DPRA4 DPRA5 DPRA6 WCLK WE
 # Outputs: DPO SPO
-RAM128X1D 5 1 17 2
+RAM128X1D 5 0 17 2
 -   -   -   -   -   -   -   - 314 314 314 314 314 314 292 - -
 347 347 347 347 347 347 296 - -   -   -   -   -   -   -   - -
diff --git a/techlibs/xilinx/cells_sim.v b/techlibs/xilinx/cells_sim.v
index 29c79f689..db47b4230 100644
--- a/techlibs/xilinx/cells_sim.v
+++ b/techlibs/xilinx/cells_sim.v
@@ -159,12 +159,12 @@ module MUXCY(output O, input CI, DI, S);
   assign O = S ? CI : DI;
 endmodule
 
-(* abc_box_id = 1, lib_whitebox *)
+(* abc_box_id = 1 /*, lib_whitebox*/ *)
 module MUXF7(output O, input I0, I1, S);
   assign O = S ? I1 : I0;
 endmodule
 
-(* abc_box_id = 2, lib_whitebox *)
+(* abc_box_id = 2 /*, lib_whitebox*/ *)
 module MUXF8(output O, input I0, I1, S);
   assign O = S ? I1 : I0;
 endmodule
@@ -173,7 +173,7 @@ module XORCY(output O, input CI, LI);
   assign O = CI ^ LI;
 endmodule
 
-(* abc_box_id = 3, lib_whitebox *)
+(* abc_box_id = 3 /*, lib_whitebox*/ *)
 module CARRY4(output [3:0] CO, O, input CI, CYINIT, input [3:0] DI, S);
   assign O = S ^ {CO[2:0], CI | CYINIT};
   assign CO[0] = S[0] ? CI | CYINIT : DI[0];
@@ -281,7 +281,7 @@ module FDPE_1 ((* abc_flop_q *) output reg Q, input C, CE, D, PRE);
   always @(negedge C, posedge PRE) if (PRE) Q <= 1'b1; else if (CE) Q <= D;
 endmodule
 
-(* abc_box_id = 4, lib_whitebox *)
+(* abc_box_id = 4 /*, lib_whitebox*/ *)
 module RAM64X1D (
   output DPO, SPO,
   input  D, WCLK, WE,
@@ -301,7 +301,7 @@ module RAM64X1D (
 `endif
 endmodule
 
-(* abc_box_id = 5, lib_whitebox *)
+(* abc_box_id = 5 /*, lib_whitebox*/ *)
 module RAM128X1D (
   output       DPO, SPO,
   input        D, WCLK, WE,
-- 
cgit v1.2.3


From 54e28eb3ea8bd79c55397d2f53771991039c7eed Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Mon, 27 May 2019 23:08:55 -0700
Subject: Re-enable lib_whitebox

---
 techlibs/xilinx/cells_sim.v | 10 +++++-----
 1 file changed, 5 insertions(+), 5 deletions(-)

(limited to 'techlibs')

diff --git a/techlibs/xilinx/cells_sim.v b/techlibs/xilinx/cells_sim.v
index db47b4230..29c79f689 100644
--- a/techlibs/xilinx/cells_sim.v
+++ b/techlibs/xilinx/cells_sim.v
@@ -159,12 +159,12 @@ module MUXCY(output O, input CI, DI, S);
   assign O = S ? CI : DI;
 endmodule
 
-(* abc_box_id = 1 /*, lib_whitebox*/ *)
+(* abc_box_id = 1, lib_whitebox *)
 module MUXF7(output O, input I0, I1, S);
   assign O = S ? I1 : I0;
 endmodule
 
-(* abc_box_id = 2 /*, lib_whitebox*/ *)
+(* abc_box_id = 2, lib_whitebox *)
 module MUXF8(output O, input I0, I1, S);
   assign O = S ? I1 : I0;
 endmodule
@@ -173,7 +173,7 @@ module XORCY(output O, input CI, LI);
   assign O = CI ^ LI;
 endmodule
 
-(* abc_box_id = 3 /*, lib_whitebox*/ *)
+(* abc_box_id = 3, lib_whitebox *)
 module CARRY4(output [3:0] CO, O, input CI, CYINIT, input [3:0] DI, S);
   assign O = S ^ {CO[2:0], CI | CYINIT};
   assign CO[0] = S[0] ? CI | CYINIT : DI[0];
@@ -281,7 +281,7 @@ module FDPE_1 ((* abc_flop_q *) output reg Q, input C, CE, D, PRE);
   always @(negedge C, posedge PRE) if (PRE) Q <= 1'b1; else if (CE) Q <= D;
 endmodule
 
-(* abc_box_id = 4 /*, lib_whitebox*/ *)
+(* abc_box_id = 4, lib_whitebox *)
 module RAM64X1D (
   output DPO, SPO,
   input  D, WCLK, WE,
@@ -301,7 +301,7 @@ module RAM64X1D (
 `endif
 endmodule
 
-(* abc_box_id = 5 /*, lib_whitebox*/ *)
+(* abc_box_id = 5, lib_whitebox *)
 module RAM128X1D (
   output       DPO, SPO,
   input        D, WCLK, WE,
-- 
cgit v1.2.3


From e032e5bcde1c9e975c6947c27495b3049cd51737 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Mon, 27 May 2019 23:09:06 -0700
Subject: Make MUXF{7,8} and CARRY4 whitebox

---
 techlibs/xilinx/abc.box | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

(limited to 'techlibs')

diff --git a/techlibs/xilinx/abc.box b/techlibs/xilinx/abc.box
index 4d907c7e2..b3972ddb3 100644
--- a/techlibs/xilinx/abc.box
+++ b/techlibs/xilinx/abc.box
@@ -3,18 +3,18 @@
 # F7BMUX slower than F7AMUX
 # Inputs: I0 I1 S0
 # Outputs: O
-F7BMUX 1 0 3 1
+F7BMUX 1 1 3 1
 217 223 296
 
 # Inputs: I0 I1 S0
 # Outputs: O
-MUXF8 2 0 3 1
+MUXF8 2 1 3 1
 104 94 273
 
 # CARRY4 + CARRY4_[ABCD]X
 # Inputs: CI CYINIT DI0 DI1 DI2 DI3 S0 S1 S2 S3
 # Outputs: CO0 CO1 CO2 CO3 O0 O1 O2 O3
-CARRY4 3 0 10 8
+CARRY4 3 1 10 8
 271 536 379 -   -   -   340 -   -   -
 157 494 465 445 -   -   433 469 -   -
 228 592 540 520 356 -   512 548 292 -
-- 
cgit v1.2.3


From f228621b80d727b4dc1d7a9b3b934c1fbc170642 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Tue, 28 May 2019 09:36:01 -0700
Subject: Typo

---
 techlibs/xilinx/cells_xtra.sh | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'techlibs')

diff --git a/techlibs/xilinx/cells_xtra.sh b/techlibs/xilinx/cells_xtra.sh
index e3b847c36..2b384f405 100644
--- a/techlibs/xilinx/cells_xtra.sh
+++ b/techlibs/xilinx/cells_xtra.sh
@@ -125,7 +125,7 @@ function xtract_cell_decl()
 	xtract_cell_decl RAM32X1S_1
 	xtract_cell_decl RAM32X2S
 	xtract_cell_decl RAM64M
-	x#tract_cell_decl RAM64X1D
+	#xtract_cell_decl RAM64X1D
 	xtract_cell_decl RAM64X1S
 	xtract_cell_decl RAM64X1S_1
 	xtract_cell_decl RAM64X2S
-- 
cgit v1.2.3


From 276f5f8b811953e79923fe30e85bc34ced88b748 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Wed, 29 May 2019 22:55:34 -0700
Subject: Some more realistic delays...

---
 techlibs/xilinx/abc.lut | 14 +++++++-------
 1 file changed, 7 insertions(+), 7 deletions(-)

(limited to 'techlibs')

diff --git a/techlibs/xilinx/abc.lut b/techlibs/xilinx/abc.lut
index 5550a4039..3a7dc268d 100644
--- a/techlibs/xilinx/abc.lut
+++ b/techlibs/xilinx/abc.lut
@@ -2,13 +2,13 @@
 
 # K	area	delay
 1 	1	124
-2	2	124 248
-3	3	124 248 372
-4	3	124 248 372 496
-5	3	124 248 372 496 620
-6	5	124 248 372 496 620 744
+2	2	124 235
+3	3	124 235 399
+4	3	124 235 399 490
+5	3	124 235 399 490 620
+6	5	124 235 399 490 620 632
                 # F7BMUX
-7	10	296 420 544 668 792 916 1040
+7	10	296 420 531 695 756 916 928
                 # F8MUX
                     # F8MUX+F7BMUX
-8	20	273 569 693 817 941 1065 1189 1313
+8	20	273 569 693 804 968 1029 1189 1201
-- 
cgit v1.2.3


From fdfc18be91123e2939f134dafc12e1e0c1a82f7b Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Thu, 30 May 2019 01:23:36 -0700
Subject: Carry in/out to be the last input/output for chains to be preserved

---
 techlibs/xilinx/abc.box     | 23 +++++++++++++----------
 techlibs/xilinx/cells_sim.v |  4 ++--
 2 files changed, 15 insertions(+), 12 deletions(-)

(limited to 'techlibs')

diff --git a/techlibs/xilinx/abc.box b/techlibs/xilinx/abc.box
index b3972ddb3..6e9e1faf6 100644
--- a/techlibs/xilinx/abc.box
+++ b/techlibs/xilinx/abc.box
@@ -12,17 +12,20 @@ MUXF8 2 1 3 1
 104 94 273
 
 # CARRY4 + CARRY4_[ABCD]X
-# Inputs: CI CYINIT DI0 DI1 DI2 DI3 S0 S1 S2 S3
-# Outputs: CO0 CO1 CO2 CO3 O0 O1 O2 O3
+# Inputs: S0 S1 S2 S3 CYINIT DI0 DI1 DI2 DI3 CI
+# Outputs:  O0 O1 O2 O3 CO0 CO1 CO2 CO3
+#   (NB: carry chain input/output must be last input/output,
+#        swapped with what normally would have been the last
+#        output, here: CI <-> S, CO <-> O
 CARRY4 3 1 10 8
-271 536 379 -   -   -   340 -   -   -
-157 494 465 445 -   -   433 469 -   -
-228 592 540 520 356 -   512 548 292 -
-114 580 526 507 398 385 508 528 378 380
-222 482 -   -   -   -   223 -   -   -
-334 598 407 -   -   -   400 205 -   -
-239 584 556 537 -   -   523 558 226 -
-313 642 615 596 438 -   582 618 330 227
+223 -   -   -   482 -   -   -   -   222
+400 205 -   -   598 407 -   -   -   334
+523 558 226 -   584 556 537 -   -   239
+582 618 330 227 642 615 596 438 -   313
+340 -   -   -   536 379 -   -   -   271
+433 469 -   -   494 465 445 -   -   157
+512 548 292 -   592 540 520 356 -   228
+508 528 378 380 580 526 507 398 385 114
 
 # SLICEM/A6LUT
 # Inputs: A0 A1 A2 A3 A4 A5 D DPRA0 DPRA1 DPRA2 DPRA3 DPRA4 DPRA5 WCLK WE
diff --git a/techlibs/xilinx/cells_sim.v b/techlibs/xilinx/cells_sim.v
index 29c79f689..120370860 100644
--- a/techlibs/xilinx/cells_sim.v
+++ b/techlibs/xilinx/cells_sim.v
@@ -173,8 +173,8 @@ module XORCY(output O, input CI, LI);
   assign O = CI ^ LI;
 endmodule
 
-(* abc_box_id = 3, lib_whitebox *)
-module CARRY4(output [3:0] CO, O, input CI, CYINIT, input [3:0] DI, S);
+(* abc_box_id = 3, lib_whitebox, abc_carry *)
+module CARRY4((* abc_carry_out *) output [3:0] CO, output [3:0] O, (* abc_carry_in *) input CI, input CYINIT, input [3:0] DI, S);
   assign O = S ^ {CO[2:0], CI | CYINIT};
   assign CO[0] = S[0] ? CI | CYINIT : DI[0];
   assign CO[1] = S[1] ? CO[0] : DI[1];
-- 
cgit v1.2.3


From 1ad33c3b5ac91fc4e6cb6e2ff4b606a693838c2b Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Thu, 30 May 2019 13:07:29 -0700
Subject: Remove whitebox attribute from DRAMs for now

---
 techlibs/xilinx/cells_sim.v | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

(limited to 'techlibs')

diff --git a/techlibs/xilinx/cells_sim.v b/techlibs/xilinx/cells_sim.v
index 120370860..7337e0ea7 100644
--- a/techlibs/xilinx/cells_sim.v
+++ b/techlibs/xilinx/cells_sim.v
@@ -281,7 +281,7 @@ module FDPE_1 ((* abc_flop_q *) output reg Q, input C, CE, D, PRE);
   always @(negedge C, posedge PRE) if (PRE) Q <= 1'b1; else if (CE) Q <= D;
 endmodule
 
-(* abc_box_id = 4, lib_whitebox *)
+(* abc_box_id = 4 /*, lib_whitebox*/ *)
 module RAM64X1D (
   output DPO, SPO,
   input  D, WCLK, WE,
@@ -301,7 +301,7 @@ module RAM64X1D (
 `endif
 endmodule
 
-(* abc_box_id = 5, lib_whitebox *)
+(* abc_box_id = 5 /*, lib_whitebox*/ *)
 module RAM128X1D (
   output       DPO, SPO,
   input        D, WCLK, WE,
-- 
cgit v1.2.3


From dea36d4366109441e84e2e84afcfd8eb0223c902 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Fri, 31 May 2019 18:10:25 -0700
Subject: Techmap flops before ABC again

---
 techlibs/xilinx/synth_xilinx.cc | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

(limited to 'techlibs')

diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc
index cc667b919..97464ffe4 100644
--- a/techlibs/xilinx/synth_xilinx.cc
+++ b/techlibs/xilinx/synth_xilinx.cc
@@ -282,7 +282,9 @@ struct SynthXilinxPass : public ScriptPass
 		}
 
 		if (check_label("map_cells")) {
-			run("techmap -map +/techmap.v -map +/xilinx/cells_map.v");
+			run("techmap -map +/techmap.v -map +/xilinx/cells_map.v -map +/xilinx/ff_map.v ");
+			run("dffinit -ff FDRE Q INIT -ff FDCE Q INIT -ff FDPE Q INIT -ff FDSE Q INIT "
+					"-ff FDRE_1 Q INIT -ff FDCE_1 Q INIT -ff FDPE_1 Q INIT -ff FDSE_1 Q INIT");
 			run("clean");
 		}
 
@@ -299,9 +301,7 @@ struct SynthXilinxPass : public ScriptPass
 			//   has performed any necessary retiming
 			if (!nosrl || help_mode)
 				run("shregmap -minlen 3 -init -params -enpol any_or_none", "(skip if '-nosrl')");
-			run("techmap -map +/xilinx/lut_map.v -map +/xilinx/ff_map.v -map +/xilinx/cells_map.v");
-			run("dffinit -ff FDRE Q INIT -ff FDCE Q INIT -ff FDPE Q INIT -ff FDSE Q INIT "
-					"-ff FDRE_1 Q INIT -ff FDCE_1 Q INIT -ff FDPE_1 Q INIT -ff FDSE_1 Q INIT");
+			run("techmap -map +/xilinx/lut_map.v -map +/xilinx/cells_map.v");
 			run("clean");
 		}
 
-- 
cgit v1.2.3


From 01f71085f281d4721386018c90d3f95b2864df5b Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Fri, 31 May 2019 18:11:24 -0700
Subject: Add FD*E_1 -> FD*E techmap rules

---
 techlibs/xilinx/cells_sim.v | 36 +++++++++++++++++++++++++++++++-----
 1 file changed, 31 insertions(+), 5 deletions(-)

(limited to 'techlibs')

diff --git a/techlibs/xilinx/cells_sim.v b/techlibs/xilinx/cells_sim.v
index 7337e0ea7..cce03980d 100644
--- a/techlibs/xilinx/cells_sim.v
+++ b/techlibs/xilinx/cells_sim.v
@@ -173,7 +173,7 @@ module XORCY(output O, input CI, LI);
   assign O = CI ^ LI;
 endmodule
 
-(* abc_box_id = 3, lib_whitebox, abc_carry *)
+(* abc_box_id = 3, abc_carry, lib_whitebox *)
 module CARRY4((* abc_carry_out *) output [3:0] CO, output [3:0] O, (* abc_carry_in *) input CI, input CYINIT, input [3:0] DI, S);
   assign O = S ^ {CO[2:0], CI | CYINIT};
   assign CO[0] = S[0] ? CI | CYINIT : DI[0];
@@ -205,56 +205,82 @@ endmodule
 
 `endif
 
-module FDRE ((* abc_flop_q *) output reg Q, input C, CE, input D, R);
+(* abc_box_id = 6, abc_flop /*, lib_whitebox */ *)
+module FDRE ((* abc_flop_q *) output reg Q, input C, CE, (* abc_flop_d *) input D, input R);
   parameter [0:0] INIT = 1'b0;
   parameter [0:0] IS_C_INVERTED = 1'b0;
   parameter [0:0] IS_D_INVERTED = 1'b0;
   parameter [0:0] IS_R_INVERTED = 1'b0;
   initial Q <= INIT;
+`ifndef _ABC
   generate case (|IS_C_INVERTED)
     1'b0: always @(posedge C) if (R == !IS_R_INVERTED) Q <= 1'b0; else if (CE) Q <= D ^ IS_D_INVERTED;
     1'b1: always @(negedge C) if (R == !IS_R_INVERTED) Q <= 1'b0; else if (CE) Q <= D ^ IS_D_INVERTED;
   endcase endgenerate
+`else
+  always @* if (R == !IS_R_INVERTED) Q <= 1'b0; else if (CE) Q <= D ^ IS_D_INVERTED;
+`endif
 endmodule
 
-module FDSE ((* abc_flop_q *) output reg Q, input C, CE, D, S);
+(* abc_box_id = 7, abc_flop /*, lib_whitebox*/ *)
+module FDSE ((* abc_flop_q *) output reg Q, input C, CE, (* abc_flop_d *) input D, input S);
   parameter [0:0] INIT = 1'b0;
   parameter [0:0] IS_C_INVERTED = 1'b0;
   parameter [0:0] IS_D_INVERTED = 1'b0;
   parameter [0:0] IS_S_INVERTED = 1'b0;
   initial Q <= INIT;
+`ifndef _ABC
   generate case (|IS_C_INVERTED)
     1'b0: always @(posedge C) if (S == !IS_S_INVERTED) Q <= 1'b1; else if (CE) Q <= D ^ IS_D_INVERTED;
     1'b1: always @(negedge C) if (S == !IS_S_INVERTED) Q <= 1'b1; else if (CE) Q <= D ^ IS_D_INVERTED;
   endcase endgenerate
+`else
+    always @* if (S == !IS_S_INVERTED) Q <= 1'b1; else if (CE) Q <= D ^ IS_D_INVERTED;
+`endif
 endmodule
 
-module FDCE ((* abc_flop_q *) output reg Q, input C, CE, D, CLR);
+(* abc_box_id = 8, abc_flop /*, lib_whitebox*/ *)
+module FDCE ((* abc_flop_q *) output reg Q, input C, CE, (* abc_flop_d *) input D, input CLR);
   parameter [0:0] INIT = 1'b0;
   parameter [0:0] IS_C_INVERTED = 1'b0;
   parameter [0:0] IS_D_INVERTED = 1'b0;
   parameter [0:0] IS_CLR_INVERTED = 1'b0;
   initial Q <= INIT;
   generate case ({|IS_C_INVERTED, |IS_CLR_INVERTED})
+`ifndef _ABC
     2'b00: always @(posedge C, posedge CLR) if ( CLR) Q <= 1'b0; else if (CE) Q <= D ^ IS_D_INVERTED;
     2'b01: always @(posedge C, negedge CLR) if (!CLR) Q <= 1'b0; else if (CE) Q <= D ^ IS_D_INVERTED;
     2'b10: always @(negedge C, posedge CLR) if ( CLR) Q <= 1'b0; else if (CE) Q <= D ^ IS_D_INVERTED;
     2'b11: always @(negedge C, negedge CLR) if (!CLR) Q <= 1'b0; else if (CE) Q <= D ^ IS_D_INVERTED;
   endcase endgenerate
+`else
+  generate case (|IS_CLR_INVERTED)
+    1'b0: always @* if ( CLR) Q <= 1'b0; else if (CE) Q <= D ^ IS_D_INVERTED;
+    1'b1: always @* if (!CLR) Q <= 1'b0; else if (CE) Q <= D ^ IS_D_INVERTED;
+  endcase endgenerate
+`endif
 endmodule
 
-module FDPE ((* abc_flop_q *) output reg Q, input C, CE, D, PRE);
+(* abc_box_id = 9, abc_flop /*, lib_whitebox*/ *)
+module FDPE ((* abc_flop_q *) output reg Q, input C, CE, (* abc_flop_q *) input D, input PRE);
   parameter [0:0] INIT = 1'b0;
   parameter [0:0] IS_C_INVERTED = 1'b0;
   parameter [0:0] IS_D_INVERTED = 1'b0;
   parameter [0:0] IS_PRE_INVERTED = 1'b0;
   initial Q <= INIT;
+`ifndef _ABC
   generate case ({|IS_C_INVERTED, |IS_PRE_INVERTED})
     2'b00: always @(posedge C, posedge PRE) if ( PRE) Q <= 1'b1; else if (CE) Q <= D ^ IS_D_INVERTED;
     2'b01: always @(posedge C, negedge PRE) if (!PRE) Q <= 1'b1; else if (CE) Q <= D ^ IS_D_INVERTED;
     2'b10: always @(negedge C, posedge PRE) if ( PRE) Q <= 1'b1; else if (CE) Q <= D ^ IS_D_INVERTED;
     2'b11: always @(negedge C, negedge PRE) if (!PRE) Q <= 1'b1; else if (CE) Q <= D ^ IS_D_INVERTED;
   endcase endgenerate
+`else
+  generate case (|IS_PRE_INVERTED)
+    1'b0: always @* if ( PRE) Q <= 1'b1; else if (CE) Q <= D ^ IS_D_INVERTED;
+    1'b1: always @* if (!PRE) Q <= 1'b1; else if (CE) Q <= D ^ IS_D_INVERTED;
+  endcase endgenerate
+`endif
 endmodule
 
 module FDRE_1 ((* abc_flop_q *) output reg Q, input C, CE, D, R);
-- 
cgit v1.2.3


From 2228cef62f8550f85b203752681e2abeef1197ea Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Fri, 31 May 2019 18:11:46 -0700
Subject: Add flops as blackboxes

---
 techlibs/xilinx/abc.box  | 20 ++++++++++++++++++++
 techlibs/xilinx/ff_map.v |  7 +++++++
 2 files changed, 27 insertions(+)

(limited to 'techlibs')

diff --git a/techlibs/xilinx/abc.box b/techlibs/xilinx/abc.box
index 6e9e1faf6..a4182ed63 100644
--- a/techlibs/xilinx/abc.box
+++ b/techlibs/xilinx/abc.box
@@ -40,3 +40,23 @@ RAM64X1D 4 0 15 2
 RAM128X1D 5 0 17 2
 -   -   -   -   -   -   -   - 314 314 314 314 314 314 292 - -
 347 347 347 347 347 347 296 - -   -   -   -   -   -   -   - -
+
+# Inputs: C CE D R
+# Outputs: Q
+FDRE 6 0 4 1
+- - - -
+
+# Inputs: C CE D S
+# Outputs: Q
+FDSE 7 0 4 1
+- - - -
+
+# Inputs: C CE CLR D
+# Outputs: Q
+FDCE 8 0 4 1
+- - 404 -
+
+# Inputs: C CE D PRE
+# Outputs: Q
+FDPE 9 0 4 1
+- - - 404
diff --git a/techlibs/xilinx/ff_map.v b/techlibs/xilinx/ff_map.v
index 13beaa6ae..7c837814a 100644
--- a/techlibs/xilinx/ff_map.v
+++ b/techlibs/xilinx/ff_map.v
@@ -38,5 +38,12 @@ module  \$_DFF_NP1_ (input D, C, R, output Q); FDPE_1 #(.INIT(|0)) _TECHMAP_REPL
 module  \$_DFF_PN1_ (input D, C, R, output Q); FDPE   #(.INIT(|0)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1'b1), .PRE(!R)); endmodule
 module  \$_DFF_PP1_ (input D, C, R, output Q); FDPE   #(.INIT(|0)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1'b1), .PRE( R)); endmodule
 
+`ifndef DEPRECATED
+module FDRE_1 (output reg Q, input C, CE, D, R);   parameter [0:0] INIT = 1'b0; FDRE #(.INIT(INIT), .IS_CLK_INVERTED(1'b1)) _TECHMAP_REPLACE_ (.C(C), .CE(CE), .D(D), .R(R), .Q(Q)); endmodule
+module FDSE_1 (output reg Q, input C, CE, D, S);   parameter [0:0] INIT = 1'b0; FDSE #(.INIT(INIT), .IS_CLK_INVERTED(1'b1)) _TECHMAP_REPLACE_ (.C(C), .CE(CE), .D(D), .S(S), .Q(Q)); endmodule
+module FDCE_1 (output reg Q, input C, CE, D, CLR); parameter [0:0] INIT = 1'b0; FDCE #(.INIT(INIT), .IS_CLK_INVERTED(1'b1)) _TECHMAP_REPLACE_ (.C(C), .CE(CE), .D(D), .CLR(CLR), .Q(Q)); endmodule
+module FDPE_1 (output reg Q, input C, CE, D, PRE); parameter [0:0] INIT = 1'b0; FDPE #(.INIT(INIT), .IS_CLK_INVERTED(1'b1)) _TECHMAP_REPLACE_ (.C(C), .CE(CE), .D(D), .PRE(PRE), .Q(Q)); endmodule
+`endif
+
 `endif
 
-- 
cgit v1.2.3


From 9f44a7171528b90e85b2f33ef8823660fbd95609 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Mon, 3 Jun 2019 09:23:43 -0700
Subject: Consistent with xilinx

---
 techlibs/ice40/abc_hx.box     | 2 +-
 techlibs/ice40/cells_sim.v    | 2 +-
 techlibs/ice40/synth_ice40.cc | 4 ++--
 3 files changed, 4 insertions(+), 4 deletions(-)

(limited to 'techlibs')

diff --git a/techlibs/ice40/abc_hx.box b/techlibs/ice40/abc_hx.box
index 994f3091d..9ebdae18b 100644
--- a/techlibs/ice40/abc_hx.box
+++ b/techlibs/ice40/abc_hx.box
@@ -4,7 +4,7 @@
 
 # Inputs: C D
 # Outputs: Q
-SB_DFF 1 1 2 1
+SB_DFF 1 0 2 1
 - -
 
 # Inputs: C D E
diff --git a/techlibs/ice40/cells_sim.v b/techlibs/ice40/cells_sim.v
index b5e10fb20..6897aeeb4 100644
--- a/techlibs/ice40/cells_sim.v
+++ b/techlibs/ice40/cells_sim.v
@@ -145,7 +145,7 @@ endmodule
 
 (* abc_box_id = 1, abc_flop, lib_whitebox *)
 module SB_DFF ((* abc_flop_q *) output `SB_DFF_REG, input C, (* abc_flop_d *) input D);
-`ifndef ABC_MODEL
+`ifndef _ABC
 	always @(posedge C)
 		Q <= D;
 `else
diff --git a/techlibs/ice40/synth_ice40.cc b/techlibs/ice40/synth_ice40.cc
index 168161a90..5afa042b0 100644
--- a/techlibs/ice40/synth_ice40.cc
+++ b/techlibs/ice40/synth_ice40.cc
@@ -240,7 +240,7 @@ struct SynthIce40Pass : public ScriptPass
 	{
 		if (check_label("begin"))
 		{
-			run("read_verilog -lib -D ABC_MODEL +/ice40/cells_sim.v");
+			run("read_verilog -lib -D_ABC +/ice40/cells_sim.v");
 			run(stringf("hierarchy -check %s", help_mode ? "-top <top>" : top_opt.c_str()));
 			run("proc");
 		}
@@ -334,7 +334,7 @@ struct SynthIce40Pass : public ScriptPass
 				if (abc == "abc9")
 					run(abc + stringf(" -dress -lut +/ice40/abc_%s.lut -box +/ice40/abc_%s.box", device_opt.c_str(), device_opt.c_str()), "(skip if -noabc)");
 				else
-					run(abc + " -lut 4", "(skip if -noabc)");
+					run(abc + " -dress -lut 4", "(skip if -noabc)");
 			}
 			run("clean");
 			if (relut || help_mode) {
-- 
cgit v1.2.3


From 4da25c76b365b7c90a368c36def81d1122434b95 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Mon, 3 Jun 2019 09:33:42 -0700
Subject: Ooopsie

---
 techlibs/ice40/cells_map.v | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'techlibs')

diff --git a/techlibs/ice40/cells_map.v b/techlibs/ice40/cells_map.v
index 287c48b11..759549e30 100644
--- a/techlibs/ice40/cells_map.v
+++ b/techlibs/ice40/cells_map.v
@@ -53,7 +53,7 @@ module \$lut (A, Y);
     end else
     if (WIDTH == 4) begin
       localparam [15:0] INIT = {LUT[15], LUT[7], LUT[11], LUT[3], LUT[13], LUT[5], LUT[9], LUT[1], LUT[14], LUT[6], LUT[10], LUT[2], LUT[12], LUT[4], LUT[8], LUT[0]};
-      SB_LUT4 #(.LUT_INIT(LUT)) _TECHMAP_REPLACE_ (.O(Y),
+      SB_LUT4 #(.LUT_INIT(INIT)) _TECHMAP_REPLACE_ (.O(Y),
         .I0(A[3]), .I1(A[2]), .I2(A[1]), .I3(A[0]));
     end else begin
       wire _TECHMAP_FAIL_ = 1;
-- 
cgit v1.2.3


From 00927703177d01ad27559aad827b72068b80b12a Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Mon, 3 Jun 2019 12:34:55 -0700
Subject: Make SB_LUT4 a whitebox, SB_DFF a blackbox (for now)

---
 techlibs/ice40/abc_hx.box  | 2 +-
 techlibs/ice40/abc_lp.box  | 4 ++--
 techlibs/ice40/abc_u.box   | 4 ++--
 techlibs/ice40/cells_sim.v | 6 +++---
 4 files changed, 8 insertions(+), 8 deletions(-)

(limited to 'techlibs')

diff --git a/techlibs/ice40/abc_hx.box b/techlibs/ice40/abc_hx.box
index 9ebdae18b..a0655643d 100644
--- a/techlibs/ice40/abc_hx.box
+++ b/techlibs/ice40/abc_hx.box
@@ -109,5 +109,5 @@ SB_CARRY 21 1 3 1
 
 # Inputs: I0 I1 I2 I3
 # Outputs: O
-SB_LUT4 22 0 4 1
+SB_LUT4 22 1 4 1
 449 400 379 316
diff --git a/techlibs/ice40/abc_lp.box b/techlibs/ice40/abc_lp.box
index 002b7bba4..dbc98d0c4 100644
--- a/techlibs/ice40/abc_lp.box
+++ b/techlibs/ice40/abc_lp.box
@@ -4,7 +4,7 @@
 
 # Inputs: C D
 # Outputs: Q
-SB_DFF 1 1 2 1
+SB_DFF 1 0 2 1
 - -
 
 # Inputs: C D E
@@ -109,5 +109,5 @@ SB_CARRY 21 1 3 1
 
 # Inputs: I0 I1 I2 I3
 # Outputs: O
-SB_LUT4 22 0 4 1
+SB_LUT4 22 1 4 1
 465 558 589 661
diff --git a/techlibs/ice40/abc_u.box b/techlibs/ice40/abc_u.box
index cb336181c..3b5834e40 100644
--- a/techlibs/ice40/abc_u.box
+++ b/techlibs/ice40/abc_u.box
@@ -4,7 +4,7 @@
 
 # Inputs: C D
 # Outputs: Q
-SB_DFF 1 1 2 1
+SB_DFF 1 0 2 1
 - -
 
 # Inputs: C D E
@@ -109,5 +109,5 @@ SB_CARRY 21 1 3 1
 
 # Inputs: I0 I1 I2 I3
 # Outputs: O
-SB_LUT4 22 0 4 1
+SB_LUT4 22 1 4 1
 1285 1231 1205 874
diff --git a/techlibs/ice40/cells_sim.v b/techlibs/ice40/cells_sim.v
index 6897aeeb4..b9f381266 100644
--- a/techlibs/ice40/cells_sim.v
+++ b/techlibs/ice40/cells_sim.v
@@ -127,7 +127,7 @@ endmodule
 
 // SiliconBlue Logic Cells
 
-(* abc_box_id = 22 *)
+(* abc_box_id = 22, lib_whitebox *)
 module SB_LUT4 (output O, input I0, I1, I2, I3);
 	parameter [15:0] LUT_INIT = 0;
 	wire [7:0] s3 = I3 ? LUT_INIT[15:8] : LUT_INIT[7:0];
@@ -136,8 +136,8 @@ module SB_LUT4 (output O, input I0, I1, I2, I3);
 	assign O = I0 ? s1[1] : s1[0];
 endmodule
 
-(* abc_box_id = 21, lib_whitebox *)
-module SB_CARRY (output CO, input I0, I1, CI);
+(* abc_box_id = 21, abc_carry, lib_whitebox *)
+module SB_CARRY ((* abc_carry_out *) output CO, input I0, I1, (* abc_carry_in *) input CI);
 	assign CO = (I0 && I1) || ((I0 || I1) && CI);
 endmodule
 
-- 
cgit v1.2.3


From ebcc85b9b86267a25e9126aa3d82ef4a0bd9f6fd Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Mon, 3 Jun 2019 12:37:02 -0700
Subject: Fix `ifndef

---
 techlibs/xilinx/cells_sim.v | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'techlibs')

diff --git a/techlibs/xilinx/cells_sim.v b/techlibs/xilinx/cells_sim.v
index cce03980d..c8450f8d1 100644
--- a/techlibs/xilinx/cells_sim.v
+++ b/techlibs/xilinx/cells_sim.v
@@ -246,8 +246,8 @@ module FDCE ((* abc_flop_q *) output reg Q, input C, CE, (* abc_flop_d *) input
   parameter [0:0] IS_D_INVERTED = 1'b0;
   parameter [0:0] IS_CLR_INVERTED = 1'b0;
   initial Q <= INIT;
-  generate case ({|IS_C_INVERTED, |IS_CLR_INVERTED})
 `ifndef _ABC
+  generate case ({|IS_C_INVERTED, |IS_CLR_INVERTED})
     2'b00: always @(posedge C, posedge CLR) if ( CLR) Q <= 1'b0; else if (CE) Q <= D ^ IS_D_INVERTED;
     2'b01: always @(posedge C, negedge CLR) if (!CLR) Q <= 1'b0; else if (CE) Q <= D ^ IS_D_INVERTED;
     2'b10: always @(negedge C, posedge CLR) if ( CLR) Q <= 1'b0; else if (CE) Q <= D ^ IS_D_INVERTED;
-- 
cgit v1.2.3


From c9a0bac5413dff55e141deb4098b63ca4c62e5b1 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Mon, 3 Jun 2019 19:45:56 -0700
Subject: IS_C_INVERTED

---
 techlibs/xilinx/ff_map.v | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

(limited to 'techlibs')

diff --git a/techlibs/xilinx/ff_map.v b/techlibs/xilinx/ff_map.v
index 7c837814a..ce465130d 100644
--- a/techlibs/xilinx/ff_map.v
+++ b/techlibs/xilinx/ff_map.v
@@ -39,10 +39,10 @@ module  \$_DFF_PN1_ (input D, C, R, output Q); FDPE   #(.INIT(|0)) _TECHMAP_REPL
 module  \$_DFF_PP1_ (input D, C, R, output Q); FDPE   #(.INIT(|0)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1'b1), .PRE( R)); endmodule
 
 `ifndef DEPRECATED
-module FDRE_1 (output reg Q, input C, CE, D, R);   parameter [0:0] INIT = 1'b0; FDRE #(.INIT(INIT), .IS_CLK_INVERTED(1'b1)) _TECHMAP_REPLACE_ (.C(C), .CE(CE), .D(D), .R(R), .Q(Q)); endmodule
-module FDSE_1 (output reg Q, input C, CE, D, S);   parameter [0:0] INIT = 1'b0; FDSE #(.INIT(INIT), .IS_CLK_INVERTED(1'b1)) _TECHMAP_REPLACE_ (.C(C), .CE(CE), .D(D), .S(S), .Q(Q)); endmodule
-module FDCE_1 (output reg Q, input C, CE, D, CLR); parameter [0:0] INIT = 1'b0; FDCE #(.INIT(INIT), .IS_CLK_INVERTED(1'b1)) _TECHMAP_REPLACE_ (.C(C), .CE(CE), .D(D), .CLR(CLR), .Q(Q)); endmodule
-module FDPE_1 (output reg Q, input C, CE, D, PRE); parameter [0:0] INIT = 1'b0; FDPE #(.INIT(INIT), .IS_CLK_INVERTED(1'b1)) _TECHMAP_REPLACE_ (.C(C), .CE(CE), .D(D), .PRE(PRE), .Q(Q)); endmodule
+module FDRE_1 (output reg Q, input C, CE, D, R);   parameter [0:0] INIT = 1'b0; FDRE #(.INIT(INIT), .IS_C_INVERTED(1'b1)) _TECHMAP_REPLACE_ (.C(C), .CE(CE), .D(D), .R(R), .Q(Q)); endmodule
+module FDSE_1 (output reg Q, input C, CE, D, S);   parameter [0:0] INIT = 1'b0; FDSE #(.INIT(INIT), .IS_C_INVERTED(1'b1)) _TECHMAP_REPLACE_ (.C(C), .CE(CE), .D(D), .S(S), .Q(Q)); endmodule
+module FDCE_1 (output reg Q, input C, CE, D, CLR); parameter [0:0] INIT = 1'b0; FDCE #(.INIT(INIT), .IS_C_INVERTED(1'b1)) _TECHMAP_REPLACE_ (.C(C), .CE(CE), .D(D), .CLR(CLR), .Q(Q)); endmodule
+module FDPE_1 (output reg Q, input C, CE, D, PRE); parameter [0:0] INIT = 1'b0; FDPE #(.INIT(INIT), .IS_C_INVERTED(1'b1)) _TECHMAP_REPLACE_ (.C(C), .CE(CE), .D(D), .PRE(PRE), .Q(Q)); endmodule
 `endif
 
 `endif
-- 
cgit v1.2.3


From b6e59741ae6e4ec57affb9ab168a9d08cdb6d04f Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Mon, 3 Jun 2019 20:21:41 -0700
Subject: Typo

---
 techlibs/xilinx/cells_sim.v | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'techlibs')

diff --git a/techlibs/xilinx/cells_sim.v b/techlibs/xilinx/cells_sim.v
index c8450f8d1..16b8b4949 100644
--- a/techlibs/xilinx/cells_sim.v
+++ b/techlibs/xilinx/cells_sim.v
@@ -262,7 +262,7 @@ module FDCE ((* abc_flop_q *) output reg Q, input C, CE, (* abc_flop_d *) input
 endmodule
 
 (* abc_box_id = 9, abc_flop /*, lib_whitebox*/ *)
-module FDPE ((* abc_flop_q *) output reg Q, input C, CE, (* abc_flop_q *) input D, input PRE);
+module FDPE ((* abc_flop_q *) output reg Q, input C, CE, (* abc_flop_d *) input D, input PRE);
   parameter [0:0] INIT = 1'b0;
   parameter [0:0] IS_C_INVERTED = 1'b0;
   parameter [0:0] IS_D_INVERTED = 1'b0;
-- 
cgit v1.2.3


From 23a73ca6241381e7272f905d1dcbf01c49ad00a8 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Mon, 3 Jun 2019 23:19:22 -0700
Subject: Merge mistake

---
 techlibs/xilinx/synth_xilinx.cc | 20 ++++++--------------
 1 file changed, 6 insertions(+), 14 deletions(-)

(limited to 'techlibs')

diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc
index e316c268e..4269870d7 100644
--- a/techlibs/xilinx/synth_xilinx.cc
+++ b/techlibs/xilinx/synth_xilinx.cc
@@ -259,13 +259,6 @@ struct SynthXilinxPass : public ScriptPass
 			run("dff2dffe");
 			run("opt -full");
 
-			if (vpr && !nocarry && !help_mode)
-				run("techmap -map +/xilinx/arith_map.v -D _EXPLICIT_CARRY");
-			else if (abc == "abc9" && !nocarry && !help_mode)
-				run("techmap -map +/xilinx/arith_map.v -D _CLB_CARRY", "(skip if '-nocarry')");
-			else if (!nocarry || help_mode)
-				run("techmap -map +/xilinx/arith_map.v", "(skip if '-nocarry')");
-
 			if (!nosrl || help_mode) {
 				// shregmap operates on bit-level flops, not word-level,
 				//   so break those down here
@@ -274,13 +267,12 @@ struct SynthXilinxPass : public ScriptPass
 				run("shregmap -tech xilinx -minlen 3", "(skip if '-nosrl')");
 			}
 
-			if (!nomux || help_mode)
-				run("techmap -map +/xilinx/cells_map.v");
-
-			if (!vpr || help_mode)
-				run("techmap -map +/techmap.v -map +/xilinx/arith_map.v");
-			else
-				run("techmap -map +/techmap.v +/xilinx/arith_map.v -D _EXPLICIT_CARRY");
+			if (vpr && !nocarry && !help_mode)
+				run("techmap -map +/techmap.v -map +/xilinx/arith_map.v -D _EXPLICIT_CARRY");
+			else if (abc == "abc9" && !nocarry && !help_mode)
+				run("techmap -map +/techmap.v -map +/xilinx/arith_map.v -D _CLB_CARRY", "(skip if '-nocarry')");
+			else if (!nocarry || help_mode)
+				run("techmap -map +/techmap.v -map +/xilinx/arith_map.v", "(skip if '-nocarry')");
 
 			run("opt -fast");
 		}
-- 
cgit v1.2.3


From 5afa42432f71443e69d1095d17066ae173b7883a Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Mon, 3 Jun 2019 23:29:45 -0700
Subject: Fix pmux2shiftx logic

---
 techlibs/xilinx/synth_xilinx.cc | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'techlibs')

diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc
index 4269870d7..19a19d14e 100644
--- a/techlibs/xilinx/synth_xilinx.cc
+++ b/techlibs/xilinx/synth_xilinx.cc
@@ -229,7 +229,7 @@ struct SynthXilinxPass : public ScriptPass
 			//   cells for identifying variable-length shift registers,
 			//   so attempt to convert $pmux-es to the former
 			// Also: wide multiplexer inference benefits from this too
-			if ((!nosrl && !nomux) || help_mode)
+			if (!(nosrl && nomux) || help_mode)
 				run("pmux2shiftx", "(skip if '-nosrl' and '-nomux')");
 
 			// Run a number of peephole optimisations, including one
-- 
cgit v1.2.3


From 09b778744dc036d54209644884e9dc9138f95771 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Mon, 3 Jun 2019 23:42:30 -0700
Subject: Respect -nocarry

---
 techlibs/xilinx/synth_xilinx.cc | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

(limited to 'techlibs')

diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc
index 19a19d14e..8ce552780 100644
--- a/techlibs/xilinx/synth_xilinx.cc
+++ b/techlibs/xilinx/synth_xilinx.cc
@@ -270,9 +270,11 @@ struct SynthXilinxPass : public ScriptPass
 			if (vpr && !nocarry && !help_mode)
 				run("techmap -map +/techmap.v -map +/xilinx/arith_map.v -D _EXPLICIT_CARRY");
 			else if (abc == "abc9" && !nocarry && !help_mode)
-				run("techmap -map +/techmap.v -map +/xilinx/arith_map.v -D _CLB_CARRY", "(skip if '-nocarry')");
+				run("techmap -map +/techmap.v -map +/xilinx/arith_map.v -D _CLB_CARRY");
 			else if (!nocarry || help_mode)
 				run("techmap -map +/techmap.v -map +/xilinx/arith_map.v", "(skip if '-nocarry')");
+			else
+				run("techmap -map +/techmap.v");
 
 			run("opt -fast");
 		}
-- 
cgit v1.2.3


From 9b9bd4e19f3da363eb3c90ef27ace282716d2e06 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Mon, 3 Jun 2019 23:43:23 -0700
Subject: Move ff_map back after ABC for shregmap

---
 techlibs/xilinx/synth_xilinx.cc | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

(limited to 'techlibs')

diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc
index 8ce552780..f45126dc5 100644
--- a/techlibs/xilinx/synth_xilinx.cc
+++ b/techlibs/xilinx/synth_xilinx.cc
@@ -280,9 +280,7 @@ struct SynthXilinxPass : public ScriptPass
 		}
 
 		if (check_label("map_cells")) {
-			run("techmap -map +/techmap.v -map +/xilinx/cells_map.v -map +/xilinx/ff_map.v ");
-			run("dffinit -ff FDRE Q INIT -ff FDCE Q INIT -ff FDPE Q INIT -ff FDSE Q INIT "
-					"-ff FDRE_1 Q INIT -ff FDCE_1 Q INIT -ff FDPE_1 Q INIT -ff FDSE_1 Q INIT");
+			run("techmap -map +/techmap.v -map +/xilinx/cells_map.v");
 			run("clean");
 		}
 
@@ -299,7 +297,9 @@ struct SynthXilinxPass : public ScriptPass
 			//   has performed any necessary retiming
 			if (!nosrl || help_mode)
 				run("shregmap -minlen 3 -init -params -enpol any_or_none", "(skip if '-nosrl')");
-			run("techmap -map +/xilinx/lut_map.v -map +/xilinx/cells_map.v");
+			run("techmap -map +/xilinx/lut_map.v -map +/xilinx/cells_map.v -map +/xilinx/ff_map.v");
+			run("dffinit -ff FDRE Q INIT -ff FDCE Q INIT -ff FDPE Q INIT -ff FDSE Q INIT "
+					"-ff FDRE_1 Q INIT -ff FDCE_1 Q INIT -ff FDPE_1 Q INIT -ff FDSE_1 Q INIT");
 			run("clean");
 		}
 
-- 
cgit v1.2.3


From e260150321f3410056da64f83783b470caa89384 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Tue, 4 Jun 2019 09:51:47 -0700
Subject: Add mux_map.v for wide mux

---
 techlibs/xilinx/Makefile.inc    |  1 +
 techlibs/xilinx/cells_map.v     | 35 +++++++++++----------------
 techlibs/xilinx/mux_map.v       | 52 +++++++++++++++++++++++++++++++++++++++++
 techlibs/xilinx/synth_xilinx.cc | 24 ++++++++++++-------
 4 files changed, 82 insertions(+), 30 deletions(-)
 create mode 100644 techlibs/xilinx/mux_map.v

(limited to 'techlibs')

diff --git a/techlibs/xilinx/Makefile.inc b/techlibs/xilinx/Makefile.inc
index 296edace9..2f3945167 100644
--- a/techlibs/xilinx/Makefile.inc
+++ b/techlibs/xilinx/Makefile.inc
@@ -30,6 +30,7 @@ $(eval $(call add_share_file,share/xilinx,techlibs/xilinx/drams_map.v))
 $(eval $(call add_share_file,share/xilinx,techlibs/xilinx/arith_map.v))
 $(eval $(call add_share_file,share/xilinx,techlibs/xilinx/ff_map.v))
 $(eval $(call add_share_file,share/xilinx,techlibs/xilinx/lut_map.v))
+$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/mux_map.v))
 $(eval $(call add_share_file,share/xilinx,techlibs/xilinx/abc.box))
 $(eval $(call add_share_file,share/xilinx,techlibs/xilinx/abc.lut))
 
diff --git a/techlibs/xilinx/cells_map.v b/techlibs/xilinx/cells_map.v
index af6414667..120d610bb 100644
--- a/techlibs/xilinx/cells_map.v
+++ b/techlibs/xilinx/cells_map.v
@@ -2,6 +2,7 @@
  *  yosys -- Yosys Open SYnthesis Suite
  *
  *  Copyright (C) 2012  Clifford Wolf <clifford@clifford.at>
+ *                2019  Eddie Hung    <eddie@fpgeh.com>
  *
  *  Permission to use, copy, modify, and/or distribute this software for any
  *  purpose with or without fee is hereby granted, provided that the above
@@ -152,7 +153,7 @@ module \$__XILINX_SHREG_ (input C, input D, input [31:0] L, input E, output Q, o
   endgenerate
 endmodule
 
-module \$shiftx (A, B, Y);
+module \$__XILINX_MUX_ (A, B, Y);
   parameter A_SIGNED = 0;
   parameter B_SIGNED = 0;
   parameter A_WIDTH = 1;
@@ -184,18 +185,10 @@ module \$shiftx (A, B, Y);
 
   generate
     genvar i, j;
-    // TODO: Check if this opt still necessary
-    if (B_SIGNED) begin
-      if (_TECHMAP_CONSTMSK_B_[B_WIDTH-1] && _TECHMAP_CONSTVAL_B_[B_WIDTH-1] == 1'b0)
-        // Optimisation to remove B_SIGNED if sign bit of B is constant-0
-        \$shiftx  #(.A_SIGNED(A_SIGNED), .B_SIGNED(0), .A_WIDTH(A_WIDTH), .B_WIDTH(B_WIDTH-1'd1), .Y_WIDTH(Y_WIDTH)) _TECHMAP_REPLACE_ (.A(A), .B(B[B_WIDTH-2:0]), .Y(Y));
-      else
-        wire _TECHMAP_FAIL_ = 1;
-    end
     // Bit-blast
-    else if (Y_WIDTH > 1) begin
+    if (Y_WIDTH > 1) begin
       for (i = 0; i < Y_WIDTH; i++)
-        \$shiftx  #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(A_WIDTH-Y_WIDTH+1), .B_WIDTH(B_WIDTH), .Y_WIDTH(1'd1)) bitblast (.A(A[A_WIDTH-Y_WIDTH+i:i]), .B(B), .Y(Y[i]));
+        \$__XILINX_MUX_  #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(A_WIDTH-Y_WIDTH+1), .B_WIDTH(B_WIDTH), .Y_WIDTH(1'd1)) bitblast (.A(A[A_WIDTH-Y_WIDTH+i:i]), .B(B), .Y(Y[i]));
     end
     // If the LSB of B is constant zero (and Y_WIDTH is 1) then
     //   we can optimise by removing every other entry from A
@@ -204,24 +197,24 @@ module \$shiftx (A, B, Y);
       wire [(A_WIDTH+1)/2-1:0] A_i;
       for (i = 0; i < (A_WIDTH+1)/2; i++)
         assign A_i[i] = A[i*2];
-      \$shiftx  #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH((A_WIDTH+1'd1)/2'd2), .B_WIDTH(B_WIDTH-1'd1), .Y_WIDTH(Y_WIDTH)) _TECHMAP_REPLACE_ (.A(A_i), .B(B[B_WIDTH-1:1]), .Y(Y));
+      \$__XILINX_MUX_  #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH((A_WIDTH+1'd1)/2'd2), .B_WIDTH(B_WIDTH-1'd1), .Y_WIDTH(Y_WIDTH)) _TECHMAP_REPLACE_ (.A(A_i), .B(B[B_WIDTH-1:1]), .Y(Y));
     end
     // Trim off any leading 1'bx -es in A, and resize B accordingly
     else if (num_leading_X_in_A > 0) begin
       localparam A_WIDTH_new = A_WIDTH - num_leading_X_in_A;
       localparam B_WIDTH_new = $clog2(A_WIDTH_new);
-      \$shiftx  #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(A_WIDTH_new), .B_WIDTH(B_WIDTH_new), .Y_WIDTH(Y_WIDTH)) _TECHMAP_REPLACE_ (.A(A[A_WIDTH_new-1:0]), .B(B[B_WIDTH_new-1:0]), .Y(Y));
+      \$__XILINX_MUX_  #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(A_WIDTH_new), .B_WIDTH(B_WIDTH_new), .Y_WIDTH(Y_WIDTH)) _TECHMAP_REPLACE_ (.A(A[A_WIDTH_new-1:0]), .B(B[B_WIDTH_new-1:0]), .Y(Y));
     end
     else if (B_WIDTH < 3 || A_WIDTH <= 4) begin
-      wire _TECHMAP_FAIL_ = 1;
+      \$shiftx  #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(A_WIDTH), .B_WIDTH(B_WIDTH), .Y_WIDTH(Y_WIDTH)) _TECHMAP_REPLACE_ (.A(A), .B(B), .Y(Y));
     end
     else if (B_WIDTH == 3) begin
       localparam a_width0 = 2 ** 2;
       localparam a_widthN = A_WIDTH - a_width0;
       wire T0, T1;
-      \$shiftx  #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(a_width0), .B_WIDTH(2),                .Y_WIDTH(Y_WIDTH)) fpga_shiftx      (.A(A[a_width0-1:0]),       .B(B[2-1:0]),                .Y(T0));
+      \$shiftx  #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(a_width0), .B_WIDTH(2),                .Y_WIDTH(Y_WIDTH)) fpga_mux      (.A(A[a_width0-1:0]),       .B(B[2-1:0]),                .Y(T0));
       if (a_widthN > 1)
-        \$shiftx  #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(a_widthN), .B_WIDTH($clog2(a_widthN)), .Y_WIDTH(Y_WIDTH)) fpga_shiftx_last (.A(A[A_WIDTH-1:a_width0]), .B(B[$clog2(a_widthN)-1:0]), .Y(T1));
+        \$shiftx  #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(a_widthN), .B_WIDTH($clog2(a_widthN)), .Y_WIDTH(Y_WIDTH)) fpga_mux_last (.A(A[A_WIDTH-1:a_width0]), .B(B[$clog2(a_widthN)-1:0]), .Y(T1));
       else
         assign T1 = A[A_WIDTH-1];
       MUXF7 fpga_mux (.I0(T0), .I1(T1), .S(B[B_WIDTH-1]), .O(Y));
@@ -234,10 +227,10 @@ module \$shiftx (A, B, Y);
       wire T0, T1;
       for (i = 0; i < 4; i++)
         if (i < num_mux8)
-          \$shiftx  #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(a_width0), .B_WIDTH(2),                .Y_WIDTH(Y_WIDTH)) fpga_shiftx      (.A(A[i*a_width0+:a_width0]), .B(B[2-1:0]),                .Y(T[i]));
+          \$shiftx  #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(a_width0), .B_WIDTH(2),                .Y_WIDTH(Y_WIDTH)) fpga_mux      (.A(A[i*a_width0+:a_width0]), .B(B[2-1:0]),                .Y(T[i]));
         else if (i == num_mux8 && a_widthN > 0) begin
           if (a_widthN > 1)
-            \$shiftx  #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(a_widthN), .B_WIDTH($clog2(a_widthN)), .Y_WIDTH(Y_WIDTH)) fpga_shiftx_last (.A(A[A_WIDTH-1:i*a_width0]), .B(B[$clog2(a_widthN)-1:0]), .Y(T[i]));
+            \$shiftx  #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(a_widthN), .B_WIDTH($clog2(a_widthN)), .Y_WIDTH(Y_WIDTH)) fpga_mux_last (.A(A[A_WIDTH-1:i*a_width0]), .B(B[$clog2(a_widthN)-1:0]), .Y(T[i]));
           else
             assign T[i] = A[A_WIDTH-1];
         end
@@ -254,16 +247,16 @@ module \$shiftx (A, B, Y);
       wire [(2**(B_WIDTH-4))-1:0] T;
       for (i = 0; i < 2 ** (B_WIDTH-4); i++)
         if (i < num_mux16)
-          \$shiftx  #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(a_width0), .B_WIDTH(4),                .Y_WIDTH(Y_WIDTH)) fpga_shiftx      (.A(A[i*a_width0+:a_width0]), .B(B[4-1:0]),                .Y(T[i]));
+          \$__XILINX_MUX_  #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(a_width0), .B_WIDTH(4),                .Y_WIDTH(Y_WIDTH)) fpga_mux      (.A(A[i*a_width0+:a_width0]), .B(B[4-1:0]),                .Y(T[i]));
         else if (i == num_mux16 && a_widthN > 0) begin
           if (a_widthN > 1)
-            \$shiftx  #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(a_widthN), .B_WIDTH($clog2(a_widthN)), .Y_WIDTH(Y_WIDTH)) fpga_shiftx_last (.A(A[A_WIDTH-1:i*a_width0]), .B(B[$clog2(a_widthN)-1:0]), .Y(T[i]));
+            \$__XILINX_MUX_  #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(a_widthN), .B_WIDTH($clog2(a_widthN)), .Y_WIDTH(Y_WIDTH)) fpga_mux_last (.A(A[A_WIDTH-1:i*a_width0]), .B(B[$clog2(a_widthN)-1:0]), .Y(T[i]));
           else
             assign T[i] = A[A_WIDTH-1];
         end
         else
           assign T[i] = 1'bx;
-      \$shiftx  #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(2**(B_WIDTH-4)), .B_WIDTH(B_WIDTH-4), .Y_WIDTH(Y_WIDTH)) fpga_shiftx (.A(T), .B(B[B_WIDTH-1:4]), .Y(Y));
+      \$__XILINX_MUX_  #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(2**(B_WIDTH-4)), .B_WIDTH(B_WIDTH-4), .Y_WIDTH(Y_WIDTH)) fpga_mux (.A(T), .B(B[B_WIDTH-1:4]), .Y(Y));
     end
   endgenerate
 endmodule
diff --git a/techlibs/xilinx/mux_map.v b/techlibs/xilinx/mux_map.v
new file mode 100644
index 000000000..2ad7f7671
--- /dev/null
+++ b/techlibs/xilinx/mux_map.v
@@ -0,0 +1,52 @@
+/*
+ *  yosys -- Yosys Open SYnthesis Suite
+ *
+ *  Copyright (C) 2012  Clifford Wolf <clifford@clifford.at>
+ *                2019  Eddie Hung    <eddie@fpgeh.com>
+ *
+ *  Permission to use, copy, modify, and/or distribute this software for any
+ *  purpose with or without fee is hereby granted, provided that the above
+ *  copyright notice and this permission notice appear in all copies.
+ *
+ *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ */
+
+module \$shiftx (A, B, Y);
+  parameter A_SIGNED = 0;
+  parameter B_SIGNED = 0;
+  parameter A_WIDTH = 1;
+  parameter B_WIDTH = 1;
+  parameter Y_WIDTH = 1;
+
+  input [A_WIDTH-1:0] A;
+  input [B_WIDTH-1:0] B;
+  output [Y_WIDTH-1:0] Y;
+
+  parameter [B_WIDTH-1:0] _TECHMAP_CONSTMSK_B_ = 0;
+  parameter [B_WIDTH-1:0] _TECHMAP_CONSTVAL_B_ = 0;
+
+  generate
+    genvar i, j;
+    // TODO: Check if this opt still necessary
+    if (B_SIGNED) begin
+      if (_TECHMAP_CONSTMSK_B_[B_WIDTH-1] && _TECHMAP_CONSTVAL_B_[B_WIDTH-1] == 1'b0)
+        // Optimisation to remove B_SIGNED if sign bit of B is constant-0
+        \$__XILINX_MUX_  #(.A_SIGNED(A_SIGNED), .B_SIGNED(0), .A_WIDTH(A_WIDTH), .B_WIDTH(B_WIDTH-1'd1), .Y_WIDTH(Y_WIDTH)) _TECHMAP_REPLACE_ (.A(A), .B(B[B_WIDTH-2:0]), .Y(Y));
+      else
+        wire _TECHMAP_FAIL_ = 1;
+    end
+    else if (B_WIDTH < 3 || A_WIDTH <= 4) begin
+      wire _TECHMAP_FAIL_ = 1;
+    end
+    else begin
+        \$__XILINX_MUX_  #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(A_WIDTH), .B_WIDTH(B_WIDTH), .Y_WIDTH(Y_WIDTH)) _TECHMAP_REPLACE_ (.A(A), .B(B), .Y(Y));
+    end
+  endgenerate
+endmodule
diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc
index f45126dc5..360418975 100644
--- a/techlibs/xilinx/synth_xilinx.cc
+++ b/techlibs/xilinx/synth_xilinx.cc
@@ -267,15 +267,21 @@ struct SynthXilinxPass : public ScriptPass
 				run("shregmap -tech xilinx -minlen 3", "(skip if '-nosrl')");
 			}
 
-			if (vpr && !nocarry && !help_mode)
-				run("techmap -map +/techmap.v -map +/xilinx/arith_map.v -D _EXPLICIT_CARRY");
-			else if (abc == "abc9" && !nocarry && !help_mode)
-				run("techmap -map +/techmap.v -map +/xilinx/arith_map.v -D _CLB_CARRY");
-			else if (!nocarry || help_mode)
-				run("techmap -map +/techmap.v -map +/xilinx/arith_map.v", "(skip if '-nocarry')");
-			else
-				run("techmap -map +/techmap.v");
-
+			std::string techmap_files = " -map +/techmap.v";
+			if (help_mode)
+					techmap_files += " [-map +/xilinx/mux_map.v]";
+			else if (!nomux)
+					techmap_files += " -map +/xilinx/mux_map.v";
+			if (help_mode)
+					techmap_files += " [-map +/xilinx/arith_map.v]";
+			else if (!nocarry) {
+					techmap_files += " -map +/xilinx/arith_map.v";
+					if (vpr)
+							techmap_files += " -D _EXPLICIT_CARRY";
+					else if (abc == "abc9")
+							techmap_files += " -D _CLB_CARRY";
+			}
+			run("techmap " + techmap_files);
 			run("opt -fast");
 		}
 
-- 
cgit v1.2.3


From 6cf092641f3e39b466f1f36617a1474f9ae36901 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Tue, 4 Jun 2019 09:56:36 -0700
Subject: Fix name clash

---
 techlibs/xilinx/cells_map.v | 22 +++++++++++-----------
 1 file changed, 11 insertions(+), 11 deletions(-)

(limited to 'techlibs')

diff --git a/techlibs/xilinx/cells_map.v b/techlibs/xilinx/cells_map.v
index 120d610bb..f3422349f 100644
--- a/techlibs/xilinx/cells_map.v
+++ b/techlibs/xilinx/cells_map.v
@@ -212,12 +212,12 @@ module \$__XILINX_MUX_ (A, B, Y);
       localparam a_width0 = 2 ** 2;
       localparam a_widthN = A_WIDTH - a_width0;
       wire T0, T1;
-      \$shiftx  #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(a_width0), .B_WIDTH(2),                .Y_WIDTH(Y_WIDTH)) fpga_mux      (.A(A[a_width0-1:0]),       .B(B[2-1:0]),                .Y(T0));
+      \$shiftx  #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(a_width0), .B_WIDTH(2),                .Y_WIDTH(Y_WIDTH)) fpga_soft_mux      (.A(A[a_width0-1:0]),       .B(B[2-1:0]),                .Y(T0));
       if (a_widthN > 1)
-        \$shiftx  #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(a_widthN), .B_WIDTH($clog2(a_widthN)), .Y_WIDTH(Y_WIDTH)) fpga_mux_last (.A(A[A_WIDTH-1:a_width0]), .B(B[$clog2(a_widthN)-1:0]), .Y(T1));
+        \$shiftx  #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(a_widthN), .B_WIDTH($clog2(a_widthN)), .Y_WIDTH(Y_WIDTH)) fpga_soft_mux_last (.A(A[A_WIDTH-1:a_width0]), .B(B[$clog2(a_widthN)-1:0]), .Y(T1));
       else
         assign T1 = A[A_WIDTH-1];
-      MUXF7 fpga_mux (.I0(T0), .I1(T1), .S(B[B_WIDTH-1]), .O(Y));
+      MUXF7 fpga_hard_mux (.I0(T0), .I1(T1), .S(B[B_WIDTH-1]), .O(Y));
     end
     else if (B_WIDTH == 4) begin
       localparam a_width0 = 2 ** 2;
@@ -227,18 +227,18 @@ module \$__XILINX_MUX_ (A, B, Y);
       wire T0, T1;
       for (i = 0; i < 4; i++)
         if (i < num_mux8)
-          \$shiftx  #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(a_width0), .B_WIDTH(2),                .Y_WIDTH(Y_WIDTH)) fpga_mux      (.A(A[i*a_width0+:a_width0]), .B(B[2-1:0]),                .Y(T[i]));
+          \$shiftx  #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(a_width0), .B_WIDTH(2),                .Y_WIDTH(Y_WIDTH)) fpga_soft_mux      (.A(A[i*a_width0+:a_width0]), .B(B[2-1:0]),                .Y(T[i]));
         else if (i == num_mux8 && a_widthN > 0) begin
           if (a_widthN > 1)
-            \$shiftx  #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(a_widthN), .B_WIDTH($clog2(a_widthN)), .Y_WIDTH(Y_WIDTH)) fpga_mux_last (.A(A[A_WIDTH-1:i*a_width0]), .B(B[$clog2(a_widthN)-1:0]), .Y(T[i]));
+            \$shiftx  #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(a_widthN), .B_WIDTH($clog2(a_widthN)), .Y_WIDTH(Y_WIDTH)) fpga_soft_mux_last (.A(A[A_WIDTH-1:i*a_width0]), .B(B[$clog2(a_widthN)-1:0]), .Y(T[i]));
           else
             assign T[i] = A[A_WIDTH-1];
         end
         else
           assign T[i] = 1'bx;
-      MUXF7 fpga_mux_0 (.I0(T[0]), .I1(T[1]), .S(B[2]), .O(T0));
-      MUXF7 fpga_mux_1 (.I0(T[2]), .I1(T[3]), .S(B[2]), .O(T1));
-      MUXF8 fpga_mux_2 (.I0(T0),   .I1(T1),   .S(B[3]), .O(Y));
+      MUXF7 fpga_hard_mux_0 (.I0(T[0]), .I1(T[1]), .S(B[2]), .O(T0));
+      MUXF7 fpga_hard_mux_1 (.I0(T[2]), .I1(T[3]), .S(B[2]), .O(T1));
+      MUXF8 fpga_hard_mux_2 (.I0(T0),   .I1(T1),   .S(B[3]), .O(Y));
     end
     else begin
       localparam a_width0 = 2 ** 4;
@@ -247,16 +247,16 @@ module \$__XILINX_MUX_ (A, B, Y);
       wire [(2**(B_WIDTH-4))-1:0] T;
       for (i = 0; i < 2 ** (B_WIDTH-4); i++)
         if (i < num_mux16)
-          \$__XILINX_MUX_  #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(a_width0), .B_WIDTH(4),                .Y_WIDTH(Y_WIDTH)) fpga_mux      (.A(A[i*a_width0+:a_width0]), .B(B[4-1:0]),                .Y(T[i]));
+          \$__XILINX_MUX_  #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(a_width0), .B_WIDTH(4),                .Y_WIDTH(Y_WIDTH)) fpga_soft_mux      (.A(A[i*a_width0+:a_width0]), .B(B[4-1:0]),                .Y(T[i]));
         else if (i == num_mux16 && a_widthN > 0) begin
           if (a_widthN > 1)
-            \$__XILINX_MUX_  #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(a_widthN), .B_WIDTH($clog2(a_widthN)), .Y_WIDTH(Y_WIDTH)) fpga_mux_last (.A(A[A_WIDTH-1:i*a_width0]), .B(B[$clog2(a_widthN)-1:0]), .Y(T[i]));
+            \$__XILINX_MUX_  #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(a_widthN), .B_WIDTH($clog2(a_widthN)), .Y_WIDTH(Y_WIDTH)) fpga_soft_mux_last (.A(A[A_WIDTH-1:i*a_width0]), .B(B[$clog2(a_widthN)-1:0]), .Y(T[i]));
           else
             assign T[i] = A[A_WIDTH-1];
         end
         else
           assign T[i] = 1'bx;
-      \$__XILINX_MUX_  #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(2**(B_WIDTH-4)), .B_WIDTH(B_WIDTH-4), .Y_WIDTH(Y_WIDTH)) fpga_mux (.A(T), .B(B[B_WIDTH-1:4]), .Y(Y));
+      \$__XILINX_MUX_  #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(2**(B_WIDTH-4)), .B_WIDTH(B_WIDTH-4), .Y_WIDTH(Y_WIDTH)) _TECHMAP_REPLACE_ (.A(T), .B(B[B_WIDTH-1:4]), .Y(Y));
     end
   endgenerate
 endmodule
-- 
cgit v1.2.3


From f0e93f33cf089a1c1924e569700792bf198b6810 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Tue, 4 Jun 2019 11:53:51 -0700
Subject: Add (* abc_flop_q *) to brams_bb.v

---
 techlibs/xilinx/brams_bb.v | 16 ++++++++--------
 1 file changed, 8 insertions(+), 8 deletions(-)

(limited to 'techlibs')

diff --git a/techlibs/xilinx/brams_bb.v b/techlibs/xilinx/brams_bb.v
index a682ba4a7..f540d299d 100644
--- a/techlibs/xilinx/brams_bb.v
+++ b/techlibs/xilinx/brams_bb.v
@@ -19,10 +19,10 @@ module RAMB18E1 (
 	input [1:0] WEA,
 	input [3:0] WEBWE,
 
-	output [15:0] DOADO,
-	output [15:0] DOBDO,
-	output [1:0] DOPADOP,
-	output [1:0] DOPBDOP
+	(* abc_flop_q *) output [15:0] DOADO,
+	(* abc_flop_q *) output [15:0] DOBDO,
+	(* abc_flop_q *) output [1:0] DOPADOP,
+	(* abc_flop_q *) output [1:0] DOPBDOP
 );
 	parameter INITP_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
 	parameter INITP_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
@@ -143,10 +143,10 @@ module RAMB36E1 (
 	input [3:0] WEA,
 	input [7:0] WEBWE,
 
-	output [31:0] DOADO,
-	output [31:0] DOBDO,
-	output [3:0] DOPADOP,
-	output [3:0] DOPBDOP
+	(* abc_flop_q *) output [31:0] DOADO,
+	(* abc_flop_q *) output [31:0] DOBDO,
+	(* abc_flop_q *) output [3:0] DOPADOP,
+	(* abc_flop_q *) output [3:0] DOPBDOP
 );
 	parameter INITP_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
 	parameter INITP_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-- 
cgit v1.2.3


From 82d41bc2f2460a06e153eac4f3968ef29ce5a63d Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Tue, 4 Jun 2019 11:54:08 -0700
Subject: Add space between -D and _ABC

---
 techlibs/xilinx/synth_xilinx.cc | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

(limited to 'techlibs')

diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc
index 360418975..e9eccfc0e 100644
--- a/techlibs/xilinx/synth_xilinx.cc
+++ b/techlibs/xilinx/synth_xilinx.cc
@@ -203,9 +203,9 @@ struct SynthXilinxPass : public ScriptPass
 	{
 		if (check_label("begin")) {
 			if (vpr)
-				run("read_verilog -lib -D_ABC -D_EXPLICIT_CARRY +/xilinx/cells_sim.v");
+				run("read_verilog -lib -D _ABC -D_EXPLICIT_CARRY +/xilinx/cells_sim.v");
 			else
-				run("read_verilog -lib -D_ABC +/xilinx/cells_sim.v");
+				run("read_verilog -lib -D _ABC +/xilinx/cells_sim.v");
 
 			run("read_verilog -lib +/xilinx/cells_xtra.v");
 
-- 
cgit v1.2.3


From 94a5f4e60985fc1e3fea75eec85638fa29874bea Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Tue, 4 Jun 2019 14:34:36 -0700
Subject: Rename shregmap -tech xilinx -> xilinx_dynamic

---
 techlibs/xilinx/synth_xilinx.cc | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

(limited to 'techlibs')

diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc
index e9eccfc0e..b2559d272 100644
--- a/techlibs/xilinx/synth_xilinx.cc
+++ b/techlibs/xilinx/synth_xilinx.cc
@@ -263,8 +263,8 @@ struct SynthXilinxPass : public ScriptPass
 				// shregmap operates on bit-level flops, not word-level,
 				//   so break those down here
 				run("simplemap t:$dff t:$dffe", "(skip if '-nosrl')");
-				// shregmap with '-tech xilinx' infers variable length shift regs
-				run("shregmap -tech xilinx -minlen 3", "(skip if '-nosrl')");
+				// shregmap to infer variable length shift regs
+				run("shregmap -tech xilinx_dynamic -minlen 3", "(skip if '-nosrl')");
 			}
 
 			std::string techmap_files = " -map +/techmap.v";
-- 
cgit v1.2.3


From e473e7456545d702c011ee7872956f94a8522865 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Wed, 5 Jun 2019 11:53:06 -0700
Subject: Revert "Move ff_map back after ABC for shregmap"

This reverts commit 9b9bd4e19f3da363eb3c90ef27ace282716d2e06.
---
 techlibs/xilinx/synth_xilinx.cc | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

(limited to 'techlibs')

diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc
index b2559d272..e825a032c 100644
--- a/techlibs/xilinx/synth_xilinx.cc
+++ b/techlibs/xilinx/synth_xilinx.cc
@@ -286,7 +286,9 @@ struct SynthXilinxPass : public ScriptPass
 		}
 
 		if (check_label("map_cells")) {
-			run("techmap -map +/techmap.v -map +/xilinx/cells_map.v");
+			run("techmap -map +/techmap.v -map +/xilinx/cells_map.v -map +/xilinx/ff_map.v ");
+			run("dffinit -ff FDRE Q INIT -ff FDCE Q INIT -ff FDPE Q INIT -ff FDSE Q INIT "
+					"-ff FDRE_1 Q INIT -ff FDCE_1 Q INIT -ff FDPE_1 Q INIT -ff FDSE_1 Q INIT");
 			run("clean");
 		}
 
@@ -303,9 +305,7 @@ struct SynthXilinxPass : public ScriptPass
 			//   has performed any necessary retiming
 			if (!nosrl || help_mode)
 				run("shregmap -minlen 3 -init -params -enpol any_or_none", "(skip if '-nosrl')");
-			run("techmap -map +/xilinx/lut_map.v -map +/xilinx/cells_map.v -map +/xilinx/ff_map.v");
-			run("dffinit -ff FDRE Q INIT -ff FDCE Q INIT -ff FDPE Q INIT -ff FDSE Q INIT "
-					"-ff FDRE_1 Q INIT -ff FDCE_1 Q INIT -ff FDPE_1 Q INIT -ff FDSE_1 Q INIT");
+			run("techmap -map +/xilinx/lut_map.v -map +/xilinx/cells_map.v");
 			run("clean");
 		}
 
-- 
cgit v1.2.3


From 2c18d530ea69094e7ed46dcf781d8f2517d4c61e Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Wed, 5 Jun 2019 12:28:26 -0700
Subject: Call shregmap -tech xilinx_static

---
 techlibs/xilinx/synth_xilinx.cc | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'techlibs')

diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc
index e825a032c..7686f2cbc 100644
--- a/techlibs/xilinx/synth_xilinx.cc
+++ b/techlibs/xilinx/synth_xilinx.cc
@@ -304,7 +304,7 @@ struct SynthXilinxPass : public ScriptPass
 			// This shregmap call infers fixed length shift registers after abc
 			//   has performed any necessary retiming
 			if (!nosrl || help_mode)
-				run("shregmap -minlen 3 -init -params -enpol any_or_none", "(skip if '-nosrl')");
+				run("shregmap -tech xilinx_static -minlen 3", "(skip if '-nosrl')");
 			run("techmap -map +/xilinx/lut_map.v -map +/xilinx/cells_map.v");
 			run("clean");
 		}
-- 
cgit v1.2.3


From 67f744d428b5385fbddc859c8e02f3e1ccfc17eb Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Wed, 5 Jun 2019 12:28:46 -0700
Subject: Cleanup

---
 techlibs/xilinx/cells_map.v | 10 ----------
 techlibs/xilinx/ff_map.v    |  7 -------
 2 files changed, 17 deletions(-)

(limited to 'techlibs')

diff --git a/techlibs/xilinx/cells_map.v b/techlibs/xilinx/cells_map.v
index f3422349f..4acf04744 100644
--- a/techlibs/xilinx/cells_map.v
+++ b/techlibs/xilinx/cells_map.v
@@ -18,16 +18,6 @@
  *
  */
 
-// Convert negative-polarity reset to positive-polarity
-(* techmap_celltype = "$_DFF_NN0_" *)
-module _90_dff_nn0_to_np0 (input D, C, R, output Q); \$_DFF_NP0_  _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .R(~R)); endmodule
-(* techmap_celltype = "$_DFF_PN0_" *)
-module _90_dff_pn0_to_pp0 (input D, C, R, output Q); \$_DFF_PP0_  _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .R(~R)); endmodule
-(* techmap_celltype = "$_DFF_NN1_" *)
-module _90_dff_nn1_to_np1 (input D, C, R, output Q); \$_DFF_NP1   _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .R(~R)); endmodule
-(* techmap_celltype = "$_DFF_PN1_" *)
-module _90_dff_pn1_to_pp1 (input D, C, R, output Q); \$_DFF_PP1   _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .R(~R)); endmodule
-
 module \$__SHREG_ (input C, input D, input E, output Q);
   parameter DEPTH = 0;
   parameter [DEPTH-1:0] INIT = 0;
diff --git a/techlibs/xilinx/ff_map.v b/techlibs/xilinx/ff_map.v
index ce465130d..13beaa6ae 100644
--- a/techlibs/xilinx/ff_map.v
+++ b/techlibs/xilinx/ff_map.v
@@ -38,12 +38,5 @@ module  \$_DFF_NP1_ (input D, C, R, output Q); FDPE_1 #(.INIT(|0)) _TECHMAP_REPL
 module  \$_DFF_PN1_ (input D, C, R, output Q); FDPE   #(.INIT(|0)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1'b1), .PRE(!R)); endmodule
 module  \$_DFF_PP1_ (input D, C, R, output Q); FDPE   #(.INIT(|0)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1'b1), .PRE( R)); endmodule
 
-`ifndef DEPRECATED
-module FDRE_1 (output reg Q, input C, CE, D, R);   parameter [0:0] INIT = 1'b0; FDRE #(.INIT(INIT), .IS_C_INVERTED(1'b1)) _TECHMAP_REPLACE_ (.C(C), .CE(CE), .D(D), .R(R), .Q(Q)); endmodule
-module FDSE_1 (output reg Q, input C, CE, D, S);   parameter [0:0] INIT = 1'b0; FDSE #(.INIT(INIT), .IS_C_INVERTED(1'b1)) _TECHMAP_REPLACE_ (.C(C), .CE(CE), .D(D), .S(S), .Q(Q)); endmodule
-module FDCE_1 (output reg Q, input C, CE, D, CLR); parameter [0:0] INIT = 1'b0; FDCE #(.INIT(INIT), .IS_C_INVERTED(1'b1)) _TECHMAP_REPLACE_ (.C(C), .CE(CE), .D(D), .CLR(CLR), .Q(Q)); endmodule
-module FDPE_1 (output reg Q, input C, CE, D, PRE); parameter [0:0] INIT = 1'b0; FDPE #(.INIT(INIT), .IS_C_INVERTED(1'b1)) _TECHMAP_REPLACE_ (.C(C), .CE(CE), .D(D), .PRE(PRE), .Q(Q)); endmodule
-`endif
-
 `endif
 
-- 
cgit v1.2.3


From 6ed15b7890091d358b7715413a844a01e9b2adf6 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Wed, 5 Jun 2019 12:33:40 -0700
Subject: Update abc attributes on FD*E_1

---
 techlibs/xilinx/cells_sim.v | 32 ++++++++++++++++++++++++++------
 1 file changed, 26 insertions(+), 6 deletions(-)

(limited to 'techlibs')

diff --git a/techlibs/xilinx/cells_sim.v b/techlibs/xilinx/cells_sim.v
index 16b8b4949..e00992bb7 100644
--- a/techlibs/xilinx/cells_sim.v
+++ b/techlibs/xilinx/cells_sim.v
@@ -283,28 +283,48 @@ module FDPE ((* abc_flop_q *) output reg Q, input C, CE, (* abc_flop_d *) input
 `endif
 endmodule
 
-module FDRE_1 ((* abc_flop_q *) output reg Q, input C, CE, D, R);
+(* abc_box_id = 6, abc_flop /*, lib_whitebox */ *)
+module FDRE_1 ((* abc_flop_q *) output reg Q, input C, CE, (* abc_flop_d *) input D, input R);
   parameter [0:0] INIT = 1'b0;
   initial Q <= INIT;
-  always @(negedge C) if (R) Q <= 1'b0; else if(CE) Q <= D;
+`ifndef _ABC
+  always @(negedge C) if (R) Q <= 1'b0; else if (CE) Q <= D;
+`else
+  always @* if (R) Q <= 1'b0; else if (CE) Q <= D;
+`endif
 endmodule
 
-module FDSE_1 ((* abc_flop_q *) output reg Q, input C, CE, D, S);
+(* abc_box_id = 7, abc_flop /*, lib_whitebox */ *)
+module FDSE_1 ((* abc_flop_q *) output reg Q, input C, CE, (* abc_flop_d *) input D, input S);
   parameter [0:0] INIT = 1'b1;
   initial Q <= INIT;
-  always @(negedge C) if (S) Q <= 1'b1; else if(CE) Q <= D;
+`ifndef _ABC
+  always @(negedge C) if (S) Q <= 1'b1; else if (CE) Q <= D;
+`else
+  always @* if (S) Q <= 1'b1; else if (CE) Q <= D;
+ `endif
 endmodule
 
-module FDCE_1 ((* abc_flop_q *) output reg Q, input C, CE, D, CLR);
+(* abc_box_id = 8, abc_flop /*, lib_whitebox */ *)
+module FDCE_1 ((* abc_flop_q *) output reg Q, input C, CE, (* abc_flop_d *) input D, input CLR);
   parameter [0:0] INIT = 1'b0;
   initial Q <= INIT;
+`ifndef _ABC
   always @(negedge C, posedge CLR) if (CLR) Q <= 1'b0; else if (CE) Q <= D;
+`else
+  always @* if (CLR) Q <= 1'b0; else if (CE) Q <= D;
+`endif
 endmodule
 
-module FDPE_1 ((* abc_flop_q *) output reg Q, input C, CE, D, PRE);
+(* abc_box_id = 9, abc_flop /*, lib_whitebox */ *)
+module FDPE_1 ((* abc_flop_q *) output reg Q, input C, CE, (* abc_flop_d *) input D, input PRE);
   parameter [0:0] INIT = 1'b1;
   initial Q <= INIT;
+`ifndef _ABC
   always @(negedge C, posedge PRE) if (PRE) Q <= 1'b1; else if (CE) Q <= D;
+`else
+  always @* if (PRE) Q <= 1'b1; else if (CE) Q <= D;
+`endif
 endmodule
 
 (* abc_box_id = 4 /*, lib_whitebox*/ *)
-- 
cgit v1.2.3


From 7166dbe418420bf8f0696b21bff22d5f66a4cc8e Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Thu, 6 Jun 2019 14:35:38 -0700
Subject: Remove abc_flop attributes for now

---
 techlibs/xilinx/cells_sim.v | 66 +++++++--------------------------------------
 1 file changed, 10 insertions(+), 56 deletions(-)

(limited to 'techlibs')

diff --git a/techlibs/xilinx/cells_sim.v b/techlibs/xilinx/cells_sim.v
index e00992bb7..88967b068 100644
--- a/techlibs/xilinx/cells_sim.v
+++ b/techlibs/xilinx/cells_sim.v
@@ -205,126 +205,80 @@ endmodule
 
 `endif
 
-(* abc_box_id = 6, abc_flop /*, lib_whitebox */ *)
-module FDRE ((* abc_flop_q *) output reg Q, input C, CE, (* abc_flop_d *) input D, input R);
+module FDRE ((* abc_flop_q *) output reg Q, input C, CE, D, R);
   parameter [0:0] INIT = 1'b0;
   parameter [0:0] IS_C_INVERTED = 1'b0;
   parameter [0:0] IS_D_INVERTED = 1'b0;
   parameter [0:0] IS_R_INVERTED = 1'b0;
   initial Q <= INIT;
-`ifndef _ABC
   generate case (|IS_C_INVERTED)
     1'b0: always @(posedge C) if (R == !IS_R_INVERTED) Q <= 1'b0; else if (CE) Q <= D ^ IS_D_INVERTED;
     1'b1: always @(negedge C) if (R == !IS_R_INVERTED) Q <= 1'b0; else if (CE) Q <= D ^ IS_D_INVERTED;
   endcase endgenerate
-`else
-  always @* if (R == !IS_R_INVERTED) Q <= 1'b0; else if (CE) Q <= D ^ IS_D_INVERTED;
-`endif
 endmodule
 
-(* abc_box_id = 7, abc_flop /*, lib_whitebox*/ *)
-module FDSE ((* abc_flop_q *) output reg Q, input C, CE, (* abc_flop_d *) input D, input S);
+module FDSE ((* abc_flop_q *) output reg Q, input C, CE, D, S);
   parameter [0:0] INIT = 1'b0;
   parameter [0:0] IS_C_INVERTED = 1'b0;
   parameter [0:0] IS_D_INVERTED = 1'b0;
   parameter [0:0] IS_S_INVERTED = 1'b0;
   initial Q <= INIT;
-`ifndef _ABC
   generate case (|IS_C_INVERTED)
     1'b0: always @(posedge C) if (S == !IS_S_INVERTED) Q <= 1'b1; else if (CE) Q <= D ^ IS_D_INVERTED;
     1'b1: always @(negedge C) if (S == !IS_S_INVERTED) Q <= 1'b1; else if (CE) Q <= D ^ IS_D_INVERTED;
   endcase endgenerate
-`else
-    always @* if (S == !IS_S_INVERTED) Q <= 1'b1; else if (CE) Q <= D ^ IS_D_INVERTED;
-`endif
 endmodule
 
-(* abc_box_id = 8, abc_flop /*, lib_whitebox*/ *)
-module FDCE ((* abc_flop_q *) output reg Q, input C, CE, (* abc_flop_d *) input D, input CLR);
+module FDCE ((* abc_flop_q *) output reg Q, input C, CE, D, CLR);
   parameter [0:0] INIT = 1'b0;
   parameter [0:0] IS_C_INVERTED = 1'b0;
   parameter [0:0] IS_D_INVERTED = 1'b0;
   parameter [0:0] IS_CLR_INVERTED = 1'b0;
   initial Q <= INIT;
-`ifndef _ABC
   generate case ({|IS_C_INVERTED, |IS_CLR_INVERTED})
     2'b00: always @(posedge C, posedge CLR) if ( CLR) Q <= 1'b0; else if (CE) Q <= D ^ IS_D_INVERTED;
     2'b01: always @(posedge C, negedge CLR) if (!CLR) Q <= 1'b0; else if (CE) Q <= D ^ IS_D_INVERTED;
     2'b10: always @(negedge C, posedge CLR) if ( CLR) Q <= 1'b0; else if (CE) Q <= D ^ IS_D_INVERTED;
     2'b11: always @(negedge C, negedge CLR) if (!CLR) Q <= 1'b0; else if (CE) Q <= D ^ IS_D_INVERTED;
   endcase endgenerate
-`else
-  generate case (|IS_CLR_INVERTED)
-    1'b0: always @* if ( CLR) Q <= 1'b0; else if (CE) Q <= D ^ IS_D_INVERTED;
-    1'b1: always @* if (!CLR) Q <= 1'b0; else if (CE) Q <= D ^ IS_D_INVERTED;
-  endcase endgenerate
-`endif
 endmodule
 
-(* abc_box_id = 9, abc_flop /*, lib_whitebox*/ *)
-module FDPE ((* abc_flop_q *) output reg Q, input C, CE, (* abc_flop_d *) input D, input PRE);
+module FDPE ((* abc_flop_q *) output reg Q, input C, CE, D, PRE);
   parameter [0:0] INIT = 1'b0;
   parameter [0:0] IS_C_INVERTED = 1'b0;
   parameter [0:0] IS_D_INVERTED = 1'b0;
   parameter [0:0] IS_PRE_INVERTED = 1'b0;
   initial Q <= INIT;
-`ifndef _ABC
   generate case ({|IS_C_INVERTED, |IS_PRE_INVERTED})
     2'b00: always @(posedge C, posedge PRE) if ( PRE) Q <= 1'b1; else if (CE) Q <= D ^ IS_D_INVERTED;
     2'b01: always @(posedge C, negedge PRE) if (!PRE) Q <= 1'b1; else if (CE) Q <= D ^ IS_D_INVERTED;
     2'b10: always @(negedge C, posedge PRE) if ( PRE) Q <= 1'b1; else if (CE) Q <= D ^ IS_D_INVERTED;
     2'b11: always @(negedge C, negedge PRE) if (!PRE) Q <= 1'b1; else if (CE) Q <= D ^ IS_D_INVERTED;
   endcase endgenerate
-`else
-  generate case (|IS_PRE_INVERTED)
-    1'b0: always @* if ( PRE) Q <= 1'b1; else if (CE) Q <= D ^ IS_D_INVERTED;
-    1'b1: always @* if (!PRE) Q <= 1'b1; else if (CE) Q <= D ^ IS_D_INVERTED;
-  endcase endgenerate
-`endif
 endmodule
 
-(* abc_box_id = 6, abc_flop /*, lib_whitebox */ *)
-module FDRE_1 ((* abc_flop_q *) output reg Q, input C, CE, (* abc_flop_d *) input D, input R);
+module FDRE_1 ((* abc_flop_q *) output reg Q, input C, CE, D, R);
   parameter [0:0] INIT = 1'b0;
   initial Q <= INIT;
-`ifndef _ABC
-  always @(negedge C) if (R) Q <= 1'b0; else if (CE) Q <= D;
-`else
-  always @* if (R) Q <= 1'b0; else if (CE) Q <= D;
-`endif
+  always @(negedge C) if (R) Q <= 1'b0; else if(CE) Q <= D;
 endmodule
 
-(* abc_box_id = 7, abc_flop /*, lib_whitebox */ *)
-module FDSE_1 ((* abc_flop_q *) output reg Q, input C, CE, (* abc_flop_d *) input D, input S);
+module FDSE_1 ((* abc_flop_q *) output reg Q, input C, CE, D, S);
   parameter [0:0] INIT = 1'b1;
   initial Q <= INIT;
-`ifndef _ABC
-  always @(negedge C) if (S) Q <= 1'b1; else if (CE) Q <= D;
-`else
-  always @* if (S) Q <= 1'b1; else if (CE) Q <= D;
- `endif
+  always @(negedge C) if (S) Q <= 1'b1; else if(CE) Q <= D;
 endmodule
 
-(* abc_box_id = 8, abc_flop /*, lib_whitebox */ *)
-module FDCE_1 ((* abc_flop_q *) output reg Q, input C, CE, (* abc_flop_d *) input D, input CLR);
+module FDCE_1 ((* abc_flop_q *) output reg Q, input C, CE, D, CLR);
   parameter [0:0] INIT = 1'b0;
   initial Q <= INIT;
-`ifndef _ABC
   always @(negedge C, posedge CLR) if (CLR) Q <= 1'b0; else if (CE) Q <= D;
-`else
-  always @* if (CLR) Q <= 1'b0; else if (CE) Q <= D;
-`endif
 endmodule
 
-(* abc_box_id = 9, abc_flop /*, lib_whitebox */ *)
-module FDPE_1 ((* abc_flop_q *) output reg Q, input C, CE, (* abc_flop_d *) input D, input PRE);
+module FDPE_1 ((* abc_flop_q *) output reg Q, input C, CE, D, PRE);
   parameter [0:0] INIT = 1'b1;
   initial Q <= INIT;
-`ifndef _ABC
   always @(negedge C, posedge PRE) if (PRE) Q <= 1'b1; else if (CE) Q <= D;
-`else
-  always @* if (PRE) Q <= 1'b1; else if (CE) Q <= D;
-`endif
 endmodule
 
 (* abc_box_id = 4 /*, lib_whitebox*/ *)
-- 
cgit v1.2.3


From a8c49168fb1e5e665e126c65dc454183a6d7826b Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Thu, 6 Jun 2019 14:43:08 -0700
Subject: Run muxpack and muxcover in synth_xilinx

---
 techlibs/xilinx/cells_map.v     | 12 ++++++++++++
 techlibs/xilinx/synth_xilinx.cc |  7 ++++++-
 2 files changed, 18 insertions(+), 1 deletion(-)

(limited to 'techlibs')

diff --git a/techlibs/xilinx/cells_map.v b/techlibs/xilinx/cells_map.v
index 4acf04744..8537dc479 100644
--- a/techlibs/xilinx/cells_map.v
+++ b/techlibs/xilinx/cells_map.v
@@ -250,3 +250,15 @@ module \$__XILINX_MUX_ (A, B, Y);
     end
   endgenerate
 endmodule
+
+module \$_MUX8_ (A, B, C, D, E, F, G, H, S, T, U, Y);
+input A, B, C, D, E, F, G, H, S, T, U;
+output Y;
+  \$__XILINX_MUX_  #(.A_SIGNED(0), .B_SIGNED(0), .A_WIDTH(8), .B_WIDTH(3), .Y_WIDTH(1)) _TECHMAP_REPLACE_ (.A({A,B,C,D,E,F,G,H}), .B({U,T,S}), .Y(Y));
+endmodule
+
+module \$_MUX16_ (A, B, C, D, E, F, G, H, I, J, K, L, M, N, O, P, S, T, U, V, Y);
+input A, B, C, D, E, F, G, H, I, J, K, L, M, N, O, P, S, T, U, V;
+output Y;
+  \$__XILINX_MUX_  #(.A_SIGNED(0), .B_SIGNED(0), .A_WIDTH(16), .B_WIDTH(3), .Y_WIDTH(1)) _TECHMAP_REPLACE_ (.A({A,B,C,D,E,F,G,H,I,J,K,L,M,N,O,P}), .B({V,U,T,S}), .Y(Y));
+endmodule
diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc
index 7686f2cbc..a70bb23f1 100644
--- a/techlibs/xilinx/synth_xilinx.cc
+++ b/techlibs/xilinx/synth_xilinx.cc
@@ -225,6 +225,9 @@ struct SynthXilinxPass : public ScriptPass
 		if (check_label("coarse")) {
 			run("synth -run coarse");
 
+			if (!nomux || help_mode)
+				run("muxpack", "(skip if '-nomux')");
+
 			// shregmap -tech xilinx can cope with $shiftx and $mux
 			//   cells for identifying variable-length shift registers,
 			//   so attempt to convert $pmux-es to the former
@@ -286,7 +289,9 @@ struct SynthXilinxPass : public ScriptPass
 		}
 
 		if (check_label("map_cells")) {
-			run("techmap -map +/techmap.v -map +/xilinx/cells_map.v -map +/xilinx/ff_map.v ");
+			if (!nomux || help_mode)
+				run("muxcover", "(skip if '-nomux')");
+			run("techmap -map +/techmap.v -map +/xilinx/cells_map.v -map +/xilinx/ff_map.v");
 			run("dffinit -ff FDRE Q INIT -ff FDCE Q INIT -ff FDPE Q INIT -ff FDSE Q INIT "
 					"-ff FDRE_1 Q INIT -ff FDCE_1 Q INIT -ff FDPE_1 Q INIT -ff FDSE_1 Q INIT");
 			run("clean");
-- 
cgit v1.2.3


From d3b7ae218bd7641a40adfba7809cf0f8bdff31e6 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Thu, 6 Jun 2019 15:31:18 -0700
Subject: Fix muxcover and its techmapping

---
 techlibs/xilinx/cells_map.v     | 4 ++--
 techlibs/xilinx/synth_xilinx.cc | 2 +-
 2 files changed, 3 insertions(+), 3 deletions(-)

(limited to 'techlibs')

diff --git a/techlibs/xilinx/cells_map.v b/techlibs/xilinx/cells_map.v
index 8537dc479..f0d3ebbac 100644
--- a/techlibs/xilinx/cells_map.v
+++ b/techlibs/xilinx/cells_map.v
@@ -254,11 +254,11 @@ endmodule
 module \$_MUX8_ (A, B, C, D, E, F, G, H, S, T, U, Y);
 input A, B, C, D, E, F, G, H, S, T, U;
 output Y;
-  \$__XILINX_MUX_  #(.A_SIGNED(0), .B_SIGNED(0), .A_WIDTH(8), .B_WIDTH(3), .Y_WIDTH(1)) _TECHMAP_REPLACE_ (.A({A,B,C,D,E,F,G,H}), .B({U,T,S}), .Y(Y));
+  \$__XILINX_MUX_  #(.A_SIGNED(0), .B_SIGNED(0), .A_WIDTH(8), .B_WIDTH(3), .Y_WIDTH(1)) _TECHMAP_REPLACE_ (.A({H,G,F,E,D,C,B,A}), .B({U,T,S}), .Y(Y));
 endmodule
 
 module \$_MUX16_ (A, B, C, D, E, F, G, H, I, J, K, L, M, N, O, P, S, T, U, V, Y);
 input A, B, C, D, E, F, G, H, I, J, K, L, M, N, O, P, S, T, U, V;
 output Y;
-  \$__XILINX_MUX_  #(.A_SIGNED(0), .B_SIGNED(0), .A_WIDTH(16), .B_WIDTH(3), .Y_WIDTH(1)) _TECHMAP_REPLACE_ (.A({A,B,C,D,E,F,G,H,I,J,K,L,M,N,O,P}), .B({V,U,T,S}), .Y(Y));
+  \$__XILINX_MUX_  #(.A_SIGNED(0), .B_SIGNED(0), .A_WIDTH(16), .B_WIDTH(4), .Y_WIDTH(1)) _TECHMAP_REPLACE_ (.A({P,O,N,M,L,K,J,I,H,G,F,E,D,C,B,A}), .B({V,U,T,S}), .Y(Y));
 endmodule
diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc
index a70bb23f1..a0c2c781d 100644
--- a/techlibs/xilinx/synth_xilinx.cc
+++ b/techlibs/xilinx/synth_xilinx.cc
@@ -290,7 +290,7 @@ struct SynthXilinxPass : public ScriptPass
 
 		if (check_label("map_cells")) {
 			if (!nomux || help_mode)
-				run("muxcover", "(skip if '-nomux')");
+				run("muxcover -mux8 -mux16", "(skip if '-nomux')");
 			run("techmap -map +/techmap.v -map +/xilinx/cells_map.v -map +/xilinx/ff_map.v");
 			run("dffinit -ff FDRE Q INIT -ff FDCE Q INIT -ff FDPE Q INIT -ff FDSE Q INIT "
 					"-ff FDRE_1 Q INIT -ff FDCE_1 Q INIT -ff FDPE_1 Q INIT -ff FDSE_1 Q INIT");
-- 
cgit v1.2.3


From 88ae13e6a55a36eb66de2424a6138b984ffb6a9e Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Thu, 6 Jun 2019 15:32:36 -0700
Subject: $__XILINX_MUX_ -> $__XILINX_SHIFTX

---
 techlibs/xilinx/cells_map.v | 18 +++++++++---------
 techlibs/xilinx/mux_map.v   |  4 ++--
 2 files changed, 11 insertions(+), 11 deletions(-)

(limited to 'techlibs')

diff --git a/techlibs/xilinx/cells_map.v b/techlibs/xilinx/cells_map.v
index f0d3ebbac..f8f9356bc 100644
--- a/techlibs/xilinx/cells_map.v
+++ b/techlibs/xilinx/cells_map.v
@@ -143,7 +143,7 @@ module \$__XILINX_SHREG_ (input C, input D, input [31:0] L, input E, output Q, o
   endgenerate
 endmodule
 
-module \$__XILINX_MUX_ (A, B, Y);
+module \$__XILINX_SHIFTX (A, B, Y);
   parameter A_SIGNED = 0;
   parameter B_SIGNED = 0;
   parameter A_WIDTH = 1;
@@ -178,7 +178,7 @@ module \$__XILINX_MUX_ (A, B, Y);
     // Bit-blast
     if (Y_WIDTH > 1) begin
       for (i = 0; i < Y_WIDTH; i++)
-        \$__XILINX_MUX_  #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(A_WIDTH-Y_WIDTH+1), .B_WIDTH(B_WIDTH), .Y_WIDTH(1'd1)) bitblast (.A(A[A_WIDTH-Y_WIDTH+i:i]), .B(B), .Y(Y[i]));
+        \$__XILINX_SHIFTX  #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(A_WIDTH-Y_WIDTH+1), .B_WIDTH(B_WIDTH), .Y_WIDTH(1'd1)) bitblast (.A(A[A_WIDTH-Y_WIDTH+i:i]), .B(B), .Y(Y[i]));
     end
     // If the LSB of B is constant zero (and Y_WIDTH is 1) then
     //   we can optimise by removing every other entry from A
@@ -187,13 +187,13 @@ module \$__XILINX_MUX_ (A, B, Y);
       wire [(A_WIDTH+1)/2-1:0] A_i;
       for (i = 0; i < (A_WIDTH+1)/2; i++)
         assign A_i[i] = A[i*2];
-      \$__XILINX_MUX_  #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH((A_WIDTH+1'd1)/2'd2), .B_WIDTH(B_WIDTH-1'd1), .Y_WIDTH(Y_WIDTH)) _TECHMAP_REPLACE_ (.A(A_i), .B(B[B_WIDTH-1:1]), .Y(Y));
+      \$__XILINX_SHIFTX  #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH((A_WIDTH+1'd1)/2'd2), .B_WIDTH(B_WIDTH-1'd1), .Y_WIDTH(Y_WIDTH)) _TECHMAP_REPLACE_ (.A(A_i), .B(B[B_WIDTH-1:1]), .Y(Y));
     end
     // Trim off any leading 1'bx -es in A, and resize B accordingly
     else if (num_leading_X_in_A > 0) begin
       localparam A_WIDTH_new = A_WIDTH - num_leading_X_in_A;
       localparam B_WIDTH_new = $clog2(A_WIDTH_new);
-      \$__XILINX_MUX_  #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(A_WIDTH_new), .B_WIDTH(B_WIDTH_new), .Y_WIDTH(Y_WIDTH)) _TECHMAP_REPLACE_ (.A(A[A_WIDTH_new-1:0]), .B(B[B_WIDTH_new-1:0]), .Y(Y));
+      \$__XILINX_SHIFTX  #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(A_WIDTH_new), .B_WIDTH(B_WIDTH_new), .Y_WIDTH(Y_WIDTH)) _TECHMAP_REPLACE_ (.A(A[A_WIDTH_new-1:0]), .B(B[B_WIDTH_new-1:0]), .Y(Y));
     end
     else if (B_WIDTH < 3 || A_WIDTH <= 4) begin
       \$shiftx  #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(A_WIDTH), .B_WIDTH(B_WIDTH), .Y_WIDTH(Y_WIDTH)) _TECHMAP_REPLACE_ (.A(A), .B(B), .Y(Y));
@@ -237,16 +237,16 @@ module \$__XILINX_MUX_ (A, B, Y);
       wire [(2**(B_WIDTH-4))-1:0] T;
       for (i = 0; i < 2 ** (B_WIDTH-4); i++)
         if (i < num_mux16)
-          \$__XILINX_MUX_  #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(a_width0), .B_WIDTH(4),                .Y_WIDTH(Y_WIDTH)) fpga_soft_mux      (.A(A[i*a_width0+:a_width0]), .B(B[4-1:0]),                .Y(T[i]));
+          \$__XILINX_SHIFTX  #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(a_width0), .B_WIDTH(4),                .Y_WIDTH(Y_WIDTH)) fpga_soft_mux      (.A(A[i*a_width0+:a_width0]), .B(B[4-1:0]),                .Y(T[i]));
         else if (i == num_mux16 && a_widthN > 0) begin
           if (a_widthN > 1)
-            \$__XILINX_MUX_  #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(a_widthN), .B_WIDTH($clog2(a_widthN)), .Y_WIDTH(Y_WIDTH)) fpga_soft_mux_last (.A(A[A_WIDTH-1:i*a_width0]), .B(B[$clog2(a_widthN)-1:0]), .Y(T[i]));
+            \$__XILINX_SHIFTX  #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(a_widthN), .B_WIDTH($clog2(a_widthN)), .Y_WIDTH(Y_WIDTH)) fpga_soft_mux_last (.A(A[A_WIDTH-1:i*a_width0]), .B(B[$clog2(a_widthN)-1:0]), .Y(T[i]));
           else
             assign T[i] = A[A_WIDTH-1];
         end
         else
           assign T[i] = 1'bx;
-      \$__XILINX_MUX_  #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(2**(B_WIDTH-4)), .B_WIDTH(B_WIDTH-4), .Y_WIDTH(Y_WIDTH)) _TECHMAP_REPLACE_ (.A(T), .B(B[B_WIDTH-1:4]), .Y(Y));
+      \$__XILINX_SHIFTX  #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(2**(B_WIDTH-4)), .B_WIDTH(B_WIDTH-4), .Y_WIDTH(Y_WIDTH)) _TECHMAP_REPLACE_ (.A(T), .B(B[B_WIDTH-1:4]), .Y(Y));
     end
   endgenerate
 endmodule
@@ -254,11 +254,11 @@ endmodule
 module \$_MUX8_ (A, B, C, D, E, F, G, H, S, T, U, Y);
 input A, B, C, D, E, F, G, H, S, T, U;
 output Y;
-  \$__XILINX_MUX_  #(.A_SIGNED(0), .B_SIGNED(0), .A_WIDTH(8), .B_WIDTH(3), .Y_WIDTH(1)) _TECHMAP_REPLACE_ (.A({H,G,F,E,D,C,B,A}), .B({U,T,S}), .Y(Y));
+  \$__XILINX_SHIFTX  #(.A_SIGNED(0), .B_SIGNED(0), .A_WIDTH(8), .B_WIDTH(3), .Y_WIDTH(1)) _TECHMAP_REPLACE_ (.A({H,G,F,E,D,C,B,A}), .B({U,T,S}), .Y(Y));
 endmodule
 
 module \$_MUX16_ (A, B, C, D, E, F, G, H, I, J, K, L, M, N, O, P, S, T, U, V, Y);
 input A, B, C, D, E, F, G, H, I, J, K, L, M, N, O, P, S, T, U, V;
 output Y;
-  \$__XILINX_MUX_  #(.A_SIGNED(0), .B_SIGNED(0), .A_WIDTH(16), .B_WIDTH(4), .Y_WIDTH(1)) _TECHMAP_REPLACE_ (.A({P,O,N,M,L,K,J,I,H,G,F,E,D,C,B,A}), .B({V,U,T,S}), .Y(Y));
+  \$__XILINX_SHIFTX  #(.A_SIGNED(0), .B_SIGNED(0), .A_WIDTH(16), .B_WIDTH(4), .Y_WIDTH(1)) _TECHMAP_REPLACE_ (.A({P,O,N,M,L,K,J,I,H,G,F,E,D,C,B,A}), .B({V,U,T,S}), .Y(Y));
 endmodule
diff --git a/techlibs/xilinx/mux_map.v b/techlibs/xilinx/mux_map.v
index 2ad7f7671..0fa8db736 100644
--- a/techlibs/xilinx/mux_map.v
+++ b/techlibs/xilinx/mux_map.v
@@ -38,7 +38,7 @@ module \$shiftx (A, B, Y);
     if (B_SIGNED) begin
       if (_TECHMAP_CONSTMSK_B_[B_WIDTH-1] && _TECHMAP_CONSTVAL_B_[B_WIDTH-1] == 1'b0)
         // Optimisation to remove B_SIGNED if sign bit of B is constant-0
-        \$__XILINX_MUX_  #(.A_SIGNED(A_SIGNED), .B_SIGNED(0), .A_WIDTH(A_WIDTH), .B_WIDTH(B_WIDTH-1'd1), .Y_WIDTH(Y_WIDTH)) _TECHMAP_REPLACE_ (.A(A), .B(B[B_WIDTH-2:0]), .Y(Y));
+        \$__XILINX_SHIFTX  #(.A_SIGNED(A_SIGNED), .B_SIGNED(0), .A_WIDTH(A_WIDTH), .B_WIDTH(B_WIDTH-1'd1), .Y_WIDTH(Y_WIDTH)) _TECHMAP_REPLACE_ (.A(A), .B(B[B_WIDTH-2:0]), .Y(Y));
       else
         wire _TECHMAP_FAIL_ = 1;
     end
@@ -46,7 +46,7 @@ module \$shiftx (A, B, Y);
       wire _TECHMAP_FAIL_ = 1;
     end
     else begin
-        \$__XILINX_MUX_  #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(A_WIDTH), .B_WIDTH(B_WIDTH), .Y_WIDTH(Y_WIDTH)) _TECHMAP_REPLACE_ (.A(A), .B(B), .Y(Y));
+        \$__XILINX_SHIFTX  #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(A_WIDTH), .B_WIDTH(B_WIDTH), .Y_WIDTH(Y_WIDTH)) _TECHMAP_REPLACE_ (.A(A), .B(B), .Y(Y));
     end
   endgenerate
 endmodule
-- 
cgit v1.2.3


From 816b5f5891adfa71586991824e9db24e7e73604a Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Fri, 7 Jun 2019 16:58:57 -0700
Subject: Comment out muxpack (currently broken)

---
 techlibs/xilinx/synth_xilinx.cc | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

(limited to 'techlibs')

diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc
index a0c2c781d..ffdb22960 100644
--- a/techlibs/xilinx/synth_xilinx.cc
+++ b/techlibs/xilinx/synth_xilinx.cc
@@ -225,8 +225,8 @@ struct SynthXilinxPass : public ScriptPass
 		if (check_label("coarse")) {
 			run("synth -run coarse");
 
-			if (!nomux || help_mode)
-				run("muxpack", "(skip if '-nomux')");
+			//if (!nomux || help_mode)
+			//	run("muxpack", "(skip if '-nomux')");
 
 			// shregmap -tech xilinx can cope with $shiftx and $mux
 			//   cells for identifying variable-length shift registers,
-- 
cgit v1.2.3


From a1d4ae78a0ee474af6782bc5e12d8bd1fc790f04 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Mon, 10 Jun 2019 14:34:43 -0700
Subject: Revert "Rename shregmap -tech xilinx -> xilinx_dynamic"

This reverts commit 94a5f4e60985fc1e3fea75eec85638fa29874bea.
---
 techlibs/xilinx/synth_xilinx.cc | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

(limited to 'techlibs')

diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc
index ffdb22960..689a40135 100644
--- a/techlibs/xilinx/synth_xilinx.cc
+++ b/techlibs/xilinx/synth_xilinx.cc
@@ -266,8 +266,8 @@ struct SynthXilinxPass : public ScriptPass
 				// shregmap operates on bit-level flops, not word-level,
 				//   so break those down here
 				run("simplemap t:$dff t:$dffe", "(skip if '-nosrl')");
-				// shregmap to infer variable length shift regs
-				run("shregmap -tech xilinx_dynamic -minlen 3", "(skip if '-nosrl')");
+				// shregmap with '-tech xilinx' infers variable length shift regs
+				run("shregmap -tech xilinx -minlen 3", "(skip if '-nosrl')");
 			}
 
 			std::string techmap_files = " -map +/techmap.v";
-- 
cgit v1.2.3


From b77c5da76919f7f99f171a0a2775896fbc8debc2 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Mon, 10 Jun 2019 14:37:09 -0700
Subject: Revert "Revert "Move ff_map back after ABC for shregmap""

This reverts commit e473e7456545d702c011ee7872956f94a8522865.
---
 techlibs/xilinx/synth_xilinx.cc | 10 +++++-----
 1 file changed, 5 insertions(+), 5 deletions(-)

(limited to 'techlibs')

diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc
index 689a40135..f5f8c43e0 100644
--- a/techlibs/xilinx/synth_xilinx.cc
+++ b/techlibs/xilinx/synth_xilinx.cc
@@ -291,9 +291,7 @@ struct SynthXilinxPass : public ScriptPass
 		if (check_label("map_cells")) {
 			if (!nomux || help_mode)
 				run("muxcover -mux8 -mux16", "(skip if '-nomux')");
-			run("techmap -map +/techmap.v -map +/xilinx/cells_map.v -map +/xilinx/ff_map.v");
-			run("dffinit -ff FDRE Q INIT -ff FDCE Q INIT -ff FDPE Q INIT -ff FDSE Q INIT "
-					"-ff FDRE_1 Q INIT -ff FDCE_1 Q INIT -ff FDPE_1 Q INIT -ff FDSE_1 Q INIT");
+			run("techmap -map +/techmap.v -map +/xilinx/cells_map.v");
 			run("clean");
 		}
 
@@ -309,8 +307,10 @@ struct SynthXilinxPass : public ScriptPass
 			// This shregmap call infers fixed length shift registers after abc
 			//   has performed any necessary retiming
 			if (!nosrl || help_mode)
-				run("shregmap -tech xilinx_static -minlen 3", "(skip if '-nosrl')");
-			run("techmap -map +/xilinx/lut_map.v -map +/xilinx/cells_map.v");
+				run("shregmap -minlen 3 -init -params -enpol any_or_none", "(skip if '-nosrl')");
+			run("techmap -map +/xilinx/lut_map.v -map +/xilinx/cells_map.v -map +/xilinx/ff_map.v");
+			run("dffinit -ff FDRE Q INIT -ff FDCE Q INIT -ff FDPE Q INIT -ff FDSE Q INIT "
+					"-ff FDRE_1 Q INIT -ff FDCE_1 Q INIT -ff FDPE_1 Q INIT -ff FDSE_1 Q INIT");
 			run("clean");
 		}
 
-- 
cgit v1.2.3


From 8a708d1fdb662f86a46720200fa15acafde30333 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Tue, 11 Jun 2019 12:02:31 -0700
Subject: Remove #ifndef ABC

---
 techlibs/xilinx/cells_sim.v | 4 ----
 1 file changed, 4 deletions(-)

(limited to 'techlibs')

diff --git a/techlibs/xilinx/cells_sim.v b/techlibs/xilinx/cells_sim.v
index 88967b068..14e35737e 100644
--- a/techlibs/xilinx/cells_sim.v
+++ b/techlibs/xilinx/cells_sim.v
@@ -295,10 +295,8 @@ module RAM64X1D (
   reg [63:0] mem = INIT;
   assign SPO = mem[a];
   assign DPO = mem[dpra];
-`ifndef _ABC
   wire clk = WCLK ^ IS_WCLK_INVERTED;
   always @(posedge clk) if (WE) mem[a] <= D;
-`endif
 endmodule
 
 (* abc_box_id = 5 /*, lib_whitebox*/ *)
@@ -312,10 +310,8 @@ module RAM128X1D (
   reg [127:0] mem = INIT;
   assign SPO = mem[A];
   assign DPO = mem[DPRA];
-`ifndef _ABC
   wire clk = WCLK ^ IS_WCLK_INVERTED;
   always @(posedge clk) if (WE) mem[A] <= D;
-`endif
 endmodule
 
 module SRL16E (
-- 
cgit v1.2.3


From 54379f9872ba3abdf5328994abcf5abfc7288c6b Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Tue, 11 Jun 2019 12:02:51 -0700
Subject: Disable dist RAM boxes due to comb loop

---
 techlibs/xilinx/cells_sim.v | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

(limited to 'techlibs')

diff --git a/techlibs/xilinx/cells_sim.v b/techlibs/xilinx/cells_sim.v
index 14e35737e..d9aa36666 100644
--- a/techlibs/xilinx/cells_sim.v
+++ b/techlibs/xilinx/cells_sim.v
@@ -281,7 +281,7 @@ module FDPE_1 ((* abc_flop_q *) output reg Q, input C, CE, D, PRE);
   always @(negedge C, posedge PRE) if (PRE) Q <= 1'b1; else if (CE) Q <= D;
 endmodule
 
-(* abc_box_id = 4 /*, lib_whitebox*/ *)
+//(* abc_box_id = 4 /*, lib_whitebox*/ *)
 module RAM64X1D (
   output DPO, SPO,
   input  D, WCLK, WE,
@@ -299,7 +299,7 @@ module RAM64X1D (
   always @(posedge clk) if (WE) mem[a] <= D;
 endmodule
 
-(* abc_box_id = 5 /*, lib_whitebox*/ *)
+//(* abc_box_id = 5 /*, lib_whitebox*/ *)
 module RAM128X1D (
   output       DPO, SPO,
   input        D, WCLK, WE,
-- 
cgit v1.2.3


From 2dffa4685b830313204f5d04314a14ed6ecac8ec Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Tue, 11 Jun 2019 17:10:47 -0700
Subject: Add "-W' wire delay arg to abc9, use from synth_xilinx

---
 techlibs/xilinx/synth_xilinx.cc | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'techlibs')

diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc
index f5f8c43e0..f966115cd 100644
--- a/techlibs/xilinx/synth_xilinx.cc
+++ b/techlibs/xilinx/synth_xilinx.cc
@@ -297,7 +297,7 @@ struct SynthXilinxPass : public ScriptPass
 
 		if (check_label("map_luts")) {
 			if (abc == "abc9")
-				run(abc + " -lut +/xilinx/abc.lut -box +/xilinx/abc.box" + string(retime ? " -dff" : ""));
+				run(abc + " -lut +/xilinx/abc.lut -box +/xilinx/abc.box -W 160" + string(retime ? " -dff" : ""));
 			else if (help_mode)
 				run(abc + " -luts 2:2,3,6:5,10,20 [-dff]");
 			else
-- 
cgit v1.2.3


From 4c9fde87d170fc8d4b729581b055407553951e4c Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Wed, 12 Jun 2019 08:48:45 -0700
Subject: Revert "Add "-W' wire delay arg to abc9, use from synth_xilinx"

This reverts commit 2dffa4685b830313204f5d04314a14ed6ecac8ec.
---
 techlibs/xilinx/synth_xilinx.cc | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'techlibs')

diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc
index f966115cd..f5f8c43e0 100644
--- a/techlibs/xilinx/synth_xilinx.cc
+++ b/techlibs/xilinx/synth_xilinx.cc
@@ -297,7 +297,7 @@ struct SynthXilinxPass : public ScriptPass
 
 		if (check_label("map_luts")) {
 			if (abc == "abc9")
-				run(abc + " -lut +/xilinx/abc.lut -box +/xilinx/abc.box -W 160" + string(retime ? " -dff" : ""));
+				run(abc + " -lut +/xilinx/abc.lut -box +/xilinx/abc.box" + string(retime ? " -dff" : ""));
 			else if (help_mode)
 				run(abc + " -luts 2:2,3,6:5,10,20 [-dff]");
 			else
-- 
cgit v1.2.3


From 1e838a8913afa36a57d425f26ea881f5071b8b5d Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Wed, 12 Jun 2019 08:49:15 -0700
Subject: Retry "Add "-W' wire delay arg to abc9, use from synth_xilinx"

---
 techlibs/xilinx/synth_xilinx.cc | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'techlibs')

diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc
index f5f8c43e0..f966115cd 100644
--- a/techlibs/xilinx/synth_xilinx.cc
+++ b/techlibs/xilinx/synth_xilinx.cc
@@ -297,7 +297,7 @@ struct SynthXilinxPass : public ScriptPass
 
 		if (check_label("map_luts")) {
 			if (abc == "abc9")
-				run(abc + " -lut +/xilinx/abc.lut -box +/xilinx/abc.box" + string(retime ? " -dff" : ""));
+				run(abc + " -lut +/xilinx/abc.lut -box +/xilinx/abc.box -W 160" + string(retime ? " -dff" : ""));
 			else if (help_mode)
 				run(abc + " -luts 2:2,3,6:5,10,20 [-dff]");
 			else
-- 
cgit v1.2.3