From 3928482a3c4fb71b8e6ccdcb362c030eef34a479 Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Sat, 4 Feb 2017 14:14:26 +0100
Subject: Add $cover cell type and SVA cover() support

---
 techlibs/common/simlib.v | 8 ++++++++
 1 file changed, 8 insertions(+)

(limited to 'techlibs')

diff --git a/techlibs/common/simlib.v b/techlibs/common/simlib.v
index 2c4db1ac6..d0abd3b34 100644
--- a/techlibs/common/simlib.v
+++ b/techlibs/common/simlib.v
@@ -1305,6 +1305,14 @@ endmodule
 
 // --------------------------------------------------------
 
+module \$cover (A, EN);
+
+input A, EN;
+
+endmodule
+
+// --------------------------------------------------------
+
 module \$initstate (Y);
 
 output reg Y = 1;
-- 
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