From 152e682bd5e448aaca20e7c9349c88bbd4a8ed3b Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Mon, 24 Jun 2019 21:54:01 -0700 Subject: Add Xilinx dist RAM as comb boxes --- techlibs/xilinx/abc_xc7.box | 14 ++++++++++++++ techlibs/xilinx/cells_sim.v | 2 ++ 2 files changed, 16 insertions(+) (limited to 'techlibs') diff --git a/techlibs/xilinx/abc_xc7.box b/techlibs/xilinx/abc_xc7.box index b5817a6e0..40b92da0c 100644 --- a/techlibs/xilinx/abc_xc7.box +++ b/techlibs/xilinx/abc_xc7.box @@ -29,3 +29,17 @@ CARRY4 3 1 10 8 494 465 445 - - 433 469 - - 157 592 540 520 356 - 512 548 292 - 228 580 526 507 398 385 508 528 378 380 114 + +# SLICEM/A6LUT +# Inputs: A0 A1 A2 A3 A4 A5 D DPRA0 DPRA1 DPRA2 DPRA3 DPRA4 DPRA5 WCLK WE +# Outputs: DPO SPO +RAM64X1D 4 0 15 2 +- - - - - - - 124 124 124 124 124 124 - - +124 124 124 124 124 124 - - - - - - 124 - - + +# SLICEM/A6LUT + F7[AB]MUX +# Inputs: A0 A1 A2 A3 A4 A5 A6 D DPRA0 DPRA1 DPRA2 DPRA3 DPRA4 DPRA5 DPRA6 WCLK WE +# Outputs: DPO SPO +RAM128X1D 5 0 17 2 +- - - - - - - - 314 314 314 314 314 314 292 - - +347 347 347 347 347 347 296 - - - - - - - - - - diff --git a/techlibs/xilinx/cells_sim.v b/techlibs/xilinx/cells_sim.v index 84939818e..8261286af 100644 --- a/techlibs/xilinx/cells_sim.v +++ b/techlibs/xilinx/cells_sim.v @@ -281,6 +281,7 @@ module FDPE_1 (output reg Q, input C, CE, D, PRE); always @(negedge C, posedge PRE) if (PRE) Q <= 1'b1; else if (CE) Q <= D; endmodule +(* abc_box_id = 4, abc_scc_break="D" *) module RAM64X1D ( output DPO, SPO, input D, WCLK, WE, @@ -298,6 +299,7 @@ module RAM64X1D ( always @(posedge clk) if (WE) mem[a] <= D; endmodule +(* abc_box_id = 5, abc_scc_break="D" *) module RAM128X1D ( output DPO, SPO, input D, WCLK, WE, -- cgit v1.2.3 From ca0225fcfaa8c9c68647034351a1569464959edf Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Mon, 24 Jun 2019 21:55:54 -0700 Subject: Re-enable dist RAM boxes for ECP5 --- techlibs/ecp5/cells_sim.v | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'techlibs') diff --git a/techlibs/ecp5/cells_sim.v b/techlibs/ecp5/cells_sim.v index f66147323..567942482 100644 --- a/techlibs/ecp5/cells_sim.v +++ b/techlibs/ecp5/cells_sim.v @@ -106,7 +106,7 @@ module PFUMX (input ALUT, BLUT, C0, output Z); endmodule // --------------------------------------- -//(* abc_box_id=2 *) +(* abc_box_id=2, abc_scc_break="D" *) module TRELLIS_DPR16X4 ( input [3:0] DI, input [3:0] WAD, -- cgit v1.2.3 From a4a7e63d84dee73554d53587f38409e25db84b66 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Mon, 24 Jun 2019 22:10:28 -0700 Subject: Revert "Re-enable dist RAM boxes for ECP5" This reverts commit ca0225fcfaa8c9c68647034351a1569464959edf. --- techlibs/ecp5/cells_sim.v | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'techlibs') diff --git a/techlibs/ecp5/cells_sim.v b/techlibs/ecp5/cells_sim.v index 567942482..f66147323 100644 --- a/techlibs/ecp5/cells_sim.v +++ b/techlibs/ecp5/cells_sim.v @@ -106,7 +106,7 @@ module PFUMX (input ALUT, BLUT, C0, output Z); endmodule // --------------------------------------- -(* abc_box_id=2, abc_scc_break="D" *) +//(* abc_box_id=2 *) module TRELLIS_DPR16X4 ( input [3:0] DI, input [3:0] WAD, -- cgit v1.2.3 From 4fadb471a3028487d4b05b3e343b3be49349f78b Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Mon, 24 Jun 2019 22:12:50 -0700 Subject: Re-enable dist RAM boxes for ECP5 --- techlibs/ecp5/cells_sim.v | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'techlibs') diff --git a/techlibs/ecp5/cells_sim.v b/techlibs/ecp5/cells_sim.v index f66147323..0239d1afe 100644 --- a/techlibs/ecp5/cells_sim.v +++ b/techlibs/ecp5/cells_sim.v @@ -106,7 +106,7 @@ module PFUMX (input ALUT, BLUT, C0, output Z); endmodule // --------------------------------------- -//(* abc_box_id=2 *) +(* abc_box_id=2, abc_scc_break="DI" *) module TRELLIS_DPR16X4 ( input [3:0] DI, input [3:0] WAD, -- cgit v1.2.3