From 5e0339855fc1f83b98694ed37dd2f195c3d8f52c Mon Sep 17 00:00:00 2001
From: Keith Rothman <537074+litghost@users.noreply.github.com>
Date: Tue, 9 Apr 2019 09:01:53 -0700
Subject: Add additional cells sim models for core 7-series primatives.

Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
---
 techlibs/xilinx/cells_sim.v | 57 +++++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 57 insertions(+)

(limited to 'techlibs')

diff --git a/techlibs/xilinx/cells_sim.v b/techlibs/xilinx/cells_sim.v
index ff5ff0726..315fd54c8 100644
--- a/techlibs/xilinx/cells_sim.v
+++ b/techlibs/xilinx/cells_sim.v
@@ -30,10 +30,15 @@ module GND(output G);
 endmodule
 
 module IBUF(output O, input I);
+  parameter IOSTANDARD = "default";
+  parameter IBUF_LOW_PWR = 0;
   assign O = I;
 endmodule
 
 module OBUF(output O, input I);
+  parameter IOSTANDARD = "default";
+  parameter DRIVE = 12;
+  parameter SLEW = "SLOW";
   assign O = I;
 endmodule
 
@@ -41,6 +46,42 @@ module BUFG(output O, input I);
   assign O = I;
 endmodule
 
+module BUFGCTRL(
+    output O,
+    input I0, input I1,
+    input S0, input S1,
+    input CE0, input CE1,
+    input IGNORE0, input IGNORE1);
+
+parameter INIT_OUT = 0;
+parameter PRESELECT_I0 = 0;
+parameter PRESELECT_I1 = 0;
+parameter IS_CE0_INVERTED = 0;
+parameter IS_CE1_INVERTED = 0;
+parameter IS_S0_INVERTED = 0;
+parameter IS_S1_INVERTED = 0;
+parameter IS_IGNORE0_INVERTED = 0;
+parameter IS_IGNORE1_INVERTED = 0;
+
+wire I0_internal = ((CE0 ^ IS_CE0_INVERTED) ? I0 : INIT_OUT);
+wire I1_internal = ((CE1 ^ IS_CE1_INVERTED) ? I1 : INIT_OUT);
+wire S0_true = (S0 ^ IS_S0_INVERTED);
+wire S1_true = (S1 ^ IS_S1_INVERTED);
+
+assign O = S0_true ? I0_internal : (S1_true ? I1_internal : INIT_OUT);
+
+endmodule
+
+module BUFHCE(output O, input I, input CE);
+
+parameter INIT_OUT = 0;
+parameter CE_TYPE = "SYNC";
+parameter IS_CE_INVERTED = 0;
+
+assign O = ((CE ^ IS_CE_INVERTED) ? I : INIT_OUT);
+
+endmodule
+
 // module OBUFT(output O, input I, T);
 //   assign O = T ? 1'bz : I;
 // endmodule
@@ -98,6 +139,22 @@ module LUT6(output O, input I0, I1, I2, I3, I4, I5);
   assign O = I0 ? s1[1] : s1[0];
 endmodule
 
+module LUT6_2(output O6, output O5, input I0, I1, I2, I3, I4, I5);
+  parameter [63:0] INIT = 0;
+  wire [31: 0] s5 = I5 ? INIT[63:32] : INIT[31: 0];
+  wire [15: 0] s4 = I4 ?   s5[31:16] :   s5[15: 0];
+  wire [ 7: 0] s3 = I3 ?   s4[15: 8] :   s4[ 7: 0];
+  wire [ 3: 0] s2 = I2 ?   s3[ 7: 4] :   s3[ 3: 0];
+  wire [ 1: 0] s1 = I1 ?   s2[ 3: 2] :   s2[ 1: 0];
+  assign O6 = I0 ? s1[1] : s1[0];
+
+  wire [15: 0] s5_4 = I4 ? INIT[31:16] : INIT[15: 0];
+  wire [ 7: 0] s5_3 = I3 ?   s4[15: 8] :   s4[ 7: 0];
+  wire [ 3: 0] s5_2 = I2 ?   s3[ 7: 4] :   s3[ 3: 0];
+  wire [ 1: 0] s5_1 = I1 ?   s2[ 3: 2] :   s2[ 1: 0];
+  assign O5 = I0 ? s5_1[1] : s5_1[0];
+endmodule
+
 module MUXCY(output O, input CI, DI, S);
   assign O = S ? CI : DI;
 endmodule
-- 
cgit v1.2.3


From e107ccdde82247e28c9c994240e4d4bf694f673f Mon Sep 17 00:00:00 2001
From: Keith Rothman <537074+litghost@users.noreply.github.com>
Date: Tue, 9 Apr 2019 11:43:19 -0700
Subject: Fix LUT6_2 definition.

Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
---
 techlibs/xilinx/cells_sim.v | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

(limited to 'techlibs')

diff --git a/techlibs/xilinx/cells_sim.v b/techlibs/xilinx/cells_sim.v
index 315fd54c8..c96e0d8f1 100644
--- a/techlibs/xilinx/cells_sim.v
+++ b/techlibs/xilinx/cells_sim.v
@@ -149,9 +149,9 @@ module LUT6_2(output O6, output O5, input I0, I1, I2, I3, I4, I5);
   assign O6 = I0 ? s1[1] : s1[0];
 
   wire [15: 0] s5_4 = I4 ? INIT[31:16] : INIT[15: 0];
-  wire [ 7: 0] s5_3 = I3 ?   s4[15: 8] :   s4[ 7: 0];
-  wire [ 3: 0] s5_2 = I2 ?   s3[ 7: 4] :   s3[ 3: 0];
-  wire [ 1: 0] s5_1 = I1 ?   s2[ 3: 2] :   s2[ 1: 0];
+  wire [ 7: 0] s5_3 = I3 ? s5_4[15: 8] : s5_4[ 7: 0];
+  wire [ 3: 0] s5_2 = I2 ? s5_3[ 7: 4] : s5_3[ 3: 0];
+  wire [ 1: 0] s5_1 = I1 ? s5_2[ 3: 2] : s5_2[ 1: 0];
   assign O5 = I0 ? s5_1[1] : s5_1[0];
 endmodule
 
-- 
cgit v1.2.3


From 9a6da9a79a22e984ee3eec02caa230b66f10e11a Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Wed, 10 Apr 2019 08:32:53 -0700
Subject: synth_* with -retime option now calls abc with -D 1 as well

---
 techlibs/achronix/synth_achronix.cc       | 4 ++--
 techlibs/anlogic/synth_anlogic.cc         | 2 +-
 techlibs/coolrunner2/synth_coolrunner2.cc | 2 +-
 techlibs/easic/synth_easic.cc             | 2 +-
 techlibs/ecp5/synth_ecp5.cc               | 2 +-
 techlibs/gowin/synth_gowin.cc             | 2 +-
 techlibs/greenpak4/synth_greenpak4.cc     | 2 +-
 techlibs/ice40/synth_ice40.cc             | 2 +-
 techlibs/intel/synth_intel.cc             | 6 +++---
 techlibs/sf2/synth_sf2.cc                 | 2 +-
 techlibs/xilinx/synth_xilinx.cc           | 4 ++--
 11 files changed, 15 insertions(+), 15 deletions(-)

(limited to 'techlibs')

diff --git a/techlibs/achronix/synth_achronix.cc b/techlibs/achronix/synth_achronix.cc
index 626860d9c..3dbf20911 100755
--- a/techlibs/achronix/synth_achronix.cc
+++ b/techlibs/achronix/synth_achronix.cc
@@ -152,12 +152,12 @@ struct SynthAchronixPass : public ScriptPass {
         run("clean -purge");
         run("setundef -undriven -zero");
         if (retime || help_mode)
-          run("abc -markgroups -dff", "(only if -retime)");
+          run("abc -markgroups -dff -D 1", "(only if -retime)");
       }
 
     if (check_label("map_luts"))
       {
-        run("abc -lut 4" + string(retime ? " -dff" : ""));
+        run("abc -lut 4" + string(retime ? " -dff -D 1" : ""));
         run("clean");
       }
 
diff --git a/techlibs/anlogic/synth_anlogic.cc b/techlibs/anlogic/synth_anlogic.cc
index 620bf3965..258e3d722 100644
--- a/techlibs/anlogic/synth_anlogic.cc
+++ b/techlibs/anlogic/synth_anlogic.cc
@@ -164,7 +164,7 @@ struct SynthAnlogicPass : public ScriptPass
 			run("opt -undriven -fine");
 			run("techmap -map +/techmap.v -map +/anlogic/arith_map.v");
 			if (retime || help_mode)
-				run("abc -dff", "(only if -retime)");
+				run("abc -dff -D 1", "(only if -retime)");
 		}
 
 		if (check_label("map_ffs"))
diff --git a/techlibs/coolrunner2/synth_coolrunner2.cc b/techlibs/coolrunner2/synth_coolrunner2.cc
index 21bbcaef4..fa4fe0f5b 100644
--- a/techlibs/coolrunner2/synth_coolrunner2.cc
+++ b/techlibs/coolrunner2/synth_coolrunner2.cc
@@ -161,7 +161,7 @@ struct SynthCoolrunner2Pass : public ScriptPass
 
 		if (check_label("map_pla"))
 		{
-			run("abc -sop -I 40 -P 56");
+			run("abc -sop -I 40 -P 56" + string(retime ? " -dff -D 1" : ""));
 			run("clean");
 		}
 
diff --git a/techlibs/easic/synth_easic.cc b/techlibs/easic/synth_easic.cc
index dd9e3dab7..7bacc7890 100644
--- a/techlibs/easic/synth_easic.cc
+++ b/techlibs/easic/synth_easic.cc
@@ -158,7 +158,7 @@ struct SynthEasicPass : public ScriptPass
 			run("techmap");
 			run("opt -fast");
 			if (retime || help_mode) {
-				run("abc -dff", " (only if -retime)");
+				run("abc -dff -D 1", " (only if -retime)");
 				run("opt_clean", "(only if -retime)");
 			}
 		}
diff --git a/techlibs/ecp5/synth_ecp5.cc b/techlibs/ecp5/synth_ecp5.cc
index 4b889d672..45f101451 100644
--- a/techlibs/ecp5/synth_ecp5.cc
+++ b/techlibs/ecp5/synth_ecp5.cc
@@ -242,7 +242,7 @@ struct SynthEcp5Pass : public ScriptPass
 			else
 				run("techmap -map +/techmap.v -map +/ecp5/arith_map.v");
 			if (retime || help_mode)
-				run("abc -dff", "(only if -retime)");
+				run("abc -dff -D 1", "(only if -retime)");
 		}
 
 		if (check_label("map_ffs"))
diff --git a/techlibs/gowin/synth_gowin.cc b/techlibs/gowin/synth_gowin.cc
index 9a3fcdbb6..0ebd77d63 100644
--- a/techlibs/gowin/synth_gowin.cc
+++ b/techlibs/gowin/synth_gowin.cc
@@ -163,7 +163,7 @@ struct SynthGowinPass : public ScriptPass
 			run("splitnets -ports");
 			run("setundef -undriven -zero");
 			if (retime || help_mode)
-				run("abc -dff", "(only if -retime)");
+				run("abc -dff -D 1", "(only if -retime)");
 		}
 
 		if (check_label("map_luts"))
diff --git a/techlibs/greenpak4/synth_greenpak4.cc b/techlibs/greenpak4/synth_greenpak4.cc
index eeb001b46..3222be2e3 100644
--- a/techlibs/greenpak4/synth_greenpak4.cc
+++ b/techlibs/greenpak4/synth_greenpak4.cc
@@ -165,7 +165,7 @@ struct SynthGreenPAK4Pass : public ScriptPass
 			run("dfflibmap -prepare -liberty +/greenpak4/gp_dff.lib");
 			run("opt -fast");
 			if (retime || help_mode)
-				run("abc -dff", "(only if -retime)");
+				run("abc -dff -D 1", "(only if -retime)");
 		}
 
 		if (check_label("map_luts"))
diff --git a/techlibs/ice40/synth_ice40.cc b/techlibs/ice40/synth_ice40.cc
index 8899bfcc4..d114b6269 100644
--- a/techlibs/ice40/synth_ice40.cc
+++ b/techlibs/ice40/synth_ice40.cc
@@ -274,7 +274,7 @@ struct SynthIce40Pass : public ScriptPass
 			else
 				run("techmap -map +/techmap.v -map +/ice40/arith_map.v");
 			if (retime || help_mode)
-				run("abc -dff", "(only if -retime)");
+				run("abc -dff -D 1", "(only if -retime)");
 			run("ice40_opt");
 		}
 
diff --git a/techlibs/intel/synth_intel.cc b/techlibs/intel/synth_intel.cc
index 0f1d7a7b5..290282bd9 100644
--- a/techlibs/intel/synth_intel.cc
+++ b/techlibs/intel/synth_intel.cc
@@ -210,15 +210,15 @@ struct SynthIntelPass : public ScriptPass {
         run("clean -purge");
         run("setundef -undriven -zero");
         if (retime || help_mode)
-          run("abc -markgroups -dff", "(only if -retime)");
+          run("abc -markgroups -dff -D 1", "(only if -retime)");
       }
 
     if (check_label("map_luts"))
       {
         if(family_opt=="a10gx" || family_opt=="cyclonev")
-          run("abc -luts 2:2,3,6:5" + string(retime ? " -dff" : ""));
+          run("abc -luts 2:2,3,6:5" + string(retime ? " -dff -D 1" : ""));
         else
-          run("abc -lut 4" + string(retime ? " -dff" : ""));
+          run("abc -lut 4" + string(retime ? " -dff -D 1" : ""));
         run("clean");
       }
 
diff --git a/techlibs/sf2/synth_sf2.cc b/techlibs/sf2/synth_sf2.cc
index 0924df7a6..3c5a58b4c 100644
--- a/techlibs/sf2/synth_sf2.cc
+++ b/techlibs/sf2/synth_sf2.cc
@@ -181,7 +181,7 @@ struct SynthSf2Pass : public ScriptPass
 			run("opt -undriven -fine");
 			run("techmap -map +/techmap.v -map +/sf2/arith_map.v");
 			if (retime || help_mode)
-				run("abc -dff", "(only if -retime)");
+				run("abc -dff -D 1", "(only if -retime)");
 		}
 
 		if (check_label("map_ffs"))
diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc
index 397c83ac6..a462b9052 100644
--- a/techlibs/xilinx/synth_xilinx.cc
+++ b/techlibs/xilinx/synth_xilinx.cc
@@ -115,7 +115,7 @@ struct SynthXilinxPass : public Pass
 		log("\n");
 		log("    map_luts:\n");
 		log("        techmap -map +/techmap.v -map +/xilinx/ff_map.v t:$_DFF_?N?\n");
-		log("        abc -luts 2:2,3,6:5,10,20 [-dff]\n");
+		log("        abc -luts 2:2,3,6:5,10,20 [-dff -D 1]\n");
 		log("        clean\n");
 		log("        techmap -map +/xilinx/lut_map.v -map +/xilinx/ff_map.v");
 		log("\n");
@@ -269,7 +269,7 @@ struct SynthXilinxPass : public Pass
 		if (check_label(active, run_from, run_to, "map_luts"))
 		{
 			Pass::call(design, "techmap -map +/techmap.v -map +/xilinx/ff_map.v t:$_DFF_?N?");
-			Pass::call(design, "abc -luts 2:2,3,6:5,10,20" + string(retime ? " -dff" : ""));
+			Pass::call(design, "abc -luts 2:2,3,6:5,10,20" + string(retime ? " -dff -D 1" : ""));
 			Pass::call(design, "clean");
 			Pass::call(design, "techmap -map +/xilinx/lut_map.v -map +/xilinx/ff_map.v");
 		}
-- 
cgit v1.2.3


From 643ae9bfc534c20444dfcd33083c6c188c2f1ec8 Mon Sep 17 00:00:00 2001
From: Diego <dhdezr@gmail.com>
Date: Thu, 11 Apr 2019 19:59:03 -0500
Subject: Fixing issues in CycloneV cell sim

---
 techlibs/intel/cyclonev/cells_sim.v | 12 +++++++++---
 1 file changed, 9 insertions(+), 3 deletions(-)

(limited to 'techlibs')

diff --git a/techlibs/intel/cyclonev/cells_sim.v b/techlibs/intel/cyclonev/cells_sim.v
index fa27c2c8e..9b2a10e72 100644
--- a/techlibs/intel/cyclonev/cells_sim.v
+++ b/techlibs/intel/cyclonev/cells_sim.v
@@ -85,7 +85,7 @@ module cyclonev_lcell_comb
       begin
          upper_lut_value = lut4(mask[31:16], dataa, datab, datac, datad);
          lower_lut_value = lut4(mask[15:0], dataa, datab, datac, datad);
-         lut5            = (datae) ? upper_mask_value : lower_mask_value;
+         lut5            = (datae) ? upper_lut_value : lower_lut_value;
       end
    endfunction // lut5
 
@@ -95,15 +95,16 @@ module cyclonev_lcell_comb
       input        dataa, datab, datac, datad, datae, dataf;
       reg          upper_lut_value;
       reg          lower_lut_value;
+      reg          out_0, out_1, out_2, out_3;
       begin
          upper_lut_value = lut5(mask[63:32], dataa, datab, datac, datad, datae);
          lower_lut_value = lut5(mask[31:0], dataa, datab, datac, datad, datae);
-         lut6            = (dataf) ?  upper_mask_value : lower_mask_value;
+         lut6            = (dataf) ?  upper_lut_value : lower_lut_value;
       end
    endfunction // lut6
 
    assign {mask_a, mask_b, mask_c, mask_d} = {lut_mask[15:0], lut_mask[31:16], lut_mask[47:32], lut_mask[63:48]};
-
+`ifdef ADVANCED_ALM
    always @(*) begin
       if(extended_lut == "on")
         shared_lut_alm = datag;
@@ -115,6 +116,11 @@ module cyclonev_lcell_comb
       out_2 = lut4(mask_c, dataa, datab, datac, datad);
       out_3 = lut4(mask_d, dataa, datab, shared_lut_alm, datad);
    end
+`else
+   `ifdef DEBUG
+       initial $display("Advanced ALM lut combine is not implemented yet");
+   `endif
+`endif
 endmodule // cyclonev_lcell_comb
 
 
-- 
cgit v1.2.3


From 1f9235ede5d5fee4ce0ad13c2905f624e9493426 Mon Sep 17 00:00:00 2001
From: Keith Rothman <537074+litghost@users.noreply.github.com>
Date: Fri, 12 Apr 2019 09:30:49 -0700
Subject: Remove BUFGCTRL, BUFHCE and LUT6_2 from cells_xtra.

Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
---
 techlibs/xilinx/cells_sim.v   | 22 +++++++++++-----------
 techlibs/xilinx/cells_xtra.sh |  6 +++---
 techlibs/xilinx/cells_xtra.v  | 38 --------------------------------------
 3 files changed, 14 insertions(+), 52 deletions(-)

(limited to 'techlibs')

diff --git a/techlibs/xilinx/cells_sim.v b/techlibs/xilinx/cells_sim.v
index c96e0d8f1..0c8f282a4 100644
--- a/techlibs/xilinx/cells_sim.v
+++ b/techlibs/xilinx/cells_sim.v
@@ -53,15 +53,15 @@ module BUFGCTRL(
     input CE0, input CE1,
     input IGNORE0, input IGNORE1);
 
-parameter INIT_OUT = 0;
-parameter PRESELECT_I0 = 0;
-parameter PRESELECT_I1 = 0;
-parameter IS_CE0_INVERTED = 0;
-parameter IS_CE1_INVERTED = 0;
-parameter IS_S0_INVERTED = 0;
-parameter IS_S1_INVERTED = 0;
-parameter IS_IGNORE0_INVERTED = 0;
-parameter IS_IGNORE1_INVERTED = 0;
+parameter [0:0] INIT_OUT = 1'b0;
+parameter PRESELECT_I0 = "FALSE";
+parameter PRESELECT_I1 = "FALSE";
+parameter [0:0] IS_CE0_INVERTED = 1'b0;
+parameter [0:0] IS_CE1_INVERTED = 1'b0;
+parameter [0:0] IS_S0_INVERTED = 1'b0;
+parameter [0:0] IS_S1_INVERTED = 1'b0;
+parameter [0:0] IS_IGNORE0_INVERTED = 1'b0;
+parameter [0:0] IS_IGNORE1_INVERTED = 1'b0;
 
 wire I0_internal = ((CE0 ^ IS_CE0_INVERTED) ? I0 : INIT_OUT);
 wire I1_internal = ((CE1 ^ IS_CE1_INVERTED) ? I1 : INIT_OUT);
@@ -74,9 +74,9 @@ endmodule
 
 module BUFHCE(output O, input I, input CE);
 
-parameter INIT_OUT = 0;
+parameter [0:0] INIT_OUT = 1'b0;
 parameter CE_TYPE = "SYNC";
-parameter IS_CE_INVERTED = 0;
+parameter [0:0] IS_CE_INVERTED = 1'b0;
 
 assign O = ((CE ^ IS_CE_INVERTED) ? I : INIT_OUT);
 
diff --git a/techlibs/xilinx/cells_xtra.sh b/techlibs/xilinx/cells_xtra.sh
index 56520ea10..8b06c3155 100644
--- a/techlibs/xilinx/cells_xtra.sh
+++ b/techlibs/xilinx/cells_xtra.sh
@@ -28,12 +28,12 @@ function xtract_cell_decl()
 	# xtract_cell_decl BUFG
 	xtract_cell_decl BUFGCE
 	xtract_cell_decl BUFGCE_1
-	xtract_cell_decl BUFGCTRL
+	#xtract_cell_decl BUFGCTRL
 	xtract_cell_decl BUFGMUX
 	xtract_cell_decl BUFGMUX_1
 	xtract_cell_decl BUFGMUX_CTRL
 	xtract_cell_decl BUFH
-	xtract_cell_decl BUFHCE
+	#xtract_cell_decl BUFHCE
 	xtract_cell_decl BUFIO
 	xtract_cell_decl BUFMR
 	xtract_cell_decl BUFMRCE
@@ -92,7 +92,7 @@ function xtract_cell_decl()
 	# xtract_cell_decl LUT4
 	# xtract_cell_decl LUT5
 	# xtract_cell_decl LUT6
-	xtract_cell_decl LUT6_2
+	#xtract_cell_decl LUT6_2
 	xtract_cell_decl MMCME2_ADV
 	xtract_cell_decl MMCME2_BASE
 	# xtract_cell_decl MUXF7
diff --git a/techlibs/xilinx/cells_xtra.v b/techlibs/xilinx/cells_xtra.v
index 497518d35..4fb6798be 100644
--- a/techlibs/xilinx/cells_xtra.v
+++ b/techlibs/xilinx/cells_xtra.v
@@ -30,29 +30,6 @@ module BUFGCE_1 (...);
     input CE, I;
 endmodule
 
-module BUFGCTRL (...);
-    output O;
-    input CE0;
-    input CE1;
-    input I0;
-    input I1;
-    input IGNORE0;
-    input IGNORE1;
-    input S0;
-    input S1;
-    parameter integer INIT_OUT = 0;
-    parameter PRESELECT_I0 = "FALSE";
-    parameter PRESELECT_I1 = "FALSE";
-    parameter [0:0] IS_CE0_INVERTED = 1'b0;
-    parameter [0:0] IS_CE1_INVERTED = 1'b0;
-    parameter [0:0] IS_I0_INVERTED = 1'b0;
-    parameter [0:0] IS_I1_INVERTED = 1'b0;
-    parameter [0:0] IS_IGNORE0_INVERTED = 1'b0;
-    parameter [0:0] IS_IGNORE1_INVERTED = 1'b0;
-    parameter [0:0] IS_S0_INVERTED = 1'b0;
-    parameter [0:0] IS_S1_INVERTED = 1'b0;
-endmodule
-
 module BUFGMUX (...);
     parameter CLK_SEL_TYPE = "SYNC";
     output O;
@@ -77,15 +54,6 @@ module BUFH (...);
     input I;
 endmodule
 
-module BUFHCE (...);
-    parameter CE_TYPE = "SYNC";
-    parameter integer INIT_OUT = 0;
-    parameter [0:0] IS_CE_INVERTED = 1'b0;
-    output O;
-    input CE;
-    input I;
-endmodule
-
 module BUFIO (...);
     output O;
     input I;
@@ -2420,12 +2388,6 @@ module LDPE (...);
     input D, G, GE, PRE;
 endmodule
 
-module LUT6_2 (...);
-    parameter [63:0] INIT = 64'h0000000000000000;
-    input I0, I1, I2, I3, I4, I5;
-    output O5, O6;
-endmodule
-
 module MMCME2_ADV (...);
     parameter BANDWIDTH = "OPTIMIZED";
     parameter real CLKFBOUT_MULT_F = 5.000;
-- 
cgit v1.2.3


From 6008bb7002f874e5c748eaa2050e7b6c17b32745 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Thu, 18 Apr 2019 07:59:16 -0700
Subject: Revert "synth_* with -retime option now calls abc with -D 1 as well"

This reverts commit 9a6da9a79a22e984ee3eec02caa230b66f10e11a.
---
 techlibs/achronix/synth_achronix.cc       | 4 ++--
 techlibs/anlogic/synth_anlogic.cc         | 2 +-
 techlibs/coolrunner2/synth_coolrunner2.cc | 2 +-
 techlibs/easic/synth_easic.cc             | 2 +-
 techlibs/ecp5/synth_ecp5.cc               | 2 +-
 techlibs/gowin/synth_gowin.cc             | 2 +-
 techlibs/greenpak4/synth_greenpak4.cc     | 2 +-
 techlibs/ice40/synth_ice40.cc             | 2 +-
 techlibs/intel/synth_intel.cc             | 6 +++---
 techlibs/sf2/synth_sf2.cc                 | 2 +-
 techlibs/xilinx/synth_xilinx.cc           | 4 ++--
 11 files changed, 15 insertions(+), 15 deletions(-)

(limited to 'techlibs')

diff --git a/techlibs/achronix/synth_achronix.cc b/techlibs/achronix/synth_achronix.cc
index 3dbf20911..626860d9c 100755
--- a/techlibs/achronix/synth_achronix.cc
+++ b/techlibs/achronix/synth_achronix.cc
@@ -152,12 +152,12 @@ struct SynthAchronixPass : public ScriptPass {
         run("clean -purge");
         run("setundef -undriven -zero");
         if (retime || help_mode)
-          run("abc -markgroups -dff -D 1", "(only if -retime)");
+          run("abc -markgroups -dff", "(only if -retime)");
       }
 
     if (check_label("map_luts"))
       {
-        run("abc -lut 4" + string(retime ? " -dff -D 1" : ""));
+        run("abc -lut 4" + string(retime ? " -dff" : ""));
         run("clean");
       }
 
diff --git a/techlibs/anlogic/synth_anlogic.cc b/techlibs/anlogic/synth_anlogic.cc
index 258e3d722..620bf3965 100644
--- a/techlibs/anlogic/synth_anlogic.cc
+++ b/techlibs/anlogic/synth_anlogic.cc
@@ -164,7 +164,7 @@ struct SynthAnlogicPass : public ScriptPass
 			run("opt -undriven -fine");
 			run("techmap -map +/techmap.v -map +/anlogic/arith_map.v");
 			if (retime || help_mode)
-				run("abc -dff -D 1", "(only if -retime)");
+				run("abc -dff", "(only if -retime)");
 		}
 
 		if (check_label("map_ffs"))
diff --git a/techlibs/coolrunner2/synth_coolrunner2.cc b/techlibs/coolrunner2/synth_coolrunner2.cc
index fa4fe0f5b..21bbcaef4 100644
--- a/techlibs/coolrunner2/synth_coolrunner2.cc
+++ b/techlibs/coolrunner2/synth_coolrunner2.cc
@@ -161,7 +161,7 @@ struct SynthCoolrunner2Pass : public ScriptPass
 
 		if (check_label("map_pla"))
 		{
-			run("abc -sop -I 40 -P 56" + string(retime ? " -dff -D 1" : ""));
+			run("abc -sop -I 40 -P 56");
 			run("clean");
 		}
 
diff --git a/techlibs/easic/synth_easic.cc b/techlibs/easic/synth_easic.cc
index 7bacc7890..dd9e3dab7 100644
--- a/techlibs/easic/synth_easic.cc
+++ b/techlibs/easic/synth_easic.cc
@@ -158,7 +158,7 @@ struct SynthEasicPass : public ScriptPass
 			run("techmap");
 			run("opt -fast");
 			if (retime || help_mode) {
-				run("abc -dff -D 1", " (only if -retime)");
+				run("abc -dff", " (only if -retime)");
 				run("opt_clean", "(only if -retime)");
 			}
 		}
diff --git a/techlibs/ecp5/synth_ecp5.cc b/techlibs/ecp5/synth_ecp5.cc
index 45f101451..4b889d672 100644
--- a/techlibs/ecp5/synth_ecp5.cc
+++ b/techlibs/ecp5/synth_ecp5.cc
@@ -242,7 +242,7 @@ struct SynthEcp5Pass : public ScriptPass
 			else
 				run("techmap -map +/techmap.v -map +/ecp5/arith_map.v");
 			if (retime || help_mode)
-				run("abc -dff -D 1", "(only if -retime)");
+				run("abc -dff", "(only if -retime)");
 		}
 
 		if (check_label("map_ffs"))
diff --git a/techlibs/gowin/synth_gowin.cc b/techlibs/gowin/synth_gowin.cc
index 0ebd77d63..9a3fcdbb6 100644
--- a/techlibs/gowin/synth_gowin.cc
+++ b/techlibs/gowin/synth_gowin.cc
@@ -163,7 +163,7 @@ struct SynthGowinPass : public ScriptPass
 			run("splitnets -ports");
 			run("setundef -undriven -zero");
 			if (retime || help_mode)
-				run("abc -dff -D 1", "(only if -retime)");
+				run("abc -dff", "(only if -retime)");
 		}
 
 		if (check_label("map_luts"))
diff --git a/techlibs/greenpak4/synth_greenpak4.cc b/techlibs/greenpak4/synth_greenpak4.cc
index 3222be2e3..eeb001b46 100644
--- a/techlibs/greenpak4/synth_greenpak4.cc
+++ b/techlibs/greenpak4/synth_greenpak4.cc
@@ -165,7 +165,7 @@ struct SynthGreenPAK4Pass : public ScriptPass
 			run("dfflibmap -prepare -liberty +/greenpak4/gp_dff.lib");
 			run("opt -fast");
 			if (retime || help_mode)
-				run("abc -dff -D 1", "(only if -retime)");
+				run("abc -dff", "(only if -retime)");
 		}
 
 		if (check_label("map_luts"))
diff --git a/techlibs/ice40/synth_ice40.cc b/techlibs/ice40/synth_ice40.cc
index d114b6269..8899bfcc4 100644
--- a/techlibs/ice40/synth_ice40.cc
+++ b/techlibs/ice40/synth_ice40.cc
@@ -274,7 +274,7 @@ struct SynthIce40Pass : public ScriptPass
 			else
 				run("techmap -map +/techmap.v -map +/ice40/arith_map.v");
 			if (retime || help_mode)
-				run("abc -dff -D 1", "(only if -retime)");
+				run("abc -dff", "(only if -retime)");
 			run("ice40_opt");
 		}
 
diff --git a/techlibs/intel/synth_intel.cc b/techlibs/intel/synth_intel.cc
index 290282bd9..0f1d7a7b5 100644
--- a/techlibs/intel/synth_intel.cc
+++ b/techlibs/intel/synth_intel.cc
@@ -210,15 +210,15 @@ struct SynthIntelPass : public ScriptPass {
         run("clean -purge");
         run("setundef -undriven -zero");
         if (retime || help_mode)
-          run("abc -markgroups -dff -D 1", "(only if -retime)");
+          run("abc -markgroups -dff", "(only if -retime)");
       }
 
     if (check_label("map_luts"))
       {
         if(family_opt=="a10gx" || family_opt=="cyclonev")
-          run("abc -luts 2:2,3,6:5" + string(retime ? " -dff -D 1" : ""));
+          run("abc -luts 2:2,3,6:5" + string(retime ? " -dff" : ""));
         else
-          run("abc -lut 4" + string(retime ? " -dff -D 1" : ""));
+          run("abc -lut 4" + string(retime ? " -dff" : ""));
         run("clean");
       }
 
diff --git a/techlibs/sf2/synth_sf2.cc b/techlibs/sf2/synth_sf2.cc
index 3c5a58b4c..0924df7a6 100644
--- a/techlibs/sf2/synth_sf2.cc
+++ b/techlibs/sf2/synth_sf2.cc
@@ -181,7 +181,7 @@ struct SynthSf2Pass : public ScriptPass
 			run("opt -undriven -fine");
 			run("techmap -map +/techmap.v -map +/sf2/arith_map.v");
 			if (retime || help_mode)
-				run("abc -dff -D 1", "(only if -retime)");
+				run("abc -dff", "(only if -retime)");
 		}
 
 		if (check_label("map_ffs"))
diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc
index a462b9052..397c83ac6 100644
--- a/techlibs/xilinx/synth_xilinx.cc
+++ b/techlibs/xilinx/synth_xilinx.cc
@@ -115,7 +115,7 @@ struct SynthXilinxPass : public Pass
 		log("\n");
 		log("    map_luts:\n");
 		log("        techmap -map +/techmap.v -map +/xilinx/ff_map.v t:$_DFF_?N?\n");
-		log("        abc -luts 2:2,3,6:5,10,20 [-dff -D 1]\n");
+		log("        abc -luts 2:2,3,6:5,10,20 [-dff]\n");
 		log("        clean\n");
 		log("        techmap -map +/xilinx/lut_map.v -map +/xilinx/ff_map.v");
 		log("\n");
@@ -269,7 +269,7 @@ struct SynthXilinxPass : public Pass
 		if (check_label(active, run_from, run_to, "map_luts"))
 		{
 			Pass::call(design, "techmap -map +/techmap.v -map +/xilinx/ff_map.v t:$_DFF_?N?");
-			Pass::call(design, "abc -luts 2:2,3,6:5,10,20" + string(retime ? " -dff -D 1" : ""));
+			Pass::call(design, "abc -luts 2:2,3,6:5,10,20" + string(retime ? " -dff" : ""));
 			Pass::call(design, "clean");
 			Pass::call(design, "techmap -map +/xilinx/lut_map.v -map +/xilinx/ff_map.v");
 		}
-- 
cgit v1.2.3