From 0acc51c3d82f65f73fa9e475c6fc41beabd925a6 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Fri, 4 Oct 2019 17:35:43 -0700 Subject: Add temporary `abc9 -nomfs` and use for `synth_xilinx -abc9` --- techlibs/xilinx/synth_xilinx.cc | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) (limited to 'techlibs') diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc index 7085214de..1cddd2a92 100644 --- a/techlibs/xilinx/synth_xilinx.cc +++ b/techlibs/xilinx/synth_xilinx.cc @@ -477,10 +477,14 @@ struct SynthXilinxPass : public ScriptPass log_warning("'synth_xilinx -abc9' currently supports '-family xc7' only.\n"); run("techmap -map +/xilinx/abc_map.v -max_iter 1"); run("read_verilog -icells -lib +/xilinx/abc_model.v"); + std::string abc9_opts = " -box +/xilinx/abc_xc7.box"; + abc9_opts += stringf(" -W %d", XC7_WIRE_DELAY); + abc9_opts += " -nomfs"; if (nowidelut) - run("abc9 -lut +/xilinx/abc_xc7_nowide.lut -box +/xilinx/abc_xc7.box -W " + std::to_string(XC7_WIRE_DELAY)); + abc9_opts += " -lut +/xilinx/abc_xc7_nowide.lut"; else - run("abc9 -lut +/xilinx/abc_xc7.lut -box +/xilinx/abc_xc7.box -W " + std::to_string(XC7_WIRE_DELAY)); + abc9_opts += " -lut +/xilinx/abc_xc7.lut"; + run("abc9" + abc9_opts); } else { if (nowidelut) -- cgit v1.2.3