From b63b2a0bd4552a7dbe0d2c4a15d4e3a1b0e2022d Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Fri, 14 Jun 2019 12:50:24 -0700
Subject: Revert "Remove wide mux inference"

This reverts commit 738fdfe8f55e18ac7f315cd68c117eae370004ca.
---
 techlibs/xilinx/Makefile.inc    |   1 +
 techlibs/xilinx/cells_map.v     | 120 ++++++++++++++++++++++++++++++++++++++++
 techlibs/xilinx/mux_map.v       |  52 +++++++++++++++++
 techlibs/xilinx/synth_xilinx.cc |  24 +++++++-
 4 files changed, 194 insertions(+), 3 deletions(-)
 create mode 100644 techlibs/xilinx/mux_map.v

(limited to 'techlibs')

diff --git a/techlibs/xilinx/Makefile.inc b/techlibs/xilinx/Makefile.inc
index 1a652eb27..59fd61cf0 100644
--- a/techlibs/xilinx/Makefile.inc
+++ b/techlibs/xilinx/Makefile.inc
@@ -30,6 +30,7 @@ $(eval $(call add_share_file,share/xilinx,techlibs/xilinx/drams_map.v))
 $(eval $(call add_share_file,share/xilinx,techlibs/xilinx/arith_map.v))
 $(eval $(call add_share_file,share/xilinx,techlibs/xilinx/ff_map.v))
 $(eval $(call add_share_file,share/xilinx,techlibs/xilinx/lut_map.v))
+$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/mux_map.v))
 $(eval $(call add_share_file,share/xilinx,techlibs/xilinx/abc_xc7.box))
 $(eval $(call add_share_file,share/xilinx,techlibs/xilinx/abc_xc7.lut))
 
diff --git a/techlibs/xilinx/cells_map.v b/techlibs/xilinx/cells_map.v
index b5114758c..f139dc5d5 100644
--- a/techlibs/xilinx/cells_map.v
+++ b/techlibs/xilinx/cells_map.v
@@ -154,3 +154,123 @@ module \$__XILINX_SHREG_ (input C, input D, input [31:0] L, input E, output Q, o
     end
   endgenerate
 endmodule
+
+module \$__XILINX_SHIFTX (A, B, Y);
+  parameter A_SIGNED = 0;
+  parameter B_SIGNED = 0;
+  parameter A_WIDTH = 1;
+  parameter B_WIDTH = 1;
+  parameter Y_WIDTH = 1;
+
+  input [A_WIDTH-1:0] A;
+  input [B_WIDTH-1:0] B;
+  output [Y_WIDTH-1:0] Y;
+
+  parameter [A_WIDTH-1:0] _TECHMAP_CONSTMSK_A_ = 0;
+  parameter [A_WIDTH-1:0] _TECHMAP_CONSTVAL_A_ = 0;
+  parameter [B_WIDTH-1:0] _TECHMAP_CONSTMSK_B_ = 0;
+  parameter [B_WIDTH-1:0] _TECHMAP_CONSTVAL_B_ = 0;
+
+  function integer compute_num_leading_X_in_A;
+    integer i, c;
+  begin
+    compute_num_leading_X_in_A = 0;
+    c = 1;
+    for (i = A_WIDTH-1; i >= 0; i=i-1) begin
+      if (!_TECHMAP_CONSTMSK_A_[i] || _TECHMAP_CONSTVAL_A_[i] !== 1'bx)
+        c = 0;
+      compute_num_leading_X_in_A = compute_num_leading_X_in_A + c;
+    end
+  end
+  endfunction
+  localparam num_leading_X_in_A = compute_num_leading_X_in_A();
+
+  generate
+    genvar i, j;
+    // Bit-blast
+    if (Y_WIDTH > 1) begin
+      for (i = 0; i < Y_WIDTH; i++)
+        \$__XILINX_SHIFTX  #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(A_WIDTH-Y_WIDTH+1), .B_WIDTH(B_WIDTH), .Y_WIDTH(1'd1)) bitblast (.A(A[A_WIDTH-Y_WIDTH+i:i]), .B(B), .Y(Y[i]));
+    end
+    // If the LSB of B is constant zero (and Y_WIDTH is 1) then
+    //   we can optimise by removing every other entry from A
+    //   and popping the constant zero from B
+    else if (_TECHMAP_CONSTMSK_B_[0] && !_TECHMAP_CONSTVAL_B_[0]) begin
+      wire [(A_WIDTH+1)/2-1:0] A_i;
+      for (i = 0; i < (A_WIDTH+1)/2; i++)
+        assign A_i[i] = A[i*2];
+      \$__XILINX_SHIFTX  #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH((A_WIDTH+1'd1)/2'd2), .B_WIDTH(B_WIDTH-1'd1), .Y_WIDTH(Y_WIDTH)) _TECHMAP_REPLACE_ (.A(A_i), .B(B[B_WIDTH-1:1]), .Y(Y));
+    end
+    // Trim off any leading 1'bx -es in A, and resize B accordingly
+    else if (num_leading_X_in_A > 0) begin
+      localparam A_WIDTH_new = A_WIDTH - num_leading_X_in_A;
+      localparam B_WIDTH_new = $clog2(A_WIDTH_new);
+      \$__XILINX_SHIFTX  #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(A_WIDTH_new), .B_WIDTH(B_WIDTH_new), .Y_WIDTH(Y_WIDTH)) _TECHMAP_REPLACE_ (.A(A[A_WIDTH_new-1:0]), .B(B[B_WIDTH_new-1:0]), .Y(Y));
+    end
+    else if (B_WIDTH < 3 || A_WIDTH <= 4) begin
+      \$shiftx  #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(A_WIDTH), .B_WIDTH(B_WIDTH), .Y_WIDTH(Y_WIDTH)) _TECHMAP_REPLACE_ (.A(A), .B(B), .Y(Y));
+    end
+    else if (B_WIDTH == 3) begin
+      localparam a_width0 = 2 ** 2;
+      localparam a_widthN = A_WIDTH - a_width0;
+      wire T0, T1;
+      \$shiftx  #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(a_width0), .B_WIDTH(2),                .Y_WIDTH(Y_WIDTH)) fpga_soft_mux      (.A(A[a_width0-1:0]),       .B(B[2-1:0]),                .Y(T0));
+      if (a_widthN > 1)
+        \$shiftx  #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(a_widthN), .B_WIDTH($clog2(a_widthN)), .Y_WIDTH(Y_WIDTH)) fpga_soft_mux_last (.A(A[A_WIDTH-1:a_width0]), .B(B[$clog2(a_widthN)-1:0]), .Y(T1));
+      else
+        assign T1 = A[A_WIDTH-1];
+      MUXF7 fpga_hard_mux (.I0(T0), .I1(T1), .S(B[B_WIDTH-1]), .O(Y));
+    end
+    else if (B_WIDTH == 4) begin
+      localparam a_width0 = 2 ** 2;
+      localparam num_mux8 = A_WIDTH / a_width0;
+      localparam a_widthN = A_WIDTH - num_mux8*a_width0;
+      wire [4-1:0] T;
+      wire T0, T1;
+      for (i = 0; i < 4; i++)
+        if (i < num_mux8)
+          \$shiftx  #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(a_width0), .B_WIDTH(2),                .Y_WIDTH(Y_WIDTH)) fpga_soft_mux      (.A(A[i*a_width0+:a_width0]), .B(B[2-1:0]),                .Y(T[i]));
+        else if (i == num_mux8 && a_widthN > 0) begin
+          if (a_widthN > 1)
+            \$shiftx  #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(a_widthN), .B_WIDTH($clog2(a_widthN)), .Y_WIDTH(Y_WIDTH)) fpga_soft_mux_last (.A(A[A_WIDTH-1:i*a_width0]), .B(B[$clog2(a_widthN)-1:0]), .Y(T[i]));
+          else
+            assign T[i] = A[A_WIDTH-1];
+        end
+        else
+          assign T[i] = 1'bx;
+      MUXF7 fpga_hard_mux_0 (.I0(T[0]), .I1(T[1]), .S(B[2]), .O(T0));
+      MUXF7 fpga_hard_mux_1 (.I0(T[2]), .I1(T[3]), .S(B[2]), .O(T1));
+      MUXF8 fpga_hard_mux_2 (.I0(T0),   .I1(T1),   .S(B[3]), .O(Y));
+    end
+    else begin
+      localparam a_width0 = 2 ** 4;
+      localparam num_mux16 = A_WIDTH / a_width0;
+      localparam a_widthN = A_WIDTH - num_mux16*a_width0;
+      wire [(2**(B_WIDTH-4))-1:0] T;
+      for (i = 0; i < 2 ** (B_WIDTH-4); i++)
+        if (i < num_mux16)
+          \$__XILINX_SHIFTX  #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(a_width0), .B_WIDTH(4),                .Y_WIDTH(Y_WIDTH)) fpga_soft_mux      (.A(A[i*a_width0+:a_width0]), .B(B[4-1:0]),                .Y(T[i]));
+        else if (i == num_mux16 && a_widthN > 0) begin
+          if (a_widthN > 1)
+            \$__XILINX_SHIFTX  #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(a_widthN), .B_WIDTH($clog2(a_widthN)), .Y_WIDTH(Y_WIDTH)) fpga_soft_mux_last (.A(A[A_WIDTH-1:i*a_width0]), .B(B[$clog2(a_widthN)-1:0]), .Y(T[i]));
+          else
+            assign T[i] = A[A_WIDTH-1];
+        end
+        else
+          assign T[i] = 1'bx;
+      \$__XILINX_SHIFTX  #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(2**(B_WIDTH-4)), .B_WIDTH(B_WIDTH-4), .Y_WIDTH(Y_WIDTH)) _TECHMAP_REPLACE_ (.A(T), .B(B[B_WIDTH-1:4]), .Y(Y));
+    end
+  endgenerate
+endmodule
+
+module \$_MUX8_ (A, B, C, D, E, F, G, H, S, T, U, Y);
+input A, B, C, D, E, F, G, H, S, T, U;
+output Y;
+  \$__XILINX_SHIFTX  #(.A_SIGNED(0), .B_SIGNED(0), .A_WIDTH(8), .B_WIDTH(3), .Y_WIDTH(1)) _TECHMAP_REPLACE_ (.A({H,G,F,E,D,C,B,A}), .B({U,T,S}), .Y(Y));
+endmodule
+
+module \$_MUX16_ (A, B, C, D, E, F, G, H, I, J, K, L, M, N, O, P, S, T, U, V, Y);
+input A, B, C, D, E, F, G, H, I, J, K, L, M, N, O, P, S, T, U, V;
+output Y;
+  \$__XILINX_SHIFTX  #(.A_SIGNED(0), .B_SIGNED(0), .A_WIDTH(16), .B_WIDTH(4), .Y_WIDTH(1)) _TECHMAP_REPLACE_ (.A({P,O,N,M,L,K,J,I,H,G,F,E,D,C,B,A}), .B({V,U,T,S}), .Y(Y));
+endmodule
diff --git a/techlibs/xilinx/mux_map.v b/techlibs/xilinx/mux_map.v
new file mode 100644
index 000000000..0fa8db736
--- /dev/null
+++ b/techlibs/xilinx/mux_map.v
@@ -0,0 +1,52 @@
+/*
+ *  yosys -- Yosys Open SYnthesis Suite
+ *
+ *  Copyright (C) 2012  Clifford Wolf <clifford@clifford.at>
+ *                2019  Eddie Hung    <eddie@fpgeh.com>
+ *
+ *  Permission to use, copy, modify, and/or distribute this software for any
+ *  purpose with or without fee is hereby granted, provided that the above
+ *  copyright notice and this permission notice appear in all copies.
+ *
+ *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ */
+
+module \$shiftx (A, B, Y);
+  parameter A_SIGNED = 0;
+  parameter B_SIGNED = 0;
+  parameter A_WIDTH = 1;
+  parameter B_WIDTH = 1;
+  parameter Y_WIDTH = 1;
+
+  input [A_WIDTH-1:0] A;
+  input [B_WIDTH-1:0] B;
+  output [Y_WIDTH-1:0] Y;
+
+  parameter [B_WIDTH-1:0] _TECHMAP_CONSTMSK_B_ = 0;
+  parameter [B_WIDTH-1:0] _TECHMAP_CONSTVAL_B_ = 0;
+
+  generate
+    genvar i, j;
+    // TODO: Check if this opt still necessary
+    if (B_SIGNED) begin
+      if (_TECHMAP_CONSTMSK_B_[B_WIDTH-1] && _TECHMAP_CONSTVAL_B_[B_WIDTH-1] == 1'b0)
+        // Optimisation to remove B_SIGNED if sign bit of B is constant-0
+        \$__XILINX_SHIFTX  #(.A_SIGNED(A_SIGNED), .B_SIGNED(0), .A_WIDTH(A_WIDTH), .B_WIDTH(B_WIDTH-1'd1), .Y_WIDTH(Y_WIDTH)) _TECHMAP_REPLACE_ (.A(A), .B(B[B_WIDTH-2:0]), .Y(Y));
+      else
+        wire _TECHMAP_FAIL_ = 1;
+    end
+    else if (B_WIDTH < 3 || A_WIDTH <= 4) begin
+      wire _TECHMAP_FAIL_ = 1;
+    end
+    else begin
+        \$__XILINX_SHIFTX  #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(A_WIDTH), .B_WIDTH(B_WIDTH), .Y_WIDTH(Y_WIDTH)) _TECHMAP_REPLACE_ (.A(A), .B(B), .Y(Y));
+    end
+  endgenerate
+endmodule
diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc
index a11648873..63ede275f 100644
--- a/techlibs/xilinx/synth_xilinx.cc
+++ b/techlibs/xilinx/synth_xilinx.cc
@@ -72,6 +72,9 @@ struct SynthXilinxPass : public ScriptPass
 		log("    -nosrl\n");
 		log("        disable inference of shift registers\n");
 		log("\n");
+		log("    -nomux\n");
+		log("        disable inference of wide multiplexers\n");
+		log("\n");
 		log("    -run <from_label>:<to_label>\n");
 		log("        only run the commands between the labels (see below). an empty\n");
 		log("        from label is synonymous to 'begin', and empty to label is\n");
@@ -93,7 +96,7 @@ struct SynthXilinxPass : public ScriptPass
 	}
 
 	std::string top_opt, edif_file, blif_file, abc, arch;
-	bool flatten, retime, vpr, nocarry, nobram, nodram, nosrl;
+	bool flatten, retime, vpr, nocarry, nobram, nodram, nosrl, nomux;
 
 	void clear_flags() YS_OVERRIDE
 	{
@@ -108,6 +111,7 @@ struct SynthXilinxPass : public ScriptPass
 		nobram = false;
 		nodram = false;
 		nosrl = false;
+		nomux = false;
 		arch = "xc7";
 	}
 
@@ -171,6 +175,10 @@ struct SynthXilinxPass : public ScriptPass
 				nosrl = true;
 				continue;
 			}
+			if (args[argidx] == "-nomux") {
+				nomux = true;
+				continue;
+			}
 			if (args[argidx] == "-abc9") {
 				abc = "abc9";
 				continue;
@@ -219,11 +227,15 @@ struct SynthXilinxPass : public ScriptPass
 		if (check_label("coarse")) {
 			run("synth -run coarse");
 
+			//if (!nomux || help_mode)
+			//	run("muxpack", "(skip if '-nomux')");
+
 			// shregmap -tech xilinx can cope with $shiftx and $mux
 			//   cells for identifying variable-length shift registers,
 			//   so attempt to convert $pmux-es to the former
-			if (!nosrl || help_mode)
-				run("pmux2shiftx", "(skip if '-nosrl')");
+			// Also: wide multiplexer inference benefits from this too
+			if (!(nosrl && nomux) || help_mode)
+				run("pmux2shiftx", "(skip if '-nosrl' and '-nomux')");
 
 			// Run a number of peephole optimisations, including one
 			//   that optimises $mul cells driving $shiftx's B input
@@ -261,6 +273,10 @@ struct SynthXilinxPass : public ScriptPass
 			}
 
 			std::string techmap_files = " -map +/techmap.v";
+			if (help_mode)
+				techmap_files += " [-map +/xilinx/mux_map.v]";
+			else if (!nomux)
+				techmap_files += " -map +/xilinx/mux_map.v";
 			if (help_mode)
 				techmap_files += " [-map +/xilinx/arith_map.v]";
 			else if (!nocarry) {
@@ -275,6 +291,8 @@ struct SynthXilinxPass : public ScriptPass
 		}
 
 		if (check_label("map_cells")) {
+			if (!nomux || help_mode)
+				run("muxcover -mux8 -mux16", "(skip if '-nomux')");
 			run("techmap -map +/techmap.v -map +/xilinx/cells_map.v");
 			run("clean");
 		}
-- 
cgit v1.2.3


From 1ec450d6bf34a7aec9b0469b6f295847eb658160 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Sun, 16 Jun 2019 12:08:03 -0700
Subject: Try -W 300

---
 techlibs/xilinx/synth_xilinx.cc | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

(limited to 'techlibs')

diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc
index 63ede275f..7b20a7132 100644
--- a/techlibs/xilinx/synth_xilinx.cc
+++ b/techlibs/xilinx/synth_xilinx.cc
@@ -25,7 +25,8 @@
 USING_YOSYS_NAMESPACE
 PRIVATE_NAMESPACE_BEGIN
 
-#define XC7_WIRE_DELAY "160"
+#define XC7_WIRE_DELAY "300" // Number with which ABC will map a 6-input gate
+                             // to one LUT6 (instead of a LUT5 + LUT2)
 
 struct SynthXilinxPass : public ScriptPass
 {
-- 
cgit v1.2.3


From 9faab38e8de1a78b0ce364a1bdefd2a9ee9c2ec6 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Thu, 20 Jun 2019 16:45:04 -0700
Subject: mux_map to drop sign bit, and eliminate 'bx-es

---
 techlibs/xilinx/mux_map.v | 60 +++++++++++++++++++++++++++++++++++++----------
 1 file changed, 47 insertions(+), 13 deletions(-)

(limited to 'techlibs')

diff --git a/techlibs/xilinx/mux_map.v b/techlibs/xilinx/mux_map.v
index 0fa8db736..6ad83a488 100644
--- a/techlibs/xilinx/mux_map.v
+++ b/techlibs/xilinx/mux_map.v
@@ -29,24 +29,58 @@ module \$shiftx (A, B, Y);
   input [B_WIDTH-1:0] B;
   output [Y_WIDTH-1:0] Y;
 
+  parameter [A_WIDTH-1:0] _TECHMAP_CONSTMSK_A_ = 0;
+  parameter [A_WIDTH-1:0] _TECHMAP_CONSTVAL_A_ = 0;
   parameter [B_WIDTH-1:0] _TECHMAP_CONSTMSK_B_ = 0;
   parameter [B_WIDTH-1:0] _TECHMAP_CONSTVAL_B_ = 0;
 
   generate
-    genvar i, j;
-    // TODO: Check if this opt still necessary
-    if (B_SIGNED) begin
-      if (_TECHMAP_CONSTMSK_B_[B_WIDTH-1] && _TECHMAP_CONSTVAL_B_[B_WIDTH-1] == 1'b0)
-        // Optimisation to remove B_SIGNED if sign bit of B is constant-0
-        \$__XILINX_SHIFTX  #(.A_SIGNED(A_SIGNED), .B_SIGNED(0), .A_WIDTH(A_WIDTH), .B_WIDTH(B_WIDTH-1'd1), .Y_WIDTH(Y_WIDTH)) _TECHMAP_REPLACE_ (.A(A), .B(B[B_WIDTH-2:0]), .Y(Y));
+    genvar i;
+    wire [A_WIDTH-1:0] A_forward;
+    assign A_forward[A_WIDTH-1] = A[A_WIDTH-1];
+    for (i = A_WIDTH-2; i >= 0; i = i - 1)
+      if (_TECHMAP_CONSTMSK_A_[i] && _TECHMAP_CONSTVAL_A_[i] === 1'bx)
+        assign A_forward[i] = A_forward[i+1];
       else
-        wire _TECHMAP_FAIL_ = 1;
-    end
-    else if (B_WIDTH < 3 || A_WIDTH <= 4) begin
-      wire _TECHMAP_FAIL_ = 1;
-    end
-    else begin
-        \$__XILINX_SHIFTX  #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(A_WIDTH), .B_WIDTH(B_WIDTH), .Y_WIDTH(Y_WIDTH)) _TECHMAP_REPLACE_ (.A(A), .B(B), .Y(Y));
+        assign A_forward[i] = A[i];
+
+      wire [A_WIDTH-1:0] A_without_x;
+      assign A_without_x[0] = A_forward[0];
+      for (i = 1; i < A_WIDTH; i = i + 1)
+        if (_TECHMAP_CONSTMSK_A_[i] && _TECHMAP_CONSTVAL_A_[i] === 1'bx)
+          assign A_without_x[i] = A_without_x[i-1];
+        else
+          assign A_without_x[i] = A[i];
+
+        if (B_SIGNED) begin
+          if (B_WIDTH < 4 || A_WIDTH <= 4)
+            wire _TECHMAP_FAIL_ = 1;
+          else
+            // Since negative indices are out of the range of A
+            // and hence return 'bx, drop the sign bit
+            \$__XILINX_SHIFTX #(
+              .A_SIGNED(A_SIGNED),
+              .B_SIGNED(0),
+              .A_WIDTH(A_WIDTH),
+              .B_WIDTH(B_WIDTH-1'd1),
+              .Y_WIDTH(Y_WIDTH)
+            ) _TECHMAP_REPLACE_ (
+              .A(A_without_x), .B(B[B_WIDTH-2:0]), .Y(Y)
+            );
+      end
+      else begin
+        if (B_WIDTH < 3 || A_WIDTH <= 4)
+          wire _TECHMAP_FAIL_ = 1;
+        else
+          \$__XILINX_SHIFTX #(
+            .A_SIGNED(A_SIGNED),
+            .B_SIGNED(B_SIGNED),
+            .A_WIDTH(A_WIDTH),
+            .B_WIDTH(B_WIDTH),
+            .Y_WIDTH(Y_WIDTH)
+          ) _TECHMAP_REPLACE_ (
+            .A(A_without_x), .B(B), .Y(Y)
+          );
     end
   endgenerate
 endmodule
-- 
cgit v1.2.3


From d1dadfcec8e5fffb1d27f067a86a606591b9c686 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Thu, 20 Jun 2019 16:45:09 -0700
Subject: Call opt_expr -mux_undef to get rid of 1'bx in muxes prior to abc

---
 techlibs/xilinx/synth_xilinx.cc | 1 +
 1 file changed, 1 insertion(+)

(limited to 'techlibs')

diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc
index 7b20a7132..f1e887df8 100644
--- a/techlibs/xilinx/synth_xilinx.cc
+++ b/techlibs/xilinx/synth_xilinx.cc
@@ -299,6 +299,7 @@ struct SynthXilinxPass : public ScriptPass
 		}
 
 		if (check_label("map_luts")) {
+			run("opt_expr -mux_undef");
 			if (abc == "abc9")
 				run(abc + " -lut +/xilinx/abc_xc7.lut -box +/xilinx/abc_xc7.box -W " + XC7_WIRE_DELAY + string(retime ? " -dff" : ""));
 			else if (help_mode)
-- 
cgit v1.2.3


From dd22edcd28f2ef9411dde9a941f1fefe05d7bff1 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Fri, 21 Jun 2019 11:12:32 -0700
Subject: Expand synth -coarse without wreduce, move muxcover

---
 techlibs/xilinx/synth_xilinx.cc | 36 ++++++++++++++++++++++++------------
 1 file changed, 24 insertions(+), 12 deletions(-)

(limited to 'techlibs')

diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc
index f1e887df8..ede2bda10 100644
--- a/techlibs/xilinx/synth_xilinx.cc
+++ b/techlibs/xilinx/synth_xilinx.cc
@@ -218,15 +218,25 @@ struct SynthXilinxPass : public ScriptPass
 			run(stringf("hierarchy -check %s", top_opt.c_str()));
 		}
 
-		if (check_label("flatten", "(with '-flatten' only)")) {
-			if (flatten || help_mode) {
-				run("proc");
-				run("flatten");
-			}
-		}
-
 		if (check_label("coarse")) {
-			run("synth -run coarse");
+			run("proc");
+			if (flatten || help_mode)
+				run("flatten", "(with -flatten only)");
+			run("opt_expr");
+			run("opt_clean");
+			run("check");
+			run("opt");
+			// FIXME
+			//run("wreduce");
+			run("peepopt");
+			run("opt_clean");
+			run("alumacc");
+			run("share");
+			run("opt");
+			run("fsm");
+			run("opt -fast");
+			run("memory -nomap");
+			run("opt_clean");
 
 			//if (!nomux || help_mode)
 			//	run("muxpack", "(skip if '-nomux')");
@@ -259,16 +269,20 @@ struct SynthXilinxPass : public ScriptPass
 		}
 
 		if (check_label("fine")) {
-			run("opt -fast -full");
+			run("opt -fast");
 			run("memory_map");
 			run("dffsr2dff");
 			run("dff2dffe");
+			if (!nomux || help_mode) {
+				run("simplemap t:$mux", "                     (skip if -nomux)");
+				run("muxcover -mux4=150 -mux8=200 -mux16=250 -dmux=0", "(skip if -nomux)");
+			}
 			run("opt -full");
 
 			if (!nosrl || help_mode) {
 				// shregmap operates on bit-level flops, not word-level,
 				//   so break those down here
-				run("simplemap t:$dff t:$dffe", "(skip if '-nosrl')");
+				run("simplemap t:$dff t:$dffe", "       (skip if '-nosrl')");
 				// shregmap with '-tech xilinx' infers variable length shift regs
 				run("shregmap -tech xilinx -minlen 3", "(skip if '-nosrl')");
 			}
@@ -292,8 +306,6 @@ struct SynthXilinxPass : public ScriptPass
 		}
 
 		if (check_label("map_cells")) {
-			if (!nomux || help_mode)
-				run("muxcover -mux8 -mux16", "(skip if '-nomux')");
 			run("techmap -map +/techmap.v -map +/xilinx/cells_map.v");
 			run("clean");
 		}
-- 
cgit v1.2.3


From c6b4653ebe83fc5bacaeb92fe7c63a8d52bd523e Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Fri, 21 Jun 2019 11:13:01 -0700
Subject: Since muxcover uses MUX4s, blast them back to gates here

---
 techlibs/xilinx/mux_map.v | 7 +++++++
 1 file changed, 7 insertions(+)

(limited to 'techlibs')

diff --git a/techlibs/xilinx/mux_map.v b/techlibs/xilinx/mux_map.v
index 6ad83a488..b7ff6ca90 100644
--- a/techlibs/xilinx/mux_map.v
+++ b/techlibs/xilinx/mux_map.v
@@ -84,3 +84,10 @@ module \$shiftx (A, B, Y);
     end
   endgenerate
 endmodule
+
+module \$_MUX4_ (A, B, C, D, S, T, Y);
+input A, B, C, D, S, T;
+output Y;
+assign Y = T ? (S ? D : C) :
+               (S ? B : A);
+endmodule
-- 
cgit v1.2.3


From f433a523742350b4bb9291ad65299015e2c81f05 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Fri, 21 Jun 2019 11:15:23 -0700
Subject: Add FIXME about need for -mux4

---
 techlibs/xilinx/synth_xilinx.cc | 2 ++
 1 file changed, 2 insertions(+)

(limited to 'techlibs')

diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc
index ede2bda10..db3f5b7e4 100644
--- a/techlibs/xilinx/synth_xilinx.cc
+++ b/techlibs/xilinx/synth_xilinx.cc
@@ -275,6 +275,8 @@ struct SynthXilinxPass : public ScriptPass
 			run("dff2dffe");
 			if (!nomux || help_mode) {
 				run("simplemap t:$mux", "                     (skip if -nomux)");
+				              // FIXME: Must specify mux4, even if we don't need it,
+					      //        otherwise it will use mux8 as mux4
 				run("muxcover -mux4=150 -mux8=200 -mux16=250 -dmux=0", "(skip if -nomux)");
 			}
 			run("opt -full");
-- 
cgit v1.2.3


From 7acbea6b2874c40cc1e3dd4dc0dc31a3985d2abf Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Fri, 21 Jun 2019 14:38:30 -0700
Subject: Fix alignment

---
 techlibs/xilinx/synth_xilinx.cc | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'techlibs')

diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc
index db3f5b7e4..567859f62 100644
--- a/techlibs/xilinx/synth_xilinx.cc
+++ b/techlibs/xilinx/synth_xilinx.cc
@@ -274,7 +274,7 @@ struct SynthXilinxPass : public ScriptPass
 			run("dffsr2dff");
 			run("dff2dffe");
 			if (!nomux || help_mode) {
-				run("simplemap t:$mux", "                     (skip if -nomux)");
+				run("simplemap t:$mux", "                               (skip if -nomux)");
 				              // FIXME: Must specify mux4, even if we don't need it,
 					      //        otherwise it will use mux8 as mux4
 				run("muxcover -mux4=150 -mux8=200 -mux16=250 -dmux=0", "(skip if -nomux)");
-- 
cgit v1.2.3


From 9abde121103a0b004e9c9fa256951553f9bb4732 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Fri, 21 Jun 2019 15:47:42 -0700
Subject: Add $__XILINX_MUXF78 to preserve entire box

---
 techlibs/xilinx/abc_xc7.box | 11 ++++++++---
 techlibs/xilinx/cells_map.v | 16 ++++++++++++----
 techlibs/xilinx/cells_sim.v |  8 ++++++++
 3 files changed, 28 insertions(+), 7 deletions(-)

(limited to 'techlibs')

diff --git a/techlibs/xilinx/abc_xc7.box b/techlibs/xilinx/abc_xc7.box
index 8a48bad4e..a312646f7 100644
--- a/techlibs/xilinx/abc_xc7.box
+++ b/techlibs/xilinx/abc_xc7.box
@@ -1,16 +1,21 @@
 # Max delays from https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLL_L.sdf
 
-# F7BMUX slower than F7AMUX
+# Average across F7[AB]MUX
 # Inputs: I0 I1 S0
 # Outputs: O
-F7BMUX 1 1 3 1
-217 223 296
+F7MUX 1 1 3 1
+204 208 286
 
 # Inputs: I0 I1 S0
 # Outputs: O
 MUXF8 2 1 3 1
 104 94 273
 
+# Inputs: I0 I1 I2 I3 S0 S1
+# Outputs: O
+MUXF78 10 1 6 1
+190 193 217 223 296 273
+
 # CARRY4 + CARRY4_[ABCD]X
 # Inputs: S0 S1 S2 S3 CYINIT DI0 DI1 DI2 DI3 CI
 # Outputs:  O0 O1 O2 O3 CO0 CO1 CO2 CO3
diff --git a/techlibs/xilinx/cells_map.v b/techlibs/xilinx/cells_map.v
index f139dc5d5..9313df7cc 100644
--- a/techlibs/xilinx/cells_map.v
+++ b/techlibs/xilinx/cells_map.v
@@ -226,7 +226,6 @@ module \$__XILINX_SHIFTX (A, B, Y);
       localparam num_mux8 = A_WIDTH / a_width0;
       localparam a_widthN = A_WIDTH - num_mux8*a_width0;
       wire [4-1:0] T;
-      wire T0, T1;
       for (i = 0; i < 4; i++)
         if (i < num_mux8)
           \$shiftx  #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(a_width0), .B_WIDTH(2),                .Y_WIDTH(Y_WIDTH)) fpga_soft_mux      (.A(A[i*a_width0+:a_width0]), .B(B[2-1:0]),                .Y(T[i]));
@@ -238,9 +237,7 @@ module \$__XILINX_SHIFTX (A, B, Y);
         end
         else
           assign T[i] = 1'bx;
-      MUXF7 fpga_hard_mux_0 (.I0(T[0]), .I1(T[1]), .S(B[2]), .O(T0));
-      MUXF7 fpga_hard_mux_1 (.I0(T[2]), .I1(T[3]), .S(B[2]), .O(T1));
-      MUXF8 fpga_hard_mux_2 (.I0(T0),   .I1(T1),   .S(B[3]), .O(Y));
+      \$__XILINX_MUXF78 fpga_hard_mux (.I0(T[0]), .I1(T[1]), .I2(T[2]), .I3(T[3]), .S0(B[2]), .S1(B[3]), .O(Y));
     end
     else begin
       localparam a_width0 = 2 ** 4;
@@ -274,3 +271,14 @@ input A, B, C, D, E, F, G, H, I, J, K, L, M, N, O, P, S, T, U, V;
 output Y;
   \$__XILINX_SHIFTX  #(.A_SIGNED(0), .B_SIGNED(0), .A_WIDTH(16), .B_WIDTH(4), .Y_WIDTH(1)) _TECHMAP_REPLACE_ (.A({P,O,N,M,L,K,J,I,H,G,F,E,D,C,B,A}), .B({V,U,T,S}), .Y(Y));
 endmodule
+
+`ifndef _ABC
+module \$__XILINX_MUXF78 (O, I0, I1, I2, I3, S0, S1);
+  output O;
+  input I0, I1, I2, I3, S0, S1;
+  wire T0, T1;
+  MUXF7 mux7a (.I0(I0), .I1(I1), .S(S0), .O(T0));
+  MUXF7 mux7b (.I0(I2), .I1(I3), .S(S0), .O(T1));
+  MUXF8 mux8 (.I0(T0), .I1(T1), .S(S1), .O(O));
+endmodule
+`endif
diff --git a/techlibs/xilinx/cells_sim.v b/techlibs/xilinx/cells_sim.v
index bf7a0ed44..3163d8446 100644
--- a/techlibs/xilinx/cells_sim.v
+++ b/techlibs/xilinx/cells_sim.v
@@ -169,6 +169,14 @@ module MUXF8(output O, input I0, I1, S);
   assign O = S ? I1 : I0;
 endmodule
 
+`ifdef _ABC
+(* abc_box_id = 10, lib_whitebox *)
+module \$__XILINX_MUXF78 (output O, input I0, I1, I2, I3, S0, S1);
+  assign O = S1 ? (S0 ? I3 : I2)
+                : (S0 ? I1 : I0);
+endmodule
+`endif
+
 module XORCY(output O, input CI, LI);
   assign O = CI ^ LI;
 endmodule
-- 
cgit v1.2.3


From aa0b107afbe800e040886829d43e0b9fcb7219c0 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Fri, 21 Jun 2019 15:48:20 -0700
Subject: synth_xilinx to use _ABC macro, and perform muxpack again

---
 techlibs/xilinx/synth_xilinx.cc | 10 +++++-----
 1 file changed, 5 insertions(+), 5 deletions(-)

(limited to 'techlibs')

diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc
index 567859f62..170b3fb07 100644
--- a/techlibs/xilinx/synth_xilinx.cc
+++ b/techlibs/xilinx/synth_xilinx.cc
@@ -206,9 +206,9 @@ struct SynthXilinxPass : public ScriptPass
 	{
 		if (check_label("begin")) {
 			if (vpr)
-				run("read_verilog -lib -D _ABC -D_EXPLICIT_CARRY +/xilinx/cells_sim.v");
+				run("read_verilog -lib -icells -D _ABC -D_EXPLICIT_CARRY +/xilinx/cells_sim.v");
 			else
-				run("read_verilog -lib -D _ABC +/xilinx/cells_sim.v");
+				run("read_verilog -lib -icells -D _ABC +/xilinx/cells_sim.v");
 
 			run("read_verilog -lib +/xilinx/cells_xtra.v");
 
@@ -238,8 +238,8 @@ struct SynthXilinxPass : public ScriptPass
 			run("memory -nomap");
 			run("opt_clean");
 
-			//if (!nomux || help_mode)
-			//	run("muxpack", "(skip if '-nomux')");
+			if (!nomux || help_mode)
+				run("muxpack", "    (skip if '-nomux')");
 
 			// shregmap -tech xilinx can cope with $shiftx and $mux
 			//   cells for identifying variable-length shift registers,
@@ -308,7 +308,7 @@ struct SynthXilinxPass : public ScriptPass
 		}
 
 		if (check_label("map_cells")) {
-			run("techmap -map +/techmap.v -map +/xilinx/cells_map.v");
+			run("techmap -map +/techmap.v -D _ABC -map +/xilinx/cells_map.v");
 			run("clean");
 		}
 
-- 
cgit v1.2.3


From 4d6fac019a9a2ca3d2f0a05eb8d08c88e04faad0 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Fri, 21 Jun 2019 16:06:13 -0700
Subject: Fix spacing

---
 techlibs/xilinx/mux_map.v | 30 +++++++++++++++---------------
 1 file changed, 15 insertions(+), 15 deletions(-)

(limited to 'techlibs')

diff --git a/techlibs/xilinx/mux_map.v b/techlibs/xilinx/mux_map.v
index b7ff6ca90..4c1bb7d05 100644
--- a/techlibs/xilinx/mux_map.v
+++ b/techlibs/xilinx/mux_map.v
@@ -52,21 +52,21 @@ module \$shiftx (A, B, Y);
         else
           assign A_without_x[i] = A[i];
 
-        if (B_SIGNED) begin
-          if (B_WIDTH < 4 || A_WIDTH <= 4)
-            wire _TECHMAP_FAIL_ = 1;
-          else
-            // Since negative indices are out of the range of A
-            // and hence return 'bx, drop the sign bit
-            \$__XILINX_SHIFTX #(
-              .A_SIGNED(A_SIGNED),
-              .B_SIGNED(0),
-              .A_WIDTH(A_WIDTH),
-              .B_WIDTH(B_WIDTH-1'd1),
-              .Y_WIDTH(Y_WIDTH)
-            ) _TECHMAP_REPLACE_ (
-              .A(A_without_x), .B(B[B_WIDTH-2:0]), .Y(Y)
-            );
+      if (B_SIGNED) begin
+        if (B_WIDTH < 4 || A_WIDTH <= 4)
+          wire _TECHMAP_FAIL_ = 1;
+        else
+          // Since negative indices are out of the range of A
+          // and hence return 'bx, drop the sign bit
+          \$__XILINX_SHIFTX #(
+            .A_SIGNED(A_SIGNED),
+            .B_SIGNED(0),
+            .A_WIDTH(A_WIDTH),
+            .B_WIDTH($clog2(A_WIDTH*B_WIDTH)),
+            .Y_WIDTH(Y_WIDTH)
+          ) _TECHMAP_REPLACE_ (
+            .A(A_without_x), .B(B[B_WIDTH-2:0]), .Y(Y)
+          );
       end
       else begin
         if (B_WIDTH < 3 || A_WIDTH <= 4)
-- 
cgit v1.2.3


From 44fc616fc701d698564d68a7facf210947b8bd9e Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Fri, 21 Jun 2019 16:18:14 -0700
Subject: Revert B_SIGNED optimisation, since only works for Y_WIDTH==1

---
 techlibs/xilinx/mux_map.v | 7 +++----
 1 file changed, 3 insertions(+), 4 deletions(-)

(limited to 'techlibs')

diff --git a/techlibs/xilinx/mux_map.v b/techlibs/xilinx/mux_map.v
index 4c1bb7d05..89586d3c3 100644
--- a/techlibs/xilinx/mux_map.v
+++ b/techlibs/xilinx/mux_map.v
@@ -55,14 +55,13 @@ module \$shiftx (A, B, Y);
       if (B_SIGNED) begin
         if (B_WIDTH < 4 || A_WIDTH <= 4)
           wire _TECHMAP_FAIL_ = 1;
-        else
-          // Since negative indices are out of the range of A
-          // and hence return 'bx, drop the sign bit
+        else if (_TECHMAP_CONSTMSK_B_[B_WIDTH-1] && _TECHMAP_CONSTVAL_B_[B_WIDTH-1] == 1'b0)
+          // Optimisation to remove B_SIGNED if sign bit of B is constant-0
           \$__XILINX_SHIFTX #(
             .A_SIGNED(A_SIGNED),
             .B_SIGNED(0),
             .A_WIDTH(A_WIDTH),
-            .B_WIDTH($clog2(A_WIDTH*B_WIDTH)),
+            .B_WIDTH(B_WIDTH-1'd1),
             .Y_WIDTH(Y_WIDTH)
           ) _TECHMAP_REPLACE_ (
             .A(A_without_x), .B(B[B_WIDTH-2:0]), .Y(Y)
-- 
cgit v1.2.3


From 11886c874c6655bf635655324faa3af31f1c5cf7 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Fri, 21 Jun 2019 16:18:29 -0700
Subject: Restore wreduce to synth_xilinx, after muxcover

---
 techlibs/xilinx/synth_xilinx.cc | 1 +
 1 file changed, 1 insertion(+)

(limited to 'techlibs')

diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc
index 170b3fb07..174138e6a 100644
--- a/techlibs/xilinx/synth_xilinx.cc
+++ b/techlibs/xilinx/synth_xilinx.cc
@@ -279,6 +279,7 @@ struct SynthXilinxPass : public ScriptPass
 					      //        otherwise it will use mux8 as mux4
 				run("muxcover -mux4=150 -mux8=200 -mux16=250 -dmux=0", "(skip if -nomux)");
 			}
+			run("wreduce"); // FIXME: Moved until after muxcover from 'coarse'
 			run("opt -full");
 
 			if (!nosrl || help_mode) {
-- 
cgit v1.2.3


From 694d40719f7a557bd82fe3d9d245353b19349123 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Fri, 21 Jun 2019 16:47:07 -0700
Subject: Fix spacing again, A_forward -> A_backward

---
 techlibs/xilinx/mux_map.v | 78 ++++++++++++++++++++++++-----------------------
 1 file changed, 40 insertions(+), 38 deletions(-)

(limited to 'techlibs')

diff --git a/techlibs/xilinx/mux_map.v b/techlibs/xilinx/mux_map.v
index 89586d3c3..441c02ac2 100644
--- a/techlibs/xilinx/mux_map.v
+++ b/techlibs/xilinx/mux_map.v
@@ -37,49 +37,51 @@ module \$shiftx (A, B, Y);
   generate
     genvar i;
     wire [A_WIDTH-1:0] A_forward;
-    assign A_forward[A_WIDTH-1] = A[A_WIDTH-1];
+    assign A_backward[A_WIDTH-1] = A[A_WIDTH-1];
     for (i = A_WIDTH-2; i >= 0; i = i - 1)
       if (_TECHMAP_CONSTMSK_A_[i] && _TECHMAP_CONSTVAL_A_[i] === 1'bx)
-        assign A_forward[i] = A_forward[i+1];
+        assign A_backward[i] = A_backward[i+1];
       else
-        assign A_forward[i] = A[i];
+        assign A_backward[i] = A[i];
 
-      wire [A_WIDTH-1:0] A_without_x;
-      assign A_without_x[0] = A_forward[0];
-      for (i = 1; i < A_WIDTH; i = i + 1)
-        if (_TECHMAP_CONSTMSK_A_[i] && _TECHMAP_CONSTVAL_A_[i] === 1'bx)
-          assign A_without_x[i] = A_without_x[i-1];
-        else
-          assign A_without_x[i] = A[i];
+    wire [A_WIDTH-1:0] A_without_x;
+    assign A_without_x[0] = A_backward[0];
+    for (i = 1; i < A_WIDTH; i = i + 1)
+      if (_TECHMAP_CONSTMSK_A_[i] && _TECHMAP_CONSTVAL_A_[i] === 1'bx)
+        assign A_without_x[i] = A_without_x[i-1];
+      else
+        assign A_without_x[i] = A[i];
 
-      if (B_SIGNED) begin
-        if (B_WIDTH < 4 || A_WIDTH <= 4)
-          wire _TECHMAP_FAIL_ = 1;
-        else if (_TECHMAP_CONSTMSK_B_[B_WIDTH-1] && _TECHMAP_CONSTVAL_B_[B_WIDTH-1] == 1'b0)
-          // Optimisation to remove B_SIGNED if sign bit of B is constant-0
-          \$__XILINX_SHIFTX #(
-            .A_SIGNED(A_SIGNED),
-            .B_SIGNED(0),
-            .A_WIDTH(A_WIDTH),
-            .B_WIDTH(B_WIDTH-1'd1),
-            .Y_WIDTH(Y_WIDTH)
-          ) _TECHMAP_REPLACE_ (
-            .A(A_without_x), .B(B[B_WIDTH-2:0]), .Y(Y)
-          );
-      end
-      else begin
-        if (B_WIDTH < 3 || A_WIDTH <= 4)
-          wire _TECHMAP_FAIL_ = 1;
-        else
-          \$__XILINX_SHIFTX #(
-            .A_SIGNED(A_SIGNED),
-            .B_SIGNED(B_SIGNED),
-            .A_WIDTH(A_WIDTH),
-            .B_WIDTH(B_WIDTH),
-            .Y_WIDTH(Y_WIDTH)
-          ) _TECHMAP_REPLACE_ (
-            .A(A_without_x), .B(B), .Y(Y)
-          );
+    if (B_SIGNED) begin
+      if (B_WIDTH < 4 || A_WIDTH <= 4)
+        wire _TECHMAP_FAIL_ = 1;
+      else if (_TECHMAP_CONSTMSK_B_[B_WIDTH-1] && (_TECHMAP_CONSTVAL_B_[B_WIDTH-1] == 1'b0 || _TECHMAP_CONSTVAL_B_[B_WIDTH-1] === 1'bx))
+        // Optimisation to remove B_SIGNED if sign bit of B is constant-0
+        \$__XILINX_SHIFTX #(
+          .A_SIGNED(A_SIGNED),
+          .B_SIGNED(0),
+          .A_WIDTH(A_WIDTH),
+          .B_WIDTH(B_WIDTH-1'd1),
+          .Y_WIDTH(Y_WIDTH)
+        ) _TECHMAP_REPLACE_ (
+          .A(A_without_x), .B(B[B_WIDTH-2:0]), .Y(Y)
+        );
+      else
+        wire _TECHMAP_FAIL_ = 1;
+    end
+    else begin
+      if (B_WIDTH < 3 || A_WIDTH <= 4)
+        wire _TECHMAP_FAIL_ = 1;
+      else
+        \$__XILINX_SHIFTX #(
+          .A_SIGNED(A_SIGNED),
+          .B_SIGNED(B_SIGNED),
+          .A_WIDTH(A_WIDTH),
+          .B_WIDTH(B_WIDTH),
+          .Y_WIDTH(Y_WIDTH)
+        ) _TECHMAP_REPLACE_ (
+          .A(A_without_x), .B(B), .Y(Y)
+        );
     end
   endgenerate
 endmodule
-- 
cgit v1.2.3


From 8bce3fb32908fd5c74b57ecb178c4d68151149e7 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Fri, 21 Jun 2019 16:55:34 -0700
Subject: Fix spacing

---
 techlibs/xilinx/cells_map.v | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

(limited to 'techlibs')

diff --git a/techlibs/xilinx/cells_map.v b/techlibs/xilinx/cells_map.v
index 9313df7cc..18c926336 100644
--- a/techlibs/xilinx/cells_map.v
+++ b/techlibs/xilinx/cells_map.v
@@ -214,7 +214,7 @@ module \$__XILINX_SHIFTX (A, B, Y);
       localparam a_width0 = 2 ** 2;
       localparam a_widthN = A_WIDTH - a_width0;
       wire T0, T1;
-      \$shiftx  #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(a_width0), .B_WIDTH(2),                .Y_WIDTH(Y_WIDTH)) fpga_soft_mux      (.A(A[a_width0-1:0]),       .B(B[2-1:0]),                .Y(T0));
+      \$shiftx  #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(a_width0), .B_WIDTH(2), .Y_WIDTH(Y_WIDTH)) fpga_soft_mux (.A(A[a_width0-1:0]), .B(B[2-1:0]), .Y(T0));
       if (a_widthN > 1)
         \$shiftx  #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(a_widthN), .B_WIDTH($clog2(a_widthN)), .Y_WIDTH(Y_WIDTH)) fpga_soft_mux_last (.A(A[A_WIDTH-1:a_width0]), .B(B[$clog2(a_widthN)-1:0]), .Y(T1));
       else
@@ -228,7 +228,7 @@ module \$__XILINX_SHIFTX (A, B, Y);
       wire [4-1:0] T;
       for (i = 0; i < 4; i++)
         if (i < num_mux8)
-          \$shiftx  #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(a_width0), .B_WIDTH(2),                .Y_WIDTH(Y_WIDTH)) fpga_soft_mux      (.A(A[i*a_width0+:a_width0]), .B(B[2-1:0]),                .Y(T[i]));
+          \$shiftx  #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(a_width0), .B_WIDTH(2), .Y_WIDTH(Y_WIDTH)) fpga_soft_mux (.A(A[i*a_width0+:a_width0]), .B(B[2-1:0]), .Y(T[i]));
         else if (i == num_mux8 && a_widthN > 0) begin
           if (a_widthN > 1)
             \$shiftx  #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(a_widthN), .B_WIDTH($clog2(a_widthN)), .Y_WIDTH(Y_WIDTH)) fpga_soft_mux_last (.A(A[A_WIDTH-1:i*a_width0]), .B(B[$clog2(a_widthN)-1:0]), .Y(T[i]));
@@ -246,7 +246,7 @@ module \$__XILINX_SHIFTX (A, B, Y);
       wire [(2**(B_WIDTH-4))-1:0] T;
       for (i = 0; i < 2 ** (B_WIDTH-4); i++)
         if (i < num_mux16)
-          \$__XILINX_SHIFTX  #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(a_width0), .B_WIDTH(4),                .Y_WIDTH(Y_WIDTH)) fpga_soft_mux      (.A(A[i*a_width0+:a_width0]), .B(B[4-1:0]),                .Y(T[i]));
+          \$__XILINX_SHIFTX  #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(a_width0), .B_WIDTH(4), .Y_WIDTH(Y_WIDTH)) fpga_soft_mux      (.A(A[i*a_width0+:a_width0]), .B(B[4-1:0]), .Y(T[i]));
         else if (i == num_mux16 && a_widthN > 0) begin
           if (a_widthN > 1)
             \$__XILINX_SHIFTX  #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(a_widthN), .B_WIDTH($clog2(a_widthN)), .Y_WIDTH(Y_WIDTH)) fpga_soft_mux_last (.A(A[A_WIDTH-1:i*a_width0]), .B(B[$clog2(a_widthN)-1:0]), .Y(T[i]));
-- 
cgit v1.2.3


From 29aee0989fb3a73388d4567409ad6998373edc99 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Fri, 21 Jun 2019 16:55:59 -0700
Subject: mux_map to no longer copy last value into 1'bx

---
 techlibs/xilinx/mux_map.v | 21 ++-------------------
 1 file changed, 2 insertions(+), 19 deletions(-)

(limited to 'techlibs')

diff --git a/techlibs/xilinx/mux_map.v b/techlibs/xilinx/mux_map.v
index 441c02ac2..0c6b2b78c 100644
--- a/techlibs/xilinx/mux_map.v
+++ b/techlibs/xilinx/mux_map.v
@@ -35,23 +35,6 @@ module \$shiftx (A, B, Y);
   parameter [B_WIDTH-1:0] _TECHMAP_CONSTVAL_B_ = 0;
 
   generate
-    genvar i;
-    wire [A_WIDTH-1:0] A_forward;
-    assign A_backward[A_WIDTH-1] = A[A_WIDTH-1];
-    for (i = A_WIDTH-2; i >= 0; i = i - 1)
-      if (_TECHMAP_CONSTMSK_A_[i] && _TECHMAP_CONSTVAL_A_[i] === 1'bx)
-        assign A_backward[i] = A_backward[i+1];
-      else
-        assign A_backward[i] = A[i];
-
-    wire [A_WIDTH-1:0] A_without_x;
-    assign A_without_x[0] = A_backward[0];
-    for (i = 1; i < A_WIDTH; i = i + 1)
-      if (_TECHMAP_CONSTMSK_A_[i] && _TECHMAP_CONSTVAL_A_[i] === 1'bx)
-        assign A_without_x[i] = A_without_x[i-1];
-      else
-        assign A_without_x[i] = A[i];
-
     if (B_SIGNED) begin
       if (B_WIDTH < 4 || A_WIDTH <= 4)
         wire _TECHMAP_FAIL_ = 1;
@@ -64,7 +47,7 @@ module \$shiftx (A, B, Y);
           .B_WIDTH(B_WIDTH-1'd1),
           .Y_WIDTH(Y_WIDTH)
         ) _TECHMAP_REPLACE_ (
-          .A(A_without_x), .B(B[B_WIDTH-2:0]), .Y(Y)
+          .A(A), .B(B[B_WIDTH-2:0]), .Y(Y)
         );
       else
         wire _TECHMAP_FAIL_ = 1;
@@ -80,7 +63,7 @@ module \$shiftx (A, B, Y);
           .B_WIDTH(B_WIDTH),
           .Y_WIDTH(Y_WIDTH)
         ) _TECHMAP_REPLACE_ (
-          .A(A_without_x), .B(B), .Y(Y)
+          .A(A), .B(B), .Y(Y)
         );
     end
   endgenerate
-- 
cgit v1.2.3


From ed00823b41becc87b52317a82c595c398dd6d10a Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Fri, 21 Jun 2019 16:56:56 -0700
Subject: synth_xilinx to now wreduce except $mux, remove extra peepopt

---
 techlibs/xilinx/synth_xilinx.cc | 9 +--------
 1 file changed, 1 insertion(+), 8 deletions(-)

(limited to 'techlibs')

diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc
index 174138e6a..3d39afcde 100644
--- a/techlibs/xilinx/synth_xilinx.cc
+++ b/techlibs/xilinx/synth_xilinx.cc
@@ -226,8 +226,7 @@ struct SynthXilinxPass : public ScriptPass
 			run("opt_clean");
 			run("check");
 			run("opt");
-			// FIXME
-			//run("wreduce");
+			run("wreduce c:* t:$mux %d");
 			run("peepopt");
 			run("opt_clean");
 			run("alumacc");
@@ -247,11 +246,6 @@ struct SynthXilinxPass : public ScriptPass
 			// Also: wide multiplexer inference benefits from this too
 			if (!(nosrl && nomux) || help_mode)
 				run("pmux2shiftx", "(skip if '-nosrl' and '-nomux')");
-
-			// Run a number of peephole optimisations, including one
-			//   that optimises $mul cells driving $shiftx's B input
-			//   and that aids wide mux analysis
-			run("peepopt");
 		}
 
 		if (check_label("bram", "(skip if '-nobram')")) {
@@ -279,7 +273,6 @@ struct SynthXilinxPass : public ScriptPass
 					      //        otherwise it will use mux8 as mux4
 				run("muxcover -mux4=150 -mux8=200 -mux16=250 -dmux=0", "(skip if -nomux)");
 			}
-			run("wreduce"); // FIXME: Moved until after muxcover from 'coarse'
 			run("opt -full");
 
 			if (!nosrl || help_mode) {
-- 
cgit v1.2.3


From aeee9dcad7f6d5fc30f133a89c5dd6f209283c11 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Fri, 21 Jun 2019 17:06:30 -0700
Subject: Simplify and comment out mux_map.v

---
 techlibs/xilinx/mux_map.v | 17 +++++++++++------
 1 file changed, 11 insertions(+), 6 deletions(-)

(limited to 'techlibs')

diff --git a/techlibs/xilinx/mux_map.v b/techlibs/xilinx/mux_map.v
index 0c6b2b78c..c47da155d 100644
--- a/techlibs/xilinx/mux_map.v
+++ b/techlibs/xilinx/mux_map.v
@@ -18,6 +18,11 @@
  *
  */
 
+// The purpose of these mapping rules is to allow preserve all (sufficiently
+// wide) $shiftx cells during 'techmap' so that they can be mapped to hard
+// resources, rather than being bit-blasted to gates during 'techmap'
+// execution
+
 module \$shiftx (A, B, Y);
   parameter A_SIGNED = 0;
   parameter B_SIGNED = 0;
@@ -29,18 +34,14 @@ module \$shiftx (A, B, Y);
   input [B_WIDTH-1:0] B;
   output [Y_WIDTH-1:0] Y;
 
-  parameter [A_WIDTH-1:0] _TECHMAP_CONSTMSK_A_ = 0;
-  parameter [A_WIDTH-1:0] _TECHMAP_CONSTVAL_A_ = 0;
   parameter [B_WIDTH-1:0] _TECHMAP_CONSTMSK_B_ = 0;
   parameter [B_WIDTH-1:0] _TECHMAP_CONSTVAL_B_ = 0;
 
   generate
     if (B_SIGNED) begin
-      if (B_WIDTH < 4 || A_WIDTH <= 4)
-        wire _TECHMAP_FAIL_ = 1;
-      else if (_TECHMAP_CONSTMSK_B_[B_WIDTH-1] && (_TECHMAP_CONSTVAL_B_[B_WIDTH-1] == 1'b0 || _TECHMAP_CONSTVAL_B_[B_WIDTH-1] === 1'bx))
+      if (_TECHMAP_CONSTMSK_B_[B_WIDTH-1] && (_TECHMAP_CONSTVAL_B_[B_WIDTH-1] == 1'b0 || _TECHMAP_CONSTVAL_B_[B_WIDTH-1] === 1'bx))
         // Optimisation to remove B_SIGNED if sign bit of B is constant-0
-        \$__XILINX_SHIFTX #(
+        \$shiftx #(
           .A_SIGNED(A_SIGNED),
           .B_SIGNED(0),
           .A_WIDTH(A_WIDTH),
@@ -69,6 +70,10 @@ module \$shiftx (A, B, Y);
   endgenerate
 endmodule
 
+// FIXME: This rule exists only because we can't block muxcover
+//        from using MUX4s -- if we disable MUX4 it will use MUX8s
+//        instead
+
 module \$_MUX4_ (A, B, C, D, S, T, Y);
 input A, B, C, D, S, T;
 output Y;
-- 
cgit v1.2.3


From faa2d6fc1c4bc10cda96c2dc3721df209d2d2117 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Fri, 21 Jun 2019 17:12:34 -0700
Subject: Constrain wreduce only if wide mux

---
 techlibs/xilinx/synth_xilinx.cc | 5 ++++-
 1 file changed, 4 insertions(+), 1 deletion(-)

(limited to 'techlibs')

diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc
index 3d39afcde..882ebe439 100644
--- a/techlibs/xilinx/synth_xilinx.cc
+++ b/techlibs/xilinx/synth_xilinx.cc
@@ -226,7 +226,10 @@ struct SynthXilinxPass : public ScriptPass
 			run("opt_clean");
 			run("check");
 			run("opt");
-			run("wreduce c:* t:$mux %d");
+			if (help_mode)
+				run("wreduce [c:* t:$mux %d]", "(no selection if -nomux)");
+			else
+				run("wreduce" + nomux ? "" : " c:* t:$mux %d");
 			run("peepopt");
 			run("opt_clean");
 			run("alumacc");
-- 
cgit v1.2.3


From 39e0e006d5a6b1ae45d95d75895284e3c48f47d7 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Fri, 21 Jun 2019 18:12:07 -0700
Subject: Fix wreduce call (!!!), tweak muxcover costs

---
 techlibs/xilinx/synth_xilinx.cc | 11 ++++++-----
 1 file changed, 6 insertions(+), 5 deletions(-)

(limited to 'techlibs')

diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc
index 882ebe439..9724dff94 100644
--- a/techlibs/xilinx/synth_xilinx.cc
+++ b/techlibs/xilinx/synth_xilinx.cc
@@ -229,7 +229,7 @@ struct SynthXilinxPass : public ScriptPass
 			if (help_mode)
 				run("wreduce [c:* t:$mux %d]", "(no selection if -nomux)");
 			else
-				run("wreduce" + nomux ? "" : " c:* t:$mux %d");
+				run("wreduce" + std::string(nomux ? "" : " c:* t:$mux %d"));
 			run("peepopt");
 			run("opt_clean");
 			run("alumacc");
@@ -271,10 +271,11 @@ struct SynthXilinxPass : public ScriptPass
 			run("dffsr2dff");
 			run("dff2dffe");
 			if (!nomux || help_mode) {
-				run("simplemap t:$mux", "                               (skip if -nomux)");
-				              // FIXME: Must specify mux4, even if we don't need it,
-					      //        otherwise it will use mux8 as mux4
-				run("muxcover -mux4=150 -mux8=200 -mux16=250 -dmux=0", "(skip if -nomux)");
+				run("simplemap t:$mux", "                     (skip if -nomux)");
+				// NB: Cost of mux2 is 100; mux8 should cost between 3 and 4
+				//     of those so that 4:1 muxes and below are implemented
+				//     out of mux2s
+				run("muxcover -mux8=350 -mux16=400 -dmux=0", "(skip if -nomux)");
 			}
 			run("opt -full");
 
-- 
cgit v1.2.3


From bbf3ad90f59a5b548d263c81ca83ca8f93f1c238 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Fri, 21 Jun 2019 18:12:33 -0700
Subject: Remove $_MUX4_ techmap rule

---
 techlibs/xilinx/mux_map.v | 11 -----------
 1 file changed, 11 deletions(-)

(limited to 'techlibs')

diff --git a/techlibs/xilinx/mux_map.v b/techlibs/xilinx/mux_map.v
index c47da155d..e28070359 100644
--- a/techlibs/xilinx/mux_map.v
+++ b/techlibs/xilinx/mux_map.v
@@ -69,14 +69,3 @@ module \$shiftx (A, B, Y);
     end
   endgenerate
 endmodule
-
-// FIXME: This rule exists only because we can't block muxcover
-//        from using MUX4s -- if we disable MUX4 it will use MUX8s
-//        instead
-
-module \$_MUX4_ (A, B, C, D, S, T, Y);
-input A, B, C, D, S, T;
-output Y;
-assign Y = T ? (S ? D : C) :
-               (S ? B : A);
-endmodule
-- 
cgit v1.2.3


From 36e6da53964b406ad379a60fc289aa3af9beb8a9 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Mon, 24 Jun 2019 10:04:01 -0700
Subject: Change synth_xilinx's -nomux to -minmuxf <int>

---
 techlibs/xilinx/cells_map.v     | 66 ++++++++++++++++++++++++---------------
 techlibs/xilinx/mux_map.v       |  2 +-
 techlibs/xilinx/synth_xilinx.cc | 68 ++++++++++++++++++++++++-----------------
 3 files changed, 82 insertions(+), 54 deletions(-)

(limited to 'techlibs')

diff --git a/techlibs/xilinx/cells_map.v b/techlibs/xilinx/cells_map.v
index 18c926336..2eb84ce04 100644
--- a/techlibs/xilinx/cells_map.v
+++ b/techlibs/xilinx/cells_map.v
@@ -155,6 +155,7 @@ module \$__XILINX_SHREG_ (input C, input D, input [31:0] L, input E, output Q, o
   endgenerate
 endmodule
 
+`ifdef MIN_MUX_INPUTS
 module \$__XILINX_SHIFTX (A, B, Y);
   parameter A_SIGNED = 0;
   parameter B_SIGNED = 0;
@@ -207,10 +208,10 @@ module \$__XILINX_SHIFTX (A, B, Y);
       localparam B_WIDTH_new = $clog2(A_WIDTH_new);
       \$__XILINX_SHIFTX  #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(A_WIDTH_new), .B_WIDTH(B_WIDTH_new), .Y_WIDTH(Y_WIDTH)) _TECHMAP_REPLACE_ (.A(A[A_WIDTH_new-1:0]), .B(B[B_WIDTH_new-1:0]), .Y(Y));
     end
-    else if (B_WIDTH < 3 || A_WIDTH <= 4) begin
-      \$shiftx  #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(A_WIDTH), .B_WIDTH(B_WIDTH), .Y_WIDTH(Y_WIDTH)) _TECHMAP_REPLACE_ (.A(A), .B(B), .Y(Y));
+    else if (A_WIDTH < `MIN_MUX_INPUTS) begin
+      wire _TECHMAP_FAIL_ = 1;
     end
-    else if (B_WIDTH == 3) begin
+    else if (A_WIDTH <= 2 ** 3) begin
       localparam a_width0 = 2 ** 2;
       localparam a_widthN = A_WIDTH - a_width0;
       wire T0, T1;
@@ -219,47 +220,61 @@ module \$__XILINX_SHIFTX (A, B, Y);
         \$shiftx  #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(a_widthN), .B_WIDTH($clog2(a_widthN)), .Y_WIDTH(Y_WIDTH)) fpga_soft_mux_last (.A(A[A_WIDTH-1:a_width0]), .B(B[$clog2(a_widthN)-1:0]), .Y(T1));
       else
         assign T1 = A[A_WIDTH-1];
-      MUXF7 fpga_hard_mux (.I0(T0), .I1(T1), .S(B[B_WIDTH-1]), .O(Y));
+      MUXF7 fpga_hard_mux (.I0(T0), .I1(T1), .S(B[2]), .O(Y));
     end
-    else if (B_WIDTH == 4) begin
+    else if (A_WIDTH <= 2 ** 4) begin
       localparam a_width0 = 2 ** 2;
       localparam num_mux8 = A_WIDTH / a_width0;
       localparam a_widthN = A_WIDTH - num_mux8*a_width0;
       wire [4-1:0] T;
-      for (i = 0; i < 4; i++)
+      for (i = 0; i < num_mux8; i++)
         if (i < num_mux8)
-          \$shiftx  #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(a_width0), .B_WIDTH(2), .Y_WIDTH(Y_WIDTH)) fpga_soft_mux (.A(A[i*a_width0+:a_width0]), .B(B[2-1:0]), .Y(T[i]));
-        else if (i == num_mux8 && a_widthN > 0) begin
-          if (a_widthN > 1)
-            \$shiftx  #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(a_widthN), .B_WIDTH($clog2(a_widthN)), .Y_WIDTH(Y_WIDTH)) fpga_soft_mux_last (.A(A[A_WIDTH-1:i*a_width0]), .B(B[$clog2(a_widthN)-1:0]), .Y(T[i]));
-          else
-            assign T[i] = A[A_WIDTH-1];
-        end
+          \$shiftx  #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(a_width0), .B_WIDTH(2), .Y_WIDTH(Y_WIDTH)) fpga_mux (.A(A[i*a_width0+:a_width0]), .B(B[2-1:0]), .Y(T[i]));
+      if (a_widthN > 0) begin
+        if (a_widthN > 1)
+          \$shiftx  #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(a_widthN), .B_WIDTH($clog2(a_widthN)), .Y_WIDTH(Y_WIDTH)) fpga_mux_last (.A(A[A_WIDTH-1:num_mux8*a_width0]), .B(B[$clog2(a_widthN)-1:0]), .Y(T[num_mux8]));
         else
-          assign T[i] = 1'bx;
+          assign T[num_mux8] = A[A_WIDTH-1];
+      end
+      else
+        assign T[num_mux8] = 1'bx;
       \$__XILINX_MUXF78 fpga_hard_mux (.I0(T[0]), .I1(T[1]), .I2(T[2]), .I3(T[3]), .S0(B[2]), .S1(B[3]), .O(Y));
     end
     else begin
       localparam a_width0 = 2 ** 4;
       localparam num_mux16 = A_WIDTH / a_width0;
       localparam a_widthN = A_WIDTH - num_mux16*a_width0;
-      wire [(2**(B_WIDTH-4))-1:0] T;
-      for (i = 0; i < 2 ** (B_WIDTH-4); i++)
-        if (i < num_mux16)
-          \$__XILINX_SHIFTX  #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(a_width0), .B_WIDTH(4), .Y_WIDTH(Y_WIDTH)) fpga_soft_mux      (.A(A[i*a_width0+:a_width0]), .B(B[4-1:0]), .Y(T[i]));
-        else if (i == num_mux16 && a_widthN > 0) begin
-          if (a_widthN > 1)
-            \$__XILINX_SHIFTX  #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(a_widthN), .B_WIDTH($clog2(a_widthN)), .Y_WIDTH(Y_WIDTH)) fpga_soft_mux_last (.A(A[A_WIDTH-1:i*a_width0]), .B(B[$clog2(a_widthN)-1:0]), .Y(T[i]));
-          else
-            assign T[i] = A[A_WIDTH-1];
-        end
+      wire [num_mux16-1:0] T;
+      for (i = 0; i < num_mux16; i++)
+        \$__XILINX_SHIFTX  #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(a_width0), .B_WIDTH(4), .Y_WIDTH(Y_WIDTH)) fpga_soft_mux (.A(A[i*a_width0+:a_width0]), .B(B[4-1:0]), .Y(T[i]));
+      if (a_widthN > 0) begin
+        if (a_widthN > 1)
+          \$__XILINX_SHIFTX  #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(a_widthN), .B_WIDTH($clog2(a_widthN)), .Y_WIDTH(Y_WIDTH)) fpga_soft_mux_last (.A(A[A_WIDTH-1:num_mux16*a_width0]), .B(B[$clog2(a_widthN)-1:0]), .Y(T[num_mux16]));
         else
-          assign T[i] = 1'bx;
+          assign T[num_mux16] = A[A_WIDTH-1];
+      end
+      else
+        assign T[num_mux16] = 1'bx;
       \$__XILINX_SHIFTX  #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(2**(B_WIDTH-4)), .B_WIDTH(B_WIDTH-4), .Y_WIDTH(Y_WIDTH)) _TECHMAP_REPLACE_ (.A(T), .B(B[B_WIDTH-1:4]), .Y(Y));
     end
   endgenerate
 endmodule
 
+(* techmap_celltype = "$__XILINX_SHIFTX" *)
+module _90__XILINX_SHIFTX (A, B, Y);
+  parameter A_SIGNED = 0;
+  parameter B_SIGNED = 0;
+  parameter A_WIDTH = 1;
+  parameter B_WIDTH = 1;
+  parameter Y_WIDTH = 1;
+
+  input [A_WIDTH-1:0] A;
+  input [B_WIDTH-1:0] B;
+  output [Y_WIDTH-1:0] Y;
+
+  \$shiftx  #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(A_WIDTH), .B_WIDTH(B_WIDTH), .Y_WIDTH(Y_WIDTH)) _TECHMAP_REPLACE_ (.A(A), .B(B), .Y(Y));
+endmodule
+
 module \$_MUX8_ (A, B, C, D, E, F, G, H, S, T, U, Y);
 input A, B, C, D, E, F, G, H, S, T, U;
 output Y;
@@ -271,6 +286,7 @@ input A, B, C, D, E, F, G, H, I, J, K, L, M, N, O, P, S, T, U, V;
 output Y;
   \$__XILINX_SHIFTX  #(.A_SIGNED(0), .B_SIGNED(0), .A_WIDTH(16), .B_WIDTH(4), .Y_WIDTH(1)) _TECHMAP_REPLACE_ (.A({P,O,N,M,L,K,J,I,H,G,F,E,D,C,B,A}), .B({V,U,T,S}), .Y(Y));
 endmodule
+`endif
 
 `ifndef _ABC
 module \$__XILINX_MUXF78 (O, I0, I1, I2, I3, S0, S1);
diff --git a/techlibs/xilinx/mux_map.v b/techlibs/xilinx/mux_map.v
index e28070359..91aaf2118 100644
--- a/techlibs/xilinx/mux_map.v
+++ b/techlibs/xilinx/mux_map.v
@@ -54,7 +54,7 @@ module \$shiftx (A, B, Y);
         wire _TECHMAP_FAIL_ = 1;
     end
     else begin
-      if (B_WIDTH < 3 || A_WIDTH <= 4)
+      if (((A_WIDTH + Y_WIDTH - 1) / Y_WIDTH) < `MIN_MUX_INPUTS)
         wire _TECHMAP_FAIL_ = 1;
       else
         \$__XILINX_SHIFTX #(
diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc
index 9724dff94..2cf28fce1 100644
--- a/techlibs/xilinx/synth_xilinx.cc
+++ b/techlibs/xilinx/synth_xilinx.cc
@@ -73,8 +73,10 @@ struct SynthXilinxPass : public ScriptPass
 		log("    -nosrl\n");
 		log("        disable inference of shift registers\n");
 		log("\n");
-		log("    -nomux\n");
-		log("        disable inference of wide multiplexers\n");
+		log("    -minmuxf <int>\n");
+		log("        enable inference of hard multiplexer resources (MuxFx) for muxes at or\n");
+		log("        above this number of inputs (minimum value 5).\n");
+		log("        default: 0 (no inference)\n");
 		log("\n");
 		log("    -run <from_label>:<to_label>\n");
 		log("        only run the commands between the labels (see below). an empty\n");
@@ -97,7 +99,8 @@ struct SynthXilinxPass : public ScriptPass
 	}
 
 	std::string top_opt, edif_file, blif_file, abc, arch;
-	bool flatten, retime, vpr, nocarry, nobram, nodram, nosrl, nomux;
+	bool flatten, retime, vpr, nocarry, nobram, nodram, nosrl;
+	int minmuxf;
 
 	void clear_flags() YS_OVERRIDE
 	{
@@ -112,8 +115,8 @@ struct SynthXilinxPass : public ScriptPass
 		nobram = false;
 		nodram = false;
 		nosrl = false;
-		nomux = false;
 		arch = "xc7";
+		minmuxf = 0;
 	}
 
 	void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
@@ -176,8 +179,8 @@ struct SynthXilinxPass : public ScriptPass
 				nosrl = true;
 				continue;
 			}
-			if (args[argidx] == "-nomux") {
-				nomux = true;
+			if (args[argidx] == "-minmuxf" && argidx+1 < args.size()) {
+				minmuxf = atoi(args[++argidx].c_str());
 				continue;
 			}
 			if (args[argidx] == "-abc9") {
@@ -191,6 +194,9 @@ struct SynthXilinxPass : public ScriptPass
 		if (arch != "xcup" && arch != "xcu" && arch != "xc7" && arch != "xc6s")
 			log_cmd_error("Invalid Xilinx -arch setting: %s\n", arch.c_str());
 
+		if (minmuxf != 0 && minmuxf < 5)
+			log_cmd_error("-minmuxf value must be 0 or >= 5.\n");
+
 		if (!design->full_selection())
 			log_cmd_error("This command only operates on fully selected designs!\n");
 
@@ -227,9 +233,9 @@ struct SynthXilinxPass : public ScriptPass
 			run("check");
 			run("opt");
 			if (help_mode)
-				run("wreduce [c:* t:$mux %d]", "(no selection if -nomux)");
+				run("wreduce [c:* t:$mux %d]", "(selection for '-minmuxf' only)");
 			else
-				run("wreduce" + std::string(nomux ? "" : " c:* t:$mux %d"));
+				run("wreduce" + std::string(minmuxf > 0 ? " c:* t:$mux %d" : ""));
 			run("peepopt");
 			run("opt_clean");
 			run("alumacc");
@@ -240,15 +246,15 @@ struct SynthXilinxPass : public ScriptPass
 			run("memory -nomap");
 			run("opt_clean");
 
-			if (!nomux || help_mode)
-				run("muxpack", "    (skip if '-nomux')");
+			if (minmuxf > 0 || help_mode)
+				run("muxpack", "    ('-minmuxf' only)");
 
 			// shregmap -tech xilinx can cope with $shiftx and $mux
 			//   cells for identifying variable-length shift registers,
 			//   so attempt to convert $pmux-es to the former
 			// Also: wide multiplexer inference benefits from this too
-			if (!(nosrl && nomux) || help_mode)
-				run("pmux2shiftx", "(skip if '-nosrl' and '-nomux')");
+			if (!(nosrl && minmuxf == 0) || help_mode)
+				run("pmux2shiftx", "(skip if '-nosrl' and '-minmuxf' < 5)");
 		}
 
 		if (check_label("bram", "(skip if '-nobram')")) {
@@ -270,12 +276,15 @@ struct SynthXilinxPass : public ScriptPass
 			run("memory_map");
 			run("dffsr2dff");
 			run("dff2dffe");
-			if (!nomux || help_mode) {
-				run("simplemap t:$mux", "                     (skip if -nomux)");
-				// NB: Cost of mux2 is 100; mux8 should cost between 3 and 4
-				//     of those so that 4:1 muxes and below are implemented
-				//     out of mux2s
-				run("muxcover -mux8=350 -mux16=400 -dmux=0", "(skip if -nomux)");
+			if (minmuxf > 0 || help_mode) {
+				run("simplemap t:$mux", "                        ('-minmuxf' only)");
+				if (minmuxf > 0 || help_mode) {
+					// NB: Cost of mux2 is 100; mux8 should cost between 3 and 4
+					//     of those so that 4:1 muxes and below are implemented
+					//     out of mux2s
+					std::string muxcover_args = " -dmux=0 -mux8=350 -mux16=400";
+					run("muxcover " + muxcover_args, "('-minmuxf' only)");
+				}
 			}
 			run("opt -full");
 
@@ -287,26 +296,29 @@ struct SynthXilinxPass : public ScriptPass
 				run("shregmap -tech xilinx -minlen 3", "(skip if '-nosrl')");
 			}
 
-			std::string techmap_files = " -map +/techmap.v";
+			std::string techmap_args = " -map +/techmap.v";
 			if (help_mode)
-				techmap_files += " [-map +/xilinx/mux_map.v]";
-			else if (!nomux)
-				techmap_files += " -map +/xilinx/mux_map.v";
+				techmap_args += " [-map +/xilinx/mux_map.v]";
+			else if (minmuxf > 0)
+				techmap_args += stringf(" -D MIN_MUX_INPUTS=%d -map +/xilinx/mux_map.v", minmuxf);
 			if (help_mode)
-				techmap_files += " [-map +/xilinx/arith_map.v]";
+				techmap_args += " [-map +/xilinx/arith_map.v]";
 			else if (!nocarry) {
-				techmap_files += " -map +/xilinx/arith_map.v";
+				techmap_args += " -map +/xilinx/arith_map.v";
 				if (vpr)
-					techmap_files += " -D _EXPLICIT_CARRY";
+					techmap_args += " -D _EXPLICIT_CARRY";
 				else if (abc == "abc9")
-					techmap_files += " -D _CLB_CARRY";
+					techmap_args += " -D _CLB_CARRY";
 			}
-			run("techmap " + techmap_files);
+			run("techmap " + techmap_args);
 			run("opt -fast");
 		}
 
 		if (check_label("map_cells")) {
-			run("techmap -map +/techmap.v -D _ABC -map +/xilinx/cells_map.v");
+			std::string techmap_args = "-map +/techmap.v -D _ABC -map +/xilinx/cells_map.v";
+			if (minmuxf > 0)
+				techmap_args += stringf(" -D MIN_MUX_INPUTS=%d", minmuxf);
+			run("techmap " + techmap_args);
 			run("clean");
 		}
 
-- 
cgit v1.2.3


From aa1eeda567d09e2d2ffd40cd008d0166d2910273 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Mon, 24 Jun 2019 11:51:55 -0700
Subject: Modify costs for muxcover

---
 techlibs/xilinx/synth_xilinx.cc | 16 +++++++++++++++-
 1 file changed, 15 insertions(+), 1 deletion(-)

(limited to 'techlibs')

diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc
index 2cf28fce1..a84f54e99 100644
--- a/techlibs/xilinx/synth_xilinx.cc
+++ b/techlibs/xilinx/synth_xilinx.cc
@@ -282,7 +282,21 @@ struct SynthXilinxPass : public ScriptPass
 					// NB: Cost of mux2 is 100; mux8 should cost between 3 and 4
 					//     of those so that 4:1 muxes and below are implemented
 					//     out of mux2s
-					std::string muxcover_args = " -dmux=0 -mux8=350 -mux16=400";
+					std::string muxcover_args = " -dmux=0";
+					switch (minmuxf) {
+						case  5: muxcover_args += " -mux8=350 -mux16=400"; break;
+						case  6: muxcover_args += " -mux8=450 -mux16=500"; break;
+						case  7: muxcover_args += " -mux8=550 -mux16=600"; break;
+						case  8: muxcover_args += " -mux8=650 -mux16=700"; break;
+						case  9: muxcover_args += " -mux16=750"; break;
+						case 10: muxcover_args += " -mux16=850"; break;
+						case 11: muxcover_args += " -mux16=950"; break;
+						case 12: muxcover_args += " -mux16=1050"; break;
+						case 13: muxcover_args += " -mux16=1150"; break;
+						case 14: muxcover_args += " -mux16=1250"; break;
+						case 15: muxcover_args += " -mux16=1350"; break;
+						default: muxcover_args += " -mux16=1450"; break;
+					}
 					run("muxcover " + muxcover_args, "('-minmuxf' only)");
 				}
 			}
-- 
cgit v1.2.3


From 2b4501503d05beaecc0f995d0681ff43e2c6fba4 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Mon, 24 Jun 2019 12:18:17 -0700
Subject: Fix mux techmapping

---
 techlibs/xilinx/cells_map.v | 39 ++++++++++++++++++++-------------------
 1 file changed, 20 insertions(+), 19 deletions(-)

(limited to 'techlibs')

diff --git a/techlibs/xilinx/cells_map.v b/techlibs/xilinx/cells_map.v
index 2eb84ce04..85f174d3d 100644
--- a/techlibs/xilinx/cells_map.v
+++ b/techlibs/xilinx/cells_map.v
@@ -226,35 +226,36 @@ module \$__XILINX_SHIFTX (A, B, Y);
       localparam a_width0 = 2 ** 2;
       localparam num_mux8 = A_WIDTH / a_width0;
       localparam a_widthN = A_WIDTH - num_mux8*a_width0;
-      wire [4-1:0] T;
-      for (i = 0; i < num_mux8; i++)
+      wire [a_width0-1:0] T;
+      for (i = 0; i < a_width0; i++)
         if (i < num_mux8)
           \$shiftx  #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(a_width0), .B_WIDTH(2), .Y_WIDTH(Y_WIDTH)) fpga_mux (.A(A[i*a_width0+:a_width0]), .B(B[2-1:0]), .Y(T[i]));
-      if (a_widthN > 0) begin
-        if (a_widthN > 1)
-          \$shiftx  #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(a_widthN), .B_WIDTH($clog2(a_widthN)), .Y_WIDTH(Y_WIDTH)) fpga_mux_last (.A(A[A_WIDTH-1:num_mux8*a_width0]), .B(B[$clog2(a_widthN)-1:0]), .Y(T[num_mux8]));
+        else if (i == num_mux8 && a_widthN > 0) begin
+          if (a_widthN > 1)
+            \$shiftx  #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(a_widthN), .B_WIDTH($clog2(a_widthN)), .Y_WIDTH(Y_WIDTH)) fpga_mux_last (.A(A[A_WIDTH-1-:a_widthN]), .B(B[$clog2(a_widthN)-1:0]), .Y(T[i]));
+          else
+            assign T[i] = A[A_WIDTH-1];
+        end
         else
-          assign T[num_mux8] = A[A_WIDTH-1];
-      end
-      else
-        assign T[num_mux8] = 1'bx;
+          assign T[i] = 1'bx;
       \$__XILINX_MUXF78 fpga_hard_mux (.I0(T[0]), .I1(T[1]), .I2(T[2]), .I3(T[3]), .S0(B[2]), .S1(B[3]), .O(Y));
     end
     else begin
       localparam a_width0 = 2 ** 4;
       localparam num_mux16 = A_WIDTH / a_width0;
       localparam a_widthN = A_WIDTH - num_mux16*a_width0;
-      wire [num_mux16-1:0] T;
-      for (i = 0; i < num_mux16; i++)
-        \$__XILINX_SHIFTX  #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(a_width0), .B_WIDTH(4), .Y_WIDTH(Y_WIDTH)) fpga_soft_mux (.A(A[i*a_width0+:a_width0]), .B(B[4-1:0]), .Y(T[i]));
-      if (a_widthN > 0) begin
-        if (a_widthN > 1)
-          \$__XILINX_SHIFTX  #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(a_widthN), .B_WIDTH($clog2(a_widthN)), .Y_WIDTH(Y_WIDTH)) fpga_soft_mux_last (.A(A[A_WIDTH-1:num_mux16*a_width0]), .B(B[$clog2(a_widthN)-1:0]), .Y(T[num_mux16]));
+      wire [a_width0-1:0] T;
+      for (i = 0; i < a_width0; i++)
+        if (i < num_mux16)
+          \$__XILINX_SHIFTX  #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(a_width0), .B_WIDTH(4), .Y_WIDTH(Y_WIDTH)) fpga_soft_mux (.A(A[i*a_width0+:a_width0]), .B(B[4-1:0]), .Y(T[i]));
+        else if (i == num_mux16 && a_widthN > 0) begin
+          if (a_widthN > 1)
+            \$__XILINX_SHIFTX  #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(a_widthN), .B_WIDTH($clog2(a_widthN)), .Y_WIDTH(Y_WIDTH)) fpga_soft_mux_last (.A(A[A_WIDTH-1-:a_widthN]), .B(B[$clog2(a_widthN)-1:0]), .Y(T[i]));
+          else
+            assign T[i] = A[A_WIDTH-1];
+        end
         else
-          assign T[num_mux16] = A[A_WIDTH-1];
-      end
-      else
-        assign T[num_mux16] = 1'bx;
+          assign T[i] = 1'bx;
       \$__XILINX_SHIFTX  #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(2**(B_WIDTH-4)), .B_WIDTH(B_WIDTH-4), .Y_WIDTH(Y_WIDTH)) _TECHMAP_REPLACE_ (.A(T), .B(B[B_WIDTH-1:4]), .Y(Y));
     end
   endgenerate
-- 
cgit v1.2.3


From 0aae3b4f4361db6d2c6b9c8d69df041f40519cec Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Mon, 24 Jun 2019 12:50:48 -0700
Subject: Fix techmapping muxes some more

---
 techlibs/xilinx/cells_map.v | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

(limited to 'techlibs')

diff --git a/techlibs/xilinx/cells_map.v b/techlibs/xilinx/cells_map.v
index 85f174d3d..f4b7888b0 100644
--- a/techlibs/xilinx/cells_map.v
+++ b/techlibs/xilinx/cells_map.v
@@ -225,7 +225,7 @@ module \$__XILINX_SHIFTX (A, B, Y);
     else if (A_WIDTH <= 2 ** 4) begin
       localparam a_width0 = 2 ** 2;
       localparam num_mux8 = A_WIDTH / a_width0;
-      localparam a_widthN = A_WIDTH - num_mux8*a_width0;
+      localparam a_widthN = A_WIDTH % a_width0;
       wire [a_width0-1:0] T;
       for (i = 0; i < a_width0; i++)
         if (i < num_mux8)
@@ -243,9 +243,9 @@ module \$__XILINX_SHIFTX (A, B, Y);
     else begin
       localparam a_width0 = 2 ** 4;
       localparam num_mux16 = A_WIDTH / a_width0;
-      localparam a_widthN = A_WIDTH - num_mux16*a_width0;
-      wire [a_width0-1:0] T;
-      for (i = 0; i < a_width0; i++)
+      localparam a_widthN = A_WIDTH % a_width0;
+      wire [(2**(B_WIDTH-4))-1:0] T;
+      for (i = 0; i < 2 ** (B_WIDTH-4); i++)
         if (i < num_mux16)
           \$__XILINX_SHIFTX  #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(a_width0), .B_WIDTH(4), .Y_WIDTH(Y_WIDTH)) fpga_soft_mux (.A(A[i*a_width0+:a_width0]), .B(B[4-1:0]), .Y(T[i]));
         else if (i == num_mux16 && a_widthN > 0) begin
-- 
cgit v1.2.3


From 7fbfcf20d16751f4c1eab0c33848c5c05b970992 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Mon, 24 Jun 2019 14:15:00 -0700
Subject: Move comment

---
 techlibs/xilinx/synth_xilinx.cc | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

(limited to 'techlibs')

diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc
index a84f54e99..69b1580b8 100644
--- a/techlibs/xilinx/synth_xilinx.cc
+++ b/techlibs/xilinx/synth_xilinx.cc
@@ -279,11 +279,11 @@ struct SynthXilinxPass : public ScriptPass
 			if (minmuxf > 0 || help_mode) {
 				run("simplemap t:$mux", "                        ('-minmuxf' only)");
 				if (minmuxf > 0 || help_mode) {
-					// NB: Cost of mux2 is 100; mux8 should cost between 3 and 4
-					//     of those so that 4:1 muxes and below are implemented
-					//     out of mux2s
 					std::string muxcover_args = " -dmux=0";
 					switch (minmuxf) {
+						// NB: Cost of mux2 is 100; mux8 should cost between 3 and 4
+						//     of those so that 4:1 muxes and below are implemented
+						//     out of mux2s
 						case  5: muxcover_args += " -mux8=350 -mux16=400"; break;
 						case  6: muxcover_args += " -mux8=450 -mux16=500"; break;
 						case  7: muxcover_args += " -mux8=550 -mux16=600"; break;
-- 
cgit v1.2.3


From 2e7992efffa1d75cf69c8942d03b53e1b6ec2895 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Mon, 24 Jun 2019 14:15:31 -0700
Subject: Revert "Fix techmapping muxes some more"

This reverts commit 0aae3b4f4361db6d2c6b9c8d69df041f40519cec.
---
 techlibs/xilinx/cells_map.v | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

(limited to 'techlibs')

diff --git a/techlibs/xilinx/cells_map.v b/techlibs/xilinx/cells_map.v
index f4b7888b0..85f174d3d 100644
--- a/techlibs/xilinx/cells_map.v
+++ b/techlibs/xilinx/cells_map.v
@@ -225,7 +225,7 @@ module \$__XILINX_SHIFTX (A, B, Y);
     else if (A_WIDTH <= 2 ** 4) begin
       localparam a_width0 = 2 ** 2;
       localparam num_mux8 = A_WIDTH / a_width0;
-      localparam a_widthN = A_WIDTH % a_width0;
+      localparam a_widthN = A_WIDTH - num_mux8*a_width0;
       wire [a_width0-1:0] T;
       for (i = 0; i < a_width0; i++)
         if (i < num_mux8)
@@ -243,9 +243,9 @@ module \$__XILINX_SHIFTX (A, B, Y);
     else begin
       localparam a_width0 = 2 ** 4;
       localparam num_mux16 = A_WIDTH / a_width0;
-      localparam a_widthN = A_WIDTH % a_width0;
-      wire [(2**(B_WIDTH-4))-1:0] T;
-      for (i = 0; i < 2 ** (B_WIDTH-4); i++)
+      localparam a_widthN = A_WIDTH - num_mux16*a_width0;
+      wire [a_width0-1:0] T;
+      for (i = 0; i < a_width0; i++)
         if (i < num_mux16)
           \$__XILINX_SHIFTX  #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(a_width0), .B_WIDTH(4), .Y_WIDTH(Y_WIDTH)) fpga_soft_mux (.A(A[i*a_width0+:a_width0]), .B(B[4-1:0]), .Y(T[i]));
         else if (i == num_mux16 && a_widthN > 0) begin
-- 
cgit v1.2.3


From db6a0b72b24022eacc84dba8b117dfb193b8d4c1 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Mon, 24 Jun 2019 14:28:56 -0700
Subject: Reduce number of decomposed muxes during techmap

---
 techlibs/xilinx/cells_map.v | 25 +++++++++++--------------
 1 file changed, 11 insertions(+), 14 deletions(-)

(limited to 'techlibs')

diff --git a/techlibs/xilinx/cells_map.v b/techlibs/xilinx/cells_map.v
index 85f174d3d..6d9860b95 100644
--- a/techlibs/xilinx/cells_map.v
+++ b/techlibs/xilinx/cells_map.v
@@ -225,7 +225,7 @@ module \$__XILINX_SHIFTX (A, B, Y);
     else if (A_WIDTH <= 2 ** 4) begin
       localparam a_width0 = 2 ** 2;
       localparam num_mux8 = A_WIDTH / a_width0;
-      localparam a_widthN = A_WIDTH - num_mux8*a_width0;
+      localparam a_widthN = A_WIDTH % a_width0;
       wire [a_width0-1:0] T;
       for (i = 0; i < a_width0; i++)
         if (i < num_mux8)
@@ -243,20 +243,17 @@ module \$__XILINX_SHIFTX (A, B, Y);
     else begin
       localparam a_width0 = 2 ** 4;
       localparam num_mux16 = A_WIDTH / a_width0;
-      localparam a_widthN = A_WIDTH - num_mux16*a_width0;
-      wire [a_width0-1:0] T;
-      for (i = 0; i < a_width0; i++)
-        if (i < num_mux16)
-          \$__XILINX_SHIFTX  #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(a_width0), .B_WIDTH(4), .Y_WIDTH(Y_WIDTH)) fpga_soft_mux (.A(A[i*a_width0+:a_width0]), .B(B[4-1:0]), .Y(T[i]));
-        else if (i == num_mux16 && a_widthN > 0) begin
-          if (a_widthN > 1)
-            \$__XILINX_SHIFTX  #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(a_widthN), .B_WIDTH($clog2(a_widthN)), .Y_WIDTH(Y_WIDTH)) fpga_soft_mux_last (.A(A[A_WIDTH-1-:a_widthN]), .B(B[$clog2(a_widthN)-1:0]), .Y(T[i]));
-          else
-            assign T[i] = A[A_WIDTH-1];
-        end
+      localparam a_widthN = A_WIDTH % a_width0;
+      wire [num_mux16 + (a_widthN > 0 ? 1 : 0) - 1:0] T;
+      for (i = 0; i < num_mux16; i++)
+        \$__XILINX_SHIFTX  #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(a_width0), .B_WIDTH(4), .Y_WIDTH(Y_WIDTH)) fpga_soft_mux (.A(A[i*a_width0+:a_width0]), .B(B[4-1:0]), .Y(T[i]));
+      if (a_widthN > 0) begin
+        if (a_widthN > 1)
+          \$__XILINX_SHIFTX  #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(a_widthN), .B_WIDTH($clog2(a_widthN)), .Y_WIDTH(Y_WIDTH)) fpga_soft_mux_last (.A(A[A_WIDTH-1-:a_widthN]), .B(B[$clog2(a_widthN)-1:0]), .Y(T[num_mux16]));
         else
-          assign T[i] = 1'bx;
-      \$__XILINX_SHIFTX  #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(2**(B_WIDTH-4)), .B_WIDTH(B_WIDTH-4), .Y_WIDTH(Y_WIDTH)) _TECHMAP_REPLACE_ (.A(T), .B(B[B_WIDTH-1:4]), .Y(Y));
+          assign T[num_mux16] = A[A_WIDTH-1];
+      end
+      \$__XILINX_SHIFTX  #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(num_mux16 + (a_widthN > 0 ? 1 : 0)), .B_WIDTH(B_WIDTH-4), .Y_WIDTH(Y_WIDTH)) _TECHMAP_REPLACE_ (.A(T), .B(B[B_WIDTH-1:4]), .Y(Y));
     end
   endgenerate
 endmodule
-- 
cgit v1.2.3


From c3df895bf464fd651c4d634ecb58ba78ca572f5f Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Mon, 24 Jun 2019 15:16:44 -0700
Subject: Reduce MuxFx resources in mux techmapping

---
 techlibs/xilinx/cells_map.v | 40 ++++++++++++++++++++++++++++++----------
 1 file changed, 30 insertions(+), 10 deletions(-)

(limited to 'techlibs')

diff --git a/techlibs/xilinx/cells_map.v b/techlibs/xilinx/cells_map.v
index 6d9860b95..bc0455b0c 100644
--- a/techlibs/xilinx/cells_map.v
+++ b/techlibs/xilinx/cells_map.v
@@ -230,14 +230,10 @@ module \$__XILINX_SHIFTX (A, B, Y);
       for (i = 0; i < a_width0; i++)
         if (i < num_mux8)
           \$shiftx  #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(a_width0), .B_WIDTH(2), .Y_WIDTH(Y_WIDTH)) fpga_mux (.A(A[i*a_width0+:a_width0]), .B(B[2-1:0]), .Y(T[i]));
-        else if (i == num_mux8 && a_widthN > 0) begin
-          if (a_widthN > 1)
-            \$shiftx  #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(a_widthN), .B_WIDTH($clog2(a_widthN)), .Y_WIDTH(Y_WIDTH)) fpga_mux_last (.A(A[A_WIDTH-1-:a_widthN]), .B(B[$clog2(a_widthN)-1:0]), .Y(T[i]));
-          else
-            assign T[i] = A[A_WIDTH-1];
-        end
+        else if (i == num_mux8 && a_widthN > 1)
+          \$shiftx  #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(a_widthN), .B_WIDTH($clog2(a_widthN)), .Y_WIDTH(Y_WIDTH)) fpga_mux_last (.A(A[A_WIDTH-1-:a_widthN]), .B(B[$clog2(a_widthN)-1:0]), .Y(T[i]));
         else
-          assign T[i] = 1'bx;
+          assign T[i] = A[A_WIDTH-1];
       \$__XILINX_MUXF78 fpga_hard_mux (.I0(T[0]), .I1(T[1]), .I2(T[2]), .I3(T[3]), .S0(B[2]), .S1(B[3]), .O(Y));
     end
     else begin
@@ -291,8 +287,32 @@ module \$__XILINX_MUXF78 (O, I0, I1, I2, I3, S0, S1);
   output O;
   input I0, I1, I2, I3, S0, S1;
   wire T0, T1;
-  MUXF7 mux7a (.I0(I0), .I1(I1), .S(S0), .O(T0));
-  MUXF7 mux7b (.I0(I2), .I1(I3), .S(S0), .O(T1));
-  MUXF8 mux8 (.I0(T0), .I1(T1), .S(S1), .O(O));
+  parameter _TECHMAP_BITS_CONNMAP_ = 0;
+  parameter [_TECHMAP_BITS_CONNMAP_-1:0] _TECHMAP_CONNMAP_I0_ = 0;
+  parameter [_TECHMAP_BITS_CONNMAP_-1:0] _TECHMAP_CONNMAP_I1_ = 0;
+  parameter [_TECHMAP_BITS_CONNMAP_-1:0] _TECHMAP_CONNMAP_I2_ = 0;
+  parameter [_TECHMAP_BITS_CONNMAP_-1:0] _TECHMAP_CONNMAP_I3_ = 0;
+  parameter _TECHMAP_CONSTMSK_S0_ = 0;
+  parameter _TECHMAP_CONSTVAL_S0_ = 0;
+  parameter _TECHMAP_CONSTMSK_S1_ = 0;
+  parameter _TECHMAP_CONSTVAL_S1_ = 0;
+  if (_TECHMAP_CONSTMSK_S0_ && _TECHMAP_CONSTVAL_S0_ === 1'b1)
+    assign T0 = I1;
+  else if (_TECHMAP_CONSTMSK_S0_ || _TECHMAP_CONNMAP_I0_ === _TECHMAP_CONNMAP_I1_)
+    assign T0 = I0;
+  else
+    MUXF7 mux7a (.I0(I0), .I1(I1), .S(S0), .O(T0));
+  if (_TECHMAP_CONSTMSK_S0_ && _TECHMAP_CONSTVAL_S0_ === 1'b1)
+    assign T1 = I3;
+  else if (_TECHMAP_CONSTMSK_S0_ || _TECHMAP_CONNMAP_I2_ === _TECHMAP_CONNMAP_I3_)
+    assign T1 = I2;
+  else
+    MUXF7 mux7b (.I0(I2), .I1(I3), .S(S0), .O(T1));
+  if (_TECHMAP_CONSTMSK_S1_ && _TECHMAP_CONSTVAL_S1_ === 1'b1)
+    assign O = T1;
+  else if (_TECHMAP_CONSTMSK_S1_ || (_TECHMAP_CONNMAP_I0_ === _TECHMAP_CONNMAP_I1_ && _TECHMAP_CONNMAP_I1_ === _TECHMAP_CONNMAP_I2_ && _TECHMAP_CONNMAP_I2_ === _TECHMAP_CONNMAP_I3_))
+    assign O = T0;
+  else
+    MUXF8 mux8 (.I0(T0), .I1(T1), .S(S1), .O(O));
 endmodule
 `endif
-- 
cgit v1.2.3


From e1ba25d79f0fc623006b250e72093199d0804d52 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Mon, 24 Jun 2019 22:54:35 -0700
Subject: Add RAM32X1D box info

---
 techlibs/xilinx/abc_xc7.box | 11 +++++++++--
 techlibs/xilinx/cells_sim.v |  5 +++--
 2 files changed, 12 insertions(+), 4 deletions(-)

(limited to 'techlibs')

diff --git a/techlibs/xilinx/abc_xc7.box b/techlibs/xilinx/abc_xc7.box
index dafef9fef..39c535303 100644
--- a/techlibs/xilinx/abc_xc7.box
+++ b/techlibs/xilinx/abc_xc7.box
@@ -35,16 +35,23 @@ CARRY4 3 1 10 8
 592 540 520 356 -   512 548 292 -   228
 580 526 507 398 385 508 528 378 380 114
 
+# SLICEM/A6LUT
+# Inputs: A0 A1 A2 A3 A4 D DPRA0 DPRA1 DPRA2 DPRA3 DPRA4 WCLK WE
+# Outputs: DPO SPO
+RAM32X1D 4 0 13 2
+-   -   -   -   -   - 124 124 124 124 124 - -
+124 124 124 124 124 - -   -   -   -   -   - -
+
 # SLICEM/A6LUT
 # Inputs: A0 A1 A2 A3 A4 A5 D DPRA0 DPRA1 DPRA2 DPRA3 DPRA4 DPRA5 WCLK WE
 # Outputs: DPO SPO
-RAM64X1D 4 0 15 2
+RAM64X1D 5 0 15 2
 -   -   -   -   -   -   - 124 124 124 124 124 124 - -
 124 124 124 124 124 124 - -   -   -   -   -   124 - -
 
 # SLICEM/A6LUT + F7[AB]MUX
 # Inputs: A0 A1 A2 A3 A4 A5 A6 D DPRA0 DPRA1 DPRA2 DPRA3 DPRA4 DPRA5 DPRA6 WCLK WE
 # Outputs: DPO SPO
-RAM128X1D 5 0 17 2
+RAM128X1D 6 0 17 2
 -   -   -   -   -   -   -   - 314 314 314 314 314 314 292 - -
 347 347 347 347 347 347 296 - -   -   -   -   -   -   -   - -
diff --git a/techlibs/xilinx/cells_sim.v b/techlibs/xilinx/cells_sim.v
index c6c49c3cd..e3391da40 100644
--- a/techlibs/xilinx/cells_sim.v
+++ b/techlibs/xilinx/cells_sim.v
@@ -289,6 +289,7 @@ module FDPE_1 (output reg Q, input C, CE, D, PRE);
   always @(negedge C, posedge PRE) if (PRE) Q <= 1'b1; else if (CE) Q <= D;
 endmodule
 
+(* abc_box_id = 4, abc_scc_break="D" *)
 module RAM32X1D (
   output DPO, SPO,
   input  D, WCLK, WE,
@@ -306,7 +307,7 @@ module RAM32X1D (
   always @(posedge clk) if (WE) mem[a] <= D;
 endmodule
 
-(* abc_box_id = 4, abc_scc_break="D" *)
+(* abc_box_id = 5, abc_scc_break="D" *)
 module RAM64X1D (
   output DPO, SPO,
   input  D, WCLK, WE,
@@ -324,7 +325,7 @@ module RAM64X1D (
   always @(posedge clk) if (WE) mem[a] <= D;
 endmodule
 
-(* abc_box_id = 5, abc_scc_break="D" *)
+(* abc_box_id = 6, abc_scc_break="D" *)
 module RAM128X1D (
   output       DPO, SPO,
   input        D, WCLK, WE,
-- 
cgit v1.2.3


From 158325956e6bf711137e6198fb88e95a1e6250b9 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Mon, 24 Jun 2019 23:05:28 -0700
Subject: Realistic delays for RAM32X1D too

---
 techlibs/xilinx/abc_xc7.box | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

(limited to 'techlibs')

diff --git a/techlibs/xilinx/abc_xc7.box b/techlibs/xilinx/abc_xc7.box
index c95ba4969..67d1ffb1e 100644
--- a/techlibs/xilinx/abc_xc7.box
+++ b/techlibs/xilinx/abc_xc7.box
@@ -39,8 +39,8 @@ CARRY4 3 1 10 8
 # Inputs: A0 A1 A2 A3 A4 D DPRA0 DPRA1 DPRA2 DPRA3 DPRA4 WCLK WE
 # Outputs: DPO SPO
 RAM32X1D 4 0 13 2
--   -   -   -   -   - 124 124 124 124 124 - -
-124 124 124 124 124 - -   -   -   -   -   - -
+-   -   -   -   -   - 631 472 407 238 127 - -
+631 472 407 238 127 - -   -   -   -   -   - -
 
 # SLICEM/A6LUT
 # Inputs: A0 A1 A2 A3 A4 A5 D DPRA0 DPRA1 DPRA2 DPRA3 DPRA4 DPRA5 WCLK WE
-- 
cgit v1.2.3


From 4238feed81920a21e48c4274f93e5c1b4f009389 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Tue, 25 Jun 2019 09:21:46 -0700
Subject: This optimisation doesn't seem to work...

---
 techlibs/xilinx/cells_map.v | 48 ++++++++++++++++++++++-----------------------
 1 file changed, 24 insertions(+), 24 deletions(-)

(limited to 'techlibs')

diff --git a/techlibs/xilinx/cells_map.v b/techlibs/xilinx/cells_map.v
index bc0455b0c..61c2c8f94 100644
--- a/techlibs/xilinx/cells_map.v
+++ b/techlibs/xilinx/cells_map.v
@@ -287,32 +287,32 @@ module \$__XILINX_MUXF78 (O, I0, I1, I2, I3, S0, S1);
   output O;
   input I0, I1, I2, I3, S0, S1;
   wire T0, T1;
-  parameter _TECHMAP_BITS_CONNMAP_ = 0;
-  parameter [_TECHMAP_BITS_CONNMAP_-1:0] _TECHMAP_CONNMAP_I0_ = 0;
-  parameter [_TECHMAP_BITS_CONNMAP_-1:0] _TECHMAP_CONNMAP_I1_ = 0;
-  parameter [_TECHMAP_BITS_CONNMAP_-1:0] _TECHMAP_CONNMAP_I2_ = 0;
-  parameter [_TECHMAP_BITS_CONNMAP_-1:0] _TECHMAP_CONNMAP_I3_ = 0;
-  parameter _TECHMAP_CONSTMSK_S0_ = 0;
-  parameter _TECHMAP_CONSTVAL_S0_ = 0;
-  parameter _TECHMAP_CONSTMSK_S1_ = 0;
-  parameter _TECHMAP_CONSTVAL_S1_ = 0;
-  if (_TECHMAP_CONSTMSK_S0_ && _TECHMAP_CONSTVAL_S0_ === 1'b1)
-    assign T0 = I1;
-  else if (_TECHMAP_CONSTMSK_S0_ || _TECHMAP_CONNMAP_I0_ === _TECHMAP_CONNMAP_I1_)
-    assign T0 = I0;
-  else
+//  parameter _TECHMAP_BITS_CONNMAP_ = 0;
+//  parameter [_TECHMAP_BITS_CONNMAP_-1:0] _TECHMAP_CONNMAP_I0_ = 0;
+//  parameter [_TECHMAP_BITS_CONNMAP_-1:0] _TECHMAP_CONNMAP_I1_ = 0;
+//  parameter [_TECHMAP_BITS_CONNMAP_-1:0] _TECHMAP_CONNMAP_I2_ = 0;
+//  parameter [_TECHMAP_BITS_CONNMAP_-1:0] _TECHMAP_CONNMAP_I3_ = 0;
+//  parameter _TECHMAP_CONSTMSK_S0_ = 0;
+//  parameter _TECHMAP_CONSTVAL_S0_ = 0;
+//  parameter _TECHMAP_CONSTMSK_S1_ = 0;
+//  parameter _TECHMAP_CONSTVAL_S1_ = 0;
+//  if (_TECHMAP_CONSTMSK_S0_ && _TECHMAP_CONSTVAL_S0_ === 1'b1)
+//    assign T0 = I1;
+//  else if (_TECHMAP_CONSTMSK_S0_ || _TECHMAP_CONNMAP_I0_ === _TECHMAP_CONNMAP_I1_)
+//    assign T0 = I0;
+//  else
     MUXF7 mux7a (.I0(I0), .I1(I1), .S(S0), .O(T0));
-  if (_TECHMAP_CONSTMSK_S0_ && _TECHMAP_CONSTVAL_S0_ === 1'b1)
-    assign T1 = I3;
-  else if (_TECHMAP_CONSTMSK_S0_ || _TECHMAP_CONNMAP_I2_ === _TECHMAP_CONNMAP_I3_)
-    assign T1 = I2;
-  else
+//  if (_TECHMAP_CONSTMSK_S0_ && _TECHMAP_CONSTVAL_S0_ === 1'b1)
+//    assign T1 = I3;
+//  else if (_TECHMAP_CONSTMSK_S0_ || _TECHMAP_CONNMAP_I2_ === _TECHMAP_CONNMAP_I3_)
+//    assign T1 = I2;
+//  else
     MUXF7 mux7b (.I0(I2), .I1(I3), .S(S0), .O(T1));
-  if (_TECHMAP_CONSTMSK_S1_ && _TECHMAP_CONSTVAL_S1_ === 1'b1)
-    assign O = T1;
-  else if (_TECHMAP_CONSTMSK_S1_ || (_TECHMAP_CONNMAP_I0_ === _TECHMAP_CONNMAP_I1_ && _TECHMAP_CONNMAP_I1_ === _TECHMAP_CONNMAP_I2_ && _TECHMAP_CONNMAP_I2_ === _TECHMAP_CONNMAP_I3_))
-    assign O = T0;
-  else
+//  if (_TECHMAP_CONSTMSK_S1_ && _TECHMAP_CONSTVAL_S1_ === 1'b1)
+//    assign O = T1;
+//  else if (_TECHMAP_CONSTMSK_S1_ || (_TECHMAP_CONNMAP_I0_ === _TECHMAP_CONNMAP_I1_ && _TECHMAP_CONNMAP_I1_ === _TECHMAP_CONNMAP_I2_ && _TECHMAP_CONNMAP_I2_ === _TECHMAP_CONNMAP_I3_))
+//    assign O = T0;
+//  else
     MUXF8 mux8 (.I0(T0), .I1(T1), .S(S1), .O(O));
 endmodule
 `endif
-- 
cgit v1.2.3


From 177c26ca359f85d0804c62f73e1df1665ffd1ec5 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Wed, 26 Jun 2019 09:16:45 -0700
Subject: Rename -minmuxf to -widemux

---
 techlibs/xilinx/synth_xilinx.cc | 46 ++++++++++++++++++++---------------------
 1 file changed, 23 insertions(+), 23 deletions(-)

(limited to 'techlibs')

diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc
index 69b1580b8..4367f2b99 100644
--- a/techlibs/xilinx/synth_xilinx.cc
+++ b/techlibs/xilinx/synth_xilinx.cc
@@ -73,7 +73,7 @@ struct SynthXilinxPass : public ScriptPass
 		log("    -nosrl\n");
 		log("        disable inference of shift registers\n");
 		log("\n");
-		log("    -minmuxf <int>\n");
+		log("    -widemux <int>\n");
 		log("        enable inference of hard multiplexer resources (MuxFx) for muxes at or\n");
 		log("        above this number of inputs (minimum value 5).\n");
 		log("        default: 0 (no inference)\n");
@@ -100,7 +100,7 @@ struct SynthXilinxPass : public ScriptPass
 
 	std::string top_opt, edif_file, blif_file, abc, arch;
 	bool flatten, retime, vpr, nocarry, nobram, nodram, nosrl;
-	int minmuxf;
+	int widemux;
 
 	void clear_flags() YS_OVERRIDE
 	{
@@ -116,7 +116,7 @@ struct SynthXilinxPass : public ScriptPass
 		nodram = false;
 		nosrl = false;
 		arch = "xc7";
-		minmuxf = 0;
+		widemux = 0;
 	}
 
 	void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
@@ -179,8 +179,8 @@ struct SynthXilinxPass : public ScriptPass
 				nosrl = true;
 				continue;
 			}
-			if (args[argidx] == "-minmuxf" && argidx+1 < args.size()) {
-				minmuxf = atoi(args[++argidx].c_str());
+			if (args[argidx] == "-widemux" && argidx+1 < args.size()) {
+				widemux = atoi(args[++argidx].c_str());
 				continue;
 			}
 			if (args[argidx] == "-abc9") {
@@ -194,8 +194,8 @@ struct SynthXilinxPass : public ScriptPass
 		if (arch != "xcup" && arch != "xcu" && arch != "xc7" && arch != "xc6s")
 			log_cmd_error("Invalid Xilinx -arch setting: %s\n", arch.c_str());
 
-		if (minmuxf != 0 && minmuxf < 5)
-			log_cmd_error("-minmuxf value must be 0 or >= 5.\n");
+		if (widemux != 0 && widemux < 5)
+			log_cmd_error("-widemux value must be 0 or >= 5.\n");
 
 		if (!design->full_selection())
 			log_cmd_error("This command only operates on fully selected designs!\n");
@@ -233,9 +233,9 @@ struct SynthXilinxPass : public ScriptPass
 			run("check");
 			run("opt");
 			if (help_mode)
-				run("wreduce [c:* t:$mux %d]", "(selection for '-minmuxf' only)");
+				run("wreduce [c:* t:$mux %d]", "(selection for '-widemux' only)");
 			else
-				run("wreduce" + std::string(minmuxf > 0 ? " c:* t:$mux %d" : ""));
+				run("wreduce" + std::string(widemux > 0 ? " c:* t:$mux %d" : ""));
 			run("peepopt");
 			run("opt_clean");
 			run("alumacc");
@@ -246,15 +246,15 @@ struct SynthXilinxPass : public ScriptPass
 			run("memory -nomap");
 			run("opt_clean");
 
-			if (minmuxf > 0 || help_mode)
-				run("muxpack", "    ('-minmuxf' only)");
+			if (widemux > 0 || help_mode)
+				run("muxpack", "    ('-widemux' only)");
 
 			// shregmap -tech xilinx can cope with $shiftx and $mux
 			//   cells for identifying variable-length shift registers,
 			//   so attempt to convert $pmux-es to the former
 			// Also: wide multiplexer inference benefits from this too
-			if (!(nosrl && minmuxf == 0) || help_mode)
-				run("pmux2shiftx", "(skip if '-nosrl' and '-minmuxf' < 5)");
+			if (!(nosrl && widemux == 0) || help_mode)
+				run("pmux2shiftx", "(skip if '-nosrl' and '-widemux' < 5)");
 		}
 
 		if (check_label("bram", "(skip if '-nobram')")) {
@@ -272,15 +272,15 @@ struct SynthXilinxPass : public ScriptPass
 		}
 
 		if (check_label("fine")) {
-			run("opt -fast");
+			run("opt -fast -full");
 			run("memory_map");
 			run("dffsr2dff");
 			run("dff2dffe");
-			if (minmuxf > 0 || help_mode) {
-				run("simplemap t:$mux", "                        ('-minmuxf' only)");
-				if (minmuxf > 0 || help_mode) {
+			if (widemux > 0 || help_mode) {
+				run("simplemap t:$mux", "                        ('-widemux' only)");
+				if (widemux > 0 || help_mode) {
 					std::string muxcover_args = " -dmux=0";
-					switch (minmuxf) {
+					switch (widemux) {
 						// NB: Cost of mux2 is 100; mux8 should cost between 3 and 4
 						//     of those so that 4:1 muxes and below are implemented
 						//     out of mux2s
@@ -297,7 +297,7 @@ struct SynthXilinxPass : public ScriptPass
 						case 15: muxcover_args += " -mux16=1350"; break;
 						default: muxcover_args += " -mux16=1450"; break;
 					}
-					run("muxcover " + muxcover_args, "('-minmuxf' only)");
+					run("muxcover " + muxcover_args, "('-widemux' only)");
 				}
 			}
 			run("opt -full");
@@ -313,8 +313,8 @@ struct SynthXilinxPass : public ScriptPass
 			std::string techmap_args = " -map +/techmap.v";
 			if (help_mode)
 				techmap_args += " [-map +/xilinx/mux_map.v]";
-			else if (minmuxf > 0)
-				techmap_args += stringf(" -D MIN_MUX_INPUTS=%d -map +/xilinx/mux_map.v", minmuxf);
+			else if (widemux > 0)
+				techmap_args += stringf(" -D MIN_MUX_INPUTS=%d -map +/xilinx/mux_map.v", widemux);
 			if (help_mode)
 				techmap_args += " [-map +/xilinx/arith_map.v]";
 			else if (!nocarry) {
@@ -330,8 +330,8 @@ struct SynthXilinxPass : public ScriptPass
 
 		if (check_label("map_cells")) {
 			std::string techmap_args = "-map +/techmap.v -D _ABC -map +/xilinx/cells_map.v";
-			if (minmuxf > 0)
-				techmap_args += stringf(" -D MIN_MUX_INPUTS=%d", minmuxf);
+			if (widemux > 0)
+				techmap_args += stringf(" -D MIN_MUX_INPUTS=%d", widemux);
 			run("techmap " + techmap_args);
 			run("clean");
 		}
-- 
cgit v1.2.3


From 4d0014d1b1a9e747389172b94a45a7dd4af86c6b Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Wed, 26 Jun 2019 11:23:57 -0700
Subject: Cleanup abc_box_id

---
 techlibs/xilinx/abc_xc7.box | 10 +++++-----
 techlibs/xilinx/cells_sim.v | 10 +++++-----
 2 files changed, 10 insertions(+), 10 deletions(-)

(limited to 'techlibs')

diff --git a/techlibs/xilinx/abc_xc7.box b/techlibs/xilinx/abc_xc7.box
index 67d1ffb1e..b1c24ed24 100644
--- a/techlibs/xilinx/abc_xc7.box
+++ b/techlibs/xilinx/abc_xc7.box
@@ -16,7 +16,7 @@ MUXF8 2 1 3 1
 
 # Inputs: I0 I1 I2 I3 S0 S1
 # Outputs: O
-MUXF78 10 1 6 1
+MUXF78 3 1 6 1
 190 193 217 223 296 273
 
 # CARRY4 + CARRY4_[ABCD]X
@@ -25,7 +25,7 @@ MUXF78 10 1 6 1
 #   (NB: carry chain input/output must be last
 #        input/output and have been moved there
 #        overriding the alphabetical ordering)
-CARRY4 3 1 10 8
+CARRY4 4 1 10 8
 482 -   -   -   -   223 -   -   -   222
 598 407 -   -   -   400 205 -   -   334
 584 556 537 -   -   523 558 226 -   239
@@ -38,20 +38,20 @@ CARRY4 3 1 10 8
 # SLICEM/A6LUT
 # Inputs: A0 A1 A2 A3 A4 D DPRA0 DPRA1 DPRA2 DPRA3 DPRA4 WCLK WE
 # Outputs: DPO SPO
-RAM32X1D 4 0 13 2
+RAM32X1D 5 0 13 2
 -   -   -   -   -   - 631 472 407 238 127 - -
 631 472 407 238 127 - -   -   -   -   -   - -
 
 # SLICEM/A6LUT
 # Inputs: A0 A1 A2 A3 A4 A5 D DPRA0 DPRA1 DPRA2 DPRA3 DPRA4 DPRA5 WCLK WE
 # Outputs: DPO SPO
-RAM64X1D 5 0 15 2
+RAM64X1D 6 0 15 2
 -   -   -   -   -   -   - 642 631 472 407 238 127 - -
 642 631 472 407 238 127 - -   -   -   -   -   -   - -
 
 # SLICEM/A6LUT + F7[AB]MUX
 # Inputs: A0 A1 A2 A3 A4 A5 A6 D DPRA0 DPRA1 DPRA2 DPRA3 DPRA4 DPRA5 DPRA6 WCLK WE
 # Outputs: DPO SPO
-RAM128X1D 6 0 17 2
+RAM128X1D 7 0 17 2
 -    -    -   -   -   -   -   - 1009 998 839 774 605 494 450 - -
 1047 1036 877 812 643 532 478 - -    -   -   -   -   -   -   - -
diff --git a/techlibs/xilinx/cells_sim.v b/techlibs/xilinx/cells_sim.v
index e3391da40..58e9c74d5 100644
--- a/techlibs/xilinx/cells_sim.v
+++ b/techlibs/xilinx/cells_sim.v
@@ -170,7 +170,7 @@ module MUXF8(output O, input I0, I1, S);
 endmodule
 
 `ifdef _ABC
-(* abc_box_id = 10, lib_whitebox *)
+(* abc_box_id = 3, lib_whitebox *)
 module \$__XILINX_MUXF78 (output O, input I0, I1, I2, I3, S0, S1);
   assign O = S1 ? (S0 ? I3 : I2)
                 : (S0 ? I1 : I0);
@@ -181,7 +181,7 @@ module XORCY(output O, input CI, LI);
   assign O = CI ^ LI;
 endmodule
 
-(* abc_box_id = 3, abc_carry, lib_whitebox *)
+(* abc_box_id = 4, abc_carry, lib_whitebox *)
 module CARRY4((* abc_carry_out *) output [3:0] CO, output [3:0] O, (* abc_carry_in *) input CI, input CYINIT, input [3:0] DI, S);
   assign O = S ^ {CO[2:0], CI | CYINIT};
   assign CO[0] = S[0] ? CI | CYINIT : DI[0];
@@ -289,7 +289,7 @@ module FDPE_1 (output reg Q, input C, CE, D, PRE);
   always @(negedge C, posedge PRE) if (PRE) Q <= 1'b1; else if (CE) Q <= D;
 endmodule
 
-(* abc_box_id = 4, abc_scc_break="D" *)
+(* abc_box_id = 5, abc_scc_break="D" *)
 module RAM32X1D (
   output DPO, SPO,
   input  D, WCLK, WE,
@@ -307,7 +307,7 @@ module RAM32X1D (
   always @(posedge clk) if (WE) mem[a] <= D;
 endmodule
 
-(* abc_box_id = 5, abc_scc_break="D" *)
+(* abc_box_id = 6, abc_scc_break="D" *)
 module RAM64X1D (
   output DPO, SPO,
   input  D, WCLK, WE,
@@ -325,7 +325,7 @@ module RAM64X1D (
   always @(posedge clk) if (WE) mem[a] <= D;
 endmodule
 
-(* abc_box_id = 6, abc_scc_break="D" *)
+(* abc_box_id = 7, abc_scc_break="D" *)
 module RAM128X1D (
   output       DPO, SPO,
   input        D, WCLK, WE,
-- 
cgit v1.2.3


From 8d8261c71fd34de7eb4cb5ae7bdb2592f33ed852 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Wed, 26 Jun 2019 11:38:28 -0700
Subject: Do not call opt with -full before muxcover

---
 techlibs/xilinx/synth_xilinx.cc | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'techlibs')

diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc
index 0372cb43c..efa4d43f0 100644
--- a/techlibs/xilinx/synth_xilinx.cc
+++ b/techlibs/xilinx/synth_xilinx.cc
@@ -288,7 +288,7 @@ struct SynthXilinxPass : public ScriptPass
 		}
 
 		if (check_label("fine")) {
-			run("opt -fast -full");
+			run("opt -fast");
 			run("memory_map");
 			run("dffsr2dff");
 			run("dff2dffe");
-- 
cgit v1.2.3


From c762be593042ed5d812a3a37d494a82565cbaad0 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Wed, 26 Jun 2019 11:48:35 -0700
Subject: Instead of blocking wreduce on $mux, use -keepdc instead #1132

---
 techlibs/xilinx/synth_xilinx.cc | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

(limited to 'techlibs')

diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc
index efa4d43f0..278098a58 100644
--- a/techlibs/xilinx/synth_xilinx.cc
+++ b/techlibs/xilinx/synth_xilinx.cc
@@ -249,9 +249,9 @@ struct SynthXilinxPass : public ScriptPass
 			run("check");
 			run("opt");
 			if (help_mode)
-				run("wreduce [c:* t:$mux %d]", "(selection for '-widemux' only)");
+				run("wreduce [-keepdc]", "('-widemux' only)");
 			else
-				run("wreduce" + std::string(widemux > 0 ? " c:* t:$mux %d" : ""));
+				run("wreduce" + std::string(widemux > 0 ? " -keepdc" : ""));
 			run("peepopt");
 			run("opt_clean");
 			run("alumacc");
-- 
cgit v1.2.3


From 5f807a7a5b3f4c1eae7b75ad93d90f3d202e2b6c Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Wed, 26 Jun 2019 16:25:48 -0700
Subject: Return to upstream synth_xilinx with opt -full and wreduce

---
 techlibs/xilinx/synth_xilinx.cc | 22 +++-------------------
 1 file changed, 3 insertions(+), 19 deletions(-)

(limited to 'techlibs')

diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc
index 278098a58..c139fb3c4 100644
--- a/techlibs/xilinx/synth_xilinx.cc
+++ b/techlibs/xilinx/synth_xilinx.cc
@@ -241,26 +241,10 @@ struct SynthXilinxPass : public ScriptPass
 		}
 
 		if (check_label("coarse")) {
-			run("proc");
-			if (flatten || help_mode)
-				run("flatten", "(with -flatten only)");
-			run("opt_expr");
-			run("opt_clean");
-			run("check");
-			run("opt");
 			if (help_mode)
-				run("wreduce [-keepdc]", "('-widemux' only)");
+				run("synth -run coarse [-flatten]", "(with '-flatten')");
 			else
-				run("wreduce" + std::string(widemux > 0 ? " -keepdc" : ""));
-			run("peepopt");
-			run("opt_clean");
-			run("alumacc");
-			run("share");
-			run("opt");
-			run("fsm");
-			run("opt -fast");
-			run("memory -nomap");
-			run("opt_clean");
+				run("synth -run coarse" + std::string(flatten ? "" : " -flatten"), "(with '-flatten')");
 
 			if (widemux > 0 || help_mode)
 				run("muxpack", "    ('-widemux' only)");
@@ -288,7 +272,7 @@ struct SynthXilinxPass : public ScriptPass
 		}
 
 		if (check_label("fine")) {
-			run("opt -fast");
+			run("opt -fast -full");
 			run("memory_map");
 			run("dffsr2dff");
 			run("dff2dffe");
-- 
cgit v1.2.3


From cae69a3eddda997c04aa7c6bd642f71ee1033477 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Wed, 26 Jun 2019 17:41:21 -0700
Subject: Rework help_mode for synth_xilinx -widemux

---
 techlibs/xilinx/synth_xilinx.cc | 45 +++++++++++++++++++++--------------------
 1 file changed, 23 insertions(+), 22 deletions(-)

(limited to 'techlibs')

diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc
index c139fb3c4..199d0737d 100644
--- a/techlibs/xilinx/synth_xilinx.cc
+++ b/techlibs/xilinx/synth_xilinx.cc
@@ -276,29 +276,30 @@ struct SynthXilinxPass : public ScriptPass
 			run("memory_map");
 			run("dffsr2dff");
 			run("dff2dffe");
-			if (widemux > 0 || help_mode) {
-				run("simplemap t:$mux", "                        ('-widemux' only)");
-				if (widemux > 0 || help_mode) {
-					std::string muxcover_args = " -dmux=0";
-					switch (widemux) {
-						// NB: Cost of mux2 is 100; mux8 should cost between 3 and 4
-						//     of those so that 4:1 muxes and below are implemented
-						//     out of mux2s
-						case  5: muxcover_args += " -mux8=350 -mux16=400"; break;
-						case  6: muxcover_args += " -mux8=450 -mux16=500"; break;
-						case  7: muxcover_args += " -mux8=550 -mux16=600"; break;
-						case  8: muxcover_args += " -mux8=650 -mux16=700"; break;
-						case  9: muxcover_args += " -mux16=750"; break;
-						case 10: muxcover_args += " -mux16=850"; break;
-						case 11: muxcover_args += " -mux16=950"; break;
-						case 12: muxcover_args += " -mux16=1050"; break;
-						case 13: muxcover_args += " -mux16=1150"; break;
-						case 14: muxcover_args += " -mux16=1250"; break;
-						case 15: muxcover_args += " -mux16=1350"; break;
-						default: muxcover_args += " -mux16=1450"; break;
-					}
-					run("muxcover " + muxcover_args, "('-widemux' only)");
+			if (help_mode) {
+				run("simplemap t:$mux", "                 ('-widemux' only)");
+				run("muxcover -dmux=0 -mux8=<cost> -mux16=<cost>, ('-widemux' only)");
+			}
+			else if (widemux > 0) {
+				std::string muxcover_args = " -dmux=0";
+				switch (widemux) {
+					// NB: Cost of mux2 is 100; mux8 should cost between 3 and 4
+					//     of those so that 4:1 muxes and below are implemented
+					//     out of mux2s
+					case  5: muxcover_args += " -mux8=350 -mux16=400"; break;
+					case  6: muxcover_args += " -mux8=450 -mux16=500"; break;
+					case  7: muxcover_args += " -mux8=550 -mux16=600"; break;
+					case  8: muxcover_args += " -mux8=650 -mux16=700"; break;
+					case  9: muxcover_args += " -mux16=750"; break;
+					case 10: muxcover_args += " -mux16=850"; break;
+					case 11: muxcover_args += " -mux16=950"; break;
+					case 12: muxcover_args += " -mux16=1050"; break;
+					case 13: muxcover_args += " -mux16=1150"; break;
+					case 14: muxcover_args += " -mux16=1250"; break;
+					case 15: muxcover_args += " -mux16=1350"; break;
+					default: muxcover_args += " -mux16=1450"; break;
 				}
+				run("muxcover " + muxcover_args);
 			}
 			run("opt -full");
 
-- 
cgit v1.2.3


From 2b104ed6c8f86a62d192b43fe3f73cc6f0b43e27 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Wed, 26 Jun 2019 17:42:50 -0700
Subject: Replace with <internal options>

---
 techlibs/xilinx/synth_xilinx.cc | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

(limited to 'techlibs')

diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc
index 199d0737d..877694e8a 100644
--- a/techlibs/xilinx/synth_xilinx.cc
+++ b/techlibs/xilinx/synth_xilinx.cc
@@ -277,8 +277,8 @@ struct SynthXilinxPass : public ScriptPass
 			run("dffsr2dff");
 			run("dff2dffe");
 			if (help_mode) {
-				run("simplemap t:$mux", "                 ('-widemux' only)");
-				run("muxcover -dmux=0 -mux8=<cost> -mux16=<cost>, ('-widemux' only)");
+				run("simplemap t:$mux", "         ('-widemux' only)");
+				run("muxcover <internal options>, ('-widemux' only)");
 			}
 			else if (widemux > 0) {
 				std::string muxcover_args = " -dmux=0";
-- 
cgit v1.2.3


From f0a1726a1ad4e14cdee81769565b80bea6cb48ed Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Wed, 26 Jun 2019 17:48:49 -0700
Subject: Accidentally removed "simplemap $mux"

---
 techlibs/xilinx/synth_xilinx.cc | 1 +
 1 file changed, 1 insertion(+)

(limited to 'techlibs')

diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc
index 877694e8a..c3f434c51 100644
--- a/techlibs/xilinx/synth_xilinx.cc
+++ b/techlibs/xilinx/synth_xilinx.cc
@@ -281,6 +281,7 @@ struct SynthXilinxPass : public ScriptPass
 				run("muxcover <internal options>, ('-widemux' only)");
 			}
 			else if (widemux > 0) {
+				run("simplemap t:$mux");
 				std::string muxcover_args = " -dmux=0";
 				switch (widemux) {
 					// NB: Cost of mux2 is 100; mux8 should cost between 3 and 4
-- 
cgit v1.2.3


From b9ff0503f39795a1f749c955b129d9972fe03f0a Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Wed, 26 Jun 2019 17:57:10 -0700
Subject: synth_xilinx's muxcover call to be very conservative -- -nodecode

---
 techlibs/xilinx/synth_xilinx.cc | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'techlibs')

diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc
index c3f434c51..2f3dfb012 100644
--- a/techlibs/xilinx/synth_xilinx.cc
+++ b/techlibs/xilinx/synth_xilinx.cc
@@ -282,7 +282,7 @@ struct SynthXilinxPass : public ScriptPass
 			}
 			else if (widemux > 0) {
 				run("simplemap t:$mux");
-				std::string muxcover_args = " -dmux=0";
+				std::string muxcover_args = " -nodecode";
 				switch (widemux) {
 					// NB: Cost of mux2 is 100; mux8 should cost between 3 and 4
 					//     of those so that 4:1 muxes and below are implemented
-- 
cgit v1.2.3


From 593e4a30bb76ac1b64945b7b8090bedbd0bfb228 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Wed, 26 Jun 2019 20:09:28 -0700
Subject: MUXF78 -> $__MUXF78 to indicate internal

---
 techlibs/xilinx/abc_xc7.box | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'techlibs')

diff --git a/techlibs/xilinx/abc_xc7.box b/techlibs/xilinx/abc_xc7.box
index 7fe8a7236..273d36573 100644
--- a/techlibs/xilinx/abc_xc7.box
+++ b/techlibs/xilinx/abc_xc7.box
@@ -16,7 +16,7 @@ MUXF8 2 1 3 1
 
 # Inputs: I0 I1 I2 I3 S0 S1
 # Outputs: O
-MUXF78 3 1 6 1
+$__MUXF78 3 1 6 1
 190 193 217 223 296 273
 
 # CARRY4 + CARRY4_[ABCD]X
-- 
cgit v1.2.3


From cf020befeb99df2296f2efe722410e49becb44dd Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Fri, 28 Jun 2019 11:28:50 -0700
Subject: Fix CARRY4 abc_box_id

---
 techlibs/xilinx/cells_sim.v | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'techlibs')

diff --git a/techlibs/xilinx/cells_sim.v b/techlibs/xilinx/cells_sim.v
index 94bc3ef86..3937d3536 100644
--- a/techlibs/xilinx/cells_sim.v
+++ b/techlibs/xilinx/cells_sim.v
@@ -181,7 +181,7 @@ module XORCY(output O, input CI, LI);
   assign O = CI ^ LI;
 endmodule
 
-(* abc_box_id = 3, abc_carry="CI,CO", lib_whitebox *)
+(* abc_box_id = 4, abc_carry="CI,CO", lib_whitebox *)
 module CARRY4(output [3:0] CO, O, input CI, CYINIT, input [3:0] DI, S);
   assign O = S ^ {CO[2:0], CI | CYINIT};
   assign CO[0] = S[0] ? CI | CYINIT : DI[0];
-- 
cgit v1.2.3


From a193bf27c94153d6cf27848391f1738bacff06b9 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Fri, 28 Jun 2019 12:03:43 -0700
Subject: Clean up trimming leading 1'bx in A during techmappnig

---
 techlibs/xilinx/cells_map.v | 24 +++++++++---------------
 1 file changed, 9 insertions(+), 15 deletions(-)

(limited to 'techlibs')

diff --git a/techlibs/xilinx/cells_map.v b/techlibs/xilinx/cells_map.v
index cce70d69e..c6e734974 100644
--- a/techlibs/xilinx/cells_map.v
+++ b/techlibs/xilinx/cells_map.v
@@ -170,19 +170,14 @@ module \$__XILINX_SHIFTX (A, B, Y);
   parameter [B_WIDTH-1:0] _TECHMAP_CONSTMSK_B_ = 0;
   parameter [B_WIDTH-1:0] _TECHMAP_CONSTVAL_B_ = 0;
 
-  function integer compute_num_leading_X_in_A;
-    integer i, c;
+  function integer A_WIDTH_trimmed;
+    input integer start;
   begin
-    compute_num_leading_X_in_A = 0;
-    c = 1;
-    for (i = A_WIDTH-1; i >= 0; i=i-1) begin
-      if (!_TECHMAP_CONSTMSK_A_[i] || _TECHMAP_CONSTVAL_A_[i] !== 1'bx)
-        c = 0;
-      compute_num_leading_X_in_A = compute_num_leading_X_in_A + c;
-    end
+    A_WIDTH_trimmed = start;
+    while (A_WIDTH_trimmed > 0 && _TECHMAP_CONSTMSK_A_[A_WIDTH_trimmed-1] && _TECHMAP_CONSTVAL_A_[A_WIDTH_trimmed-1] === 1'bx)
+      A_WIDTH_trimmed = A_WIDTH_trimmed - 1;
   end
   endfunction
-  localparam num_leading_X_in_A = compute_num_leading_X_in_A();
 
   generate
     genvar i, j;
@@ -200,11 +195,10 @@ module \$__XILINX_SHIFTX (A, B, Y);
         assign A_i[i] = A[i*2];
       \$__XILINX_SHIFTX  #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH((A_WIDTH+1'd1)/2'd2), .B_WIDTH(B_WIDTH-1'd1), .Y_WIDTH(Y_WIDTH)) _TECHMAP_REPLACE_ (.A(A_i), .B(B[B_WIDTH-1:1]), .Y(Y));
     end
-    // Trim off any leading 1'bx -es in A, and resize B accordingly
-    else if (num_leading_X_in_A > 0) begin
-      localparam A_WIDTH_new = A_WIDTH - num_leading_X_in_A;
-      localparam B_WIDTH_new = $clog2(A_WIDTH_new);
-      \$__XILINX_SHIFTX  #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(A_WIDTH_new), .B_WIDTH(B_WIDTH_new), .Y_WIDTH(Y_WIDTH)) _TECHMAP_REPLACE_ (.A(A[A_WIDTH_new-1:0]), .B(B[B_WIDTH_new-1:0]), .Y(Y));
+    // Trim off any leading 1'bx -es in A
+    else if (_TECHMAP_CONSTMSK_A_[A_WIDTH-1] && _TECHMAP_CONSTVAL_A_[A_WIDTH-1] === 1'bx) begin
+      localparam A_WIDTH_new = A_WIDTH_trimmed(A_WIDTH-1);
+      \$__XILINX_SHIFTX  #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(A_WIDTH_new), .B_WIDTH(B_WIDTH), .Y_WIDTH(Y_WIDTH)) _TECHMAP_REPLACE_ (.A(A[A_WIDTH_new-1:0]), .B(B), .Y(Y));
     end
     else if (A_WIDTH < `MIN_MUX_INPUTS) begin
       wire _TECHMAP_FAIL_ = 1;
-- 
cgit v1.2.3


From ea0f7c9be9283e927591d1a33c2db663d3bbd82c Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Fri, 28 Jun 2019 12:12:41 -0700
Subject: Restore $__XILINX_MUXF78 const optimisation

---
 techlibs/xilinx/cells_map.v | 48 ++++++++++++++++++++++-----------------------
 1 file changed, 24 insertions(+), 24 deletions(-)

(limited to 'techlibs')

diff --git a/techlibs/xilinx/cells_map.v b/techlibs/xilinx/cells_map.v
index c6e734974..b13f8d1ee 100644
--- a/techlibs/xilinx/cells_map.v
+++ b/techlibs/xilinx/cells_map.v
@@ -279,32 +279,32 @@ module \$__XILINX_MUXF78 (O, I0, I1, I2, I3, S0, S1);
   output O;
   input I0, I1, I2, I3, S0, S1;
   wire T0, T1;
-//  parameter _TECHMAP_BITS_CONNMAP_ = 0;
-//  parameter [_TECHMAP_BITS_CONNMAP_-1:0] _TECHMAP_CONNMAP_I0_ = 0;
-//  parameter [_TECHMAP_BITS_CONNMAP_-1:0] _TECHMAP_CONNMAP_I1_ = 0;
-//  parameter [_TECHMAP_BITS_CONNMAP_-1:0] _TECHMAP_CONNMAP_I2_ = 0;
-//  parameter [_TECHMAP_BITS_CONNMAP_-1:0] _TECHMAP_CONNMAP_I3_ = 0;
-//  parameter _TECHMAP_CONSTMSK_S0_ = 0;
-//  parameter _TECHMAP_CONSTVAL_S0_ = 0;
-//  parameter _TECHMAP_CONSTMSK_S1_ = 0;
-//  parameter _TECHMAP_CONSTVAL_S1_ = 0;
-//  if (_TECHMAP_CONSTMSK_S0_ && _TECHMAP_CONSTVAL_S0_ === 1'b1)
-//    assign T0 = I1;
-//  else if (_TECHMAP_CONSTMSK_S0_ || _TECHMAP_CONNMAP_I0_ === _TECHMAP_CONNMAP_I1_)
-//    assign T0 = I0;
-//  else
+  parameter _TECHMAP_BITS_CONNMAP_ = 0;
+  parameter [_TECHMAP_BITS_CONNMAP_-1:0] _TECHMAP_CONNMAP_I0_ = 0;
+  parameter [_TECHMAP_BITS_CONNMAP_-1:0] _TECHMAP_CONNMAP_I1_ = 0;
+  parameter [_TECHMAP_BITS_CONNMAP_-1:0] _TECHMAP_CONNMAP_I2_ = 0;
+  parameter [_TECHMAP_BITS_CONNMAP_-1:0] _TECHMAP_CONNMAP_I3_ = 0;
+  parameter _TECHMAP_CONSTMSK_S0_ = 0;
+  parameter _TECHMAP_CONSTVAL_S0_ = 0;
+  parameter _TECHMAP_CONSTMSK_S1_ = 0;
+  parameter _TECHMAP_CONSTVAL_S1_ = 0;
+  if (_TECHMAP_CONSTMSK_S0_ && _TECHMAP_CONSTVAL_S0_ === 1'b1)
+    assign T0 = I1;
+  else if (_TECHMAP_CONSTMSK_S0_ || _TECHMAP_CONNMAP_I0_ === _TECHMAP_CONNMAP_I1_)
+    assign T0 = I0;
+  else
     MUXF7 mux7a (.I0(I0), .I1(I1), .S(S0), .O(T0));
-//  if (_TECHMAP_CONSTMSK_S0_ && _TECHMAP_CONSTVAL_S0_ === 1'b1)
-//    assign T1 = I3;
-//  else if (_TECHMAP_CONSTMSK_S0_ || _TECHMAP_CONNMAP_I2_ === _TECHMAP_CONNMAP_I3_)
-//    assign T1 = I2;
-//  else
+  if (_TECHMAP_CONSTMSK_S0_ && _TECHMAP_CONSTVAL_S0_ === 1'b1)
+    assign T1 = I3;
+  else if (_TECHMAP_CONSTMSK_S0_ || _TECHMAP_CONNMAP_I2_ === _TECHMAP_CONNMAP_I3_)
+    assign T1 = I2;
+  else
     MUXF7 mux7b (.I0(I2), .I1(I3), .S(S0), .O(T1));
-//  if (_TECHMAP_CONSTMSK_S1_ && _TECHMAP_CONSTVAL_S1_ === 1'b1)
-//    assign O = T1;
-//  else if (_TECHMAP_CONSTMSK_S1_ || (_TECHMAP_CONNMAP_I0_ === _TECHMAP_CONNMAP_I1_ && _TECHMAP_CONNMAP_I1_ === _TECHMAP_CONNMAP_I2_ && _TECHMAP_CONNMAP_I2_ === _TECHMAP_CONNMAP_I3_))
-//    assign O = T0;
-//  else
+  if (_TECHMAP_CONSTMSK_S1_ && _TECHMAP_CONSTVAL_S1_ === 1'b1)
+    assign O = T1;
+  else if (_TECHMAP_CONSTMSK_S1_ || (_TECHMAP_CONNMAP_I0_ === _TECHMAP_CONNMAP_I1_ && _TECHMAP_CONNMAP_I1_ === _TECHMAP_CONNMAP_I2_ && _TECHMAP_CONNMAP_I2_ === _TECHMAP_CONNMAP_I3_))
+    assign O = T0;
+  else
     MUXF8 mux8 (.I0(T0), .I1(T1), .S(S1), .O(O));
 endmodule
 `endif
-- 
cgit v1.2.3


From 85f1c2dcbe1ebd3fa609f2a9a558810dfcc8484c Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Sat, 29 Jun 2019 21:42:20 -0700
Subject: Cleanup SRL inference/make more consistent

---
 techlibs/xilinx/cells_map.v | 44 +++++++++++++++++++++++++-------------------
 1 file changed, 25 insertions(+), 19 deletions(-)

(limited to 'techlibs')

diff --git a/techlibs/xilinx/cells_map.v b/techlibs/xilinx/cells_map.v
index 9a316fc96..89671c0fc 100644
--- a/techlibs/xilinx/cells_map.v
+++ b/techlibs/xilinx/cells_map.v
@@ -56,7 +56,6 @@ module \$__XILINX_SHREG_ (input C, input D, input [31:0] L, input E, output Q, o
   localparam [DEPTH-1:0] INIT_R = brev(INIT);
 
   parameter _TECHMAP_CONSTMSK_L_ = 0;
-  parameter _TECHMAP_CONSTVAL_L_ = 0;
 
   wire CE;
   generate
@@ -129,26 +128,33 @@ module \$__XILINX_SHREG_ (input C, input D, input [31:0] L, input E, output Q, o
         MUXF8 fpga_mux_2 (.O(Q), .I0(T7), .I1(T8), .S(L[6]));
       end
     end
-    else if (DEPTH <= 129 && ~&_TECHMAP_CONSTMSK_L_) begin
-      // Handle cases where fixed-length depth is
-      // just 1 over a convenient value
-      \$__XILINX_SHREG_ #(.DEPTH(DEPTH+1), .INIT({INIT,1'b0}), .CLKPOL(CLKPOL), .ENPOL(ENPOL)) _TECHMAP_REPLACE_ (.C(C), .D(D), .L(L), .E(E), .Q(Q));
+    // For fixed length, if just 1 over a convenient value, decompose
+    else if (DEPTH <= 129 && &_TECHMAP_CONSTMSK_L_) begin
+      wire T;
+      \$__XILINX_SHREG_ #(.DEPTH(DEPTH-1), .INIT(INIT[DEPTH-1:1]), .CLKPOL(CLKPOL), .ENPOL(ENPOL)) fpga_srl      (.C(C), .D(D), .L({32{1'b1}}), .E(E), .Q(T));
+      \$__XILINX_SHREG_ #(.DEPTH(1),       .INIT(INIT[0]),         .CLKPOL(CLKPOL), .ENPOL(ENPOL)) fpga_srl_last (.C(C), .D(T), .L(L), .E(E), .Q(Q));
     end
+    // For variable length, if just 1 over a convenient value, then bump up one more
+    else if (DEPTH < 129 && ~&_TECHMAP_CONSTMSK_L_)
+      \$__XILINX_SHREG_ #(.DEPTH(DEPTH+1), .INIT({INIT,1'b0}), .CLKPOL(CLKPOL), .ENPOL(ENPOL)) _TECHMAP_REPLACE_ (.C(C), .D(D), .L(L), .E(E), .Q(Q));
     else begin
-      localparam lower_clog2 = $clog2((DEPTH+1)/2);
-      localparam lower_depth = 2 ** lower_clog2;
-      wire T0, T1, T2, T3;
-      if (&_TECHMAP_CONSTMSK_L_) begin
-        \$__XILINX_SHREG_ #(.DEPTH(lower_depth), .INIT(INIT[DEPTH-1:DEPTH-lower_depth]), .CLKPOL(CLKPOL), .ENPOL(ENPOL)) fpga_srl_0 (.C(C), .D(D), .L(lower_depth-1), .E(E), .Q(T0));
-        \$__XILINX_SHREG_ #(.DEPTH(DEPTH-lower_depth), .INIT(INIT[DEPTH-lower_depth-1:0]), .CLKPOL(CLKPOL), .ENPOL(ENPOL)) fpga_srl_1 (.C(C), .D(T0), .L(DEPTH-lower_depth-1), .E(E), .Q(Q), .SO(T3));
-      end
-      else begin
-        \$__XILINX_SHREG_ #(.DEPTH(lower_depth), .INIT(INIT[DEPTH-1:DEPTH-lower_depth]), .CLKPOL(CLKPOL), .ENPOL(ENPOL)) fpga_srl_0 (.C(C), .D(D), .L(L[lower_clog2-1:0]), .E(E), .Q(T0), .SO(T1));
-        \$__XILINX_SHREG_ #(.DEPTH(DEPTH-lower_depth), .INIT(INIT[DEPTH-lower_depth-1:0]), .CLKPOL(CLKPOL), .ENPOL(ENPOL)) fpga_srl_1 (.C(C), .D(T1), .L(L[lower_clog2-1:0]), .E(E), .Q(T2), .SO(T3));
-        assign Q = L[lower_clog2] ? T2 : T0;
-      end
-      if (DEPTH == 2 * lower_depth)
-          assign SO = T3;
+      localparam depth0 = 128;
+      localparam num_srl128 = DEPTH / depth0;
+      localparam depthN = DEPTH % depth0;
+      wire [num_srl128 + (depthN > 0 ? 1 : 0) - 1:0] T;
+      wire [num_srl128 + (depthN > 0 ? 1 : 0) :0] S;
+      assign S[0] = D;
+      genvar i;
+      for (i = 0; i < num_srl128; i++)
+        \$__XILINX_SHREG_ #(.DEPTH(depth0), .INIT(INIT[DEPTH-1-i*depth0-:depth0]), .CLKPOL(CLKPOL), .ENPOL(ENPOL)) fpga_srl      (.C(C), .D(S[i]),          .L(L[$clog2(depth0)-1:0]), .E(E), .Q(T[i]), .SO(S[i+1]));
+
+      if (depthN > 0)
+        \$__XILINX_SHREG_ #(.DEPTH(depthN), .INIT(INIT[depthN-1:0]),               .CLKPOL(CLKPOL), .ENPOL(ENPOL)) fpga_srl_last (.C(C), .D(S[num_srl128]), .L(L[$clog2(depth0)-1:0]), .E(E), .Q(T[num_srl128]));
+
+      if (&_TECHMAP_CONSTMSK_L_)
+        assign Q = T[num_srl128 + (depthN > 0 ? 1 : 0) - 1];
+      else
+        assign Q = T[L[DEPTH-1:$clog2(depth0)]];
     end
   endgenerate
 endmodule
-- 
cgit v1.2.3


From a9a140aa6c84e71edc1a244cfe363400c7e09d90 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Mon, 1 Jul 2019 13:36:27 -0700
Subject: Fix broken MUXFx box, use MUXF7x2 box instead

---
 techlibs/xilinx/abc_xc7.box |  9 +++----
 techlibs/xilinx/cells_map.v | 58 ++++++++++++++++++++++-----------------------
 techlibs/xilinx/cells_sim.v |  6 ++---
 3 files changed, 37 insertions(+), 36 deletions(-)

(limited to 'techlibs')

diff --git a/techlibs/xilinx/abc_xc7.box b/techlibs/xilinx/abc_xc7.box
index 273d36573..0f24d6d66 100644
--- a/techlibs/xilinx/abc_xc7.box
+++ b/techlibs/xilinx/abc_xc7.box
@@ -14,10 +14,11 @@ F7MUX 1 1 3 1
 MUXF8 2 1 3 1
 104 94 273
 
-# Inputs: I0 I1 I2 I3 S0 S1
-# Outputs: O
-$__MUXF78 3 1 6 1
-190 193 217 223 296 273
+# Inputs: I0 I1 I2 I3 S
+# Outputs: O0 O1
+$__MUXF7x2 3 1 5 2
+190 193 -   -   276
+-   -   217 223 296
 
 # CARRY4 + CARRY4_[ABCD]X
 # Inputs: CYINIT DI0 DI1 DI2 DI3 S0 S1 S2 S3 CI
diff --git a/techlibs/xilinx/cells_map.v b/techlibs/xilinx/cells_map.v
index 27e860801..af4427dcf 100644
--- a/techlibs/xilinx/cells_map.v
+++ b/techlibs/xilinx/cells_map.v
@@ -95,7 +95,9 @@ module \$__XILINX_SHREG_ (input C, input D, input [31:0] L, input E, output Q, o
       if (&_TECHMAP_CONSTMSK_L_)
         assign Q = T4;
       else
-        \$__XILINX_MUXF78 fpga_hard_mux (.I0(T0), .I1(T2), .I2(T4), .I3(1'bx), .S0(L[5]), .S1(L[6]), .O(Q));
+        wire TA, TB;
+        \$__XILINX_MUXF7x2 fpga_hard_mux7 (.I0(T0), .I1(T2), .I2(T4), .I3(1'bx), .S(L[5]), .O0(TA), .O1(TB));
+        MUXF8 fpga_hard_mux8 (.I0(TA), .I1(TB), .S(L[6]), .O(Q));
     end else
     if (DEPTH > 97 && DEPTH < 128) begin
       wire T0, T1, T2, T3, T4, T5, T6, T7, T8;
@@ -106,7 +108,9 @@ module \$__XILINX_SHREG_ (input C, input D, input [31:0] L, input E, output Q, o
       if (&_TECHMAP_CONSTMSK_L_)
         assign Q = T6;
       else
-        \$__XILINX_MUXF78 fpga_hard_mux (.I0(T0), .I1(T2), .I2(T4), .I3(T6), .S0(L[5]), .S1(L[6]), .O(Q));
+        wire TA, TB;
+        \$__XILINX_MUXF7x2 fpga_hard_mux (.I0(T0), .I1(T2), .I2(T4), .I3(T6), .S(L[5]), .O0(TA), .O1(TB));
+        MUXF8 fpga_hard_mux8 (.I0(TA), .I1(TB), .S(L[6]), .O(Q));
     end
     else if (DEPTH == 128) begin
       wire T0, T1, T2, T3, T4, T5, T6;
@@ -116,8 +120,11 @@ module \$__XILINX_SHREG_ (input C, input D, input [31:0] L, input E, output Q, o
       SRLC32E #(.INIT(INIT_R[128-1:96]), .IS_CLK_INVERTED(~CLKPOL[0])) fpga_srl_3 (.A(L[4:0]), .CE(CE), .CLK(C), .D(T5), .Q(T6), .Q31(SO));
       if (&_TECHMAP_CONSTMSK_L_)
         assign Q = T6;
-      else
-        \$__XILINX_MUXF78 fpga_hard_mux (.I0(T0), .I1(T2), .I2(T4), .I3(T6), .S0(L[5]), .S1(L[6]), .O(Q));
+      else begin
+        wire TA, TB;
+        \$__XILINX_MUXF7x2 fpga_hard_mux (.I0(T0), .I1(T2), .I2(T4), .I3(T6), .S(L[5]), .O0(T7), .O1(T8));
+        MUXF8 fpga_hard_mux8 (.I0(TA), .I1(TB), .S(L[6]), .O(Q));
+      end
     end
     else if (DEPTH <= 129 && ~&_TECHMAP_CONSTMSK_L_) begin
       // Handle cases where fixed-length depth is
@@ -216,7 +223,9 @@ module \$__XILINX_SHIFTX (A, B, Y);
           \$shiftx  #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(a_widthN), .B_WIDTH($clog2(a_widthN)), .Y_WIDTH(Y_WIDTH)) fpga_mux_last (.A(A[A_WIDTH-1-:a_widthN]), .B(B[$clog2(a_widthN)-1:0]), .Y(T[i]));
         else
           assign T[i] = A[A_WIDTH-1];
-      \$__XILINX_MUXF78 fpga_hard_mux (.I0(T[0]), .I1(T[1]), .I2(T[2]), .I3(T[3]), .S0(B[2]), .S1(B[3]), .O(Y));
+      wire TA, TB;
+      \$__XILINX_MUXF7x2 fpga_hard_mux (.I0(T[0]), .I1(T[2]), .I2(T[4]), .I3(T[6]), .S(B[2]), .O0(TA), .O1(TB));
+      MUXF8 fpga_hard_mux8 (.I0(TA), .I1(TB), .S(B[3]), .O(Q));
     end
     else begin
       localparam a_width0 = 2 ** 4;
@@ -265,36 +274,27 @@ endmodule
 `endif
 
 `ifndef _ABC
-module \$__XILINX_MUXF78 (O, I0, I1, I2, I3, S0, S1);
-  output O;
-  input I0, I1, I2, I3, S0, S1;
-  wire T0, T1;
+module \$__XILINX_MUXF7x2 (O0, O1, I0, I1, I2, I3, S);
+  output O0, O1;
+  input I0, I1, I2, I3, S;
   parameter _TECHMAP_BITS_CONNMAP_ = 0;
   parameter [_TECHMAP_BITS_CONNMAP_-1:0] _TECHMAP_CONNMAP_I0_ = 0;
   parameter [_TECHMAP_BITS_CONNMAP_-1:0] _TECHMAP_CONNMAP_I1_ = 0;
   parameter [_TECHMAP_BITS_CONNMAP_-1:0] _TECHMAP_CONNMAP_I2_ = 0;
   parameter [_TECHMAP_BITS_CONNMAP_-1:0] _TECHMAP_CONNMAP_I3_ = 0;
-  parameter _TECHMAP_CONSTMSK_S0_ = 0;
-  parameter _TECHMAP_CONSTVAL_S0_ = 0;
-  parameter _TECHMAP_CONSTMSK_S1_ = 0;
-  parameter _TECHMAP_CONSTVAL_S1_ = 0;
-  if (_TECHMAP_CONSTMSK_S0_ && _TECHMAP_CONSTVAL_S0_ === 1'b1)
-    assign T0 = I1;
-  else if (_TECHMAP_CONSTMSK_S0_ || _TECHMAP_CONNMAP_I0_ === _TECHMAP_CONNMAP_I1_)
-    assign T0 = I0;
-  else
-    MUXF7 mux7a (.I0(I0), .I1(I1), .S(S0), .O(T0));
-  if (_TECHMAP_CONSTMSK_S0_ && _TECHMAP_CONSTVAL_S0_ === 1'b1)
-    assign T1 = I3;
-  else if (_TECHMAP_CONSTMSK_S0_ || _TECHMAP_CONNMAP_I2_ === _TECHMAP_CONNMAP_I3_)
-    assign T1 = I2;
+  parameter _TECHMAP_CONSTMSK_S_ = 0;
+  parameter _TECHMAP_CONSTVAL_S_ = 0;
+  if (_TECHMAP_CONSTMSK_S_ && _TECHMAP_CONSTVAL_S_ === 1'b1)
+    assign O0 = I1;
+  else if (_TECHMAP_CONSTMSK_S_ || _TECHMAP_CONNMAP_I0_ === _TECHMAP_CONNMAP_I1_)
+    assign O0 = I0;
   else
-    MUXF7 mux7b (.I0(I2), .I1(I3), .S(S0), .O(T1));
-  if (_TECHMAP_CONSTMSK_S1_ && _TECHMAP_CONSTVAL_S1_ === 1'b1)
-    assign O = T1;
-  else if (_TECHMAP_CONSTMSK_S1_ || (_TECHMAP_CONNMAP_I0_ === _TECHMAP_CONNMAP_I1_ && _TECHMAP_CONNMAP_I1_ === _TECHMAP_CONNMAP_I2_ && _TECHMAP_CONNMAP_I2_ === _TECHMAP_CONNMAP_I3_))
-    assign O = T0;
+    MUXF7 mux7a (.I0(I0), .I1(I1), .S(S), .O(O0));
+  if (_TECHMAP_CONSTMSK_S_ && _TECHMAP_CONSTVAL_S_ === 1'b1)
+    assign O1 = I3;
+  else if (_TECHMAP_CONSTMSK_S_ || _TECHMAP_CONNMAP_I2_ === _TECHMAP_CONNMAP_I3_)
+    assign O1 = I2;
   else
-    MUXF8 mux8 (.I0(T0), .I1(T1), .S(S1), .O(O));
+    MUXF7 mux7b (.I0(I2), .I1(I3), .S(S), .O(O1));
 endmodule
 `endif
diff --git a/techlibs/xilinx/cells_sim.v b/techlibs/xilinx/cells_sim.v
index 3937d3536..d1877cf1a 100644
--- a/techlibs/xilinx/cells_sim.v
+++ b/techlibs/xilinx/cells_sim.v
@@ -171,9 +171,9 @@ endmodule
 
 `ifdef _ABC
 (* abc_box_id = 3, lib_whitebox *)
-module \$__XILINX_MUXF78 (output O, input I0, I1, I2, I3, S0, S1);
-  assign O = S1 ? (S0 ? I3 : I2)
-                : (S0 ? I1 : I0);
+module \$__XILINX_MUXF7x2 (output O0, O1, input I0, I1, I2, I3, S);
+  assign O0 = S ? I1 : I0;
+  assign O1 = S ? I3 : I2;
 endmodule
 `endif
 
-- 
cgit v1.2.3


From 09ac27471667d1316b09984624dde981e860a94e Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Mon, 1 Jul 2019 14:01:09 -0700
Subject: Revert "Fix broken MUXFx box, use MUXF7x2 box instead"

This reverts commit a9a140aa6c84e71edc1a244cfe363400c7e09d90.
---
 techlibs/xilinx/abc_xc7.box |  9 ++++---
 techlibs/xilinx/cells_map.v | 58 ++++++++++++++++++++++-----------------------
 techlibs/xilinx/cells_sim.v |  6 ++---
 3 files changed, 36 insertions(+), 37 deletions(-)

(limited to 'techlibs')

diff --git a/techlibs/xilinx/abc_xc7.box b/techlibs/xilinx/abc_xc7.box
index 0f24d6d66..273d36573 100644
--- a/techlibs/xilinx/abc_xc7.box
+++ b/techlibs/xilinx/abc_xc7.box
@@ -14,11 +14,10 @@ F7MUX 1 1 3 1
 MUXF8 2 1 3 1
 104 94 273
 
-# Inputs: I0 I1 I2 I3 S
-# Outputs: O0 O1
-$__MUXF7x2 3 1 5 2
-190 193 -   -   276
--   -   217 223 296
+# Inputs: I0 I1 I2 I3 S0 S1
+# Outputs: O
+$__MUXF78 3 1 6 1
+190 193 217 223 296 273
 
 # CARRY4 + CARRY4_[ABCD]X
 # Inputs: CYINIT DI0 DI1 DI2 DI3 S0 S1 S2 S3 CI
diff --git a/techlibs/xilinx/cells_map.v b/techlibs/xilinx/cells_map.v
index af4427dcf..27e860801 100644
--- a/techlibs/xilinx/cells_map.v
+++ b/techlibs/xilinx/cells_map.v
@@ -95,9 +95,7 @@ module \$__XILINX_SHREG_ (input C, input D, input [31:0] L, input E, output Q, o
       if (&_TECHMAP_CONSTMSK_L_)
         assign Q = T4;
       else
-        wire TA, TB;
-        \$__XILINX_MUXF7x2 fpga_hard_mux7 (.I0(T0), .I1(T2), .I2(T4), .I3(1'bx), .S(L[5]), .O0(TA), .O1(TB));
-        MUXF8 fpga_hard_mux8 (.I0(TA), .I1(TB), .S(L[6]), .O(Q));
+        \$__XILINX_MUXF78 fpga_hard_mux (.I0(T0), .I1(T2), .I2(T4), .I3(1'bx), .S0(L[5]), .S1(L[6]), .O(Q));
     end else
     if (DEPTH > 97 && DEPTH < 128) begin
       wire T0, T1, T2, T3, T4, T5, T6, T7, T8;
@@ -108,9 +106,7 @@ module \$__XILINX_SHREG_ (input C, input D, input [31:0] L, input E, output Q, o
       if (&_TECHMAP_CONSTMSK_L_)
         assign Q = T6;
       else
-        wire TA, TB;
-        \$__XILINX_MUXF7x2 fpga_hard_mux (.I0(T0), .I1(T2), .I2(T4), .I3(T6), .S(L[5]), .O0(TA), .O1(TB));
-        MUXF8 fpga_hard_mux8 (.I0(TA), .I1(TB), .S(L[6]), .O(Q));
+        \$__XILINX_MUXF78 fpga_hard_mux (.I0(T0), .I1(T2), .I2(T4), .I3(T6), .S0(L[5]), .S1(L[6]), .O(Q));
     end
     else if (DEPTH == 128) begin
       wire T0, T1, T2, T3, T4, T5, T6;
@@ -120,11 +116,8 @@ module \$__XILINX_SHREG_ (input C, input D, input [31:0] L, input E, output Q, o
       SRLC32E #(.INIT(INIT_R[128-1:96]), .IS_CLK_INVERTED(~CLKPOL[0])) fpga_srl_3 (.A(L[4:0]), .CE(CE), .CLK(C), .D(T5), .Q(T6), .Q31(SO));
       if (&_TECHMAP_CONSTMSK_L_)
         assign Q = T6;
-      else begin
-        wire TA, TB;
-        \$__XILINX_MUXF7x2 fpga_hard_mux (.I0(T0), .I1(T2), .I2(T4), .I3(T6), .S(L[5]), .O0(T7), .O1(T8));
-        MUXF8 fpga_hard_mux8 (.I0(TA), .I1(TB), .S(L[6]), .O(Q));
-      end
+      else
+        \$__XILINX_MUXF78 fpga_hard_mux (.I0(T0), .I1(T2), .I2(T4), .I3(T6), .S0(L[5]), .S1(L[6]), .O(Q));
     end
     else if (DEPTH <= 129 && ~&_TECHMAP_CONSTMSK_L_) begin
       // Handle cases where fixed-length depth is
@@ -223,9 +216,7 @@ module \$__XILINX_SHIFTX (A, B, Y);
           \$shiftx  #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(a_widthN), .B_WIDTH($clog2(a_widthN)), .Y_WIDTH(Y_WIDTH)) fpga_mux_last (.A(A[A_WIDTH-1-:a_widthN]), .B(B[$clog2(a_widthN)-1:0]), .Y(T[i]));
         else
           assign T[i] = A[A_WIDTH-1];
-      wire TA, TB;
-      \$__XILINX_MUXF7x2 fpga_hard_mux (.I0(T[0]), .I1(T[2]), .I2(T[4]), .I3(T[6]), .S(B[2]), .O0(TA), .O1(TB));
-      MUXF8 fpga_hard_mux8 (.I0(TA), .I1(TB), .S(B[3]), .O(Q));
+      \$__XILINX_MUXF78 fpga_hard_mux (.I0(T[0]), .I1(T[1]), .I2(T[2]), .I3(T[3]), .S0(B[2]), .S1(B[3]), .O(Y));
     end
     else begin
       localparam a_width0 = 2 ** 4;
@@ -274,27 +265,36 @@ endmodule
 `endif
 
 `ifndef _ABC
-module \$__XILINX_MUXF7x2 (O0, O1, I0, I1, I2, I3, S);
-  output O0, O1;
-  input I0, I1, I2, I3, S;
+module \$__XILINX_MUXF78 (O, I0, I1, I2, I3, S0, S1);
+  output O;
+  input I0, I1, I2, I3, S0, S1;
+  wire T0, T1;
   parameter _TECHMAP_BITS_CONNMAP_ = 0;
   parameter [_TECHMAP_BITS_CONNMAP_-1:0] _TECHMAP_CONNMAP_I0_ = 0;
   parameter [_TECHMAP_BITS_CONNMAP_-1:0] _TECHMAP_CONNMAP_I1_ = 0;
   parameter [_TECHMAP_BITS_CONNMAP_-1:0] _TECHMAP_CONNMAP_I2_ = 0;
   parameter [_TECHMAP_BITS_CONNMAP_-1:0] _TECHMAP_CONNMAP_I3_ = 0;
-  parameter _TECHMAP_CONSTMSK_S_ = 0;
-  parameter _TECHMAP_CONSTVAL_S_ = 0;
-  if (_TECHMAP_CONSTMSK_S_ && _TECHMAP_CONSTVAL_S_ === 1'b1)
-    assign O0 = I1;
-  else if (_TECHMAP_CONSTMSK_S_ || _TECHMAP_CONNMAP_I0_ === _TECHMAP_CONNMAP_I1_)
-    assign O0 = I0;
+  parameter _TECHMAP_CONSTMSK_S0_ = 0;
+  parameter _TECHMAP_CONSTVAL_S0_ = 0;
+  parameter _TECHMAP_CONSTMSK_S1_ = 0;
+  parameter _TECHMAP_CONSTVAL_S1_ = 0;
+  if (_TECHMAP_CONSTMSK_S0_ && _TECHMAP_CONSTVAL_S0_ === 1'b1)
+    assign T0 = I1;
+  else if (_TECHMAP_CONSTMSK_S0_ || _TECHMAP_CONNMAP_I0_ === _TECHMAP_CONNMAP_I1_)
+    assign T0 = I0;
+  else
+    MUXF7 mux7a (.I0(I0), .I1(I1), .S(S0), .O(T0));
+  if (_TECHMAP_CONSTMSK_S0_ && _TECHMAP_CONSTVAL_S0_ === 1'b1)
+    assign T1 = I3;
+  else if (_TECHMAP_CONSTMSK_S0_ || _TECHMAP_CONNMAP_I2_ === _TECHMAP_CONNMAP_I3_)
+    assign T1 = I2;
   else
-    MUXF7 mux7a (.I0(I0), .I1(I1), .S(S), .O(O0));
-  if (_TECHMAP_CONSTMSK_S_ && _TECHMAP_CONSTVAL_S_ === 1'b1)
-    assign O1 = I3;
-  else if (_TECHMAP_CONSTMSK_S_ || _TECHMAP_CONNMAP_I2_ === _TECHMAP_CONNMAP_I3_)
-    assign O1 = I2;
+    MUXF7 mux7b (.I0(I2), .I1(I3), .S(S0), .O(T1));
+  if (_TECHMAP_CONSTMSK_S1_ && _TECHMAP_CONSTVAL_S1_ === 1'b1)
+    assign O = T1;
+  else if (_TECHMAP_CONSTMSK_S1_ || (_TECHMAP_CONNMAP_I0_ === _TECHMAP_CONNMAP_I1_ && _TECHMAP_CONNMAP_I1_ === _TECHMAP_CONNMAP_I2_ && _TECHMAP_CONNMAP_I2_ === _TECHMAP_CONNMAP_I3_))
+    assign O = T0;
   else
-    MUXF7 mux7b (.I0(I2), .I1(I3), .S(S), .O(O1));
+    MUXF8 mux8 (.I0(T0), .I1(T1), .S(S1), .O(O));
 endmodule
 `endif
diff --git a/techlibs/xilinx/cells_sim.v b/techlibs/xilinx/cells_sim.v
index d1877cf1a..3937d3536 100644
--- a/techlibs/xilinx/cells_sim.v
+++ b/techlibs/xilinx/cells_sim.v
@@ -171,9 +171,9 @@ endmodule
 
 `ifdef _ABC
 (* abc_box_id = 3, lib_whitebox *)
-module \$__XILINX_MUXF7x2 (output O0, O1, input I0, I1, I2, I3, S);
-  assign O0 = S ? I1 : I0;
-  assign O1 = S ? I3 : I2;
+module \$__XILINX_MUXF78 (output O, input I0, I1, I2, I3, S0, S1);
+  assign O = S1 ? (S0 ? I3 : I2)
+                : (S0 ? I1 : I0);
 endmodule
 `endif
 
-- 
cgit v1.2.3


From 2ea6083b7ecea979838c2be40f5f7ef907f553d6 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Mon, 1 Jul 2019 14:04:06 -0700
Subject: Fix $__XILINX_MUXF78 box timing

---
 techlibs/xilinx/abc_xc7.box | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'techlibs')

diff --git a/techlibs/xilinx/abc_xc7.box b/techlibs/xilinx/abc_xc7.box
index 273d36573..3789ff350 100644
--- a/techlibs/xilinx/abc_xc7.box
+++ b/techlibs/xilinx/abc_xc7.box
@@ -17,7 +17,7 @@ MUXF8 2 1 3 1
 # Inputs: I0 I1 I2 I3 S0 S1
 # Outputs: O
 $__MUXF78 3 1 6 1
-190 193 217 223 296 273
+294 297 311 317 390 273
 
 # CARRY4 + CARRY4_[ABCD]X
 # Inputs: CYINIT DI0 DI1 DI2 DI3 S0 S1 S2 S3 CI
-- 
cgit v1.2.3


From 4f798cda9d1b05d141e16a21b9e357de364021de Mon Sep 17 00:00:00 2001
From: Dan Ravensloft <dan.ravensloft@gmail.com>
Date: Sun, 7 Jul 2019 16:00:38 +0100
Subject: synth_intel: Warn about untested Quartus backend

---
 techlibs/intel/synth_intel.cc | 3 +++
 1 file changed, 3 insertions(+)

(limited to 'techlibs')

diff --git a/techlibs/intel/synth_intel.cc b/techlibs/intel/synth_intel.cc
index 639cba2c2..09c9ba3af 100644
--- a/techlibs/intel/synth_intel.cc
+++ b/techlibs/intel/synth_intel.cc
@@ -48,6 +48,8 @@ struct SynthIntelPass : public ScriptPass {
 		log("    -vqm <file>\n");
 		log("        write the design to the specified Verilog Quartus Mapping File. Writing of an\n");
 		log("        output file is omitted if this parameter is not specified.\n");
+		log("        Note that this backend has not been tested and is likely incompatible\n");
+		log("        with recent versions of Quartus.\n");
 		log("\n");
 		log("    -vpr <file>\n");
 		log("        write BLIF files for VPR flow experiments. The synthesized BLIF output file is not\n");
@@ -108,6 +110,7 @@ struct SynthIntelPass : public ScriptPass {
 			}
 			if (args[argidx] == "-vqm" && argidx + 1 < args.size()) {
 				vout_file = args[++argidx];
+				log_warning("The Quartus backend has not been tested recently and is likely incompatible with modern versions of Quartus.\n");
 				continue;
 			}
 			if (args[argidx] == "-vpr" && argidx + 1 < args.size()) {
-- 
cgit v1.2.3


From c58998a7d2c1066ea28cabe9bc6e1e52bb6668f0 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Mon, 8 Jul 2019 10:48:10 -0700
Subject: atoi -> stoi as per @daveshah1

---
 techlibs/xilinx/synth_xilinx.cc | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'techlibs')

diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc
index 0a30848aa..c18c3918f 100644
--- a/techlibs/xilinx/synth_xilinx.cc
+++ b/techlibs/xilinx/synth_xilinx.cc
@@ -194,7 +194,7 @@ struct SynthXilinxPass : public ScriptPass
 				continue;
 			}
 			if (args[argidx] == "-widemux" && argidx+1 < args.size()) {
-				widemux = atoi(args[++argidx].c_str());
+				widemux = std::stoi(args[++argidx]);
 				continue;
 			}
 			if (args[argidx] == "-abc9") {
-- 
cgit v1.2.3


From dbe1326573e878f4f9d4fc80ce1afcd0f7d84ec6 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Mon, 8 Jul 2019 11:08:20 -0700
Subject: Parametric muxcover costs as per @daveshah1

---
 techlibs/xilinx/synth_xilinx.cc | 30 ++++++++++++++----------------
 1 file changed, 14 insertions(+), 16 deletions(-)

(limited to 'techlibs')

diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc
index c18c3918f..f43923afb 100644
--- a/techlibs/xilinx/synth_xilinx.cc
+++ b/techlibs/xilinx/synth_xilinx.cc
@@ -280,23 +280,21 @@ struct SynthXilinxPass : public ScriptPass
 			}
 			else if (widemux > 0) {
 				run("simplemap t:$mux");
-				std::string muxcover_args = " -nodecode";
+				constexpr int cost_mux2 = 100;
+				std::string muxcover_args = stringf(" -nodecode -mux2=%d", cost_mux2);
 				switch (widemux) {
-					// NB: Cost of mux2 is 100; mux8 should cost between 3 and 4
-					//     of those so that 4:1 muxes and below are implemented
-					//     out of mux2s
-					case  5: muxcover_args += " -mux8=350 -mux16=400"; break;
-					case  6: muxcover_args += " -mux8=450 -mux16=500"; break;
-					case  7: muxcover_args += " -mux8=550 -mux16=600"; break;
-					case  8: muxcover_args += " -mux8=650 -mux16=700"; break;
-					case  9: muxcover_args += " -mux16=750"; break;
-					case 10: muxcover_args += " -mux16=850"; break;
-					case 11: muxcover_args += " -mux16=950"; break;
-					case 12: muxcover_args += " -mux16=1050"; break;
-					case 13: muxcover_args += " -mux16=1150"; break;
-					case 14: muxcover_args += " -mux16=1250"; break;
-					case 15: muxcover_args += " -mux16=1350"; break;
-					default: muxcover_args += " -mux16=1450"; break;
+					case  5:
+					case  6:
+					case  7:
+					case  8: muxcover_args += stringf(" -mux8=%d -mux16=%d", cost_mux2*(widemux-1)-1, cost_mux2*(widemux-1)); break;
+					case  9:
+					case 10:
+					case 11:
+					case 12:
+					case 13:
+					case 14:
+					case 15:
+					default: muxcover_args += stringf(" -mux16=%d", cost_mux2*(widemux-1)-1); break;
 				}
 				run("muxcover " + muxcover_args);
 			}
-- 
cgit v1.2.3


From 0944acf3affd8c6b161a2381b37eed3931c801a5 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Mon, 8 Jul 2019 11:29:21 -0700
Subject: synth_xilinx -widemux=2 is minimum now

---
 techlibs/xilinx/synth_xilinx.cc | 11 +++++++----
 1 file changed, 7 insertions(+), 4 deletions(-)

(limited to 'techlibs')

diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc
index f43923afb..4f597de4d 100644
--- a/techlibs/xilinx/synth_xilinx.cc
+++ b/techlibs/xilinx/synth_xilinx.cc
@@ -79,7 +79,7 @@ struct SynthXilinxPass : public ScriptPass
 		log("\n");
 		log("    -widemux <int>\n");
 		log("        enable inference of hard multiplexer resources (MuxFx) for muxes at or\n");
-		log("        above this number of inputs (minimum value 5).\n");
+		log("        above this number of inputs (minimum value 2).\n");
 		log("        default: 0 (no inference)\n");
 		log("\n");
 		log("    -run <from_label>:<to_label>\n");
@@ -208,8 +208,8 @@ struct SynthXilinxPass : public ScriptPass
 		if (family != "xcup" && family != "xcu" && family != "xc7" && family != "xc6s")
 			log_cmd_error("Invalid Xilinx -family setting: %s\n", family.c_str());
 
-		if (widemux != 0 && widemux < 5)
-			log_cmd_error("-widemux value must be 0 or >= 5.\n");
+		if (widemux != 0 && widemux < 2)
+			log_cmd_error("-widemux value must be 0 or >= 2.\n");
 
 		if (!design->full_selection())
 			log_cmd_error("This command only operates on fully selected designs!\n");
@@ -252,7 +252,7 @@ struct SynthXilinxPass : public ScriptPass
 			//   so attempt to convert $pmux-es to the former
 			// Also: wide multiplexer inference benefits from this too
 			if (!(nosrl && widemux == 0) || help_mode)
-				run("pmux2shiftx", "(skip if '-nosrl' and '-widemux' < 5)");
+				run("pmux2shiftx", "(skip if '-nosrl' and '-widemux=0')");
 		}
 
 		if (check_label("bram", "(skip if '-nobram')")) {
@@ -283,6 +283,9 @@ struct SynthXilinxPass : public ScriptPass
 				constexpr int cost_mux2 = 100;
 				std::string muxcover_args = stringf(" -nodecode -mux2=%d", cost_mux2);
 				switch (widemux) {
+				        case  2:
+					case  3:
+					case  4: muxcover_args += stringf(" -mux4=%d -mux8=%d -mux16=%d", cost_mux2*(widemux-1)-2, cost_mux2*(widemux-1)-1, cost_mux2*(widemux-1)); break;
 					case  5:
 					case  6:
 					case  7:
-- 
cgit v1.2.3


From 895ca501734d2f33b61f118a288832b55a366bd2 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Mon, 8 Jul 2019 12:03:38 -0700
Subject: Fixes for 2:1 muxes

---
 techlibs/xilinx/cells_map.v     | 33 +++++++++++++++++++++++++++++----
 techlibs/xilinx/synth_xilinx.cc |  2 +-
 2 files changed, 30 insertions(+), 5 deletions(-)

(limited to 'techlibs')

diff --git a/techlibs/xilinx/cells_map.v b/techlibs/xilinx/cells_map.v
index 27e860801..e12dd2833 100644
--- a/techlibs/xilinx/cells_map.v
+++ b/techlibs/xilinx/cells_map.v
@@ -193,6 +193,14 @@ module \$__XILINX_SHIFTX (A, B, Y);
     else if (A_WIDTH < `MIN_MUX_INPUTS) begin
       wire _TECHMAP_FAIL_ = 1;
     end
+    else if (A_WIDTH == 2) begin
+      MUXF7 fpga_hard_mux (.I0(A[0]), .I1(A[1]), .S(B[0]), .O(Y));
+    end
+    else if (A_WIDTH <= 2 ** 2) begin
+      wire [4-1:0] T;
+      assign T = {{(4-A_WIDTH){1'bx}}, A};
+      \$__XILINX_MUXF78 fpga_hard_mux (.I0(T[0]), .I1(T[1]), .I2(T[2]), .I3(T[3]), .S0(B[0]), .S1(B[1]), .O(Y));
+    end
     else if (A_WIDTH <= 2 ** 3) begin
       localparam a_width0 = 2 ** 2;
       localparam a_widthN = A_WIDTH - a_width0;
@@ -251,15 +259,32 @@ module _90__XILINX_SHIFTX (A, B, Y);
   \$shiftx  #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(A_WIDTH), .B_WIDTH(B_WIDTH), .Y_WIDTH(Y_WIDTH)) _TECHMAP_REPLACE_ (.A(A), .B(B), .Y(Y));
 endmodule
 
+module \$_MUX_ (A, B, S, Y);
+  input A, B, S;
+  output Y;
+  generate
+    if (`MIN_MUX_INPUTS == 2)
+      \$__XILINX_SHIFTX  #(.A_SIGNED(0), .B_SIGNED(0), .A_WIDTH(2), .B_WIDTH(1), .Y_WIDTH(1)) _TECHMAP_REPLACE_ (.A({B,A}), .B(S), .Y(Y));
+    else
+      wire _TECHMAP_FAIL_ = 1;
+  endgenerate
+endmodule
+
+module \$_MUX4_ (A, B, C, D, S, T, Y);
+  input A, B, C, D, S, T;
+  output Y;
+  \$__XILINX_SHIFTX  #(.A_SIGNED(0), .B_SIGNED(0), .A_WIDTH(4), .B_WIDTH(2), .Y_WIDTH(1)) _TECHMAP_REPLACE_ (.A({D,C,B,A}), .B({T,S}), .Y(Y));
+endmodule
+
 module \$_MUX8_ (A, B, C, D, E, F, G, H, S, T, U, Y);
-input A, B, C, D, E, F, G, H, S, T, U;
-output Y;
+  input A, B, C, D, E, F, G, H, S, T, U;
+  output Y;
   \$__XILINX_SHIFTX  #(.A_SIGNED(0), .B_SIGNED(0), .A_WIDTH(8), .B_WIDTH(3), .Y_WIDTH(1)) _TECHMAP_REPLACE_ (.A({H,G,F,E,D,C,B,A}), .B({U,T,S}), .Y(Y));
 endmodule
 
 module \$_MUX16_ (A, B, C, D, E, F, G, H, I, J, K, L, M, N, O, P, S, T, U, V, Y);
-input A, B, C, D, E, F, G, H, I, J, K, L, M, N, O, P, S, T, U, V;
-output Y;
+  input A, B, C, D, E, F, G, H, I, J, K, L, M, N, O, P, S, T, U, V;
+  output Y;
   \$__XILINX_SHIFTX  #(.A_SIGNED(0), .B_SIGNED(0), .A_WIDTH(16), .B_WIDTH(4), .Y_WIDTH(1)) _TECHMAP_REPLACE_ (.A({P,O,N,M,L,K,J,I,H,G,F,E,D,C,B,A}), .B({V,U,T,S}), .Y(Y));
 endmodule
 `endif
diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc
index 4f597de4d..62bfaaaf1 100644
--- a/techlibs/xilinx/synth_xilinx.cc
+++ b/techlibs/xilinx/synth_xilinx.cc
@@ -283,7 +283,7 @@ struct SynthXilinxPass : public ScriptPass
 				constexpr int cost_mux2 = 100;
 				std::string muxcover_args = stringf(" -nodecode -mux2=%d", cost_mux2);
 				switch (widemux) {
-				        case  2:
+				        case  2: muxcover_args += stringf(" -mux4=%d -mux8=%d -mux16=%d", cost_mux2+1, cost_mux2+2, cost_mux2+3); break;
 					case  3:
 					case  4: muxcover_args += stringf(" -mux4=%d -mux8=%d -mux16=%d", cost_mux2*(widemux-1)-2, cost_mux2*(widemux-1)-1, cost_mux2*(widemux-1)); break;
 					case  5:
-- 
cgit v1.2.3


From baf47e496f35cb90e5c7181079d38c04907c42da Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Mon, 8 Jul 2019 17:04:39 -0700
Subject: Add synth_xilinx -widemux recommended value

---
 techlibs/xilinx/synth_xilinx.cc | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'techlibs')

diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc
index 62bfaaaf1..7836f9f3e 100644
--- a/techlibs/xilinx/synth_xilinx.cc
+++ b/techlibs/xilinx/synth_xilinx.cc
@@ -79,7 +79,7 @@ struct SynthXilinxPass : public ScriptPass
 		log("\n");
 		log("    -widemux <int>\n");
 		log("        enable inference of hard multiplexer resources (MuxFx) for muxes at or\n");
-		log("        above this number of inputs (minimum value 2).\n");
+		log("        above this number of inputs (minimum value 2, recommended value >= 5).\n");
 		log("        default: 0 (no inference)\n");
 		log("\n");
 		log("    -run <from_label>:<to_label>\n");
-- 
cgit v1.2.3


From 78914e2e0e0a92e65cb1594c4858bc2225322ade Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Mon, 8 Jul 2019 17:06:22 -0700
Subject: Capitalisation

---
 techlibs/xilinx/synth_xilinx.cc | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'techlibs')

diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc
index 7836f9f3e..b404dc8e7 100644
--- a/techlibs/xilinx/synth_xilinx.cc
+++ b/techlibs/xilinx/synth_xilinx.cc
@@ -78,7 +78,7 @@ struct SynthXilinxPass : public ScriptPass
 		log("        do not use MUXF[78] resources to implement LUTs larger than LUT6s\n");
 		log("\n");
 		log("    -widemux <int>\n");
-		log("        enable inference of hard multiplexer resources (MuxFx) for muxes at or\n");
+		log("        enable inference of hard multiplexer resources (MUXF[78]) for muxes at or\n");
 		log("        above this number of inputs (minimum value 2, recommended value >= 5).\n");
 		log("        default: 0 (no inference)\n");
 		log("\n");
-- 
cgit v1.2.3


From 3f86407cc32e20a8885c73f959082c5c0449bf9a Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Mon, 8 Jul 2019 17:06:35 -0700
Subject: Map $__XILINX_SHIFTX in a more balanced manner

---
 techlibs/xilinx/cells_map.v | 85 ++++++++++++++++++++++++++-------------------
 1 file changed, 49 insertions(+), 36 deletions(-)

(limited to 'techlibs')

diff --git a/techlibs/xilinx/cells_map.v b/techlibs/xilinx/cells_map.v
index e12dd2833..d48a3f15c 100644
--- a/techlibs/xilinx/cells_map.v
+++ b/techlibs/xilinx/cells_map.v
@@ -197,49 +197,62 @@ module \$__XILINX_SHIFTX (A, B, Y);
       MUXF7 fpga_hard_mux (.I0(A[0]), .I1(A[1]), .S(B[0]), .O(Y));
     end
     else if (A_WIDTH <= 2 ** 2) begin
-      wire [4-1:0] T;
-      assign T = {{(4-A_WIDTH){1'bx}}, A};
-      \$__XILINX_MUXF78 fpga_hard_mux (.I0(T[0]), .I1(T[1]), .I2(T[2]), .I3(T[3]), .S0(B[0]), .S1(B[1]), .O(Y));
+      wire [4-1:0] Ax = {{(4-A_WIDTH){A[A_WIDTH-1]}}, A};
+      \$__XILINX_MUXF78 fpga_hard_mux (.I0(Ax[0]), .I1(Ax[1]), .I2(Ax[2]), .I3(Ax[3]), .S0(B[0]), .S1(B[1]), .O(Y));
     end
     else if (A_WIDTH <= 2 ** 3) begin
-      localparam a_width0 = 2 ** 2;
-      localparam a_widthN = A_WIDTH - a_width0;
-      wire T0, T1;
-      \$shiftx  #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(a_width0), .B_WIDTH(2), .Y_WIDTH(Y_WIDTH)) fpga_soft_mux (.A(A[a_width0-1:0]), .B(B[2-1:0]), .Y(T0));
-      if (a_widthN > 1)
-        \$shiftx  #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(a_widthN), .B_WIDTH($clog2(a_widthN)), .Y_WIDTH(Y_WIDTH)) fpga_soft_mux_last (.A(A[A_WIDTH-1:a_width0]), .B(B[$clog2(a_widthN)-1:0]), .Y(T1));
-      else
-        assign T1 = A[A_WIDTH-1];
-      MUXF7 fpga_hard_mux (.I0(T0), .I1(T1), .S(B[2]), .O(Y));
+      // Rather than extend with 1'bx which gets flattened to 1'b0
+      // causing the "don't care" state to get lost, extend with MSB
+      // so that we can recognise again later when mapping MUXF78
+      wire [8-1:0] Ax = {{(8-A_WIDTH){A[A_WIDTH-1]}}, A};
+      wire T0 = B[0] ? Ax[1] : Ax[0];
+      wire T1 = B[0] ? Ax[3] : Ax[2];
+      wire T2 = B[0] ? Ax[5] : Ax[4];
+      wire T3 = B[0] ? Ax[7] : Ax[6];
+      \$__XILINX_MUXF78 fpga_hard_mux (.I0(T0), .I1(T1), .I2(T2), .I3(T3), .S0(B[1]), .S1(B[2]), .O(Y));
     end
     else if (A_WIDTH <= 2 ** 4) begin
-      localparam a_width0 = 2 ** 2;
-      localparam num_mux8 = A_WIDTH / a_width0;
-      localparam a_widthN = A_WIDTH % a_width0;
-      wire [a_width0-1:0] T;
-      for (i = 0; i < a_width0; i++)
-        if (i < num_mux8)
-          \$shiftx  #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(a_width0), .B_WIDTH(2), .Y_WIDTH(Y_WIDTH)) fpga_mux (.A(A[i*a_width0+:a_width0]), .B(B[2-1:0]), .Y(T[i]));
-        else if (i == num_mux8 && a_widthN > 1)
-          \$shiftx  #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(a_widthN), .B_WIDTH($clog2(a_widthN)), .Y_WIDTH(Y_WIDTH)) fpga_mux_last (.A(A[A_WIDTH-1-:a_widthN]), .B(B[$clog2(a_widthN)-1:0]), .Y(T[i]));
-        else
-          assign T[i] = A[A_WIDTH-1];
-      \$__XILINX_MUXF78 fpga_hard_mux (.I0(T[0]), .I1(T[1]), .I2(T[2]), .I3(T[3]), .S0(B[2]), .S1(B[3]), .O(Y));
+      // Rather than extend with 1'bx which gets flattened to 1'b0
+      // causing the "don't care" state to get lost, extend with MSB
+      // so that we can recognise again later when mapping MUXF78
+      wire [16-1:0] Ax = {{(16-A_WIDTH){A[A_WIDTH-1]}}, A};
+      wire T0 = B[1] ? B[0] ? Ax[ 3] : Ax[ 2]
+                     : B[0] ? Ax[ 1] : Ax[ 0];
+      wire T1 = B[1] ? B[0] ? Ax[ 7] : Ax[ 6]
+                     : B[0] ? Ax[ 5] : Ax[ 4];
+      wire T2 = B[1] ? B[0] ? Ax[11] : Ax[10]
+                     : B[0] ? Ax[ 9] : Ax[ 8];
+      wire T3 = B[1] ? B[0] ? Ax[15] : Ax[14]
+                     : B[0] ? Ax[13] : Ax[12];
+      \$__XILINX_MUXF78 fpga_hard_mux (.I0(T0), .I1(T1), .I2(T2), .I3(T3), .S0(B[2]), .S1(B[3]), .O(Y));
     end
     else begin
-      localparam a_width0 = 2 ** 4;
-      localparam num_mux16 = A_WIDTH / a_width0;
-      localparam a_widthN = A_WIDTH % a_width0;
-      wire [num_mux16 + (a_widthN > 0 ? 1 : 0) - 1:0] T;
+      localparam num_mux16 = (A_WIDTH+15) / 16;
+      localparam clog2_num_mux16 = $clog2(num_mux16);
+      wire [num_mux16-1:0] T;
+      wire [num_mux16*16-1:0] Ax = {{(num_mux16*16-A_WIDTH){1'bx}}, A};
       for (i = 0; i < num_mux16; i++)
-        \$__XILINX_SHIFTX  #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(a_width0), .B_WIDTH(4), .Y_WIDTH(Y_WIDTH)) fpga_soft_mux (.A(A[i*a_width0+:a_width0]), .B(B[4-1:0]), .Y(T[i]));
-      if (a_widthN > 0) begin
-        if (a_widthN > 1)
-          \$__XILINX_SHIFTX  #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(a_widthN), .B_WIDTH($clog2(a_widthN)), .Y_WIDTH(Y_WIDTH)) fpga_soft_mux_last (.A(A[A_WIDTH-1-:a_widthN]), .B(B[$clog2(a_widthN)-1:0]), .Y(T[num_mux16]));
-        else
-          assign T[num_mux16] = A[A_WIDTH-1];
-      end
-      \$__XILINX_SHIFTX  #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(num_mux16 + (a_widthN > 0 ? 1 : 0)), .B_WIDTH(B_WIDTH-4), .Y_WIDTH(Y_WIDTH)) _TECHMAP_REPLACE_ (.A(T), .B(B[B_WIDTH-1:4]), .Y(Y));
+        \$__XILINX_SHIFTX  #(
+          .A_SIGNED(A_SIGNED),
+          .B_SIGNED(B_SIGNED),
+          .A_WIDTH(16),
+          .B_WIDTH(4),
+          .Y_WIDTH(Y_WIDTH)
+        ) fpga_mux (
+          .A(Ax[i*16+:16]),
+          .B(B[3:0]),
+          .Y(T[i])
+        );
+      \$__XILINX_SHIFTX  #(
+          .A_SIGNED(A_SIGNED),
+          .B_SIGNED(B_SIGNED),
+          .A_WIDTH(num_mux16),
+          .B_WIDTH(clog2_num_mux16),
+          .Y_WIDTH(Y_WIDTH)
+      ) _TECHMAP_REPLACE_ (
+          .A(T),
+          .B(B[B_WIDTH-1-:clog2_num_mux16]),
+          .Y(Y));
     end
   endgenerate
 endmodule
-- 
cgit v1.2.3


From dd9771cbcdc14366c6acc501833c6050c39251de Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Mon, 8 Jul 2019 19:14:54 -0700
Subject: Add synth -keepdc option

---
 techlibs/common/synth.cc | 15 +++++++++++++--
 1 file changed, 13 insertions(+), 2 deletions(-)

(limited to 'techlibs')

diff --git a/techlibs/common/synth.cc b/techlibs/common/synth.cc
index 555de9fba..af70cc498 100644
--- a/techlibs/common/synth.cc
+++ b/techlibs/common/synth.cc
@@ -78,6 +78,9 @@ struct SynthPass : public ScriptPass
 		log("    -abc9\n");
 		log("        use new ABC9 flow (EXPERIMENTAL)\n");
 		log("\n");
+		log("    -keepdc\n");
+		log("        do not optimize explicit don't-care values on $mux cells.\n");
+		log("\n");
 		log("\n");
 		log("The following commands are executed by this synthesis command:\n");
 		help_script();
@@ -85,7 +88,7 @@ struct SynthPass : public ScriptPass
 	}
 
 	string top_module, fsm_opts, memory_opts, abc;
-	bool autotop, flatten, noalumacc, nofsm, noabc, noshare;
+	bool autotop, flatten, noalumacc, nofsm, noabc, noshare, keepdc;
 	int lut;
 
 	void clear_flags() YS_OVERRIDE
@@ -102,6 +105,7 @@ struct SynthPass : public ScriptPass
 		noabc = false;
 		noshare = false;
 		abc = "abc";
+		keepdc = false;
 	}
 
 	void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
@@ -167,6 +171,10 @@ struct SynthPass : public ScriptPass
 				abc = "abc9";
 				continue;
 			}
+			if (args[argidx] == "-keepdc") {
+				keepdc = true;
+				continue;
+			}
 			break;
 		}
 		extra_args(args, argidx, design);
@@ -211,7 +219,10 @@ struct SynthPass : public ScriptPass
 			run("opt_clean");
 			run("check");
 			run("opt");
-			run("wreduce");
+			if (help_mode)
+				run("wreduce [-keepdc]");
+			else
+				run("wreduce" + std::string(keepdc ? " -keepdc" : ""));
 			run("peepopt");
 			run("opt_clean");
 			if (help_mode)
-- 
cgit v1.2.3


From 7f964859ec99500e471853f5914b6e5b7c35a031 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Mon, 8 Jul 2019 19:23:24 -0700
Subject: synth_xilinx to call "synth -run coarse" with "-keepdc"

---
 techlibs/xilinx/synth_xilinx.cc | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

(limited to 'techlibs')

diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc
index b404dc8e7..15a37a439 100644
--- a/techlibs/xilinx/synth_xilinx.cc
+++ b/techlibs/xilinx/synth_xilinx.cc
@@ -240,9 +240,9 @@ struct SynthXilinxPass : public ScriptPass
 
 		if (check_label("coarse")) {
 			if (help_mode)
-				run("synth -run coarse [-flatten]", "(with '-flatten')");
+				run("synth -keepdc -run coarse [-flatten]", "(with '-flatten')");
 			else
-				run("synth -run coarse" + std::string(flatten ? "" : " -flatten"), "(with '-flatten')");
+				run("synth -keepdc -run coarse" + std::string(flatten ? "" : " -flatten"), "(with '-flatten')");
 
 			if (widemux > 0 || help_mode)
 				run("muxpack", "    ('-widemux' only)");
-- 
cgit v1.2.3


From de404535538fe4d2548be82724515961e6e92519 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Mon, 8 Jul 2019 22:56:19 -0700
Subject: Reword

---
 techlibs/xilinx/cells_map.v | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

(limited to 'techlibs')

diff --git a/techlibs/xilinx/cells_map.v b/techlibs/xilinx/cells_map.v
index d48a3f15c..63095880e 100644
--- a/techlibs/xilinx/cells_map.v
+++ b/techlibs/xilinx/cells_map.v
@@ -202,7 +202,7 @@ module \$__XILINX_SHIFTX (A, B, Y);
     end
     else if (A_WIDTH <= 2 ** 3) begin
       // Rather than extend with 1'bx which gets flattened to 1'b0
-      // causing the "don't care" state to get lost, extend with MSB
+      // causing the "don't care" status to get lost, extend with MSB
       // so that we can recognise again later when mapping MUXF78
       wire [8-1:0] Ax = {{(8-A_WIDTH){A[A_WIDTH-1]}}, A};
       wire T0 = B[0] ? Ax[1] : Ax[0];
@@ -213,7 +213,7 @@ module \$__XILINX_SHIFTX (A, B, Y);
     end
     else if (A_WIDTH <= 2 ** 4) begin
       // Rather than extend with 1'bx which gets flattened to 1'b0
-      // causing the "don't care" state to get lost, extend with MSB
+      // causing the "don't care" status to get lost, extend with MSB
       // so that we can recognise again later when mapping MUXF78
       wire [16-1:0] Ax = {{(16-A_WIDTH){A[A_WIDTH-1]}}, A};
       wire T0 = B[1] ? B[0] ? Ax[ 3] : Ax[ 2]
-- 
cgit v1.2.3


From 939a225f921efc4276121fe957f545a98d252fa0 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Mon, 8 Jul 2019 23:02:57 -0700
Subject: Less thinking

---
 techlibs/xilinx/cells_map.v | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

(limited to 'techlibs')

diff --git a/techlibs/xilinx/cells_map.v b/techlibs/xilinx/cells_map.v
index 63095880e..7c67c7a79 100644
--- a/techlibs/xilinx/cells_map.v
+++ b/techlibs/xilinx/cells_map.v
@@ -196,11 +196,11 @@ module \$__XILINX_SHIFTX (A, B, Y);
     else if (A_WIDTH == 2) begin
       MUXF7 fpga_hard_mux (.I0(A[0]), .I1(A[1]), .S(B[0]), .O(Y));
     end
-    else if (A_WIDTH <= 2 ** 2) begin
+    else if (A_WIDTH <= 4) begin
       wire [4-1:0] Ax = {{(4-A_WIDTH){A[A_WIDTH-1]}}, A};
       \$__XILINX_MUXF78 fpga_hard_mux (.I0(Ax[0]), .I1(Ax[1]), .I2(Ax[2]), .I3(Ax[3]), .S0(B[0]), .S1(B[1]), .O(Y));
     end
-    else if (A_WIDTH <= 2 ** 3) begin
+    else if (A_WIDTH <= 8) begin
       // Rather than extend with 1'bx which gets flattened to 1'b0
       // causing the "don't care" status to get lost, extend with MSB
       // so that we can recognise again later when mapping MUXF78
@@ -211,7 +211,7 @@ module \$__XILINX_SHIFTX (A, B, Y);
       wire T3 = B[0] ? Ax[7] : Ax[6];
       \$__XILINX_MUXF78 fpga_hard_mux (.I0(T0), .I1(T1), .I2(T2), .I3(T3), .S0(B[1]), .S1(B[2]), .O(Y));
     end
-    else if (A_WIDTH <= 2 ** 4) begin
+    else if (A_WIDTH <= 16) begin
       // Rather than extend with 1'bx which gets flattened to 1'b0
       // causing the "don't care" status to get lost, extend with MSB
       // so that we can recognise again later when mapping MUXF78
-- 
cgit v1.2.3


From d4ab43d9403899dcae74a24e71385fd959de98f8 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Mon, 8 Jul 2019 23:05:48 -0700
Subject: Add one more comment

---
 techlibs/xilinx/cells_map.v | 3 +++
 1 file changed, 3 insertions(+)

(limited to 'techlibs')

diff --git a/techlibs/xilinx/cells_map.v b/techlibs/xilinx/cells_map.v
index 7c67c7a79..39427cc90 100644
--- a/techlibs/xilinx/cells_map.v
+++ b/techlibs/xilinx/cells_map.v
@@ -197,6 +197,9 @@ module \$__XILINX_SHIFTX (A, B, Y);
       MUXF7 fpga_hard_mux (.I0(A[0]), .I1(A[1]), .S(B[0]), .O(Y));
     end
     else if (A_WIDTH <= 4) begin
+      // Rather than extend with 1'bx which gets flattened to 1'b0
+      // causing the "don't care" status to get lost, extend with MSB
+      // so that we can recognise again later when mapping MUXF78
       wire [4-1:0] Ax = {{(4-A_WIDTH){A[A_WIDTH-1]}}, A};
       \$__XILINX_MUXF78 fpga_hard_mux (.I0(Ax[0]), .I1(Ax[1]), .I2(Ax[2]), .I3(Ax[3]), .S0(B[0]), .S1(B[1]), .O(Y));
     end
-- 
cgit v1.2.3


From 45da3ada7babc8f2b23a8b23ce25430a98e2e58e Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Mon, 8 Jul 2019 23:49:16 -0700
Subject: Do not call opt -mux_undef (part of -full) before muxcover

---
 techlibs/xilinx/synth_xilinx.cc | 6 +++++-
 1 file changed, 5 insertions(+), 1 deletion(-)

(limited to 'techlibs')

diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc
index 15a37a439..6eab74a21 100644
--- a/techlibs/xilinx/synth_xilinx.cc
+++ b/techlibs/xilinx/synth_xilinx.cc
@@ -270,7 +270,11 @@ struct SynthXilinxPass : public ScriptPass
 		}
 
 		if (check_label("fine")) {
-			run("opt -fast -full");
+		        if (widemux > 0)
+				run("opt -fast -mux_bool -undriven -fine"); // Necessary to omit -mux_undef otherwise muxcover
+									    // performs less efficiently
+			else
+				run("opt -fast -full");
 			run("memory_map");
 			run("dffsr2dff");
 			run("dff2dffe");
-- 
cgit v1.2.3


From 6951e3207063f66814e765d7d72e553b8b8eace1 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Mon, 8 Jul 2019 23:51:13 -0700
Subject: Decompose mux inputs in delay-orientated (rather than area) fashion

---
 techlibs/xilinx/cells_map.v | 48 ++++++++++++++++++++++++++++-----------------
 1 file changed, 30 insertions(+), 18 deletions(-)

(limited to 'techlibs')

diff --git a/techlibs/xilinx/cells_map.v b/techlibs/xilinx/cells_map.v
index 39427cc90..35eea9858 100644
--- a/techlibs/xilinx/cells_map.v
+++ b/techlibs/xilinx/cells_map.v
@@ -200,34 +200,46 @@ module \$__XILINX_SHIFTX (A, B, Y);
       // Rather than extend with 1'bx which gets flattened to 1'b0
       // causing the "don't care" status to get lost, extend with MSB
       // so that we can recognise again later when mapping MUXF78
-      wire [4-1:0] Ax = {{(4-A_WIDTH){A[A_WIDTH-1]}}, A};
-      \$__XILINX_MUXF78 fpga_hard_mux (.I0(Ax[0]), .I1(Ax[1]), .I2(Ax[2]), .I3(Ax[3]), .S0(B[0]), .S1(B[1]), .O(Y));
+      wire [4-1:0] Ax;
+      if (A_WIDTH == 4)
+        assign Ax = A;
+      else
+        assign Ax = {A[1-:4-A_WIDTH], A};
+      \$__XILINX_MUXF78 fpga_hard_mux (.I0(Ax[0]), .I1(Ax[2]), .I2(Ax[1]), .I3(Ax[3]), .S0(B[1]), .S1(B[0]), .O(Y));
     end
     else if (A_WIDTH <= 8) begin
       // Rather than extend with 1'bx which gets flattened to 1'b0
       // causing the "don't care" status to get lost, extend with MSB
       // so that we can recognise again later when mapping MUXF78
-      wire [8-1:0] Ax = {{(8-A_WIDTH){A[A_WIDTH-1]}}, A};
-      wire T0 = B[0] ? Ax[1] : Ax[0];
-      wire T1 = B[0] ? Ax[3] : Ax[2];
-      wire T2 = B[0] ? Ax[5] : Ax[4];
-      wire T3 = B[0] ? Ax[7] : Ax[6];
-      \$__XILINX_MUXF78 fpga_hard_mux (.I0(T0), .I1(T1), .I2(T2), .I3(T3), .S0(B[1]), .S1(B[2]), .O(Y));
+      wire [8-1:0] Ax;
+      if (A_WIDTH == 8)
+        assign Ax = A;
+      else
+        assign Ax = {A[3-:8-A_WIDTH], A};
+      wire T0 = B[2] ? Ax[4] : Ax[0];
+      wire T1 = B[2] ? Ax[5] : Ax[1];
+      wire T2 = B[2] ? Ax[6] : Ax[2];
+      wire T3 = B[2] ? Ax[7] : Ax[3];
+      \$__XILINX_MUXF78 fpga_hard_mux (.I0(T0), .I1(T2), .I2(T1), .I3(T3), .S0(B[1]), .S1(B[0]), .O(Y));
     end
     else if (A_WIDTH <= 16) begin
       // Rather than extend with 1'bx which gets flattened to 1'b0
       // causing the "don't care" status to get lost, extend with MSB
       // so that we can recognise again later when mapping MUXF78
-      wire [16-1:0] Ax = {{(16-A_WIDTH){A[A_WIDTH-1]}}, A};
-      wire T0 = B[1] ? B[0] ? Ax[ 3] : Ax[ 2]
-                     : B[0] ? Ax[ 1] : Ax[ 0];
-      wire T1 = B[1] ? B[0] ? Ax[ 7] : Ax[ 6]
-                     : B[0] ? Ax[ 5] : Ax[ 4];
-      wire T2 = B[1] ? B[0] ? Ax[11] : Ax[10]
-                     : B[0] ? Ax[ 9] : Ax[ 8];
-      wire T3 = B[1] ? B[0] ? Ax[15] : Ax[14]
-                     : B[0] ? Ax[13] : Ax[12];
-      \$__XILINX_MUXF78 fpga_hard_mux (.I0(T0), .I1(T1), .I2(T2), .I3(T3), .S0(B[2]), .S1(B[3]), .O(Y));
+      wire [16-1:0] Ax;
+      if (A_WIDTH == 16)
+        assign Ax = A;
+      else
+        assign Ax = {A[7-:8-A_WIDTH], A};
+      wire T0 = B[2] ? B[3] ? Ax[12] : Ax[4]
+                     : B[3] ? Ax[ 8] : Ax[0];
+      wire T1 = B[2] ? B[3] ? Ax[13] : Ax[5]
+                     : B[3] ? Ax[ 9] : Ax[1];
+      wire T2 = B[2] ? B[3] ? Ax[14] : Ax[6]
+                     : B[3] ? Ax[10] : Ax[2];
+      wire T3 = B[2] ? B[3] ? Ax[15] : Ax[7]
+                     : B[3] ? Ax[11] : Ax[3];
+      \$__XILINX_MUXF78 fpga_hard_mux (.I0(T0), .I1(T2), .I2(T1), .I3(T3), .S0(B[1]), .S1(B[0]), .O(Y));
     end
     else begin
       localparam num_mux16 = (A_WIDTH+15) / 16;
-- 
cgit v1.2.3


From 667199d46013d116bdbeb9be8592a77503a470e2 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Tue, 9 Jul 2019 09:16:00 -0700
Subject: Fix spacing

---
 techlibs/xilinx/synth_xilinx.cc | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'techlibs')

diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc
index 6eab74a21..abdf7f9cc 100644
--- a/techlibs/xilinx/synth_xilinx.cc
+++ b/techlibs/xilinx/synth_xilinx.cc
@@ -287,7 +287,7 @@ struct SynthXilinxPass : public ScriptPass
 				constexpr int cost_mux2 = 100;
 				std::string muxcover_args = stringf(" -nodecode -mux2=%d", cost_mux2);
 				switch (widemux) {
-				        case  2: muxcover_args += stringf(" -mux4=%d -mux8=%d -mux16=%d", cost_mux2+1, cost_mux2+2, cost_mux2+3); break;
+					case  2: muxcover_args += stringf(" -mux4=%d -mux8=%d -mux16=%d", cost_mux2+1, cost_mux2+2, cost_mux2+3); break;
 					case  3:
 					case  4: muxcover_args += stringf(" -mux4=%d -mux8=%d -mux16=%d", cost_mux2*(widemux-1)-2, cost_mux2*(widemux-1)-1, cost_mux2*(widemux-1)); break;
 					case  5:
-- 
cgit v1.2.3


From bc84f7dd10ad44118fd6d800cb7a896069fd223d Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Tue, 9 Jul 2019 09:22:12 -0700
Subject: Fix spacing

---
 techlibs/xilinx/synth_xilinx.cc | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'techlibs')

diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc
index abdf7f9cc..2a77ce397 100644
--- a/techlibs/xilinx/synth_xilinx.cc
+++ b/techlibs/xilinx/synth_xilinx.cc
@@ -270,7 +270,7 @@ struct SynthXilinxPass : public ScriptPass
 		}
 
 		if (check_label("fine")) {
-		        if (widemux > 0)
+			if (widemux > 0)
 				run("opt -fast -mux_bool -undriven -fine"); // Necessary to omit -mux_undef otherwise muxcover
 									    // performs less efficiently
 			else
-- 
cgit v1.2.3


From 713337255e6ab57b0679d64539d5c87d036c067f Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddieh@ece.ubc.ca>
Date: Tue, 9 Jul 2019 10:14:23 -0700
Subject: Revert "Add "synth -keepdc" option"

---
 techlibs/common/synth.cc | 15 ++-------------
 1 file changed, 2 insertions(+), 13 deletions(-)

(limited to 'techlibs')

diff --git a/techlibs/common/synth.cc b/techlibs/common/synth.cc
index af70cc498..555de9fba 100644
--- a/techlibs/common/synth.cc
+++ b/techlibs/common/synth.cc
@@ -78,9 +78,6 @@ struct SynthPass : public ScriptPass
 		log("    -abc9\n");
 		log("        use new ABC9 flow (EXPERIMENTAL)\n");
 		log("\n");
-		log("    -keepdc\n");
-		log("        do not optimize explicit don't-care values on $mux cells.\n");
-		log("\n");
 		log("\n");
 		log("The following commands are executed by this synthesis command:\n");
 		help_script();
@@ -88,7 +85,7 @@ struct SynthPass : public ScriptPass
 	}
 
 	string top_module, fsm_opts, memory_opts, abc;
-	bool autotop, flatten, noalumacc, nofsm, noabc, noshare, keepdc;
+	bool autotop, flatten, noalumacc, nofsm, noabc, noshare;
 	int lut;
 
 	void clear_flags() YS_OVERRIDE
@@ -105,7 +102,6 @@ struct SynthPass : public ScriptPass
 		noabc = false;
 		noshare = false;
 		abc = "abc";
-		keepdc = false;
 	}
 
 	void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
@@ -171,10 +167,6 @@ struct SynthPass : public ScriptPass
 				abc = "abc9";
 				continue;
 			}
-			if (args[argidx] == "-keepdc") {
-				keepdc = true;
-				continue;
-			}
 			break;
 		}
 		extra_args(args, argidx, design);
@@ -219,10 +211,7 @@ struct SynthPass : public ScriptPass
 			run("opt_clean");
 			run("check");
 			run("opt");
-			if (help_mode)
-				run("wreduce [-keepdc]");
-			else
-				run("wreduce" + std::string(keepdc ? " -keepdc" : ""));
+			run("wreduce");
 			run("peepopt");
 			run("opt_clean");
 			if (help_mode)
-- 
cgit v1.2.3


From 737340327fd8bae4a3b958d85cb14eecb767ed67 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Tue, 9 Jul 2019 10:15:02 -0700
Subject: Revert "synth_xilinx to call "synth -run coarse" with "-keepdc""

This reverts commit 7f964859ec99500e471853f5914b6e5b7c35a031.
---
 techlibs/xilinx/synth_xilinx.cc | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

(limited to 'techlibs')

diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc
index 2a77ce397..8da6df57e 100644
--- a/techlibs/xilinx/synth_xilinx.cc
+++ b/techlibs/xilinx/synth_xilinx.cc
@@ -240,9 +240,9 @@ struct SynthXilinxPass : public ScriptPass
 
 		if (check_label("coarse")) {
 			if (help_mode)
-				run("synth -keepdc -run coarse [-flatten]", "(with '-flatten')");
+				run("synth -run coarse [-flatten]", "(with '-flatten')");
 			else
-				run("synth -keepdc -run coarse" + std::string(flatten ? "" : " -flatten"), "(with '-flatten')");
+				run("synth -run coarse" + std::string(flatten ? "" : " -flatten"), "(with '-flatten')");
 
 			if (widemux > 0 || help_mode)
 				run("muxpack", "    ('-widemux' only)");
-- 
cgit v1.2.3


From c68b9092100280dbc059526a88f9d8e2902ff6a3 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Tue, 9 Jul 2019 10:21:54 -0700
Subject: synth_xilinx to call commands of synth -coarse directly

---
 techlibs/xilinx/synth_xilinx.cc | 23 ++++++++++++++++++++---
 1 file changed, 20 insertions(+), 3 deletions(-)

(limited to 'techlibs')

diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc
index 8da6df57e..0152af481 100644
--- a/techlibs/xilinx/synth_xilinx.cc
+++ b/techlibs/xilinx/synth_xilinx.cc
@@ -239,10 +239,25 @@ struct SynthXilinxPass : public ScriptPass
 		}
 
 		if (check_label("coarse")) {
+			run("proc");
+			if (help_mode || flatten)
+				run("flatten", "(if -flatten)");
+			run("opt_expr");
+			run("opt_clean");
+			run("check");
+			run("opt");
 			if (help_mode)
-				run("synth -run coarse [-flatten]", "(with '-flatten')");
+				run("wreduce [-keepdc]", "(option for '-widemux')");
 			else
-				run("synth -run coarse" + std::string(flatten ? "" : " -flatten"), "(with '-flatten')");
+				run("wreduce" + std::string(widemux > 0 ? " -keepdc" : ""));
+			run("peepopt");
+			run("opt_clean");
+			run("alumacc");
+			run("share");
+			run("opt");
+			run("fsm");
+			run("opt -fast");
+			run("memory -nomap");
 
 			if (widemux > 0 || help_mode)
 				run("muxpack", "    ('-widemux' only)");
@@ -253,6 +268,8 @@ struct SynthXilinxPass : public ScriptPass
 			// Also: wide multiplexer inference benefits from this too
 			if (!(nosrl && widemux == 0) || help_mode)
 				run("pmux2shiftx", "(skip if '-nosrl' and '-widemux=0')");
+
+			run("opt_clean");
 		}
 
 		if (check_label("bram", "(skip if '-nobram')")) {
@@ -344,7 +361,7 @@ struct SynthXilinxPass : public ScriptPass
 		if (check_label("map_luts")) {
 			run("opt_expr -mux_undef");
 			if (help_mode)
-				run("abc -luts 2:2,3,6:5[,10,20] [-dff]", "(skip if 'nowidelut', only for '-retime')");
+				run("abc -luts 2:2,3,6:5[,10,20] [-dff]", "(option for 'nowidelut', option for '-retime')");
 			else if (abc9) {
 				if (family != "xc7")
 					log_warning("'synth_xilinx -abc9' currently supports '-family xc7' only.\n");
-- 
cgit v1.2.3


From c8649953431d3789296c4a7c1bd559ec136af6e3 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Tue, 9 Jul 2019 10:38:07 -0700
Subject: Fix typo and comments

---
 techlibs/xilinx/cells_map.v | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

(limited to 'techlibs')

diff --git a/techlibs/xilinx/cells_map.v b/techlibs/xilinx/cells_map.v
index d3f6a60cc..233a56003 100644
--- a/techlibs/xilinx/cells_map.v
+++ b/techlibs/xilinx/cells_map.v
@@ -204,7 +204,7 @@ module \$__XILINX_SHIFTX (A, B, Y);
     end
     else if (A_WIDTH <= 4) begin
       // Rather than extend with 1'bx which gets flattened to 1'b0
-      // causing the "don't care" status to get lost, extend with MSB
+      // causing the "don't care" status to get lost, extend with MSBs
       // so that we can recognise again later when mapping MUXF78
       wire [4-1:0] Ax;
       if (A_WIDTH == 4)
@@ -215,7 +215,7 @@ module \$__XILINX_SHIFTX (A, B, Y);
     end
     else if (A_WIDTH <= 8) begin
       // Rather than extend with 1'bx which gets flattened to 1'b0
-      // causing the "don't care" status to get lost, extend with MSB
+      // causing the "don't care" status to get lost, extend with MSBs
       // so that we can recognise again later when mapping MUXF78
       wire [8-1:0] Ax;
       if (A_WIDTH == 8)
@@ -230,13 +230,13 @@ module \$__XILINX_SHIFTX (A, B, Y);
     end
     else if (A_WIDTH <= 16) begin
       // Rather than extend with 1'bx which gets flattened to 1'b0
-      // causing the "don't care" status to get lost, extend with MSB
+      // causing the "don't care" status to get lost, extend with MSBs
       // so that we can recognise again later when mapping MUXF78
       wire [16-1:0] Ax;
       if (A_WIDTH == 16)
         assign Ax = A;
       else
-        assign Ax = {A[7-:8-A_WIDTH], A};
+        assign Ax = {A[7-:16-A_WIDTH], A};
       wire T0 = B[2] ? B[3] ? Ax[12] : Ax[4]
                      : B[3] ? Ax[ 8] : Ax[0];
       wire T1 = B[2] ? B[3] ? Ax[13] : Ax[5]
-- 
cgit v1.2.3


From 93522b0ae15466297e45edecf55f7e33c4ebcc1c Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Tue, 9 Jul 2019 10:59:37 -0700
Subject: Extend during mux decomposition with 1'bx

---
 techlibs/xilinx/cells_map.v | 27 +++------------------------
 1 file changed, 3 insertions(+), 24 deletions(-)

(limited to 'techlibs')

diff --git a/techlibs/xilinx/cells_map.v b/techlibs/xilinx/cells_map.v
index 233a56003..e81ff8f53 100644
--- a/techlibs/xilinx/cells_map.v
+++ b/techlibs/xilinx/cells_map.v
@@ -203,25 +203,11 @@ module \$__XILINX_SHIFTX (A, B, Y);
       MUXF7 fpga_hard_mux (.I0(A[0]), .I1(A[1]), .S(B[0]), .O(Y));
     end
     else if (A_WIDTH <= 4) begin
-      // Rather than extend with 1'bx which gets flattened to 1'b0
-      // causing the "don't care" status to get lost, extend with MSBs
-      // so that we can recognise again later when mapping MUXF78
-      wire [4-1:0] Ax;
-      if (A_WIDTH == 4)
-        assign Ax = A;
-      else
-        assign Ax = {A[1-:4-A_WIDTH], A};
+      wire [4-1:0] Ax = {{{4-A_WIDTH}{1'bx}}, A};
       \$__XILINX_MUXF78 fpga_hard_mux (.I0(Ax[0]), .I1(Ax[2]), .I2(Ax[1]), .I3(Ax[3]), .S0(B[1]), .S1(B[0]), .O(Y));
     end
     else if (A_WIDTH <= 8) begin
-      // Rather than extend with 1'bx which gets flattened to 1'b0
-      // causing the "don't care" status to get lost, extend with MSBs
-      // so that we can recognise again later when mapping MUXF78
-      wire [8-1:0] Ax;
-      if (A_WIDTH == 8)
-        assign Ax = A;
-      else
-        assign Ax = {A[3-:8-A_WIDTH], A};
+      wire [8-1:0] Ax = {{{8-A_WIDTH}{1'bx}}, A};
       wire T0 = B[2] ? Ax[4] : Ax[0];
       wire T1 = B[2] ? Ax[5] : Ax[1];
       wire T2 = B[2] ? Ax[6] : Ax[2];
@@ -229,14 +215,7 @@ module \$__XILINX_SHIFTX (A, B, Y);
       \$__XILINX_MUXF78 fpga_hard_mux (.I0(T0), .I1(T2), .I2(T1), .I3(T3), .S0(B[1]), .S1(B[0]), .O(Y));
     end
     else if (A_WIDTH <= 16) begin
-      // Rather than extend with 1'bx which gets flattened to 1'b0
-      // causing the "don't care" status to get lost, extend with MSBs
-      // so that we can recognise again later when mapping MUXF78
-      wire [16-1:0] Ax;
-      if (A_WIDTH == 16)
-        assign Ax = A;
-      else
-        assign Ax = {A[7-:16-A_WIDTH], A};
+      wire [16-1:0] Ax = {{{16-A_WIDTH}{1'bx}}, A};
       wire T0 = B[2] ? B[3] ? Ax[12] : Ax[4]
                      : B[3] ? Ax[ 8] : Ax[0];
       wire T1 = B[2] ? B[3] ? Ax[13] : Ax[5]
-- 
cgit v1.2.3


From b1a048a703b12bc02433d8c2c98b4b35cc799979 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Tue, 9 Jul 2019 12:35:41 -0700
Subject: Extend using A[1] to preserve don't care

---
 techlibs/xilinx/cells_map.v | 10 +++++++++-
 1 file changed, 9 insertions(+), 1 deletion(-)

(limited to 'techlibs')

diff --git a/techlibs/xilinx/cells_map.v b/techlibs/xilinx/cells_map.v
index e81ff8f53..f20fe253e 100644
--- a/techlibs/xilinx/cells_map.v
+++ b/techlibs/xilinx/cells_map.v
@@ -203,7 +203,15 @@ module \$__XILINX_SHIFTX (A, B, Y);
       MUXF7 fpga_hard_mux (.I0(A[0]), .I1(A[1]), .S(B[0]), .O(Y));
     end
     else if (A_WIDTH <= 4) begin
-      wire [4-1:0] Ax = {{{4-A_WIDTH}{1'bx}}, A};
+      wire [4-1:0] Ax;
+      if (A_WIDTH == 4)
+        assign Ax = A;
+      else
+        // Rather than extend with 1'bx which gets flattened to 1'b0
+        // causing the "don't care" status to get lost, extend with
+        // the same driver of F7B.I0 so that we can optimise F7B away
+        // later
+        assign Ax = {A[1], A};
       \$__XILINX_MUXF78 fpga_hard_mux (.I0(Ax[0]), .I1(Ax[2]), .I2(Ax[1]), .I3(Ax[3]), .S0(B[1]), .S1(B[0]), .O(Y));
     end
     else if (A_WIDTH <= 8) begin
-- 
cgit v1.2.3


From 27b27b8781ab8d57aa85a432aba7e914570feffb Mon Sep 17 00:00:00 2001
From: David Shah <dave@ds0.me>
Date: Tue, 9 Jul 2019 22:26:10 +0100
Subject: synth_ecp5: Fix typo in copyright header

Signed-off-by: David Shah <dave@ds0.me>
---
 techlibs/ecp5/synth_ecp5.cc | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'techlibs')

diff --git a/techlibs/ecp5/synth_ecp5.cc b/techlibs/ecp5/synth_ecp5.cc
index f16a47f01..3b0c2ea9e 100644
--- a/techlibs/ecp5/synth_ecp5.cc
+++ b/techlibs/ecp5/synth_ecp5.cc
@@ -2,7 +2,7 @@
  *  yosys -- Yosys Open SYnthesis Suite
  *
  *  Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
- *  Copyright (C) 2018 Clifford Wolf <dave@ds0.me>
+ *  Copyright (C) 2018 David Shah <dave@ds0.me>
  *
  *  Permission to use, copy, modify, and/or distribute this software for any
  *  purpose with or without fee is hereby granted, provided that the above
-- 
cgit v1.2.3


From 5b48b18d29dabfaa3aa51fc4946f14b0ea8954e2 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Tue, 9 Jul 2019 14:28:54 -0700
Subject: Restore missing techmap -map +/cmp2lut.v with LUT_WIDTH=6

---
 techlibs/xilinx/synth_xilinx.cc | 2 ++
 1 file changed, 2 insertions(+)

(limited to 'techlibs')

diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc
index 0152af481..7e10a392a 100644
--- a/techlibs/xilinx/synth_xilinx.cc
+++ b/techlibs/xilinx/synth_xilinx.cc
@@ -2,6 +2,7 @@
  *  yosys -- Yosys Open SYnthesis Suite
  *
  *  Copyright (C) 2012  Clifford Wolf <clifford@clifford.at>
+ *            (C) 2019  Eddie Hung    <eddie@fpgeh.com>
  *
  *  Permission to use, copy, modify, and/or distribute this software for any
  *  purpose with or without fee is hereby granted, provided that the above
@@ -252,6 +253,7 @@ struct SynthXilinxPass : public ScriptPass
 				run("wreduce" + std::string(widemux > 0 ? " -keepdc" : ""));
 			run("peepopt");
 			run("opt_clean");
+			run("techmap -map +/cmp2lut.v -D LUT_WIDTH=6");
 			run("alumacc");
 			run("share");
 			run("opt");
-- 
cgit v1.2.3


From c55530b90197302e7c27eb106094fa74a178fc67 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Tue, 9 Jul 2019 14:29:58 -0700
Subject: Restore opt_clean back to original place

---
 techlibs/xilinx/synth_xilinx.cc | 3 +--
 1 file changed, 1 insertion(+), 2 deletions(-)

(limited to 'techlibs')

diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc
index 7e10a392a..c4877c8af 100644
--- a/techlibs/xilinx/synth_xilinx.cc
+++ b/techlibs/xilinx/synth_xilinx.cc
@@ -260,6 +260,7 @@ struct SynthXilinxPass : public ScriptPass
 			run("fsm");
 			run("opt -fast");
 			run("memory -nomap");
+			run("opt_clean");
 
 			if (widemux > 0 || help_mode)
 				run("muxpack", "    ('-widemux' only)");
@@ -270,8 +271,6 @@ struct SynthXilinxPass : public ScriptPass
 			// Also: wide multiplexer inference benefits from this too
 			if (!(nosrl && widemux == 0) || help_mode)
 				run("pmux2shiftx", "(skip if '-nosrl' and '-widemux=0')");
-
-			run("opt_clean");
 		}
 
 		if (check_label("bram", "(skip if '-nobram')")) {
-- 
cgit v1.2.3


From e573d024a257a6cf8925784f6f22d192a1f24693 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Tue, 9 Jul 2019 21:26:38 -0700
Subject: Call muxpack and pmux2shiftx before cmp2lut

---
 techlibs/xilinx/synth_xilinx.cc | 21 ++++++++++++---------
 1 file changed, 12 insertions(+), 9 deletions(-)

(limited to 'techlibs')

diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc
index c4877c8af..ef7660288 100644
--- a/techlibs/xilinx/synth_xilinx.cc
+++ b/techlibs/xilinx/synth_xilinx.cc
@@ -253,14 +253,6 @@ struct SynthXilinxPass : public ScriptPass
 				run("wreduce" + std::string(widemux > 0 ? " -keepdc" : ""));
 			run("peepopt");
 			run("opt_clean");
-			run("techmap -map +/cmp2lut.v -D LUT_WIDTH=6");
-			run("alumacc");
-			run("share");
-			run("opt");
-			run("fsm");
-			run("opt -fast");
-			run("memory -nomap");
-			run("opt_clean");
 
 			if (widemux > 0 || help_mode)
 				run("muxpack", "    ('-widemux' only)");
@@ -269,8 +261,19 @@ struct SynthXilinxPass : public ScriptPass
 			//   cells for identifying variable-length shift registers,
 			//   so attempt to convert $pmux-es to the former
 			// Also: wide multiplexer inference benefits from this too
-			if (!(nosrl && widemux == 0) || help_mode)
+			if (!(nosrl && widemux == 0) || help_mode) {
 				run("pmux2shiftx", "(skip if '-nosrl' and '-widemux=0')");
+				run("clean", "      (skip if '-nosrl' and '-widemux=0')");
+			}
+
+			run("techmap -map +/cmp2lut.v -D LUT_WIDTH=6");
+			run("alumacc");
+			run("share");
+			run("opt");
+			run("fsm");
+			run("opt -fast");
+			run("memory -nomap");
+			run("opt_clean");
 		}
 
 		if (check_label("bram", "(skip if '-nobram')")) {
-- 
cgit v1.2.3


From 521971e32ef54fa64474a8ed1c2748572901aaf5 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Wed, 10 Jul 2019 12:20:04 -0700
Subject: Add some ASCII art explaining mux decomposition

---
 techlibs/xilinx/cells_map.v | 21 +++++++++++++++++++++
 1 file changed, 21 insertions(+)

(limited to 'techlibs')

diff --git a/techlibs/xilinx/cells_map.v b/techlibs/xilinx/cells_map.v
index f20fe253e..82399be08 100644
--- a/techlibs/xilinx/cells_map.v
+++ b/techlibs/xilinx/cells_map.v
@@ -214,6 +214,27 @@ module \$__XILINX_SHIFTX (A, B, Y);
         assign Ax = {A[1], A};
       \$__XILINX_MUXF78 fpga_hard_mux (.I0(Ax[0]), .I1(Ax[2]), .I2(Ax[1]), .I3(Ax[3]), .S0(B[1]), .S1(B[0]), .O(Y));
     end
+    // Note that the following decompositions are 'backwards' in that
+    // the LSBs are placed on the hard resources, and the soft resources
+    // are used for MSBs.
+    // This has the effect of more effectively utilising the hard mux;
+    // take for example a 5:1 multiplexer, currently this would map as:
+    //
+    // A[0] \___  __                       A[0] \__  __
+    // A[4] /   \|  \     whereas the more A[1] /  \|  \
+    // A[1] _____|   |    obvious mapping  A[2] \___|   |
+    // A[2] _____|   |--  of MSBs to hard  A[3] /   |   |__
+    // A[3]______|   |    resources would  A[4] ____|   |
+    //           |__/     lead to:         1'bx ____|   |
+    //            ||                                |__/
+    //            ||                                 ||
+    //          B[1:0]                             B[1:2]
+    //
+    // Expectation would be that the 'forward' mapping (right) is more
+    // area efficient (consider a 9:1 multiplexer using 2x4:1 multiplexers
+    // on its I0 and I1 inputs, and A[8] and 1'bx on its I2 and I3 inputs)
+    // but that the 'backwards' mapping (left) is more delay efficient
+    // since smaller LUTs are faster than wider ones.
     else if (A_WIDTH <= 8) begin
       wire [8-1:0] Ax = {{{8-A_WIDTH}{1'bx}}, A};
       wire T0 = B[2] ? Ax[4] : Ax[0];
-- 
cgit v1.2.3


From 58bb84e5b22ba66310fd54fecdbf5817138a5fd1 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Wed, 10 Jul 2019 12:32:33 -0700
Subject: Add some spacing

---
 techlibs/xilinx/cells_map.v | 18 +++++++++---------
 1 file changed, 9 insertions(+), 9 deletions(-)

(limited to 'techlibs')

diff --git a/techlibs/xilinx/cells_map.v b/techlibs/xilinx/cells_map.v
index 82399be08..2eb9fa2c1 100644
--- a/techlibs/xilinx/cells_map.v
+++ b/techlibs/xilinx/cells_map.v
@@ -220,15 +220,15 @@ module \$__XILINX_SHIFTX (A, B, Y);
     // This has the effect of more effectively utilising the hard mux;
     // take for example a 5:1 multiplexer, currently this would map as:
     //
-    // A[0] \___  __                       A[0] \__  __
-    // A[4] /   \|  \     whereas the more A[1] /  \|  \
-    // A[1] _____|   |    obvious mapping  A[2] \___|   |
-    // A[2] _____|   |--  of MSBs to hard  A[3] /   |   |__
-    // A[3]______|   |    resources would  A[4] ____|   |
-    //           |__/     lead to:         1'bx ____|   |
-    //            ||                                |__/
-    //            ||                                 ||
-    //          B[1:0]                             B[1:2]
+    //     A[0] \___  __                             A[0] \__  __
+    //     A[4] /   \|  \       whereas the more     A[1] /  \|  \
+    //     A[1] _____|   |      obvious mapping      A[2] \___|   |
+    //     A[2] _____|   |--    of MSBs to hard      A[3] /   |   |__
+    //     A[3]______|   |      resources would      A[4] ____|   |
+    //               |__/       lead to:             1'bx ____|   |
+    //                ||                                      |__/
+    //                ||                                       ||
+    //              B[1:0]                                   B[1:2]
     //
     // Expectation would be that the 'forward' mapping (right) is more
     // area efficient (consider a 9:1 multiplexer using 2x4:1 multiplexers
-- 
cgit v1.2.3


From 6bbd286e033ed25bb49684316a86d6227dec4cd7 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Wed, 10 Jul 2019 12:47:48 -0700
Subject: Error out if -abc9 and -retime specified

---
 techlibs/ecp5/synth_ecp5.cc     |  3 +++
 techlibs/ice40/synth_ice40.cc   |  5 ++++-
 techlibs/xilinx/synth_xilinx.cc | 13 ++++++++-----
 3 files changed, 15 insertions(+), 6 deletions(-)

(limited to 'techlibs')

diff --git a/techlibs/ecp5/synth_ecp5.cc b/techlibs/ecp5/synth_ecp5.cc
index 3b0c2ea9e..9f409ca51 100644
--- a/techlibs/ecp5/synth_ecp5.cc
+++ b/techlibs/ecp5/synth_ecp5.cc
@@ -199,6 +199,9 @@ struct SynthEcp5Pass : public ScriptPass
 		if (!design->full_selection())
 			log_cmd_error("This command only operates on fully selected designs!\n");
 
+		if (abc9 && retime)
+				log_cmd_error("-retime option not currently compatible with -abc9!\n");
+
 		log_header(design, "Executing SYNTH_ECP5 pass.\n");
 		log_push();
 
diff --git a/techlibs/ice40/synth_ice40.cc b/techlibs/ice40/synth_ice40.cc
index 9dd5d81f7..2c75215cb 100644
--- a/techlibs/ice40/synth_ice40.cc
+++ b/techlibs/ice40/synth_ice40.cc
@@ -227,6 +227,9 @@ struct SynthIce40Pass : public ScriptPass
 		if (device_opt != "hx" && device_opt != "lp" && device_opt !="u")
 			log_cmd_error("Invalid or no device specified: '%s'\n", device_opt.c_str());
 
+		if (abc == "abc9" && retime)
+			log_cmd_error("-retime option not currently compatible with -abc9!\n");
+
 		log_header(design, "Executing SYNTH_ICE40 pass.\n");
 		log_push();
 
@@ -296,7 +299,7 @@ struct SynthIce40Pass : public ScriptPass
 				run("techmap");
 			else
 				run("techmap -map +/techmap.v -map +/ice40/arith_map.v");
-			if ((retime || help_mode) && abc != "abc9")
+			if (retime || help_mode)
 				run(abc + " -dff", "(only if -retime)");
 			run("ice40_opt");
 		}
diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc
index b7c32d2e0..22c4a1a1b 100644
--- a/techlibs/xilinx/synth_xilinx.cc
+++ b/techlibs/xilinx/synth_xilinx.cc
@@ -25,8 +25,8 @@
 USING_YOSYS_NAMESPACE
 PRIVATE_NAMESPACE_BEGIN
 
-#define XC7_WIRE_DELAY "300" // Number with which ABC will map a 6-input gate
-                             // to one LUT6 (instead of a LUT5 + LUT2)
+#define XC7_WIRE_DELAY 300 // Number with which ABC will map a 6-input gate
+                           // to one LUT6 (instead of a LUT5 + LUT2)
 
 struct SynthXilinxPass : public ScriptPass
 {
@@ -195,11 +195,14 @@ struct SynthXilinxPass : public ScriptPass
 		extra_args(args, argidx, design);
 
 		if (family != "xcup" && family != "xcu" && family != "xc7" && family != "xc6s")
-			log_cmd_error("Invalid Xilinx -family setting: %s\n", family.c_str());
+			log_cmd_error("Invalid Xilinx -family setting: '%s'.\n", family.c_str());
 
 		if (!design->full_selection())
 			log_cmd_error("This command only operates on fully selected designs!\n");
 
+		if (abc9 && retime)
+			log_cmd_error("-retime option not currently compatible with -abc9!\n");
+
 		log_header(design, "Executing SYNTH_XILINX pass.\n");
 		log_push();
 
@@ -297,9 +300,9 @@ struct SynthXilinxPass : public ScriptPass
 				if (family != "xc7")
 					log_warning("'synth_xilinx -abc9' currently supports '-family xc7' only.\n");
 				if (nowidelut)
-					run("abc9 -lut +/xilinx/abc_xc7_nowide.lut -box +/xilinx/abc_xc7.box -W " + std::string(XC7_WIRE_DELAY) + string(retime ? " -dff" : ""));
+					run("abc9 -lut +/xilinx/abc_xc7_nowide.lut -box +/xilinx/abc_xc7.box -W " + std::to_string(XC7_WIRE_DELAY));
 				else
-					run("abc9 -lut +/xilinx/abc_xc7.lut -box +/xilinx/abc_xc7.box -W " + std::string(XC7_WIRE_DELAY) + string(retime ? " -dff" : ""));
+					run("abc9 -lut +/xilinx/abc_xc7.lut -box +/xilinx/abc_xc7.box -W " + std::to_string(XC7_WIRE_DELAY));
 			}
 			else {
 				if (nowidelut)
-- 
cgit v1.2.3