From 295bb23ae06d36acc8ced4825ece6003470cd357 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Sat, 15 Jun 2019 09:08:56 -0700 Subject: Wrap FDRE with $__ABC_FDRE containing comb --- techlibs/xilinx/abc_xc7.box | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) (limited to 'techlibs/xilinx/abc_xc7.box') diff --git a/techlibs/xilinx/abc_xc7.box b/techlibs/xilinx/abc_xc7.box index 8a48bad4e..653f6bcb3 100644 --- a/techlibs/xilinx/abc_xc7.box +++ b/techlibs/xilinx/abc_xc7.box @@ -41,10 +41,10 @@ RAM128X1D 5 0 17 2 - - - - - - - - 314 314 314 314 314 314 292 - - 347 347 347 347 347 347 296 - - - - - - - - - - -# Inputs: C CE D R -# Outputs: Q -FDRE 6 0 4 1 -- - - - +# Inputs: C CE D R Q_past +# Outputs: Q_next +FDRE 6 1 5 1 +- - - - - # Inputs: C CE D S # Outputs: Q -- cgit v1.2.3 From 65c7bafc64682276d6c1f3cc53b97aa04d8c9039 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Sat, 15 Jun 2019 10:19:05 -0700 Subject: Re-order alphabetically --- techlibs/xilinx/abc_xc7.box | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'techlibs/xilinx/abc_xc7.box') diff --git a/techlibs/xilinx/abc_xc7.box b/techlibs/xilinx/abc_xc7.box index 653f6bcb3..42f563898 100644 --- a/techlibs/xilinx/abc_xc7.box +++ b/techlibs/xilinx/abc_xc7.box @@ -41,7 +41,7 @@ RAM128X1D 5 0 17 2 - - - - - - - - 314 314 314 314 314 314 292 - - 347 347 347 347 347 347 296 - - - - - - - - - - -# Inputs: C CE D R Q_past +# Inputs: C CE D Q_past R # Outputs: Q_next FDRE 6 1 5 1 - - - - - -- cgit v1.2.3 From 0c59bc0b75ba2985e6ae0806d410fe2fa1c94e37 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Sun, 16 Jun 2019 10:42:00 -0700 Subject: Cleanup --- techlibs/xilinx/abc_xc7.box | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'techlibs/xilinx/abc_xc7.box') diff --git a/techlibs/xilinx/abc_xc7.box b/techlibs/xilinx/abc_xc7.box index 42f563898..9aef37545 100644 --- a/techlibs/xilinx/abc_xc7.box +++ b/techlibs/xilinx/abc_xc7.box @@ -41,8 +41,8 @@ RAM128X1D 5 0 17 2 - - - - - - - - 314 314 314 314 314 314 292 - - 347 347 347 347 347 347 296 - - - - - - - - - - -# Inputs: C CE D Q_past R -# Outputs: Q_next +# Inputs: C CE D R \$pastQ +# Outputs: Q FDRE 6 1 5 1 - - - - - -- cgit v1.2.3 From 8a86f9bb6259d335a250868c6f060936a482be8a Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Mon, 17 Jun 2019 15:13:05 -0700 Subject: Add box delays for FD* --- techlibs/xilinx/abc_xc7.box | 20 ++++++++++---------- 1 file changed, 10 insertions(+), 10 deletions(-) (limited to 'techlibs/xilinx/abc_xc7.box') diff --git a/techlibs/xilinx/abc_xc7.box b/techlibs/xilinx/abc_xc7.box index 9aef37545..4caf69320 100644 --- a/techlibs/xilinx/abc_xc7.box +++ b/techlibs/xilinx/abc_xc7.box @@ -44,19 +44,19 @@ RAM128X1D 5 0 17 2 # Inputs: C CE D R \$pastQ # Outputs: Q FDRE 6 1 5 1 -- - - - - +- 109 -46 358 0 -# Inputs: C CE D S +# Inputs: C CE D S \$pastQ # Outputs: Q -FDSE 7 0 4 1 -- - - - +FDSE 7 0 5 1 +- 109 -46 358 0 -# Inputs: C CE CLR D +# Inputs: C CE CLR D \$pastQ # Outputs: Q -FDCE 8 0 4 1 -- - - - +FDCE 8 0 5 1 +- 109 - -46 0 -# Inputs: C CE D PRE +# Inputs: C CE D PRE \$pastQ # Outputs: Q -FDPE 9 0 4 1 -- - - - +FDPE 9 0 5 1 +- 109 -46 - 0 -- cgit v1.2.3 From 659c04a68d15b20a9421ea5d154b259265f39494 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Mon, 1 Jul 2019 10:47:14 -0700 Subject: Update abc_box_id numbering --- techlibs/xilinx/abc_xc7.box | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) (limited to 'techlibs/xilinx/abc_xc7.box') diff --git a/techlibs/xilinx/abc_xc7.box b/techlibs/xilinx/abc_xc7.box index bb9258e78..633e2d484 100644 --- a/techlibs/xilinx/abc_xc7.box +++ b/techlibs/xilinx/abc_xc7.box @@ -54,20 +54,20 @@ RAM128X1D 6 0 17 2 # Inputs: C CE D R \$pastQ # Outputs: Q -FDRE 6 1 5 1 +FDRE 7 1 5 1 - 109 -46 358 0 # Inputs: C CE D S \$pastQ # Outputs: Q -FDSE 7 0 5 1 +FDSE 8 0 5 1 - 109 -46 358 0 # Inputs: C CE CLR D \$pastQ # Outputs: Q -FDCE 8 0 5 1 +FDCE 9 0 5 1 - 109 - -46 0 # Inputs: C CE D PRE \$pastQ # Outputs: Q -FDPE 9 0 5 1 +FDPE 10 0 5 1 - 109 -46 - 0 -- cgit v1.2.3 From 73c8f1a59e69c5c2f06827d365afc6504fdfad82 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Wed, 10 Jul 2019 16:12:33 -0700 Subject: Fix box numbering --- techlibs/xilinx/abc_xc7.box | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) (limited to 'techlibs/xilinx/abc_xc7.box') diff --git a/techlibs/xilinx/abc_xc7.box b/techlibs/xilinx/abc_xc7.box index 69ff9aeab..1e1afbc1d 100644 --- a/techlibs/xilinx/abc_xc7.box +++ b/techlibs/xilinx/abc_xc7.box @@ -59,20 +59,20 @@ RAM128X1D 7 0 17 2 # Inputs: C CE D R \$pastQ # Outputs: Q -FDRE 7 1 5 1 +FDRE 8 1 5 1 - 109 -46 358 0 # Inputs: C CE D S \$pastQ # Outputs: Q -FDSE 8 0 5 1 +FDSE 9 0 5 1 - 109 -46 358 0 # Inputs: C CE CLR D \$pastQ # Outputs: Q -FDCE 9 0 5 1 +FDCE 10 0 5 1 - 109 - -46 0 # Inputs: C CE D PRE \$pastQ # Outputs: Q -FDPE 10 0 5 1 +FDPE 11 0 5 1 - 109 -46 - 0 -- cgit v1.2.3 From 7b2599cb94a718d3c3d6fa4b5eb3ad4824ed13c4 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Wed, 10 Jul 2019 17:06:05 -0700 Subject: Move ABC FF stuff to abc_ff.v; add support for other FD* types --- techlibs/xilinx/abc_xc7.box | 25 ++++++++++++++++++++----- 1 file changed, 20 insertions(+), 5 deletions(-) (limited to 'techlibs/xilinx/abc_xc7.box') diff --git a/techlibs/xilinx/abc_xc7.box b/techlibs/xilinx/abc_xc7.box index 1e1afbc1d..ed283deac 100644 --- a/techlibs/xilinx/abc_xc7.box +++ b/techlibs/xilinx/abc_xc7.box @@ -57,22 +57,37 @@ RAM128X1D 7 0 17 2 - - - - - - - - 1009 998 839 774 605 494 450 - - 1047 1036 877 812 643 532 478 - - - - - - - - - - +# Inputs: A B S +# Outputs: Y +$__ABC_FD_ASYNC_MUX_ 1000 0 3 1 +0 0 764 + # Inputs: C CE D R \$pastQ # Outputs: Q -FDRE 8 1 5 1 +FDRE 1001 1 5 1 - 109 -46 358 0 -# Inputs: C CE D S \$pastQ +# Inputs: C CE D R \$pastQ # Outputs: Q -FDSE 9 0 5 1 +FDRE_1 1002 1 5 1 - 109 -46 358 0 # Inputs: C CE CLR D \$pastQ # Outputs: Q -FDCE 10 0 5 1 +FDCE 1003 1 5 1 +- 109 - -46 0 + +# Inputs: C CE CLR D \$pastQ +# Outputs: Q +FDCE_1004 11 1 5 1 - 109 - -46 0 # Inputs: C CE D PRE \$pastQ # Outputs: Q -FDPE 11 0 5 1 +FDPE 1005 1 5 1 +- 109 -46 - 0 + +# Inputs: C CE D PRE \$pastQ +# Outputs: Q +FDPE_1 1006 1 5 1 - 109 -46 - 0 -- cgit v1.2.3 From 8fef4c359419998eb4b068b019cbeb7faae331b7 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Thu, 11 Jul 2019 10:52:33 -0700 Subject: Simplify to $__ABC_ASYNC box --- techlibs/xilinx/abc_xc7.box | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'techlibs/xilinx/abc_xc7.box') diff --git a/techlibs/xilinx/abc_xc7.box b/techlibs/xilinx/abc_xc7.box index ed283deac..df16c3af1 100644 --- a/techlibs/xilinx/abc_xc7.box +++ b/techlibs/xilinx/abc_xc7.box @@ -57,10 +57,10 @@ RAM128X1D 7 0 17 2 - - - - - - - - 1009 998 839 774 605 494 450 - - 1047 1036 877 812 643 532 478 - - - - - - - - - - -# Inputs: A B S +# Inputs: A S # Outputs: Y -$__ABC_FD_ASYNC_MUX_ 1000 0 3 1 -0 0 764 +$__ABC_ASYNC 1000 0 2 1 +0 764 # Inputs: C CE D R \$pastQ # Outputs: Q -- cgit v1.2.3 From 021f8e549266fb500d19f7a3b7747cad6eda22c2 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Thu, 11 Jul 2019 13:23:07 -0700 Subject: Fix typo --- techlibs/xilinx/abc_xc7.box | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'techlibs/xilinx/abc_xc7.box') diff --git a/techlibs/xilinx/abc_xc7.box b/techlibs/xilinx/abc_xc7.box index df16c3af1..24512ecf7 100644 --- a/techlibs/xilinx/abc_xc7.box +++ b/techlibs/xilinx/abc_xc7.box @@ -79,7 +79,7 @@ FDCE 1003 1 5 1 # Inputs: C CE CLR D \$pastQ # Outputs: Q -FDCE_1004 11 1 5 1 +FDCE_1004 1 1 5 1 - 109 - -46 0 # Inputs: C CE D PRE \$pastQ -- cgit v1.2.3 From 8f9d529929f43e6ba98f06159ae9533984c6264f Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Thu, 11 Jul 2019 13:54:40 -0700 Subject: $pastQ should be first input --- techlibs/xilinx/abc_xc7.box | 26 +++++++++++++------------- 1 file changed, 13 insertions(+), 13 deletions(-) (limited to 'techlibs/xilinx/abc_xc7.box') diff --git a/techlibs/xilinx/abc_xc7.box b/techlibs/xilinx/abc_xc7.box index 24512ecf7..5dc93e508 100644 --- a/techlibs/xilinx/abc_xc7.box +++ b/techlibs/xilinx/abc_xc7.box @@ -62,32 +62,32 @@ RAM128X1D 7 0 17 2 $__ABC_ASYNC 1000 0 2 1 0 764 -# Inputs: C CE D R \$pastQ +# Inputs: $pastQ C CE D R # Outputs: Q FDRE 1001 1 5 1 -- 109 -46 358 0 +0 - 0 0 0 -# Inputs: C CE D R \$pastQ +# Inputs: $pastQ C CE D R # Outputs: Q FDRE_1 1002 1 5 1 -- 109 -46 358 0 +0 - 109 -46 358 -# Inputs: C CE CLR D \$pastQ +# Inputs: $pastQ C CE CLR D # Outputs: Q FDCE 1003 1 5 1 -- 109 - -46 0 +0 - 109 - -46 -# Inputs: C CE CLR D \$pastQ +# Inputs: $pastQ C CE CLR D # Outputs: Q -FDCE_1004 1 1 5 1 -- 109 - -46 0 +FDCE_1 1004 1 5 1 +0 - 109 - -46 -# Inputs: C CE D PRE \$pastQ +# Inputs: $pastQ C CE D PRE # Outputs: Q FDPE 1005 1 5 1 -- 109 -46 - 0 +0 - 109 -46 - -# Inputs: C CE D PRE \$pastQ +# Inputs: $pastQ C CE D PRE # Outputs: Q FDPE_1 1006 1 5 1 -- 109 -46 - 0 +0 - 109 -46 - -- cgit v1.2.3 From 1ada5681340aca5132e4a7bf8fa2d4a6e80adc59 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Thu, 11 Jul 2019 14:23:45 -0700 Subject: Revert "$pastQ should be first input" This reverts commit 8f9d529929f43e6ba98f06159ae9533984c6264f. --- techlibs/xilinx/abc_xc7.box | 26 +++++++++++++------------- 1 file changed, 13 insertions(+), 13 deletions(-) (limited to 'techlibs/xilinx/abc_xc7.box') diff --git a/techlibs/xilinx/abc_xc7.box b/techlibs/xilinx/abc_xc7.box index 5dc93e508..24512ecf7 100644 --- a/techlibs/xilinx/abc_xc7.box +++ b/techlibs/xilinx/abc_xc7.box @@ -62,32 +62,32 @@ RAM128X1D 7 0 17 2 $__ABC_ASYNC 1000 0 2 1 0 764 -# Inputs: $pastQ C CE D R +# Inputs: C CE D R \$pastQ # Outputs: Q FDRE 1001 1 5 1 -0 - 0 0 0 +- 109 -46 358 0 -# Inputs: $pastQ C CE D R +# Inputs: C CE D R \$pastQ # Outputs: Q FDRE_1 1002 1 5 1 -0 - 109 -46 358 +- 109 -46 358 0 -# Inputs: $pastQ C CE CLR D +# Inputs: C CE CLR D \$pastQ # Outputs: Q FDCE 1003 1 5 1 -0 - 109 - -46 +- 109 - -46 0 -# Inputs: $pastQ C CE CLR D +# Inputs: C CE CLR D \$pastQ # Outputs: Q -FDCE_1 1004 1 5 1 -0 - 109 - -46 +FDCE_1004 1 1 5 1 +- 109 - -46 0 -# Inputs: $pastQ C CE D PRE +# Inputs: C CE D PRE \$pastQ # Outputs: Q FDPE 1005 1 5 1 -0 - 109 -46 - +- 109 -46 - 0 -# Inputs: $pastQ C CE D PRE +# Inputs: C CE D PRE \$pastQ # Outputs: Q FDPE_1 1006 1 5 1 -0 - 109 -46 - +- 109 -46 - 0 -- cgit v1.2.3 From 3ef927647c04bccce1d72751f6fb95ac4ac7e98b Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Thu, 11 Jul 2019 14:25:47 -0700 Subject: Fix FDCE_1 box --- techlibs/xilinx/abc_xc7.box | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'techlibs/xilinx/abc_xc7.box') diff --git a/techlibs/xilinx/abc_xc7.box b/techlibs/xilinx/abc_xc7.box index 24512ecf7..73f532711 100644 --- a/techlibs/xilinx/abc_xc7.box +++ b/techlibs/xilinx/abc_xc7.box @@ -79,7 +79,7 @@ FDCE 1003 1 5 1 # Inputs: C CE CLR D \$pastQ # Outputs: Q -FDCE_1004 1 1 5 1 +FDCE_1 1004 1 5 1 - 109 - -46 0 # Inputs: C CE D PRE \$pastQ -- cgit v1.2.3 From d386177e6d99ea2b3ef4b798653c0b1d7786e6b8 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Thu, 11 Jul 2019 17:09:17 -0700 Subject: ABC doesn't like negative delays in flop boxes... --- techlibs/xilinx/abc_xc7.box | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) (limited to 'techlibs/xilinx/abc_xc7.box') diff --git a/techlibs/xilinx/abc_xc7.box b/techlibs/xilinx/abc_xc7.box index 73f532711..f59cdcde8 100644 --- a/techlibs/xilinx/abc_xc7.box +++ b/techlibs/xilinx/abc_xc7.box @@ -65,29 +65,29 @@ $__ABC_ASYNC 1000 0 2 1 # Inputs: C CE D R \$pastQ # Outputs: Q FDRE 1001 1 5 1 -- 109 -46 358 0 +0 109 0 358 0 # Inputs: C CE D R \$pastQ # Outputs: Q FDRE_1 1002 1 5 1 -- 109 -46 358 0 +0 109 0 358 0 # Inputs: C CE CLR D \$pastQ # Outputs: Q FDCE 1003 1 5 1 -- 109 - -46 0 +0 109 764 0 0 # Inputs: C CE CLR D \$pastQ # Outputs: Q FDCE_1 1004 1 5 1 -- 109 - -46 0 +0 109 764 0 0 # Inputs: C CE D PRE \$pastQ # Outputs: Q FDPE 1005 1 5 1 -- 109 -46 - 0 +0 109 0 764 0 # Inputs: C CE D PRE \$pastQ # Outputs: Q FDPE_1 1006 1 5 1 -- 109 -46 - 0 +0 109 0 764 0 -- cgit v1.2.3 From 1c9f3fadb9f60653fc9d1d7d72ba22033e077468 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Thu, 11 Jul 2019 17:17:26 -0700 Subject: Add Tsu offset to boxes, and comments --- techlibs/xilinx/abc_xc7.box | 17 +++++++++++------ 1 file changed, 11 insertions(+), 6 deletions(-) (limited to 'techlibs/xilinx/abc_xc7.box') diff --git a/techlibs/xilinx/abc_xc7.box b/techlibs/xilinx/abc_xc7.box index f59cdcde8..044ed1bff 100644 --- a/techlibs/xilinx/abc_xc7.box +++ b/techlibs/xilinx/abc_xc7.box @@ -14,6 +14,7 @@ F7MUX 1 1 3 1 MUXF8 2 1 3 1 104 94 273 +# Box containing MUXF7.[AB] + MUXF8 # Inputs: I0 I1 I2 I3 S0 S1 # Outputs: O $__MUXF78 3 1 6 1 @@ -57,37 +58,41 @@ RAM128X1D 7 0 17 2 - - - - - - - - 1009 998 839 774 605 494 450 - - 1047 1036 877 812 643 532 478 - - - - - - - - - - +# Box to emulate async behaviour of FD[CP]* # Inputs: A S # Outputs: Y $__ABC_ASYNC 1000 0 2 1 0 764 +# The following FD*.{CE,R,CLR,PRE) are offset by 46ps to +# reflect the -46ps Tsu + # Inputs: C CE D R \$pastQ # Outputs: Q FDRE 1001 1 5 1 -0 109 0 358 0 +0 155 0 404 0 # Inputs: C CE D R \$pastQ # Outputs: Q FDRE_1 1002 1 5 1 -0 109 0 358 0 +0 155 0 404 0 # Inputs: C CE CLR D \$pastQ # Outputs: Q FDCE 1003 1 5 1 -0 109 764 0 0 +0 155 810 0 0 # Inputs: C CE CLR D \$pastQ # Outputs: Q FDCE_1 1004 1 5 1 -0 109 764 0 0 +0 155 810 0 0 # Inputs: C CE D PRE \$pastQ # Outputs: Q FDPE 1005 1 5 1 -0 109 0 764 0 +0 155 0 810 0 # Inputs: C CE D PRE \$pastQ # Outputs: Q FDPE_1 1006 1 5 1 -0 109 0 764 0 +0 155 0 810 0 -- cgit v1.2.3 From f25837f8e8482036a761fc631f7f79e5a2c777c5 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Mon, 19 Aug 2019 11:31:40 -0700 Subject: Update box timings --- techlibs/xilinx/abc_xc7.box | 15 +++++++++------ 1 file changed, 9 insertions(+), 6 deletions(-) (limited to 'techlibs/xilinx/abc_xc7.box') diff --git a/techlibs/xilinx/abc_xc7.box b/techlibs/xilinx/abc_xc7.box index 044ed1bff..16040662c 100644 --- a/techlibs/xilinx/abc_xc7.box +++ b/techlibs/xilinx/abc_xc7.box @@ -1,4 +1,5 @@ # Max delays from https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLL_L.sdf +# https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/slicel.sdf # NB: Inputs/Outputs must be ordered alphabetically # (with exceptions for carry in/out) @@ -66,33 +67,35 @@ $__ABC_ASYNC 1000 0 2 1 # The following FD*.{CE,R,CLR,PRE) are offset by 46ps to # reflect the -46ps Tsu +# https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/slicel.sdf#L237-L251 +# https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/slicel.sdf#L265-L277 # Inputs: C CE D R \$pastQ # Outputs: Q FDRE 1001 1 5 1 -0 155 0 404 0 +0 151 0 446 0 # Inputs: C CE D R \$pastQ # Outputs: Q FDRE_1 1002 1 5 1 -0 155 0 404 0 +0 151 0 446 0 # Inputs: C CE CLR D \$pastQ # Outputs: Q FDCE 1003 1 5 1 -0 155 810 0 0 +0 151 806 0 0 # Inputs: C CE CLR D \$pastQ # Outputs: Q FDCE_1 1004 1 5 1 -0 155 810 0 0 +0 151 806 0 0 # Inputs: C CE D PRE \$pastQ # Outputs: Q FDPE 1005 1 5 1 -0 155 0 810 0 +0 151 0 806 0 # Inputs: C CE D PRE \$pastQ # Outputs: Q FDPE_1 1006 1 5 1 -0 155 0 810 0 +0 151 0 806 0 -- cgit v1.2.3 From 808f07630fc79bf5f6e44986985dd07f83bb9d46 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Tue, 20 Aug 2019 14:49:11 -0700 Subject: Wrap LUTRAMs in order to capture comb/seq behaviour --- techlibs/xilinx/abc_xc7.box | 35 ++++++++++++++--------------------- 1 file changed, 14 insertions(+), 21 deletions(-) (limited to 'techlibs/xilinx/abc_xc7.box') diff --git a/techlibs/xilinx/abc_xc7.box b/techlibs/xilinx/abc_xc7.box index 16040662c..c08af6320 100644 --- a/techlibs/xilinx/abc_xc7.box +++ b/techlibs/xilinx/abc_xc7.box @@ -38,27 +38,6 @@ CARRY4 4 1 10 8 592 540 520 356 - 512 548 292 - 228 580 526 507 398 385 508 528 378 380 114 -# SLICEM/A6LUT -# Inputs: A0 A1 A2 A3 A4 D DPRA0 DPRA1 DPRA2 DPRA3 DPRA4 WCLK WE -# Outputs: DPO SPO -RAM32X1D 5 0 13 2 -- - - - - - 631 472 407 238 127 - - -631 472 407 238 127 - - - - - - - - - -# SLICEM/A6LUT -# Inputs: A0 A1 A2 A3 A4 A5 D DPRA0 DPRA1 DPRA2 DPRA3 DPRA4 DPRA5 WCLK WE -# Outputs: DPO SPO -RAM64X1D 6 0 15 2 -- - - - - - - 642 631 472 407 238 127 - - -642 631 472 407 238 127 - - - - - - - - - - -# SLICEM/A6LUT + F7[AB]MUX -# Inputs: A0 A1 A2 A3 A4 A5 A6 D DPRA0 DPRA1 DPRA2 DPRA3 DPRA4 DPRA5 DPRA6 WCLK WE -# Outputs: DPO SPO -RAM128X1D 7 0 17 2 -- - - - - - - - 1009 998 839 774 605 494 450 - - -1047 1036 877 812 643 532 478 - - - - - - - - - - - # Box to emulate async behaviour of FD[CP]* # Inputs: A S # Outputs: Y @@ -99,3 +78,17 @@ FDPE 1005 1 5 1 # Outputs: Q FDPE_1 1006 1 5 1 0 151 0 806 0 + +# SLICEM/A6LUT +# Box to emulate comb/seq behaviour of RAMD{32,64} and SRL{16,32} +# Inputs: A S0 S1 S2 S3 S4 S5 +# Outputs: Y +$__ABC_LUTRAM6 2000 0 7 1 +0 642 631 472 407 238 127 + +# SLICEM/A6LUT + F7BMUX +# Box to emulate comb/seq behaviour of RAMD128 +# Inputs: A S0 S1 S2 S3 S4 S5 S6 +# Outputs: DPO SPO +$__ABC_LUTRAM7 2001 0 8 1 +0 1047 1036 877 812 643 532 478 -- cgit v1.2.3 From 091bf4a18b2f4bf84fe62b61577c88d961468b3c Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Tue, 20 Aug 2019 18:16:37 -0700 Subject: Remove sequential extension --- techlibs/xilinx/abc_xc7.box | 41 ----------------------------------------- 1 file changed, 41 deletions(-) (limited to 'techlibs/xilinx/abc_xc7.box') diff --git a/techlibs/xilinx/abc_xc7.box b/techlibs/xilinx/abc_xc7.box index c08af6320..61b89b8af 100644 --- a/techlibs/xilinx/abc_xc7.box +++ b/techlibs/xilinx/abc_xc7.box @@ -38,47 +38,6 @@ CARRY4 4 1 10 8 592 540 520 356 - 512 548 292 - 228 580 526 507 398 385 508 528 378 380 114 -# Box to emulate async behaviour of FD[CP]* -# Inputs: A S -# Outputs: Y -$__ABC_ASYNC 1000 0 2 1 -0 764 - -# The following FD*.{CE,R,CLR,PRE) are offset by 46ps to -# reflect the -46ps Tsu -# https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/slicel.sdf#L237-L251 -# https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/slicel.sdf#L265-L277 - -# Inputs: C CE D R \$pastQ -# Outputs: Q -FDRE 1001 1 5 1 -0 151 0 446 0 - -# Inputs: C CE D R \$pastQ -# Outputs: Q -FDRE_1 1002 1 5 1 -0 151 0 446 0 - -# Inputs: C CE CLR D \$pastQ -# Outputs: Q -FDCE 1003 1 5 1 -0 151 806 0 0 - -# Inputs: C CE CLR D \$pastQ -# Outputs: Q -FDCE_1 1004 1 5 1 -0 151 806 0 0 - -# Inputs: C CE D PRE \$pastQ -# Outputs: Q -FDPE 1005 1 5 1 -0 151 0 806 0 - -# Inputs: C CE D PRE \$pastQ -# Outputs: Q -FDPE_1 1006 1 5 1 -0 151 0 806 0 - # SLICEM/A6LUT # Box to emulate comb/seq behaviour of RAMD{32,64} and SRL{16,32} # Inputs: A S0 S1 S2 S3 S4 S5 -- cgit v1.2.3 From c26c5563845d81048dea35c4aef5f4678e177b23 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Tue, 20 Aug 2019 19:47:11 -0700 Subject: xilinx to use abc_map.v with -max_iter 1 --- techlibs/xilinx/abc_xc7.box | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'techlibs/xilinx/abc_xc7.box') diff --git a/techlibs/xilinx/abc_xc7.box b/techlibs/xilinx/abc_xc7.box index 61b89b8af..554cc0cf0 100644 --- a/techlibs/xilinx/abc_xc7.box +++ b/techlibs/xilinx/abc_xc7.box @@ -42,12 +42,12 @@ CARRY4 4 1 10 8 # Box to emulate comb/seq behaviour of RAMD{32,64} and SRL{16,32} # Inputs: A S0 S1 S2 S3 S4 S5 # Outputs: Y -$__ABC_LUTRAM6 2000 0 7 1 +$__ABC_LUT6 2000 0 7 1 0 642 631 472 407 238 127 # SLICEM/A6LUT + F7BMUX # Box to emulate comb/seq behaviour of RAMD128 # Inputs: A S0 S1 S2 S3 S4 S5 S6 # Outputs: DPO SPO -$__ABC_LUTRAM7 2001 0 8 1 +$__ABC_LUT7 2001 0 8 1 0 1047 1036 877 812 643 532 478 -- cgit v1.2.3 From 3459d283492769263e73a0e35d0e5d253c0bbec7 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Mon, 2 Sep 2019 12:22:15 -0700 Subject: Add comments --- techlibs/xilinx/abc_xc7.box | 10 +++++++++- 1 file changed, 9 insertions(+), 1 deletion(-) (limited to 'techlibs/xilinx/abc_xc7.box') diff --git a/techlibs/xilinx/abc_xc7.box b/techlibs/xilinx/abc_xc7.box index 554cc0cf0..20da3b8a0 100644 --- a/techlibs/xilinx/abc_xc7.box +++ b/techlibs/xilinx/abc_xc7.box @@ -15,7 +15,10 @@ F7MUX 1 1 3 1 MUXF8 2 1 3 1 104 94 273 -# Box containing MUXF7.[AB] + MUXF8 +# Box containing MUXF7.[AB] + MUXF8, +# Necessary to make these an atomic unit so that +# ABC cannot optimise just one of the MUXF7 away +# and expect to save on its delay # Inputs: I0 I1 I2 I3 S0 S1 # Outputs: O $__MUXF78 3 1 6 1 @@ -40,6 +43,11 @@ CARRY4 4 1 10 8 # SLICEM/A6LUT # Box to emulate comb/seq behaviour of RAMD{32,64} and SRL{16,32} +# Necessary since RAMD* and SRL* have both combinatorial (i.e. +# same-cycle read operation) and sequential (write operation +# is only committed on the next clock edge). +# To model the combinatorial path, such cells have to be split +# into comb and seq parts, with this box modelling only the former. # Inputs: A S0 S1 S2 S3 S4 S5 # Outputs: Y $__ABC_LUT6 2000 0 7 1 -- cgit v1.2.3