From be9e4f1b674ef4fb3f02e99efcfda04ea27b2a68 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Tue, 20 Aug 2019 12:39:11 -0700 Subject: Use abc_{map,unmap,model}.v --- techlibs/xilinx/abc_model.v | 148 ++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 148 insertions(+) create mode 100644 techlibs/xilinx/abc_model.v (limited to 'techlibs/xilinx/abc_model.v') diff --git a/techlibs/xilinx/abc_model.v b/techlibs/xilinx/abc_model.v new file mode 100644 index 000000000..41c232650 --- /dev/null +++ b/techlibs/xilinx/abc_model.v @@ -0,0 +1,148 @@ +/* + * yosys -- Yosys Open SYnthesis Suite + * + * Copyright (C) 2012 Clifford Wolf + * 2019 Eddie Hung + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + * + */ + +// ============================================================================ + +(* abc_box_id = 3, lib_whitebox *) +module \$__XILINX_MUXF78 (output O, input I0, I1, I2, I3, S0, S1); + assign O = S1 ? (S0 ? I3 : I2) + : (S0 ? I1 : I0); +endmodule + +module \$__ABC_FF_ (input C, D, output Q); +endmodule + +(* abc_box_id = 1000 *) +module \$__ABC_ASYNC (input A, S, output Y); +endmodule + +(* abc_box_id=1001, lib_whitebox, abc_flop *) +module \$__ABC_FDRE ((* abc_flop_q, abc_arrival=303 *) output Q, + (* abc_flop_clk *) input C, + (* abc_flop_en *) input CE, + (* abc_flop_d *) input D, + input R, \$pastQ ); + parameter [0:0] INIT = 1'b0; + parameter [0:0] IS_C_INVERTED = 1'b0; + parameter [0:0] IS_D_INVERTED = 1'b0; + parameter [0:0] IS_R_INVERTED = 1'b0; + parameter CLK_POLARITY = !IS_C_INVERTED; + parameter EN_POLARITY = 1'b1; + assign Q = (R ^ IS_R_INVERTED) ? 1'b0 : (CE ? (D ^ IS_D_INVERTED) : \$pastQ ); +endmodule + +(* abc_box_id=1002, lib_whitebox, abc_flop *) +module \$__ABC_FDRE_1 ((* abc_flop_q, abc_arrival=303 *) output Q, + (* abc_flop_clk *) input C, + (* abc_flop_en *) input CE, + (* abc_flop_d *) input D, + input R, \$pastQ ); + parameter [0:0] INIT = 1'b0; + parameter CLK_POLARITY = 1'b0; + parameter EN_POLARITY = 1'b1; + assign Q = R ? 1'b0 : (CE ? D : \$pastQ ); +endmodule + +(* abc_box_id=1003, lib_whitebox, abc_flop *) +module \$__ABC_FDCE ((* abc_flop_q, abc_arrival=303 *) output Q, + (* abc_flop_clk *) input C, + (* abc_flop_en *) input CE, + (* abc_flop_d *) input D, + input CLR, \$pastQ ); + parameter [0:0] INIT = 1'b0; + parameter [0:0] IS_C_INVERTED = 1'b0; + parameter [0:0] IS_D_INVERTED = 1'b0; + parameter [0:0] IS_CLR_INVERTED = 1'b0; + parameter CLK_POLARITY = !IS_C_INVERTED; + parameter EN_POLARITY = 1'b1; + assign Q = (CE && !(CLR ^ IS_CLR_INVERTED)) ? (D ^ IS_D_INVERTED) : \$pastQ ; +endmodule + +(* abc_box_id=1004, lib_whitebox, abc_flop *) +module \$__ABC_FDCE_1 ((* abc_flop_q, abc_arrival=303 *) output Q, + (* abc_flop_clk *) input C, + (* abc_flop_en *) input CE, + (* abc_flop_d *) input D, + input CLR, \$pastQ ); + parameter [0:0] INIT = 1'b0; + parameter CLK_POLARITY = 1'b0; + parameter EN_POLARITY = 1'b1; + assign Q = (CE && !CLR) ? D : \$pastQ ; +endmodule + +(* abc_box_id=1005, lib_whitebox, abc_flop *) +module \$__ABC_FDPE ((* abc_flop_q, abc_arrival=303 *) output Q, + (* abc_flop_clk *) input C, + (* abc_flop_en *) input CE, + (* abc_flop_d *) input D, + input PRE, \$pastQ ); + parameter [0:0] INIT = 1'b0; + parameter [0:0] IS_C_INVERTED = 1'b0; + parameter [0:0] IS_D_INVERTED = 1'b0; + parameter [0:0] IS_PRE_INVERTED = 1'b0; + parameter CLK_POLARITY = !IS_C_INVERTED; + parameter EN_POLARITY = 1'b1; + assign Q = (CE && !(PRE ^ IS_PRE_INVERTED)) ? (D ^ IS_D_INVERTED) : \$pastQ ; +endmodule + +(* abc_box_id=1006, lib_whitebox, abc_flop *) +module \$__ABC_FDPE_1 ((* abc_flop_q, abc_arrival=303 *) output Q, + (* abc_flop_clk *) input C, + (* abc_flop_en *) input CE, + (* abc_flop_d *) input D, + input PRE, \$pastQ ); + parameter [0:0] INIT = 1'b0; + parameter CLK_POLARITY = 1'b0; + parameter EN_POLARITY = 1'b1; + assign Q = (CE && !PRE) ? D : \$pastQ ; +endmodule + +module \$__XILINX_MUXF78 (O, I0, I1, I2, I3, S0, S1); + output O; + input I0, I1, I2, I3, S0, S1; + wire T0, T1; + parameter _TECHMAP_BITS_CONNMAP_ = 0; + parameter [_TECHMAP_BITS_CONNMAP_-1:0] _TECHMAP_CONNMAP_I0_ = 0; + parameter [_TECHMAP_BITS_CONNMAP_-1:0] _TECHMAP_CONNMAP_I1_ = 0; + parameter [_TECHMAP_BITS_CONNMAP_-1:0] _TECHMAP_CONNMAP_I2_ = 0; + parameter [_TECHMAP_BITS_CONNMAP_-1:0] _TECHMAP_CONNMAP_I3_ = 0; + parameter _TECHMAP_CONSTMSK_S0_ = 0; + parameter _TECHMAP_CONSTVAL_S0_ = 0; + parameter _TECHMAP_CONSTMSK_S1_ = 0; + parameter _TECHMAP_CONSTVAL_S1_ = 0; + if (_TECHMAP_CONSTMSK_S0_ && _TECHMAP_CONSTVAL_S0_ === 1'b1) + assign T0 = I1; + else if (_TECHMAP_CONSTMSK_S0_ || _TECHMAP_CONNMAP_I0_ === _TECHMAP_CONNMAP_I1_) + assign T0 = I0; + else + MUXF7 mux7a (.I0(I0), .I1(I1), .S(S0), .O(T0)); + if (_TECHMAP_CONSTMSK_S0_ && _TECHMAP_CONSTVAL_S0_ === 1'b1) + assign T1 = I3; + else if (_TECHMAP_CONSTMSK_S0_ || _TECHMAP_CONNMAP_I2_ === _TECHMAP_CONNMAP_I3_) + assign T1 = I2; + else + MUXF7 mux7b (.I0(I2), .I1(I3), .S(S0), .O(T1)); + if (_TECHMAP_CONSTMSK_S1_ && _TECHMAP_CONSTVAL_S1_ === 1'b1) + assign O = T1; + else if (_TECHMAP_CONSTMSK_S1_ || (_TECHMAP_CONNMAP_I0_ === _TECHMAP_CONNMAP_I1_ && _TECHMAP_CONNMAP_I1_ === _TECHMAP_CONNMAP_I2_ && _TECHMAP_CONNMAP_I2_ === _TECHMAP_CONNMAP_I3_)) + assign O = T0; + else + MUXF8 mux8 (.I0(T0), .I1(T1), .S(S1), .O(O)); +endmodule -- cgit v1.2.3 From 8d0cffaf20c55c733bb5d286b5de1ed85cde77f6 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Tue, 20 Aug 2019 13:11:39 -0700 Subject: Remove mapping rules --- techlibs/xilinx/abc_model.v | 33 --------------------------------- 1 file changed, 33 deletions(-) (limited to 'techlibs/xilinx/abc_model.v') diff --git a/techlibs/xilinx/abc_model.v b/techlibs/xilinx/abc_model.v index 41c232650..243a93403 100644 --- a/techlibs/xilinx/abc_model.v +++ b/techlibs/xilinx/abc_model.v @@ -113,36 +113,3 @@ module \$__ABC_FDPE_1 ((* abc_flop_q, abc_arrival=303 *) output Q, parameter EN_POLARITY = 1'b1; assign Q = (CE && !PRE) ? D : \$pastQ ; endmodule - -module \$__XILINX_MUXF78 (O, I0, I1, I2, I3, S0, S1); - output O; - input I0, I1, I2, I3, S0, S1; - wire T0, T1; - parameter _TECHMAP_BITS_CONNMAP_ = 0; - parameter [_TECHMAP_BITS_CONNMAP_-1:0] _TECHMAP_CONNMAP_I0_ = 0; - parameter [_TECHMAP_BITS_CONNMAP_-1:0] _TECHMAP_CONNMAP_I1_ = 0; - parameter [_TECHMAP_BITS_CONNMAP_-1:0] _TECHMAP_CONNMAP_I2_ = 0; - parameter [_TECHMAP_BITS_CONNMAP_-1:0] _TECHMAP_CONNMAP_I3_ = 0; - parameter _TECHMAP_CONSTMSK_S0_ = 0; - parameter _TECHMAP_CONSTVAL_S0_ = 0; - parameter _TECHMAP_CONSTMSK_S1_ = 0; - parameter _TECHMAP_CONSTVAL_S1_ = 0; - if (_TECHMAP_CONSTMSK_S0_ && _TECHMAP_CONSTVAL_S0_ === 1'b1) - assign T0 = I1; - else if (_TECHMAP_CONSTMSK_S0_ || _TECHMAP_CONNMAP_I0_ === _TECHMAP_CONNMAP_I1_) - assign T0 = I0; - else - MUXF7 mux7a (.I0(I0), .I1(I1), .S(S0), .O(T0)); - if (_TECHMAP_CONSTMSK_S0_ && _TECHMAP_CONSTVAL_S0_ === 1'b1) - assign T1 = I3; - else if (_TECHMAP_CONSTMSK_S0_ || _TECHMAP_CONNMAP_I2_ === _TECHMAP_CONNMAP_I3_) - assign T1 = I2; - else - MUXF7 mux7b (.I0(I2), .I1(I3), .S(S0), .O(T1)); - if (_TECHMAP_CONSTMSK_S1_ && _TECHMAP_CONSTVAL_S1_ === 1'b1) - assign O = T1; - else if (_TECHMAP_CONSTMSK_S1_ || (_TECHMAP_CONNMAP_I0_ === _TECHMAP_CONNMAP_I1_ && _TECHMAP_CONNMAP_I1_ === _TECHMAP_CONNMAP_I2_ && _TECHMAP_CONNMAP_I2_ === _TECHMAP_CONNMAP_I3_)) - assign O = T0; - else - MUXF8 mux8 (.I0(T0), .I1(T1), .S(S1), .O(O)); -endmodule -- cgit v1.2.3 From 808f07630fc79bf5f6e44986985dd07f83bb9d46 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Tue, 20 Aug 2019 14:49:11 -0700 Subject: Wrap LUTRAMs in order to capture comb/seq behaviour --- techlibs/xilinx/abc_model.v | 44 ++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 44 insertions(+) (limited to 'techlibs/xilinx/abc_model.v') diff --git a/techlibs/xilinx/abc_model.v b/techlibs/xilinx/abc_model.v index 243a93403..76ef41a91 100644 --- a/techlibs/xilinx/abc_model.v +++ b/techlibs/xilinx/abc_model.v @@ -113,3 +113,47 @@ module \$__ABC_FDPE_1 ((* abc_flop_q, abc_arrival=303 *) output Q, parameter EN_POLARITY = 1'b1; assign Q = (CE && !PRE) ? D : \$pastQ ; endmodule + +(* abc_box_id=2000 *) +module \$__ABC_LUTMUX6 (input A, input [5:0] S, output Y); +endmodule +(* abc_box_id=2001 *) +module \$__ABC_LUTMUX7 (input A, input [6:0] S, output Y); +endmodule + + +module \$__ABC_RAM32X1D ( + // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L904-L905 + (* abc_arrival=1472 *) output DPO, SPO, + input D, + input WCLK, + input WE, + input A0, A1, A2, A3, A4, + input DPRA0, DPRA1, DPRA2, DPRA3, DPRA4 +); +endmodule + +module \$__ABC_RAM64X1D ( + // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L904-L905 + (* abc_arrival=1472 *) output DPO, SPO, + input D, + input WCLK, + input WE, + input A0, A1, A2, A3, A4, A5, + input DPRA0, DPRA1, DPRA2, DPRA3, DPRA4, DPRA5 +); + parameter INIT = 64'h0; + parameter IS_WCLK_INVERTED = 1'b0; +endmodule + +module \$__ABC_RAM128X1D ( + // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L904-L905 + (* abc_arrival=1472 *) output DPO, SPO, + input D, + input WCLK, + input WE, + input [6:0] A, DPRA +); + parameter INIT = 128'h0; + parameter IS_WCLK_INVERTED = 1'b0; +endmodule -- cgit v1.2.3 From e273ed52758599cb156cf3c309905da70826fe2d Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Tue, 20 Aug 2019 15:09:38 -0700 Subject: Wrap SRL{16,32} too --- techlibs/xilinx/abc_model.v | 32 ++++++++++++++++++++++++++------ 1 file changed, 26 insertions(+), 6 deletions(-) (limited to 'techlibs/xilinx/abc_model.v') diff --git a/techlibs/xilinx/abc_model.v b/techlibs/xilinx/abc_model.v index 76ef41a91..7162bd213 100644 --- a/techlibs/xilinx/abc_model.v +++ b/techlibs/xilinx/abc_model.v @@ -123,8 +123,8 @@ endmodule module \$__ABC_RAM32X1D ( - // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L904-L905 - (* abc_arrival=1472 *) output DPO, SPO, + // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L957 + (* abc_arrival=1153 *) output DPO, SPO, input D, input WCLK, input WE, @@ -134,8 +134,8 @@ module \$__ABC_RAM32X1D ( endmodule module \$__ABC_RAM64X1D ( - // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L904-L905 - (* abc_arrival=1472 *) output DPO, SPO, + // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L957 + (* abc_arrival=1153 *) output DPO, SPO, input D, input WCLK, input WE, @@ -147,8 +147,8 @@ module \$__ABC_RAM64X1D ( endmodule module \$__ABC_RAM128X1D ( - // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L904-L905 - (* abc_arrival=1472 *) output DPO, SPO, + // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L957 + (* abc_arrival=1153 *) output DPO, SPO, input D, input WCLK, input WE, @@ -157,3 +157,23 @@ module \$__ABC_RAM128X1D ( parameter INIT = 128'h0; parameter IS_WCLK_INVERTED = 1'b0; endmodule + +module SRL16E ( + // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L904-L905 + (* abc_arrival=1472 *) output Q, + input A0, A1, A2, A3, CE, CLK, D +); + parameter [15:0] INIT = 16'h0000; + parameter [0:0] IS_CLK_INVERTED = 1'b0; +endmodule + +module SRLC32E ( + // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L904-L905 + (* abc_arrival=1472 *) output Q, + (* abc_arrival=1114 *) output Q31, + input [4:0] A, + input CE, CLK, D +); + parameter [31:0] INIT = 32'h00000000; + parameter [0:0] IS_CLK_INVERTED = 1'b0; +endmodule -- cgit v1.2.3 From 091bf4a18b2f4bf84fe62b61577c88d961468b3c Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Tue, 20 Aug 2019 18:16:37 -0700 Subject: Remove sequential extension --- techlibs/xilinx/abc_model.v | 89 --------------------------------------------- 1 file changed, 89 deletions(-) (limited to 'techlibs/xilinx/abc_model.v') diff --git a/techlibs/xilinx/abc_model.v b/techlibs/xilinx/abc_model.v index 7162bd213..e3e9686b5 100644 --- a/techlibs/xilinx/abc_model.v +++ b/techlibs/xilinx/abc_model.v @@ -26,94 +26,6 @@ module \$__XILINX_MUXF78 (output O, input I0, I1, I2, I3, S0, S1); : (S0 ? I1 : I0); endmodule -module \$__ABC_FF_ (input C, D, output Q); -endmodule - -(* abc_box_id = 1000 *) -module \$__ABC_ASYNC (input A, S, output Y); -endmodule - -(* abc_box_id=1001, lib_whitebox, abc_flop *) -module \$__ABC_FDRE ((* abc_flop_q, abc_arrival=303 *) output Q, - (* abc_flop_clk *) input C, - (* abc_flop_en *) input CE, - (* abc_flop_d *) input D, - input R, \$pastQ ); - parameter [0:0] INIT = 1'b0; - parameter [0:0] IS_C_INVERTED = 1'b0; - parameter [0:0] IS_D_INVERTED = 1'b0; - parameter [0:0] IS_R_INVERTED = 1'b0; - parameter CLK_POLARITY = !IS_C_INVERTED; - parameter EN_POLARITY = 1'b1; - assign Q = (R ^ IS_R_INVERTED) ? 1'b0 : (CE ? (D ^ IS_D_INVERTED) : \$pastQ ); -endmodule - -(* abc_box_id=1002, lib_whitebox, abc_flop *) -module \$__ABC_FDRE_1 ((* abc_flop_q, abc_arrival=303 *) output Q, - (* abc_flop_clk *) input C, - (* abc_flop_en *) input CE, - (* abc_flop_d *) input D, - input R, \$pastQ ); - parameter [0:0] INIT = 1'b0; - parameter CLK_POLARITY = 1'b0; - parameter EN_POLARITY = 1'b1; - assign Q = R ? 1'b0 : (CE ? D : \$pastQ ); -endmodule - -(* abc_box_id=1003, lib_whitebox, abc_flop *) -module \$__ABC_FDCE ((* abc_flop_q, abc_arrival=303 *) output Q, - (* abc_flop_clk *) input C, - (* abc_flop_en *) input CE, - (* abc_flop_d *) input D, - input CLR, \$pastQ ); - parameter [0:0] INIT = 1'b0; - parameter [0:0] IS_C_INVERTED = 1'b0; - parameter [0:0] IS_D_INVERTED = 1'b0; - parameter [0:0] IS_CLR_INVERTED = 1'b0; - parameter CLK_POLARITY = !IS_C_INVERTED; - parameter EN_POLARITY = 1'b1; - assign Q = (CE && !(CLR ^ IS_CLR_INVERTED)) ? (D ^ IS_D_INVERTED) : \$pastQ ; -endmodule - -(* abc_box_id=1004, lib_whitebox, abc_flop *) -module \$__ABC_FDCE_1 ((* abc_flop_q, abc_arrival=303 *) output Q, - (* abc_flop_clk *) input C, - (* abc_flop_en *) input CE, - (* abc_flop_d *) input D, - input CLR, \$pastQ ); - parameter [0:0] INIT = 1'b0; - parameter CLK_POLARITY = 1'b0; - parameter EN_POLARITY = 1'b1; - assign Q = (CE && !CLR) ? D : \$pastQ ; -endmodule - -(* abc_box_id=1005, lib_whitebox, abc_flop *) -module \$__ABC_FDPE ((* abc_flop_q, abc_arrival=303 *) output Q, - (* abc_flop_clk *) input C, - (* abc_flop_en *) input CE, - (* abc_flop_d *) input D, - input PRE, \$pastQ ); - parameter [0:0] INIT = 1'b0; - parameter [0:0] IS_C_INVERTED = 1'b0; - parameter [0:0] IS_D_INVERTED = 1'b0; - parameter [0:0] IS_PRE_INVERTED = 1'b0; - parameter CLK_POLARITY = !IS_C_INVERTED; - parameter EN_POLARITY = 1'b1; - assign Q = (CE && !(PRE ^ IS_PRE_INVERTED)) ? (D ^ IS_D_INVERTED) : \$pastQ ; -endmodule - -(* abc_box_id=1006, lib_whitebox, abc_flop *) -module \$__ABC_FDPE_1 ((* abc_flop_q, abc_arrival=303 *) output Q, - (* abc_flop_clk *) input C, - (* abc_flop_en *) input CE, - (* abc_flop_d *) input D, - input PRE, \$pastQ ); - parameter [0:0] INIT = 1'b0; - parameter CLK_POLARITY = 1'b0; - parameter EN_POLARITY = 1'b1; - assign Q = (CE && !PRE) ? D : \$pastQ ; -endmodule - (* abc_box_id=2000 *) module \$__ABC_LUTMUX6 (input A, input [5:0] S, output Y); endmodule @@ -121,7 +33,6 @@ endmodule module \$__ABC_LUTMUX7 (input A, input [6:0] S, output Y); endmodule - module \$__ABC_RAM32X1D ( // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L957 (* abc_arrival=1153 *) output DPO, SPO, -- cgit v1.2.3 From c26c5563845d81048dea35c4aef5f4678e177b23 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Tue, 20 Aug 2019 19:47:11 -0700 Subject: xilinx to use abc_map.v with -max_iter 1 --- techlibs/xilinx/abc_model.v | 60 ++------------------------------------------- 1 file changed, 2 insertions(+), 58 deletions(-) (limited to 'techlibs/xilinx/abc_model.v') diff --git a/techlibs/xilinx/abc_model.v b/techlibs/xilinx/abc_model.v index e3e9686b5..655b993f6 100644 --- a/techlibs/xilinx/abc_model.v +++ b/techlibs/xilinx/abc_model.v @@ -27,64 +27,8 @@ module \$__XILINX_MUXF78 (output O, input I0, I1, I2, I3, S0, S1); endmodule (* abc_box_id=2000 *) -module \$__ABC_LUTMUX6 (input A, input [5:0] S, output Y); +module \$__ABC_LUT6 (input A, input [5:0] S, output Y); endmodule (* abc_box_id=2001 *) -module \$__ABC_LUTMUX7 (input A, input [6:0] S, output Y); -endmodule - -module \$__ABC_RAM32X1D ( - // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L957 - (* abc_arrival=1153 *) output DPO, SPO, - input D, - input WCLK, - input WE, - input A0, A1, A2, A3, A4, - input DPRA0, DPRA1, DPRA2, DPRA3, DPRA4 -); -endmodule - -module \$__ABC_RAM64X1D ( - // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L957 - (* abc_arrival=1153 *) output DPO, SPO, - input D, - input WCLK, - input WE, - input A0, A1, A2, A3, A4, A5, - input DPRA0, DPRA1, DPRA2, DPRA3, DPRA4, DPRA5 -); - parameter INIT = 64'h0; - parameter IS_WCLK_INVERTED = 1'b0; -endmodule - -module \$__ABC_RAM128X1D ( - // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L957 - (* abc_arrival=1153 *) output DPO, SPO, - input D, - input WCLK, - input WE, - input [6:0] A, DPRA -); - parameter INIT = 128'h0; - parameter IS_WCLK_INVERTED = 1'b0; -endmodule - -module SRL16E ( - // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L904-L905 - (* abc_arrival=1472 *) output Q, - input A0, A1, A2, A3, CE, CLK, D -); - parameter [15:0] INIT = 16'h0000; - parameter [0:0] IS_CLK_INVERTED = 1'b0; -endmodule - -module SRLC32E ( - // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L904-L905 - (* abc_arrival=1472 *) output Q, - (* abc_arrival=1114 *) output Q31, - input [4:0] A, - input CE, CLK, D -); - parameter [31:0] INIT = 32'h00000000; - parameter [0:0] IS_CLK_INVERTED = 1'b0; +module \$__ABC_LUT7 (input A, input [6:0] S, output Y); endmodule -- cgit v1.2.3 From 6bb8e6a7267b4e3d8c1717cde87d41d04fdac82d Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Thu, 12 Sep 2019 17:11:01 -0700 Subject: Initial DSP48E1 box support --- techlibs/xilinx/abc_model.v | 108 ++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 108 insertions(+) (limited to 'techlibs/xilinx/abc_model.v') diff --git a/techlibs/xilinx/abc_model.v b/techlibs/xilinx/abc_model.v index 655b993f6..95a368306 100644 --- a/techlibs/xilinx/abc_model.v +++ b/techlibs/xilinx/abc_model.v @@ -20,15 +20,123 @@ // ============================================================================ +// Box containing MUXF7.[AB] + MUXF8, +// Necessary to make these an atomic unit so that +// ABC cannot optimise just one of the MUXF7 away +// and expect to save on its delay (* abc_box_id = 3, lib_whitebox *) module \$__XILINX_MUXF78 (output O, input I0, I1, I2, I3, S0, S1); assign O = S1 ? (S0 ? I3 : I2) : (S0 ? I1 : I0); endmodule +// Box to emulate comb/seq behaviour of RAMD{32,64} and SRL{16,32} +// Necessary since RAMD* and SRL* have both combinatorial (i.e. +// same-cycle read operation) and sequential (write operation +// is only committed on the next clock edge). +// To model the combinatorial path, such cells have to be split +// into comb and seq parts, with this box modelling only the former. (* abc_box_id=2000 *) module \$__ABC_LUT6 (input A, input [5:0] S, output Y); endmodule +// Box to emulate comb/seq behaviour of RAMD128 (* abc_box_id=2001 *) module \$__ABC_LUT7 (input A, input [6:0] S, output Y); endmodule + +(* abc_box_id=2100 *) +module \$__ABC_DSP48E1_MULT_P_MUX (input Aq, ADq, Bq, Cq, Dq, Mq, input [47:0] P, input Pq, output [47:0] O); +endmodule +(* abc_box_id=2101 *) +module \$__ABC_DSP48E1_MULT_PCOUT_MUX (input Aq, ADq, Bq, Cq, Dq, Mq, input [47:0] P, input Pq, output [47:0] O); +endmodule + +// Box used to represent the comb/seq behaviour of DSP48E1 +// abc_map.v is responsible for disconnecting inputs to +// the combinatorial DSP48E1 model by a register (e.g. +// disconnecting A when AREG, MREG or PREG is enabled) +(* abc_box_id=3000 *) +module \$__ABC_DSP48E1_MULT ( + output [29:0] ACOUT, + output [17:0] BCOUT, + output reg CARRYCASCOUT, + output reg [3:0] CARRYOUT, + output reg MULTSIGNOUT, + output OVERFLOW, + output reg signed [47:0] P, + output PATTERNBDETECT, + output PATTERNDETECT, + output [47:0] PCOUT, + output UNDERFLOW, + input signed [29:0] A, + input [29:0] ACIN, + input [3:0] ALUMODE, + input signed [17:0] B, + input [17:0] BCIN, + input [47:0] C, + input CARRYCASCIN, + input CARRYIN, + input [2:0] CARRYINSEL, + input CEA1, + input CEA2, + input CEAD, + input CEALUMODE, + input CEB1, + input CEB2, + input CEC, + input CECARRYIN, + input CECTRL, + input CED, + input CEINMODE, + input CEM, + input CEP, + input CLK, + input [24:0] D, + input [4:0] INMODE, + input MULTSIGNIN, + input [6:0] OPMODE, + input [47:0] PCIN, + input RSTA, + input RSTALLCARRYIN, + input RSTALUMODE, + input RSTB, + input RSTC, + input RSTCTRL, + input RSTD, + input RSTINMODE, + input RSTM, + input RSTP +); + parameter integer ACASCREG = 1; + parameter integer ADREG = 1; + parameter integer ALUMODEREG = 1; + parameter integer AREG = 1; + parameter AUTORESET_PATDET = "NO_RESET"; + parameter A_INPUT = "DIRECT"; + parameter integer BCASCREG = 1; + parameter integer BREG = 1; + parameter B_INPUT = "DIRECT"; + parameter integer CARRYINREG = 1; + parameter integer CARRYINSELREG = 1; + parameter integer CREG = 1; + parameter integer DREG = 1; + parameter integer INMODEREG = 1; + parameter integer MREG = 1; + parameter integer OPMODEREG = 1; + parameter integer PREG = 1; + parameter SEL_MASK = "MASK"; + parameter SEL_PATTERN = "PATTERN"; + parameter USE_DPORT = "FALSE"; + parameter USE_MULT = "MULTIPLY"; + parameter USE_PATTERN_DETECT = "NO_PATDET"; + parameter USE_SIMD = "ONE48"; + parameter [47:0] MASK = 48'h3FFFFFFFFFFF; + parameter [47:0] PATTERN = 48'h000000000000; + parameter [3:0] IS_ALUMODE_INVERTED = 4'b0; + parameter [0:0] IS_CARRYIN_INVERTED = 1'b0; + parameter [0:0] IS_CLK_INVERTED = 1'b0; + parameter [4:0] IS_INMODE_INVERTED = 5'b0; + parameter [6:0] IS_OPMODE_INVERTED = 7'b0; +endmodule + + -- cgit v1.2.3 From c52863f147c45727dc38dd349f3f5d756baf27ce Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Thu, 12 Sep 2019 18:01:49 -0700 Subject: Finish explanation --- techlibs/xilinx/abc_model.v | 14 ++++++++++---- 1 file changed, 10 insertions(+), 4 deletions(-) (limited to 'techlibs/xilinx/abc_model.v') diff --git a/techlibs/xilinx/abc_model.v b/techlibs/xilinx/abc_model.v index 95a368306..504f8a0d8 100644 --- a/techlibs/xilinx/abc_model.v +++ b/techlibs/xilinx/abc_model.v @@ -44,6 +44,16 @@ endmodule module \$__ABC_LUT7 (input A, input [6:0] S, output Y); endmodule +// Boxes used to represent the comb/seq behaviour of DSP48E1 +// With abc_map.v responsible for disconnecting inputs to +// the combinatorial DSP48E1 model by a register (e.g. +// disconnecting A when AREG, MREG or PREG is enabled) +// this mux captures the existence of a replacement path +// between AREG/BREG/CREG/etc. and P/PCOUT. +// Since the Aq/ADq/Bq/etc. inputs are assumed to arrive at +// the mux at zero time, the combinatorial delay through +// these muxes thus represents the clock-to-q delay at +// P/PCOUT. (* abc_box_id=2100 *) module \$__ABC_DSP48E1_MULT_P_MUX (input Aq, ADq, Bq, Cq, Dq, Mq, input [47:0] P, input Pq, output [47:0] O); endmodule @@ -51,10 +61,6 @@ endmodule module \$__ABC_DSP48E1_MULT_PCOUT_MUX (input Aq, ADq, Bq, Cq, Dq, Mq, input [47:0] P, input Pq, output [47:0] O); endmodule -// Box used to represent the comb/seq behaviour of DSP48E1 -// abc_map.v is responsible for disconnecting inputs to -// the combinatorial DSP48E1 model by a register (e.g. -// disconnecting A when AREG, MREG or PREG is enabled) (* abc_box_id=3000 *) module \$__ABC_DSP48E1_MULT ( output [29:0] ACOUT, -- cgit v1.2.3 From 734034a8727023fdb74c9a6acd2cb6d1bfe3e81c Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Thu, 12 Sep 2019 18:13:46 -0700 Subject: Add an ASCII drawing --- techlibs/xilinx/abc_model.v | 25 ++++++++++++++++++++++--- 1 file changed, 22 insertions(+), 3 deletions(-) (limited to 'techlibs/xilinx/abc_model.v') diff --git a/techlibs/xilinx/abc_model.v b/techlibs/xilinx/abc_model.v index 504f8a0d8..109804f09 100644 --- a/techlibs/xilinx/abc_model.v +++ b/techlibs/xilinx/abc_model.v @@ -48,12 +48,31 @@ endmodule // With abc_map.v responsible for disconnecting inputs to // the combinatorial DSP48E1 model by a register (e.g. // disconnecting A when AREG, MREG or PREG is enabled) -// this mux captures the existence of a replacement path -// between AREG/BREG/CREG/etc. and P/PCOUT. +// this blackbox captures the existence of a replacement +// path between AREG/BREG/CREG/etc. and P/PCOUT. // Since the Aq/ADq/Bq/etc. inputs are assumed to arrive at -// the mux at zero time, the combinatorial delay through +// the box at zero time, the combinatorial delay through // these muxes thus represents the clock-to-q delay at // P/PCOUT. +// Doing so should means that ABC is able to analyse the +// worst-case delay through to P. +// However, the true value of being as complete as this is +// questionable since if AREG=1 and BREG=0 (as below) +// then the worse-case path would very likely be through B +// and very unlikely to be through AREG.Q...? +// +// In graphical form: +// +// NEW "PI" >>---+ +// for AREG.Q | +// | +// +---------+ | __ +// A --X X-| | +--| \ +// | DSP48E1 |P | |--- P +// | AREG=1 |-------|__/ +// B ------| | +// +---------+ +// (* abc_box_id=2100 *) module \$__ABC_DSP48E1_MULT_P_MUX (input Aq, ADq, Bq, Cq, Dq, Mq, input [47:0] P, input Pq, output [47:0] O); endmodule -- cgit v1.2.3 From e235dd07854ad31617a4609c59dbdeacb9323ad0 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Fri, 13 Sep 2019 09:34:40 -0700 Subject: Refine diagram --- techlibs/xilinx/abc_model.v | 26 ++++++++++++++------------ 1 file changed, 14 insertions(+), 12 deletions(-) (limited to 'techlibs/xilinx/abc_model.v') diff --git a/techlibs/xilinx/abc_model.v b/techlibs/xilinx/abc_model.v index 109804f09..5963258e8 100644 --- a/techlibs/xilinx/abc_model.v +++ b/techlibs/xilinx/abc_model.v @@ -52,10 +52,12 @@ endmodule // path between AREG/BREG/CREG/etc. and P/PCOUT. // Since the Aq/ADq/Bq/etc. inputs are assumed to arrive at // the box at zero time, the combinatorial delay through -// these muxes thus represents the clock-to-q delay at -// P/PCOUT. +// these boxes thus represents the clock-to-q delay +// (arrival time) at P/PCOUT. // Doing so should means that ABC is able to analyse the -// worst-case delay through to P. +// worst-case delay through to P, regardless of if it was +// through any combinatorial paths (e.g. B, below) or an +// internal register (A2REG). // However, the true value of being as complete as this is // questionable since if AREG=1 and BREG=0 (as below) // then the worse-case path would very likely be through B @@ -63,15 +65,15 @@ endmodule // // In graphical form: // -// NEW "PI" >>---+ -// for AREG.Q | -// | -// +---------+ | __ -// A --X X-| | +--| \ -// | DSP48E1 |P | |--- P -// | AREG=1 |-------|__/ -// B ------| | -// +---------+ +// NEW "PI" >>---+ +// for AREG.Q | +// | +// +---------+ | __ +// A >>--X X-| | +--| \ +// | DSP48E1 |P | |--->> P +// | AREG=1 |-------|__/ +// B >>------| | +// +---------+ // (* abc_box_id=2100 *) module \$__ABC_DSP48E1_MULT_P_MUX (input Aq, ADq, Bq, Cq, Dq, Mq, input [47:0] P, input Pq, output [47:0] O); -- cgit v1.2.3 From 247a63f55df2e85f0aa15a9a05f436c1225f9ec1 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Fri, 13 Sep 2019 11:45:55 -0700 Subject: Add support for MULT and DPORT --- techlibs/xilinx/abc_model.v | 90 ++++++++++++++++++++++++++++++++++++++++++++- 1 file changed, 89 insertions(+), 1 deletion(-) (limited to 'techlibs/xilinx/abc_model.v') diff --git a/techlibs/xilinx/abc_model.v b/techlibs/xilinx/abc_model.v index 5963258e8..4310ad39e 100644 --- a/techlibs/xilinx/abc_model.v +++ b/techlibs/xilinx/abc_model.v @@ -81,6 +81,12 @@ endmodule (* abc_box_id=2101 *) module \$__ABC_DSP48E1_MULT_PCOUT_MUX (input Aq, ADq, Bq, Cq, Dq, Mq, input [47:0] P, input Pq, output [47:0] O); endmodule +(* abc_box_id=2102 *) +module \$__ABC_DSP48E1_MULT_DPORT_P_MUX (input Aq, ADq, Bq, Cq, Dq, Mq, input [47:0] P, input Pq, output [47:0] O); +endmodule +(* abc_box_id=2103 *) +module \$__ABC_DSP48E1_MULT_DPORT_PCOUT_MUX (input Aq, ADq, Bq, Cq, Dq, Mq, input [47:0] P, input Pq, output [47:0] O); +endmodule (* abc_box_id=3000 *) module \$__ABC_DSP48E1_MULT ( @@ -166,4 +172,86 @@ module \$__ABC_DSP48E1_MULT ( parameter [6:0] IS_OPMODE_INVERTED = 7'b0; endmodule - +(* abc_box_id=3001 *) +module \$__ABC_DSP48E1_MULT_DPORT ( + output [29:0] ACOUT, + output [17:0] BCOUT, + output reg CARRYCASCOUT, + output reg [3:0] CARRYOUT, + output reg MULTSIGNOUT, + output OVERFLOW, + output reg signed [47:0] P, + output PATTERNBDETECT, + output PATTERNDETECT, + output [47:0] PCOUT, + output UNDERFLOW, + input signed [29:0] A, + input [29:0] ACIN, + input [3:0] ALUMODE, + input signed [17:0] B, + input [17:0] BCIN, + input [47:0] C, + input CARRYCASCIN, + input CARRYIN, + input [2:0] CARRYINSEL, + input CEA1, + input CEA2, + input CEAD, + input CEALUMODE, + input CEB1, + input CEB2, + input CEC, + input CECARRYIN, + input CECTRL, + input CED, + input CEINMODE, + input CEM, + input CEP, + input CLK, + input [24:0] D, + input [4:0] INMODE, + input MULTSIGNIN, + input [6:0] OPMODE, + input [47:0] PCIN, + input RSTA, + input RSTALLCARRYIN, + input RSTALUMODE, + input RSTB, + input RSTC, + input RSTCTRL, + input RSTD, + input RSTINMODE, + input RSTM, + input RSTP +); + parameter integer ACASCREG = 1; + parameter integer ADREG = 1; + parameter integer ALUMODEREG = 1; + parameter integer AREG = 1; + parameter AUTORESET_PATDET = "NO_RESET"; + parameter A_INPUT = "DIRECT"; + parameter integer BCASCREG = 1; + parameter integer BREG = 1; + parameter B_INPUT = "DIRECT"; + parameter integer CARRYINREG = 1; + parameter integer CARRYINSELREG = 1; + parameter integer CREG = 1; + parameter integer DREG = 1; + parameter integer INMODEREG = 1; + parameter integer MREG = 1; + parameter integer OPMODEREG = 1; + parameter integer PREG = 1; + parameter SEL_MASK = "MASK"; + parameter SEL_PATTERN = "PATTERN"; + parameter USE_DPORT = "FALSE"; + parameter USE_MULT = "MULTIPLY"; + parameter USE_PATTERN_DETECT = "NO_PATDET"; + parameter USE_SIMD = "ONE48"; + parameter [47:0] MASK = 48'h3FFFFFFFFFFF; + parameter [47:0] PATTERN = 48'h000000000000; + parameter [3:0] IS_ALUMODE_INVERTED = 4'b0; + parameter [0:0] IS_CARRYIN_INVERTED = 1'b0; + parameter [0:0] IS_CLK_INVERTED = 1'b0; + parameter [4:0] IS_INMODE_INVERTED = 5'b0; + parameter [6:0] IS_OPMODE_INVERTED = 7'b0; +endmodule -- cgit v1.2.3 From d0b202c58d45145e79243caac55f155328008d39 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Fri, 13 Sep 2019 12:05:14 -0700 Subject: Add no MULT no DPORT config --- techlibs/xilinx/abc_model.v | 110 ++++++-------------------------------------- 1 file changed, 14 insertions(+), 96 deletions(-) (limited to 'techlibs/xilinx/abc_model.v') diff --git a/techlibs/xilinx/abc_model.v b/techlibs/xilinx/abc_model.v index 4310ad39e..a8f6deafc 100644 --- a/techlibs/xilinx/abc_model.v +++ b/techlibs/xilinx/abc_model.v @@ -75,20 +75,18 @@ endmodule // B >>------| | // +---------+ // -(* abc_box_id=2100 *) -module \$__ABC_DSP48E1_MULT_P_MUX (input Aq, ADq, Bq, Cq, Dq, Mq, input [47:0] P, input Pq, output [47:0] O); -endmodule -(* abc_box_id=2101 *) -module \$__ABC_DSP48E1_MULT_PCOUT_MUX (input Aq, ADq, Bq, Cq, Dq, Mq, input [47:0] P, input Pq, output [47:0] O); -endmodule -(* abc_box_id=2102 *) -module \$__ABC_DSP48E1_MULT_DPORT_P_MUX (input Aq, ADq, Bq, Cq, Dq, Mq, input [47:0] P, input Pq, output [47:0] O); -endmodule -(* abc_box_id=2103 *) -module \$__ABC_DSP48E1_MULT_DPORT_PCOUT_MUX (input Aq, ADq, Bq, Cq, Dq, Mq, input [47:0] P, input Pq, output [47:0] O); +`define ABC_DSP48E1_MUX(__NAME__) """ +module __NAME__ (input Aq, ADq, Bq, Cq, Dq, Mq, input [47:0] P, input Pq, output [47:0] O); endmodule +""" +(* abc_box_id=2100 *) `ABC_DSP48E1_MUX(\$__ABC_DSP48E1_MULT_P_MUX ) +(* abc_box_id=2101 *) `ABC_DSP48E1_MUX(\$__ABC_DSP48E1_MULT_PCOUT_MUX ) +(* abc_box_id=2102 *) `ABC_DSP48E1_MUX(\$__ABC_DSP48E1_MULT_DPORT_P_MUX ) +(* abc_box_id=2103 *) `ABC_DSP48E1_MUX(\$__ABC_DSP48E1_MULT_DPORT_PCOUT_MUX ) +(* abc_box_id=2104 *) `ABC_DSP48E1_MUX(\$__ABC_DSP48E1_P_MUX ) +(* abc_box_id=2105 *) `ABC_DSP48E1_MUX(\$__ABC_DSP48E1_PCOUT_MUX ) -(* abc_box_id=3000 *) +`define ABC_DSP48E1(__NAME__) """ module \$__ABC_DSP48E1_MULT ( output [29:0] ACOUT, output [17:0] BCOUT, @@ -171,87 +169,7 @@ module \$__ABC_DSP48E1_MULT ( parameter [4:0] IS_INMODE_INVERTED = 5'b0; parameter [6:0] IS_OPMODE_INVERTED = 7'b0; endmodule - -(* abc_box_id=3001 *) -module \$__ABC_DSP48E1_MULT_DPORT ( - output [29:0] ACOUT, - output [17:0] BCOUT, - output reg CARRYCASCOUT, - output reg [3:0] CARRYOUT, - output reg MULTSIGNOUT, - output OVERFLOW, - output reg signed [47:0] P, - output PATTERNBDETECT, - output PATTERNDETECT, - output [47:0] PCOUT, - output UNDERFLOW, - input signed [29:0] A, - input [29:0] ACIN, - input [3:0] ALUMODE, - input signed [17:0] B, - input [17:0] BCIN, - input [47:0] C, - input CARRYCASCIN, - input CARRYIN, - input [2:0] CARRYINSEL, - input CEA1, - input CEA2, - input CEAD, - input CEALUMODE, - input CEB1, - input CEB2, - input CEC, - input CECARRYIN, - input CECTRL, - input CED, - input CEINMODE, - input CEM, - input CEP, - input CLK, - input [24:0] D, - input [4:0] INMODE, - input MULTSIGNIN, - input [6:0] OPMODE, - input [47:0] PCIN, - input RSTA, - input RSTALLCARRYIN, - input RSTALUMODE, - input RSTB, - input RSTC, - input RSTCTRL, - input RSTD, - input RSTINMODE, - input RSTM, - input RSTP -); - parameter integer ACASCREG = 1; - parameter integer ADREG = 1; - parameter integer ALUMODEREG = 1; - parameter integer AREG = 1; - parameter AUTORESET_PATDET = "NO_RESET"; - parameter A_INPUT = "DIRECT"; - parameter integer BCASCREG = 1; - parameter integer BREG = 1; - parameter B_INPUT = "DIRECT"; - parameter integer CARRYINREG = 1; - parameter integer CARRYINSELREG = 1; - parameter integer CREG = 1; - parameter integer DREG = 1; - parameter integer INMODEREG = 1; - parameter integer MREG = 1; - parameter integer OPMODEREG = 1; - parameter integer PREG = 1; - parameter SEL_MASK = "MASK"; - parameter SEL_PATTERN = "PATTERN"; - parameter USE_DPORT = "FALSE"; - parameter USE_MULT = "MULTIPLY"; - parameter USE_PATTERN_DETECT = "NO_PATDET"; - parameter USE_SIMD = "ONE48"; - parameter [47:0] MASK = 48'h3FFFFFFFFFFF; - parameter [47:0] PATTERN = 48'h000000000000; - parameter [3:0] IS_ALUMODE_INVERTED = 4'b0; - parameter [0:0] IS_CARRYIN_INVERTED = 1'b0; - parameter [0:0] IS_CLK_INVERTED = 1'b0; - parameter [4:0] IS_INMODE_INVERTED = 5'b0; - parameter [6:0] IS_OPMODE_INVERTED = 7'b0; -endmodule +""" +(* abc_box_id=3000 *) `ABC_DSP48E1(\$__ABC_DSP48E1_MULT ) +(* abc_box_id=3001 *) `ABC_DSP48E1(\$__ABC_DSP48E1_MULT_DPORT ) +(* abc_box_id=3002 *) `ABC_DSP48E1(\$__ABC_DSP48E1 ) -- cgit v1.2.3 From 41256f48a5f3231e231cbdf9380a26128f272044 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Thu, 19 Sep 2019 18:33:29 -0700 Subject: Different approach to timing --- techlibs/xilinx/abc_model.v | 105 ++++++++++++++++++++++++++------------------ 1 file changed, 63 insertions(+), 42 deletions(-) (limited to 'techlibs/xilinx/abc_model.v') diff --git a/techlibs/xilinx/abc_model.v b/techlibs/xilinx/abc_model.v index a8f6deafc..79cca6b7b 100644 --- a/techlibs/xilinx/abc_model.v +++ b/techlibs/xilinx/abc_model.v @@ -44,48 +44,6 @@ endmodule module \$__ABC_LUT7 (input A, input [6:0] S, output Y); endmodule -// Boxes used to represent the comb/seq behaviour of DSP48E1 -// With abc_map.v responsible for disconnecting inputs to -// the combinatorial DSP48E1 model by a register (e.g. -// disconnecting A when AREG, MREG or PREG is enabled) -// this blackbox captures the existence of a replacement -// path between AREG/BREG/CREG/etc. and P/PCOUT. -// Since the Aq/ADq/Bq/etc. inputs are assumed to arrive at -// the box at zero time, the combinatorial delay through -// these boxes thus represents the clock-to-q delay -// (arrival time) at P/PCOUT. -// Doing so should means that ABC is able to analyse the -// worst-case delay through to P, regardless of if it was -// through any combinatorial paths (e.g. B, below) or an -// internal register (A2REG). -// However, the true value of being as complete as this is -// questionable since if AREG=1 and BREG=0 (as below) -// then the worse-case path would very likely be through B -// and very unlikely to be through AREG.Q...? -// -// In graphical form: -// -// NEW "PI" >>---+ -// for AREG.Q | -// | -// +---------+ | __ -// A >>--X X-| | +--| \ -// | DSP48E1 |P | |--->> P -// | AREG=1 |-------|__/ -// B >>------| | -// +---------+ -// -`define ABC_DSP48E1_MUX(__NAME__) """ -module __NAME__ (input Aq, ADq, Bq, Cq, Dq, Mq, input [47:0] P, input Pq, output [47:0] O); -endmodule -""" -(* abc_box_id=2100 *) `ABC_DSP48E1_MUX(\$__ABC_DSP48E1_MULT_P_MUX ) -(* abc_box_id=2101 *) `ABC_DSP48E1_MUX(\$__ABC_DSP48E1_MULT_PCOUT_MUX ) -(* abc_box_id=2102 *) `ABC_DSP48E1_MUX(\$__ABC_DSP48E1_MULT_DPORT_P_MUX ) -(* abc_box_id=2103 *) `ABC_DSP48E1_MUX(\$__ABC_DSP48E1_MULT_DPORT_PCOUT_MUX ) -(* abc_box_id=2104 *) `ABC_DSP48E1_MUX(\$__ABC_DSP48E1_P_MUX ) -(* abc_box_id=2105 *) `ABC_DSP48E1_MUX(\$__ABC_DSP48E1_PCOUT_MUX ) - `define ABC_DSP48E1(__NAME__) """ module \$__ABC_DSP48E1_MULT ( output [29:0] ACOUT, @@ -173,3 +131,66 @@ endmodule (* abc_box_id=3000 *) `ABC_DSP48E1(\$__ABC_DSP48E1_MULT ) (* abc_box_id=3001 *) `ABC_DSP48E1(\$__ABC_DSP48E1_MULT_DPORT ) (* abc_box_id=3002 *) `ABC_DSP48E1(\$__ABC_DSP48E1 ) + + +// Modules used to model the comb/seq behaviour of DSP48E1 +// With abc_map.v responsible for splicing the below modules +// into between the combinatorial DSP48E1 box (e.g. disconnecting +// A when AREG, MREG or PREG is enabled and splicing in the +// "$__ABC_DSP48E1_MULT_AREG" blackbox as "REG" in the diagram +// below) this acts to first disables the combinatorial path +// (as there is no connectivity through REG), and secondly, +// since this is blackbox a new PI will be introduced, one which +// will have the relevant arrival time (corresponding to delay from +// AREG to P) attached. +// Note: Since these "$__ABC_DSP48E1*_*REG" modules are of a +// sequential nature, they are not passed as a box to ABC./ +// +// On the other hand, the "$__ABC_DSP48E1_MUX" is a combinatorial +// blackbox that is passed to ABC, with zero delay. +// +// Doing so should means that ABC is able to analyse the +// worst-case delay through to P, regardless of if it was +// through any combinatorial paths (e.g. B, below) or an +// internal register (A2REG). +// However, the true value of being as complete as this is +// questionable since if AREG=1 and BREG=0 (as below) +// then the worse-case path would very likely be through B +// and very unlikely to be through AREG.Q...? +// +// In graphical form: +// +// +-----+ +// +-------| REG |-----+ +// | +-----+ | +// | | +// | +---------+ | __ +// A >>-+X X-| | +--| \ +// | DSP48E1 |P | M |--->> P +// | AREG=1 |-------|__/ +// B >>------| | +// +---------+ +// + +(* abc_box_id=2100 *) +module \$__ABC_DSP48E1_MUX (input Aq, ADq, Bq, Cq, Dq, Mq, input [47:0] P, input Pq, output [47:0] O); +endmodule + +module $__ABC_DSP48E1_MULT_AREG (input [29:0] I, output [29:0] O, (* abc_arrival=2952 *) output P, (* abc_arrival=3098 *) output PCOUT); endmodule +module $__ABC_DSP48E1_MULT_BREG (input [17:0] I, output [17:0] O, (* abc_arrival=2813 *) output P, (* abc_arrival=2960 *) output PCOUT); endmodule +module $__ABC_DSP48E1_MULT_CREG (input [47:0] I, output [47:0] O, (* abc_arrival=1687 *) output P, (* abc_arrival=1835 *) output PCOUT); endmodule +module $__ABC_DSP48E1_MULT_MREG (input [47:0] I, output [47:0] O, (* abc_arrival=1671 *) output P, (* abc_arrival=1819 *) output PCOUT); endmodule +module $__ABC_DSP48E1_MULT_PREG (input [47:0] I, output [47:0] O, (* abc_arrival= 329 *) output P, (* abc_arrival= 435 *) output PCOUT); endmodule + +module $__ABC_DSP48E1_MULT_DPORT_AREG (input [29:0] I, output [29:0] O, (* abc_arrival=3935 *) output P, (* abc_arrival=4083 *) output PCOUT); endmodule +module $__ABC_DSP48E1_MULT_DPORT_BREG (input [17:0] I, output [17:0] O, (* abc_arrival=2813 *) output P, (* abc_arrival=2960 *) output PCOUT); endmodule +module $__ABC_DSP48E1_MULT_DPORT_CREG (input [47:0] I, output [47:0] O, (* abc_arrival=1687 *) output P, (* abc_arrival=1835 *) output PCOUT); endmodule +module $__ABC_DSP48E1_MULT_DPORT_DREG (input [47:0] I, output [47:0] O, (* abc_arrival=3908 *) output P, (* abc_arrival=4056 *) output PCOUT); endmodule +module $__ABC_DSP48E1_MULT_DPORT_ADREG (input [47:0] I, output [47:0] O, (* abc_arrival=2958 *) output P, (* abc_arrival=2859 *) output PCOUT); endmodule +module $__ABC_DSP48E1_MULT_DPORT_MREG (input [47:0] I, output [47:0] O, (* abc_arrival=1671 *) output P, (* abc_arrival=1819 *) output PCOUT); endmodule +module $__ABC_DSP48E1_MULT_DPORT_PREG (input [47:0] I, output [47:0] O, (* abc_arrival= 329 *) output P, (* abc_arrival= 435 *) output PCOUT); endmodule + +module $__ABC_DSP48E1_AREG (input [29:0] I, output [29:0] O, (* abc_arrival=1632 *) output P, (* abc_arrival=1780 *) output PCOUT); endmodule +module $__ABC_DSP48E1_BREG (input [17:0] I, output [17:0] O, (* abc_arrival=1616 *) output P, (* abc_arrival=1765 *) output PCOUT); endmodule +module $__ABC_DSP48E1_CREG (input [47:0] I, output [47:0] O, (* abc_arrival=1687 *) output P, (* abc_arrival=1835 *) output PCOUT); endmodule +module $__ABC_DSP48E1_PREG (input [47:0] I, output [47:0] O, (* abc_arrival= 329 *) output P, (* abc_arrival= 435 *) output PCOUT); endmodule -- cgit v1.2.3 From 362a803779ac1a8a3af1e4991b80b0c4c71e02ff Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Thu, 19 Sep 2019 18:33:38 -0700 Subject: Revert "Different approach to timing" This reverts commit 41256f48a5f3231e231cbdf9380a26128f272044. --- techlibs/xilinx/abc_model.v | 105 ++++++++++++++++++-------------------------- 1 file changed, 42 insertions(+), 63 deletions(-) (limited to 'techlibs/xilinx/abc_model.v') diff --git a/techlibs/xilinx/abc_model.v b/techlibs/xilinx/abc_model.v index 79cca6b7b..a8f6deafc 100644 --- a/techlibs/xilinx/abc_model.v +++ b/techlibs/xilinx/abc_model.v @@ -44,6 +44,48 @@ endmodule module \$__ABC_LUT7 (input A, input [6:0] S, output Y); endmodule +// Boxes used to represent the comb/seq behaviour of DSP48E1 +// With abc_map.v responsible for disconnecting inputs to +// the combinatorial DSP48E1 model by a register (e.g. +// disconnecting A when AREG, MREG or PREG is enabled) +// this blackbox captures the existence of a replacement +// path between AREG/BREG/CREG/etc. and P/PCOUT. +// Since the Aq/ADq/Bq/etc. inputs are assumed to arrive at +// the box at zero time, the combinatorial delay through +// these boxes thus represents the clock-to-q delay +// (arrival time) at P/PCOUT. +// Doing so should means that ABC is able to analyse the +// worst-case delay through to P, regardless of if it was +// through any combinatorial paths (e.g. B, below) or an +// internal register (A2REG). +// However, the true value of being as complete as this is +// questionable since if AREG=1 and BREG=0 (as below) +// then the worse-case path would very likely be through B +// and very unlikely to be through AREG.Q...? +// +// In graphical form: +// +// NEW "PI" >>---+ +// for AREG.Q | +// | +// +---------+ | __ +// A >>--X X-| | +--| \ +// | DSP48E1 |P | |--->> P +// | AREG=1 |-------|__/ +// B >>------| | +// +---------+ +// +`define ABC_DSP48E1_MUX(__NAME__) """ +module __NAME__ (input Aq, ADq, Bq, Cq, Dq, Mq, input [47:0] P, input Pq, output [47:0] O); +endmodule +""" +(* abc_box_id=2100 *) `ABC_DSP48E1_MUX(\$__ABC_DSP48E1_MULT_P_MUX ) +(* abc_box_id=2101 *) `ABC_DSP48E1_MUX(\$__ABC_DSP48E1_MULT_PCOUT_MUX ) +(* abc_box_id=2102 *) `ABC_DSP48E1_MUX(\$__ABC_DSP48E1_MULT_DPORT_P_MUX ) +(* abc_box_id=2103 *) `ABC_DSP48E1_MUX(\$__ABC_DSP48E1_MULT_DPORT_PCOUT_MUX ) +(* abc_box_id=2104 *) `ABC_DSP48E1_MUX(\$__ABC_DSP48E1_P_MUX ) +(* abc_box_id=2105 *) `ABC_DSP48E1_MUX(\$__ABC_DSP48E1_PCOUT_MUX ) + `define ABC_DSP48E1(__NAME__) """ module \$__ABC_DSP48E1_MULT ( output [29:0] ACOUT, @@ -131,66 +173,3 @@ endmodule (* abc_box_id=3000 *) `ABC_DSP48E1(\$__ABC_DSP48E1_MULT ) (* abc_box_id=3001 *) `ABC_DSP48E1(\$__ABC_DSP48E1_MULT_DPORT ) (* abc_box_id=3002 *) `ABC_DSP48E1(\$__ABC_DSP48E1 ) - - -// Modules used to model the comb/seq behaviour of DSP48E1 -// With abc_map.v responsible for splicing the below modules -// into between the combinatorial DSP48E1 box (e.g. disconnecting -// A when AREG, MREG or PREG is enabled and splicing in the -// "$__ABC_DSP48E1_MULT_AREG" blackbox as "REG" in the diagram -// below) this acts to first disables the combinatorial path -// (as there is no connectivity through REG), and secondly, -// since this is blackbox a new PI will be introduced, one which -// will have the relevant arrival time (corresponding to delay from -// AREG to P) attached. -// Note: Since these "$__ABC_DSP48E1*_*REG" modules are of a -// sequential nature, they are not passed as a box to ABC./ -// -// On the other hand, the "$__ABC_DSP48E1_MUX" is a combinatorial -// blackbox that is passed to ABC, with zero delay. -// -// Doing so should means that ABC is able to analyse the -// worst-case delay through to P, regardless of if it was -// through any combinatorial paths (e.g. B, below) or an -// internal register (A2REG). -// However, the true value of being as complete as this is -// questionable since if AREG=1 and BREG=0 (as below) -// then the worse-case path would very likely be through B -// and very unlikely to be through AREG.Q...? -// -// In graphical form: -// -// +-----+ -// +-------| REG |-----+ -// | +-----+ | -// | | -// | +---------+ | __ -// A >>-+X X-| | +--| \ -// | DSP48E1 |P | M |--->> P -// | AREG=1 |-------|__/ -// B >>------| | -// +---------+ -// - -(* abc_box_id=2100 *) -module \$__ABC_DSP48E1_MUX (input Aq, ADq, Bq, Cq, Dq, Mq, input [47:0] P, input Pq, output [47:0] O); -endmodule - -module $__ABC_DSP48E1_MULT_AREG (input [29:0] I, output [29:0] O, (* abc_arrival=2952 *) output P, (* abc_arrival=3098 *) output PCOUT); endmodule -module $__ABC_DSP48E1_MULT_BREG (input [17:0] I, output [17:0] O, (* abc_arrival=2813 *) output P, (* abc_arrival=2960 *) output PCOUT); endmodule -module $__ABC_DSP48E1_MULT_CREG (input [47:0] I, output [47:0] O, (* abc_arrival=1687 *) output P, (* abc_arrival=1835 *) output PCOUT); endmodule -module $__ABC_DSP48E1_MULT_MREG (input [47:0] I, output [47:0] O, (* abc_arrival=1671 *) output P, (* abc_arrival=1819 *) output PCOUT); endmodule -module $__ABC_DSP48E1_MULT_PREG (input [47:0] I, output [47:0] O, (* abc_arrival= 329 *) output P, (* abc_arrival= 435 *) output PCOUT); endmodule - -module $__ABC_DSP48E1_MULT_DPORT_AREG (input [29:0] I, output [29:0] O, (* abc_arrival=3935 *) output P, (* abc_arrival=4083 *) output PCOUT); endmodule -module $__ABC_DSP48E1_MULT_DPORT_BREG (input [17:0] I, output [17:0] O, (* abc_arrival=2813 *) output P, (* abc_arrival=2960 *) output PCOUT); endmodule -module $__ABC_DSP48E1_MULT_DPORT_CREG (input [47:0] I, output [47:0] O, (* abc_arrival=1687 *) output P, (* abc_arrival=1835 *) output PCOUT); endmodule -module $__ABC_DSP48E1_MULT_DPORT_DREG (input [47:0] I, output [47:0] O, (* abc_arrival=3908 *) output P, (* abc_arrival=4056 *) output PCOUT); endmodule -module $__ABC_DSP48E1_MULT_DPORT_ADREG (input [47:0] I, output [47:0] O, (* abc_arrival=2958 *) output P, (* abc_arrival=2859 *) output PCOUT); endmodule -module $__ABC_DSP48E1_MULT_DPORT_MREG (input [47:0] I, output [47:0] O, (* abc_arrival=1671 *) output P, (* abc_arrival=1819 *) output PCOUT); endmodule -module $__ABC_DSP48E1_MULT_DPORT_PREG (input [47:0] I, output [47:0] O, (* abc_arrival= 329 *) output P, (* abc_arrival= 435 *) output PCOUT); endmodule - -module $__ABC_DSP48E1_AREG (input [29:0] I, output [29:0] O, (* abc_arrival=1632 *) output P, (* abc_arrival=1780 *) output PCOUT); endmodule -module $__ABC_DSP48E1_BREG (input [17:0] I, output [17:0] O, (* abc_arrival=1616 *) output P, (* abc_arrival=1765 *) output PCOUT); endmodule -module $__ABC_DSP48E1_CREG (input [47:0] I, output [47:0] O, (* abc_arrival=1687 *) output P, (* abc_arrival=1835 *) output PCOUT); endmodule -module $__ABC_DSP48E1_PREG (input [47:0] I, output [47:0] O, (* abc_arrival= 329 *) output P, (* abc_arrival= 435 *) output PCOUT); endmodule -- cgit v1.2.3 From e09f80479e6d16cf95c26e406bf06d81b94231f4 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Thu, 19 Sep 2019 18:59:28 -0700 Subject: Fix DSP48E1 timing by breaking P path if MREG or PREG --- techlibs/xilinx/abc_model.v | 49 +++++++++++++++++++++++++++++---------------- 1 file changed, 32 insertions(+), 17 deletions(-) (limited to 'techlibs/xilinx/abc_model.v') diff --git a/techlibs/xilinx/abc_model.v b/techlibs/xilinx/abc_model.v index a8f6deafc..1c69dd21c 100644 --- a/techlibs/xilinx/abc_model.v +++ b/techlibs/xilinx/abc_model.v @@ -44,16 +44,30 @@ endmodule module \$__ABC_LUT7 (input A, input [6:0] S, output Y); endmodule -// Boxes used to represent the comb/seq behaviour of DSP48E1 -// With abc_map.v responsible for disconnecting inputs to -// the combinatorial DSP48E1 model by a register (e.g. -// disconnecting A when AREG, MREG or PREG is enabled) -// this blackbox captures the existence of a replacement -// path between AREG/BREG/CREG/etc. and P/PCOUT. -// Since the Aq/ADq/Bq/etc. inputs are assumed to arrive at -// the box at zero time, the combinatorial delay through -// these boxes thus represents the clock-to-q delay -// (arrival time) at P/PCOUT. + +// Modules used to model the comb/seq behaviour of DSP48E1 +// With abc_map.v responsible for splicing the below modules +// into between the combinatorial DSP48E1 box (e.g. disconnecting +// A when AREG, MREG or PREG is enabled and splicing in the +// "$__ABC_DSP48E1_REG" blackbox as "REG" in the diagram below) +// this acts to first disables the combinatorial path (as there +// is no connectivity through REG), and secondly, since this is +// blackbox a new PI will be introduced with an arrival time of +// zero. +// Note: Since these "$__ABC_DSP48E1_REG" modules are of a +// sequential nature, they are not passed as a box to ABC and +// (desirably) represented as PO/PIs. +// +// At the DSP output, we place a blackbox mux ("M" in the diagram +// below) to capture the fact that the critical-path could come +// from any one of its inputs. +// In contrast to "REG", the "$__ABC_DSP48E1_*_MUX" modules are +// combinatorial blackboxes that do get passed to ABC. +// The propagation delay through this box (specified in the box +// file) captures the arrival time of the register (i.e. +// propagation from AREG to P after clock edge), or zero delay +// for the combinatorial path from the DSP. +// // Doing so should means that ABC is able to analyse the // worst-case delay through to P, regardless of if it was // through any combinatorial paths (e.g. B, below) or an @@ -65,18 +79,19 @@ endmodule // // In graphical form: // -// NEW "PI" >>---+ -// for AREG.Q | -// | -// +---------+ | __ -// A >>--X X-| | +--| \ -// | DSP48E1 |P | |--->> P +// +-----+ +// +------>> REG >>----+ +// | +-----+ | +// | | +// | +---------+ | __ +// A >>-+X X-| | +--| \ +// | DSP48E1 |P | M |--->> P // | AREG=1 |-------|__/ // B >>------| | // +---------+ // `define ABC_DSP48E1_MUX(__NAME__) """ -module __NAME__ (input Aq, ADq, Bq, Cq, Dq, Mq, input [47:0] P, input Pq, output [47:0] O); +module __NAME__ (input Aq, ADq, Bq, Cq, Dq, input [47:0] I, input Mq, input [47:0] P, input Pq, output [47:0] O); endmodule """ (* abc_box_id=2100 *) `ABC_DSP48E1_MUX(\$__ABC_DSP48E1_MULT_P_MUX ) -- cgit v1.2.3 From 4401e5f142d9728c09ac95e1cab9b30c449210fe Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Fri, 20 Sep 2019 14:24:31 -0700 Subject: Grammar --- techlibs/xilinx/abc_model.v | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'techlibs/xilinx/abc_model.v') diff --git a/techlibs/xilinx/abc_model.v b/techlibs/xilinx/abc_model.v index 1c69dd21c..0a8d531d7 100644 --- a/techlibs/xilinx/abc_model.v +++ b/techlibs/xilinx/abc_model.v @@ -47,7 +47,7 @@ endmodule // Modules used to model the comb/seq behaviour of DSP48E1 // With abc_map.v responsible for splicing the below modules -// into between the combinatorial DSP48E1 box (e.g. disconnecting +// between the combinatorial DSP48E1 box (e.g. disconnecting // A when AREG, MREG or PREG is enabled and splicing in the // "$__ABC_DSP48E1_REG" blackbox as "REG" in the diagram below) // this acts to first disables the combinatorial path (as there -- cgit v1.2.3 From 93363c94a2e88e2cdbdb962ff9e10ba5dfe3f586 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Wed, 25 Sep 2019 10:33:16 -0700 Subject: Oops. Actually use __NAME__ in ABC_DSP48E1 macro --- techlibs/xilinx/abc_model.v | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'techlibs/xilinx/abc_model.v') diff --git a/techlibs/xilinx/abc_model.v b/techlibs/xilinx/abc_model.v index 0a8d531d7..f19235a27 100644 --- a/techlibs/xilinx/abc_model.v +++ b/techlibs/xilinx/abc_model.v @@ -102,7 +102,7 @@ endmodule (* abc_box_id=2105 *) `ABC_DSP48E1_MUX(\$__ABC_DSP48E1_PCOUT_MUX ) `define ABC_DSP48E1(__NAME__) """ -module \$__ABC_DSP48E1_MULT ( +module __NAME__ ( output [29:0] ACOUT, output [17:0] BCOUT, output reg CARRYCASCOUT, -- cgit v1.2.3