From 8fbb55f4aba9ccb850680dc9c7ab582e8c964a4a Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Thu, 16 Apr 2020 10:25:41 -0700
Subject: synth_*: no need to explicitly read +/abc9_model.v

---
 techlibs/intel_alm/synth_intel_alm.cc | 1 -
 1 file changed, 1 deletion(-)

(limited to 'techlibs/intel_alm')

diff --git a/techlibs/intel_alm/synth_intel_alm.cc b/techlibs/intel_alm/synth_intel_alm.cc
index bf9e746b8..0f844961e 100644
--- a/techlibs/intel_alm/synth_intel_alm.cc
+++ b/techlibs/intel_alm/synth_intel_alm.cc
@@ -209,7 +209,6 @@ struct SynthIntelALMPass : public ScriptPass {
 		}
 
 		if (check_label("map_luts")) {
-			run("read_verilog -icells -specify -lib +/abc9_model.v");
 			run("abc9 -maxlut 6 -W 200");
 			run("techmap -map +/intel_alm/common/alm_map.v");
 			run("opt -fast");
-- 
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