From cd65eeb3b3a2410e6e42f35e8ab58be4276fd104 Mon Sep 17 00:00:00 2001
From: David Shah <davey1576@gmail.com>
Date: Fri, 13 Jul 2018 13:09:18 +0200
Subject: ice40: Add CIN_CONST and CIN_SET parameters to ICESTORM_LC

Signed-off-by: David Shah <davey1576@gmail.com>
---
 techlibs/ice40/cells_sim.v | 8 ++++++--
 1 file changed, 6 insertions(+), 2 deletions(-)

(limited to 'techlibs/ice40')

diff --git a/techlibs/ice40/cells_sim.v b/techlibs/ice40/cells_sim.v
index 45a02111f..9f73aeb07 100644
--- a/techlibs/ice40/cells_sim.v
+++ b/techlibs/ice40/cells_sim.v
@@ -657,7 +657,12 @@ module ICESTORM_LC (
 	parameter [0:0] SET_NORESET  = 0;
 	parameter [0:0] ASYNC_SR     = 0;
 
-	assign COUT = CARRY_ENABLE ? (I1 && I2) || ((I1 || I2) && CIN) : 1'bx;
+	parameter [0:0] CIN_CONST    = 0;
+	parameter [0:0] CIN_SET      = 0;
+
+	wire mux_cin = CIN_CONST ? CIN_SET : CIN;
+
+	assign COUT = CARRY_ENABLE ? (I1 && I2) || ((I1 || I2) && mux_cin) : 1'bx;
 
 	wire [7:0] lut_s3 = I3 ? LUT_INIT[15:8] : LUT_INIT[7:0];
 	wire [3:0] lut_s2 = I2 ?   lut_s3[ 7:4] :   lut_s3[3:0];
@@ -1226,4 +1231,3 @@ module SB_IO_OD (
 	endgenerate
 `endif
 endmodule
-
-- 
cgit v1.2.3


From 3aa4484a3cd9a2e82fddd499cde575eaf8c565cc Mon Sep 17 00:00:00 2001
From: Henner Zeller <h.zeller@acm.org>
Date: Fri, 20 Jul 2018 23:41:18 -0700
Subject: Consistent use of 'override' for virtual methods in derived classes.

o Not all derived methods were marked 'override', but it is a great
  feature of C++11 that we should make use of.
o While at it: touched header files got a -*- c++ -*- for emacs to
  provide support for that language.
o use YS_OVERRIDE for all override keywords (though we should probably
  use the plain keyword going forward now that C++11 is established)
---
 techlibs/ice40/ice40_ffinit.cc | 4 ++--
 techlibs/ice40/ice40_ffssr.cc  | 4 ++--
 techlibs/ice40/ice40_opt.cc    | 4 ++--
 techlibs/ice40/synth_ice40.cc  | 8 ++++----
 4 files changed, 10 insertions(+), 10 deletions(-)

(limited to 'techlibs/ice40')

diff --git a/techlibs/ice40/ice40_ffinit.cc b/techlibs/ice40/ice40_ffinit.cc
index c914b20e8..3089d8932 100644
--- a/techlibs/ice40/ice40_ffinit.cc
+++ b/techlibs/ice40/ice40_ffinit.cc
@@ -25,7 +25,7 @@ PRIVATE_NAMESPACE_BEGIN
 
 struct Ice40FfinitPass : public Pass {
 	Ice40FfinitPass() : Pass("ice40_ffinit", "iCE40: handle FF init values") { }
-	virtual void help()
+	void help() YS_OVERRIDE
 	{
 		//   |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
 		log("\n");
@@ -35,7 +35,7 @@ struct Ice40FfinitPass : public Pass {
 		log("nonzero init values.\n");
 		log("\n");
 	}
-	virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
+	void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
 	{
 		log_header(design, "Executing ICE40_FFINIT pass (implement FF init values).\n");
 
diff --git a/techlibs/ice40/ice40_ffssr.cc b/techlibs/ice40/ice40_ffssr.cc
index 9afbc0fce..668df09dd 100644
--- a/techlibs/ice40/ice40_ffssr.cc
+++ b/techlibs/ice40/ice40_ffssr.cc
@@ -25,7 +25,7 @@ PRIVATE_NAMESPACE_BEGIN
 
 struct Ice40FfssrPass : public Pass {
 	Ice40FfssrPass() : Pass("ice40_ffssr", "iCE40: merge synchronous set/reset into FF cells") { }
-	virtual void help()
+	void help() YS_OVERRIDE
 	{
 		log("\n");
 		log("    ice40_ffssr [options] [selection]\n");
@@ -33,7 +33,7 @@ struct Ice40FfssrPass : public Pass {
 		log("Merge synchronous set/reset $_MUX_ cells into iCE40 FFs.\n");
 		log("\n");
 	}
-	virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
+	void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
 	{
 		log_header(design, "Executing ICE40_FFSSR pass (merge synchronous set/reset into FF cells).\n");
 
diff --git a/techlibs/ice40/ice40_opt.cc b/techlibs/ice40/ice40_opt.cc
index 7af60f297..162740059 100644
--- a/techlibs/ice40/ice40_opt.cc
+++ b/techlibs/ice40/ice40_opt.cc
@@ -136,7 +136,7 @@ static void run_ice40_opts(Module *module, bool unlut_mode)
 
 struct Ice40OptPass : public Pass {
 	Ice40OptPass() : Pass("ice40_opt", "iCE40: perform simple optimizations") { }
-	virtual void help()
+	void help() YS_OVERRIDE
 	{
 		//   |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
 		log("\n");
@@ -156,7 +156,7 @@ struct Ice40OptPass : public Pass {
 		log("mapped SB_LUT4 cells back to logic.\n");
 		log("\n");
 	}
-	virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
+	void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
 	{
 		string opt_expr_args = "-mux_undef -undriven";
 		bool unlut_mode = false;
diff --git a/techlibs/ice40/synth_ice40.cc b/techlibs/ice40/synth_ice40.cc
index abd890a56..b0687e5e3 100644
--- a/techlibs/ice40/synth_ice40.cc
+++ b/techlibs/ice40/synth_ice40.cc
@@ -29,7 +29,7 @@ struct SynthIce40Pass : public ScriptPass
 {
 	SynthIce40Pass() : ScriptPass("synth_ice40", "synthesis for iCE40 FPGAs") { }
 
-	virtual void help() YS_OVERRIDE
+	void help() YS_OVERRIDE
 	{
 		//   |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
 		log("\n");
@@ -88,7 +88,7 @@ struct SynthIce40Pass : public ScriptPass
 	string top_opt, blif_file, edif_file, json_file;
 	bool nocarry, nodffe, nobram, flatten, retime, abc2, vpr;
 
-	virtual void clear_flags() YS_OVERRIDE
+	void clear_flags() YS_OVERRIDE
 	{
 		top_opt = "-auto-top";
 		blif_file = "";
@@ -103,7 +103,7 @@ struct SynthIce40Pass : public ScriptPass
 		vpr = false;
 	}
 
-	virtual void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
+	void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
 	{
 		string run_from, run_to;
 		clear_flags();
@@ -182,7 +182,7 @@ struct SynthIce40Pass : public ScriptPass
 		log_pop();
 	}
 
-	virtual void script() YS_OVERRIDE
+	void script() YS_OVERRIDE
 	{
 		if (check_label("begin"))
 		{
-- 
cgit v1.2.3


From 51f1bbeeb08020a9b739d2bd0cf4d79ca6e62015 Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Mon, 10 Sep 2018 11:57:24 +0200
Subject: Add iCE40 SB_SPRAM256KA simulation model

Signed-off-by: Clifford Wolf <clifford@clifford.at>
---
 techlibs/ice40/cells_sim.v | 39 ++++++++++++++++++++++++++++++---------
 1 file changed, 30 insertions(+), 9 deletions(-)

(limited to 'techlibs/ice40')

diff --git a/techlibs/ice40/cells_sim.v b/techlibs/ice40/cells_sim.v
index 9f73aeb07..e0a07af32 100644
--- a/techlibs/ice40/cells_sim.v
+++ b/techlibs/ice40/cells_sim.v
@@ -920,19 +920,40 @@ parameter A_SIGNED = 1'b0;
 parameter B_SIGNED = 1'b0;
 endmodule
 
-(* blackbox *)
-module SB_SPRAM256KA(
+module SB_SPRAM256KA (
 	input [13:0] ADDRESS,
 	input [15:0] DATAIN,
 	input [3:0] MASKWREN,
-	input WREN,
-	input CHIPSELECT,
-	input CLOCK,
-	input STANDBY,
-	input SLEEP,
-	input POWEROFF,
-	output [15:0] DATAOUT
+	input WREN, CHIPSELECT, CLOCK, STANDBY, SLEEP, POWEROFF,
+	output reg [15:0] DATAOUT
 );
+`ifndef BLACKBOX
+	reg [15:0] mem [0:16383];
+	wire off = SLEEP || !POWEROFF;
+	integer i;
+
+	always @(negedge POWEROFF) begin
+		for (i = 0; i <= 16383; i = i+1)
+			mem[i] = 'bx;
+	end
+
+	always @(posedge CLOCK, posedge off) begin
+		if (off) begin
+			DATAOUT <= 0;
+		end else
+		if (CHIPSELECT && !STANDBY && !WREN) begin
+			DATAOUT <= mem[ADDRESS];
+		end else begin
+			if (CHIPSELECT && !STANDBY && WREN) begin
+				if (MASKWREN[0]) mem[ADDRESS][ 3: 0] = DATAIN[ 3: 0];
+				if (MASKWREN[1]) mem[ADDRESS][ 7: 4] = DATAIN[ 7: 4];
+				if (MASKWREN[2]) mem[ADDRESS][11: 8] = DATAIN[11: 8];
+				if (MASKWREN[3]) mem[ADDRESS][15:12] = DATAIN[15:12];
+			end
+			DATAOUT <= 'bx;
+		end
+	end
+`endif
 endmodule
 
 (* blackbox *)
-- 
cgit v1.2.3


From 3e5ab50a73ec05badee2a8808cc0953a34dc9ae2 Mon Sep 17 00:00:00 2001
From: Sylvain Munaut <tnt@246tNt.com>
Date: Thu, 15 Nov 2018 02:49:35 +0100
Subject: ice40: Add option to only use CE if it'd be use by more than X FFs

Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
---
 techlibs/ice40/synth_ice40.cc | 14 ++++++++++++++
 1 file changed, 14 insertions(+)

(limited to 'techlibs/ice40')

diff --git a/techlibs/ice40/synth_ice40.cc b/techlibs/ice40/synth_ice40.cc
index b0687e5e3..93965a55d 100644
--- a/techlibs/ice40/synth_ice40.cc
+++ b/techlibs/ice40/synth_ice40.cc
@@ -69,6 +69,10 @@ struct SynthIce40Pass : public ScriptPass
 		log("    -nodffe\n");
 		log("        do not use SB_DFFE* cells in output netlist\n");
 		log("\n");
+		log("    -dffe_min_ce_use <min_ce_use>\n");
+		log("        do not use SB_DFFE* cells if the resulting CE line would go to less\n");
+		log("        than min_ce_use SB_DFFE*in output netlist\n");
+		log("\n");
 		log("    -nobram\n");
 		log("        do not use SB_RAM40_4K* cells in output netlist\n");
 		log("\n");
@@ -87,6 +91,7 @@ struct SynthIce40Pass : public ScriptPass
 
 	string top_opt, blif_file, edif_file, json_file;
 	bool nocarry, nodffe, nobram, flatten, retime, abc2, vpr;
+	int min_ce_use;
 
 	void clear_flags() YS_OVERRIDE
 	{
@@ -96,6 +101,7 @@ struct SynthIce40Pass : public ScriptPass
 		json_file = "";
 		nocarry = false;
 		nodffe = false;
+		min_ce_use = -1;
 		nobram = false;
 		flatten = true;
 		retime = false;
@@ -155,6 +161,10 @@ struct SynthIce40Pass : public ScriptPass
 				nodffe = true;
 				continue;
 			}
+			if (args[argidx] == "-dffe_min_ce_use" && argidx+1 < args.size()) {
+				min_ce_use = std::stoi(args[++argidx]);
+				continue;
+			}
 			if (args[argidx] == "-nobram") {
 				nobram = true;
 				continue;
@@ -228,6 +238,10 @@ struct SynthIce40Pass : public ScriptPass
 			run("dffsr2dff");
 			if (!nodffe)
 				run("dff2dffe -direct-match $_DFF_*");
+			if (min_ce_use >= 0) {
+				run("opt_merge");
+				run(stringf("dff2dffe -unmap-mince %d", min_ce_use));
+			}
 			run("techmap -D NO_LUT -map +/ice40/cells_map.v");
 			run("opt_expr -mux_undef");
 			run("simplemap");
-- 
cgit v1.2.3


From 1719aa88acf9f6d52caa81384bc50237605157e3 Mon Sep 17 00:00:00 2001
From: whitequark <whitequark@whitequark.org>
Date: Tue, 4 Dec 2018 19:43:33 +0000
Subject: Extract ice40_unlut pass from ice40_opt.

Currently, `ice40_opt -unlut` would map SB_LUT4 to $lut and convert
them back to logic immediately. This is not desirable if the goal
is to operate on $lut cells. If this is desirable, the same result
as `ice40_opt -unlut` can be achieved by running simplemap and opt
after ice40_unlut.
---
 techlibs/ice40/Makefile.inc   |   1 +
 techlibs/ice40/ice40_opt.cc   |  15 +-----
 techlibs/ice40/ice40_unlut.cc | 106 ++++++++++++++++++++++++++++++++++++++++++
 3 files changed, 109 insertions(+), 13 deletions(-)
 create mode 100644 techlibs/ice40/ice40_unlut.cc

(limited to 'techlibs/ice40')

diff --git a/techlibs/ice40/Makefile.inc b/techlibs/ice40/Makefile.inc
index 14761c6c8..2750901c8 100644
--- a/techlibs/ice40/Makefile.inc
+++ b/techlibs/ice40/Makefile.inc
@@ -3,6 +3,7 @@ OBJS += techlibs/ice40/synth_ice40.o
 OBJS += techlibs/ice40/ice40_ffssr.o
 OBJS += techlibs/ice40/ice40_ffinit.o
 OBJS += techlibs/ice40/ice40_opt.o
+OBJS += techlibs/ice40/ice40_unlut.o
 
 GENFILES += techlibs/ice40/brams_init1.vh
 GENFILES += techlibs/ice40/brams_init2.vh
diff --git a/techlibs/ice40/ice40_opt.cc b/techlibs/ice40/ice40_opt.cc
index 162740059..f528607d6 100644
--- a/techlibs/ice40/ice40_opt.cc
+++ b/techlibs/ice40/ice40_opt.cc
@@ -33,7 +33,7 @@ static SigBit get_bit_or_zero(const SigSpec &sig)
 	return sig[0];
 }
 
-static void run_ice40_opts(Module *module, bool unlut_mode)
+static void run_ice40_opts(Module *module)
 {
 	pool<SigBit> optimized_co;
 	vector<Cell*> sb_lut_cells;
@@ -95,9 +95,6 @@ static void run_ice40_opts(Module *module, bool unlut_mode)
 		inbits.append(get_bit_or_zero(cell->getPort("\\I3")));
 		sigmap.apply(inbits);
 
-		if (unlut_mode)
-			goto remap_lut;
-
 		if (optimized_co.count(inbits[0])) goto remap_lut;
 		if (optimized_co.count(inbits[1])) goto remap_lut;
 		if (optimized_co.count(inbits[2])) goto remap_lut;
@@ -152,14 +149,10 @@ struct Ice40OptPass : public Pass {
 		log("        opt_clean\n");
 		log("    while <changed design>\n");
 		log("\n");
-		log("When called with the option -unlut, this command will transform all already\n");
-		log("mapped SB_LUT4 cells back to logic.\n");
-		log("\n");
 	}
 	void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
 	{
 		string opt_expr_args = "-mux_undef -undriven";
-		bool unlut_mode = false;
 
 		log_header(design, "Executing ICE40_OPT pass (performing simple optimizations).\n");
 		log_push();
@@ -170,10 +163,6 @@ struct Ice40OptPass : public Pass {
 				opt_expr_args += " -full";
 				continue;
 			}
-			if (args[argidx] == "-unlut") {
-				unlut_mode = true;
-				continue;
-			}
 			break;
 		}
 		extra_args(args, argidx, design);
@@ -184,7 +173,7 @@ struct Ice40OptPass : public Pass {
 
 			log_header(design, "Running ICE40 specific optimizations.\n");
 			for (auto module : design->selected_modules())
-				run_ice40_opts(module, unlut_mode);
+				run_ice40_opts(module);
 
 			Pass::call(design, "opt_expr " + opt_expr_args);
 			Pass::call(design, "opt_merge");
diff --git a/techlibs/ice40/ice40_unlut.cc b/techlibs/ice40/ice40_unlut.cc
new file mode 100644
index 000000000..2428a8e78
--- /dev/null
+++ b/techlibs/ice40/ice40_unlut.cc
@@ -0,0 +1,106 @@
+/*
+ *  yosys -- Yosys Open SYnthesis Suite
+ *
+ *  Copyright (C) 2012  Clifford Wolf <clifford@clifford.at>
+ *
+ *  Permission to use, copy, modify, and/or distribute this software for any
+ *  purpose with or without fee is hereby granted, provided that the above
+ *  copyright notice and this permission notice appear in all copies.
+ *
+ *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ */
+
+#include "kernel/yosys.h"
+#include "kernel/sigtools.h"
+#include <stdlib.h>
+#include <stdio.h>
+
+USING_YOSYS_NAMESPACE
+PRIVATE_NAMESPACE_BEGIN
+
+static SigBit get_bit_or_zero(const SigSpec &sig)
+{
+	if (GetSize(sig) == 0)
+		return State::S0;
+	return sig[0];
+}
+
+static void run_ice40_unlut(Module *module)
+{
+	SigMap sigmap(module);
+
+	for (auto cell : module->selected_cells())
+	{
+		if (cell->type == "\\SB_LUT4")
+		{
+			SigSpec inbits;
+
+			inbits.append(get_bit_or_zero(cell->getPort("\\I0")));
+			inbits.append(get_bit_or_zero(cell->getPort("\\I1")));
+			inbits.append(get_bit_or_zero(cell->getPort("\\I2")));
+			inbits.append(get_bit_or_zero(cell->getPort("\\I3")));
+			sigmap.apply(inbits);
+
+			log("Mapping SB_LUT4 cell %s.%s to $lut.\n", log_id(module), log_id(cell));
+
+			cell->type ="$lut";
+			cell->setParam("\\WIDTH", 4);
+			cell->setParam("\\LUT", cell->getParam("\\LUT_INIT"));
+			cell->unsetParam("\\LUT_INIT");
+
+			cell->setPort("\\A", SigSpec({
+				get_bit_or_zero(cell->getPort("\\I3")),
+				get_bit_or_zero(cell->getPort("\\I2")),
+				get_bit_or_zero(cell->getPort("\\I1")),
+				get_bit_or_zero(cell->getPort("\\I0"))
+			}));
+			cell->setPort("\\Y", cell->getPort("\\O")[0]);
+			cell->unsetPort("\\I0");
+			cell->unsetPort("\\I1");
+			cell->unsetPort("\\I2");
+			cell->unsetPort("\\I3");
+			cell->unsetPort("\\O");
+
+			cell->check();
+		}
+	}
+}
+
+struct Ice40UnlutPass : public Pass {
+	Ice40UnlutPass() : Pass("ice40_unlut", "iCE40: perform simple optimizations") { }
+	void help() YS_OVERRIDE
+	{
+		//   |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
+		log("\n");
+		log("    ice40_unlut [options] [selection]\n");
+		log("\n");
+		log("This command transforms all SB_LUT4 cells to generic $lut cells.\n");
+		log("\n");
+	}
+	void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
+	{
+		log_header(design, "Executing ICE40_UNLUT pass (convert SB_LUT4 to $lut).\n");
+		log_push();
+
+		size_t argidx;
+		for (argidx = 1; argidx < args.size(); argidx++) {
+			// if (args[argidx] == "-???") {
+			//  continue;
+			// }
+			break;
+		}
+		extra_args(args, argidx, design);
+
+		for (auto module : design->selected_modules())
+			run_ice40_unlut(module);
+	}
+} Ice40UnlutPass;
+
+PRIVATE_NAMESPACE_END
-- 
cgit v1.2.3


From ea4870b12690bd313852c952f4fd17efaf63abb6 Mon Sep 17 00:00:00 2001
From: whitequark <whitequark@whitequark.org>
Date: Wed, 5 Dec 2018 00:28:03 +0000
Subject: synth_ice40: add -relut option, to run ice40_unlut and opt_lut.

---
 techlibs/ice40/synth_ice40.cc | 14 +++++++++++++-
 1 file changed, 13 insertions(+), 1 deletion(-)

(limited to 'techlibs/ice40')

diff --git a/techlibs/ice40/synth_ice40.cc b/techlibs/ice40/synth_ice40.cc
index 93965a55d..7094db50d 100644
--- a/techlibs/ice40/synth_ice40.cc
+++ b/techlibs/ice40/synth_ice40.cc
@@ -63,6 +63,9 @@ struct SynthIce40Pass : public ScriptPass
 		log("    -retime\n");
 		log("        run 'abc' with -dff option\n");
 		log("\n");
+		log("    -relut\n");
+		log("        combine LUTs after synthesis\n");
+		log("\n");
 		log("    -nocarry\n");
 		log("        do not use SB_CARRY cells in output netlist\n");
 		log("\n");
@@ -90,7 +93,7 @@ struct SynthIce40Pass : public ScriptPass
 	}
 
 	string top_opt, blif_file, edif_file, json_file;
-	bool nocarry, nodffe, nobram, flatten, retime, abc2, vpr;
+	bool nocarry, nodffe, nobram, flatten, retime, relut, abc2, vpr;
 	int min_ce_use;
 
 	void clear_flags() YS_OVERRIDE
@@ -105,6 +108,7 @@ struct SynthIce40Pass : public ScriptPass
 		nobram = false;
 		flatten = true;
 		retime = false;
+		relut = false;
 		abc2 = false;
 		vpr = false;
 	}
@@ -153,6 +157,10 @@ struct SynthIce40Pass : public ScriptPass
 				retime = true;
 				continue;
 			}
+			if (args[argidx] == "-relut") {
+				relut = true;
+				continue;
+			}
 			if (args[argidx] == "-nocarry") {
 				nocarry = true;
 				continue;
@@ -259,6 +267,10 @@ struct SynthIce40Pass : public ScriptPass
 			run("techmap -map +/ice40/latches_map.v");
 			run("abc -lut 4");
 			run("clean");
+			if (relut || help_mode) {
+				run("ice40_unlut", "(only if -relut)");
+				run("opt_lut", "    (only if -relut)");
+			}
 		}
 
 		if (check_label("map_cells"))
-- 
cgit v1.2.3


From 45cb6200af13469724de42656f2c1f0f61c8766a Mon Sep 17 00:00:00 2001
From: whitequark <whitequark@whitequark.org>
Date: Wed, 5 Dec 2018 15:26:40 +0000
Subject: opt_lut: add -dlogic, to avoid disturbing logic such as carry chains.

---
 techlibs/ice40/synth_ice40.cc | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

(limited to 'techlibs/ice40')

diff --git a/techlibs/ice40/synth_ice40.cc b/techlibs/ice40/synth_ice40.cc
index 7094db50d..cc4627cd3 100644
--- a/techlibs/ice40/synth_ice40.cc
+++ b/techlibs/ice40/synth_ice40.cc
@@ -268,8 +268,8 @@ struct SynthIce40Pass : public ScriptPass
 			run("abc -lut 4");
 			run("clean");
 			if (relut || help_mode) {
-				run("ice40_unlut", "(only if -relut)");
-				run("opt_lut", "    (only if -relut)");
+				run("ice40_unlut", "                            (only if -relut)");
+				run("opt_lut -dlogic SB_CARRY:I0=1:I1=2:CI=3", "(only if -relut)");
 			}
 		}
 
-- 
cgit v1.2.3


From d9fa4387c97745c558acdd8ea7f436917302796e Mon Sep 17 00:00:00 2001
From: whitequark <whitequark@whitequark.org>
Date: Wed, 5 Dec 2018 05:24:15 +0000
Subject: synth_ice40: add -noabc option, to use built-in LUT techmapping.

This should be combined with -relut to get sensible results.
---
 techlibs/ice40/synth_ice40.cc | 18 ++++++++++++++++--
 1 file changed, 16 insertions(+), 2 deletions(-)

(limited to 'techlibs/ice40')

diff --git a/techlibs/ice40/synth_ice40.cc b/techlibs/ice40/synth_ice40.cc
index cc4627cd3..931a190e7 100644
--- a/techlibs/ice40/synth_ice40.cc
+++ b/techlibs/ice40/synth_ice40.cc
@@ -79,6 +79,9 @@ struct SynthIce40Pass : public ScriptPass
 		log("    -nobram\n");
 		log("        do not use SB_RAM40_4K* cells in output netlist\n");
 		log("\n");
+		log("    -noabc\n");
+		log("        use built-in Yosys LUT techmapping instead of abc\n");
+		log("\n");
 		log("    -abc2\n");
 		log("        run two passes of 'abc' for slightly improved logic density\n");
 		log("\n");
@@ -93,7 +96,7 @@ struct SynthIce40Pass : public ScriptPass
 	}
 
 	string top_opt, blif_file, edif_file, json_file;
-	bool nocarry, nodffe, nobram, flatten, retime, relut, abc2, vpr;
+	bool nocarry, nodffe, nobram, flatten, retime, relut, noabc, abc2, vpr;
 	int min_ce_use;
 
 	void clear_flags() YS_OVERRIDE
@@ -109,6 +112,7 @@ struct SynthIce40Pass : public ScriptPass
 		flatten = true;
 		retime = false;
 		relut = false;
+		noabc = false;
 		abc2 = false;
 		vpr = false;
 	}
@@ -177,6 +181,10 @@ struct SynthIce40Pass : public ScriptPass
 				nobram = true;
 				continue;
 			}
+			if (args[argidx] == "-noabc") {
+				noabc = true;
+				continue;
+			}
 			if (args[argidx] == "-abc2") {
 				abc2 = true;
 				continue;
@@ -265,7 +273,13 @@ struct SynthIce40Pass : public ScriptPass
 				run("ice40_opt", "(only if -abc2)");
 			}
 			run("techmap -map +/ice40/latches_map.v");
-			run("abc -lut 4");
+			if (noabc || help_mode) {
+				run("simplemap", "                               (only if -noabc)");
+				run("techmap -map +/gate2lut.v -D LUT_WIDTH=4", "(only if -noabc)");
+			}
+			if (!noabc) {
+				run("abc -lut 4", "(skip if -noabc)");
+			}
 			run("clean");
 			if (relut || help_mode) {
 				run("ice40_unlut", "                            (only if -relut)");
-- 
cgit v1.2.3


From 6e559ee3c78c0984e1f486ecedf61c3011aa0f0d Mon Sep 17 00:00:00 2001
From: whitequark <whitequark@whitequark.org>
Date: Thu, 6 Dec 2018 12:02:42 +0000
Subject: synth_ice40: split `map_gates` off `fine`.

---
 techlibs/ice40/synth_ice40.cc | 4 ++++
 1 file changed, 4 insertions(+)

(limited to 'techlibs/ice40')

diff --git a/techlibs/ice40/synth_ice40.cc b/techlibs/ice40/synth_ice40.cc
index 931a190e7..37b924dfd 100644
--- a/techlibs/ice40/synth_ice40.cc
+++ b/techlibs/ice40/synth_ice40.cc
@@ -240,6 +240,10 @@ struct SynthIce40Pass : public ScriptPass
 			run("opt -fast -mux_undef -undriven -fine");
 			run("memory_map");
 			run("opt -undriven -fine");
+		}
+
+		if (check_label("map_gates"))
+		{
 			if (nocarry)
 				run("techmap");
 			else
-- 
cgit v1.2.3


From 889297c62a6e99c41995bcb3606e8be4490a2c9c Mon Sep 17 00:00:00 2001
From: Olof Kindgren <olof.kindgren@gmail.com>
Date: Thu, 6 Dec 2018 21:45:59 +0100
Subject: Only use non-blocking assignments of SB_RAM40_4K for yosys

In an initial statement, blocking assignments are normally used
and e.g. verilator throws a warning if non-blocking ones are used.

Yosys cannot however properly resolve the interdependencies if
blocking assignments are used in the initialization of SB_RAM_40_4K
and thus this has been used.

This patch will change to use non-blocking assignments only for yosys
---
 techlibs/ice40/cells_sim.v | 19 +++++++++++++++++++
 1 file changed, 19 insertions(+)

(limited to 'techlibs/ice40')

diff --git a/techlibs/ice40/cells_sim.v b/techlibs/ice40/cells_sim.v
index e0a07af32..a2a842275 100644
--- a/techlibs/ice40/cells_sim.v
+++ b/techlibs/ice40/cells_sim.v
@@ -409,6 +409,7 @@ module SB_RAM40_4K (
 
 	initial begin
 		for (i=0; i<16; i=i+1) begin
+`ifdef YOSYS
 			memory[ 0*16 + i] <= INIT_0[16*i +: 16];
 			memory[ 1*16 + i] <= INIT_1[16*i +: 16];
 			memory[ 2*16 + i] <= INIT_2[16*i +: 16];
@@ -425,6 +426,24 @@ module SB_RAM40_4K (
 			memory[13*16 + i] <= INIT_D[16*i +: 16];
 			memory[14*16 + i] <= INIT_E[16*i +: 16];
 			memory[15*16 + i] <= INIT_F[16*i +: 16];
+`else
+			memory[ 0*16 + i] = INIT_0[16*i +: 16];
+			memory[ 1*16 + i] = INIT_1[16*i +: 16];
+			memory[ 2*16 + i] = INIT_2[16*i +: 16];
+			memory[ 3*16 + i] = INIT_3[16*i +: 16];
+			memory[ 4*16 + i] = INIT_4[16*i +: 16];
+			memory[ 5*16 + i] = INIT_5[16*i +: 16];
+			memory[ 6*16 + i] = INIT_6[16*i +: 16];
+			memory[ 7*16 + i] = INIT_7[16*i +: 16];
+			memory[ 8*16 + i] = INIT_8[16*i +: 16];
+			memory[ 9*16 + i] = INIT_9[16*i +: 16];
+			memory[10*16 + i] = INIT_A[16*i +: 16];
+			memory[11*16 + i] = INIT_B[16*i +: 16];
+			memory[12*16 + i] = INIT_C[16*i +: 16];
+			memory[13*16 + i] = INIT_D[16*i +: 16];
+			memory[14*16 + i] = INIT_E[16*i +: 16];
+			memory[15*16 + i] = INIT_F[16*i +: 16];
+`endif
 		end
 	end
 
-- 
cgit v1.2.3


From 7ff5a9db2d17c384260c2220c9205a7b4891f001 Mon Sep 17 00:00:00 2001
From: whitequark <whitequark@whitequark.org>
Date: Fri, 7 Dec 2018 16:58:33 +0000
Subject: equiv_opt: pass -D EQUIV when techmapping.

This allows avoiding techmap crashes e.g. because of large memories
in white-box cell models.
---
 techlibs/ice40/cells_sim.v | 2 ++
 1 file changed, 2 insertions(+)

(limited to 'techlibs/ice40')

diff --git a/techlibs/ice40/cells_sim.v b/techlibs/ice40/cells_sim.v
index e0a07af32..c554c3f35 100644
--- a/techlibs/ice40/cells_sim.v
+++ b/techlibs/ice40/cells_sim.v
@@ -928,6 +928,7 @@ module SB_SPRAM256KA (
 	output reg [15:0] DATAOUT
 );
 `ifndef BLACKBOX
+`ifndef EQUIV
 	reg [15:0] mem [0:16383];
 	wire off = SLEEP || !POWEROFF;
 	integer i;
@@ -954,6 +955,7 @@ module SB_SPRAM256KA (
 		end
 	end
 `endif
+`endif
 endmodule
 
 (* blackbox *)
-- 
cgit v1.2.3


From add6ab9b2a8d94bee0e7949a4524cc673ec336b1 Mon Sep 17 00:00:00 2001
From: Sylvain Munaut <tnt@246tNt.com>
Date: Sat, 8 Dec 2018 22:46:28 +0100
Subject: ice40: Honor the "dont_touch" attribute in FFSSR pass

This is useful if you want to place FF manually ... can't merge SR in those
because it might make the manual placement invalid

Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
---
 techlibs/ice40/ice40_ffssr.cc | 3 +++
 1 file changed, 3 insertions(+)

(limited to 'techlibs/ice40')

diff --git a/techlibs/ice40/ice40_ffssr.cc b/techlibs/ice40/ice40_ffssr.cc
index 668df09dd..a7649d7a0 100644
--- a/techlibs/ice40/ice40_ffssr.cc
+++ b/techlibs/ice40/ice40_ffssr.cc
@@ -81,6 +81,9 @@ struct Ice40FfssrPass : public Pass {
 
 			for (auto cell : ff_cells)
 			{
+				if (cell->get_bool_attribute("\\dont_touch"))
+					continue;
+
 				SigSpec sig_d = cell->getPort("\\D");
 
 				if (GetSize(sig_d) < 1)
-- 
cgit v1.2.3


From 5fa5dbbddab03af89e00426e21df9f30d020a94e Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Sun, 16 Dec 2018 16:36:19 +0100
Subject: Rename "fine:" label to "map:" in "synth_ice40"

Signed-off-by: Clifford Wolf <clifford@clifford.at>
---
 techlibs/ice40/synth_ice40.cc | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'techlibs/ice40')

diff --git a/techlibs/ice40/synth_ice40.cc b/techlibs/ice40/synth_ice40.cc
index 37b924dfd..c2aed873b 100644
--- a/techlibs/ice40/synth_ice40.cc
+++ b/techlibs/ice40/synth_ice40.cc
@@ -235,7 +235,7 @@ struct SynthIce40Pass : public ScriptPass
 			run("techmap -map +/ice40/brams_map.v");
 		}
 
-		if (check_label("fine"))
+		if (check_label("map"))
 		{
 			run("opt -fast -mux_undef -undriven -fine");
 			run("memory_map");
-- 
cgit v1.2.3


From 17b283135658b84a0dfeec8b35f7d2bfe782be19 Mon Sep 17 00:00:00 2001
From: whitequark <whitequark@whitequark.org>
Date: Wed, 2 Jan 2019 08:25:55 +0000
Subject: synth_ice40: use 4-LUT coarse synthesis mode.

---
 techlibs/ice40/synth_ice40.cc | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'techlibs/ice40')

diff --git a/techlibs/ice40/synth_ice40.cc b/techlibs/ice40/synth_ice40.cc
index c2aed873b..4c4fdf7be 100644
--- a/techlibs/ice40/synth_ice40.cc
+++ b/techlibs/ice40/synth_ice40.cc
@@ -226,7 +226,7 @@ struct SynthIce40Pass : public ScriptPass
 
 		if (check_label("coarse"))
 		{
-			run("synth -run coarse");
+			run("synth -lut 4 -run coarse");
 		}
 
 		if (!nobram && check_label("bram", "(skip if -nobram)"))
-- 
cgit v1.2.3


From efa278e232d20ea080743801bd91d55ec62955cf Mon Sep 17 00:00:00 2001
From: whitequark <whitequark@whitequark.org>
Date: Fri, 7 Dec 2018 19:14:07 +0000
Subject: Fix typographical and grammatical errors and inconsistencies.

The initial list of hits was generated with the codespell command
below, and each hit was evaluated and fixed manually while taking
context into consideration.

    DIRS="kernel/ frontends/ backends/ passes/ techlibs/"
    DIRS="${DIRS} libs/ezsat/ libs/subcircuit"
    codespell $DIRS -S *.o -L upto,iff,thru,synopsys,uint

More hits were found by looking through comments and strings manually.
---
 techlibs/ice40/synth_ice40.cc | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'techlibs/ice40')

diff --git a/techlibs/ice40/synth_ice40.cc b/techlibs/ice40/synth_ice40.cc
index c2aed873b..626f6d381 100644
--- a/techlibs/ice40/synth_ice40.cc
+++ b/techlibs/ice40/synth_ice40.cc
@@ -198,7 +198,7 @@ struct SynthIce40Pass : public ScriptPass
 		extra_args(args, argidx, design);
 
 		if (!design->full_selection())
-			log_cmd_error("This comannd only operates on fully selected designs!\n");
+			log_cmd_error("This command only operates on fully selected designs!\n");
 
 		log_header(design, "Executing SYNTH_ICE40 pass.\n");
 		log_push();
-- 
cgit v1.2.3


From 7ef2333497940a9f235d36f38a727f2533bab902 Mon Sep 17 00:00:00 2001
From: David Shah <davey1576@gmail.com>
Date: Sun, 16 Dec 2018 17:43:57 +0000
Subject: ice40: Use abc -dress in synth_ice40

Signed-off-by: David Shah <davey1576@gmail.com>
---
 techlibs/ice40/synth_ice40.cc | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'techlibs/ice40')

diff --git a/techlibs/ice40/synth_ice40.cc b/techlibs/ice40/synth_ice40.cc
index f900453e8..ba013fef2 100644
--- a/techlibs/ice40/synth_ice40.cc
+++ b/techlibs/ice40/synth_ice40.cc
@@ -282,7 +282,7 @@ struct SynthIce40Pass : public ScriptPass
 				run("techmap -map +/gate2lut.v -D LUT_WIDTH=4", "(only if -noabc)");
 			}
 			if (!noabc) {
-				run("abc -lut 4", "(skip if -noabc)");
+				run("abc -dress -lut 4", "(skip if -noabc)");
 			}
 			run("clean");
 			if (relut || help_mode) {
-- 
cgit v1.2.3


From 323dd0e608b38116db1e2bcda1ebc4ba98823990 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddieh@ece.ubc.ca>
Date: Thu, 14 Feb 2019 13:19:27 -0800
Subject: synth_ice40 to have new -abc9 arg

---
 techlibs/ice40/synth_ice40.cc | 16 ++++++++++++----
 1 file changed, 12 insertions(+), 4 deletions(-)

(limited to 'techlibs/ice40')

diff --git a/techlibs/ice40/synth_ice40.cc b/techlibs/ice40/synth_ice40.cc
index f900453e8..f77ea7f80 100644
--- a/techlibs/ice40/synth_ice40.cc
+++ b/techlibs/ice40/synth_ice40.cc
@@ -89,13 +89,16 @@ struct SynthIce40Pass : public ScriptPass
 		log("        generate an output netlist (and BLIF file) suitable for VPR\n");
 		log("        (this feature is experimental and incomplete)\n");
 		log("\n");
+		log("    -abc9\n");
+		log("        use abc9 instead of abc\n");
+		log("\n");
 		log("\n");
 		log("The following commands are executed by this synthesis command:\n");
 		help_script();
 		log("\n");
 	}
 
-	string top_opt, blif_file, edif_file, json_file;
+	string top_opt, blif_file, edif_file, json_file, abc;
 	bool nocarry, nodffe, nobram, flatten, retime, relut, noabc, abc2, vpr;
 	int min_ce_use;
 
@@ -115,6 +118,7 @@ struct SynthIce40Pass : public ScriptPass
 		noabc = false;
 		abc2 = false;
 		vpr = false;
+		abc = "abc";
 	}
 
 	void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
@@ -193,6 +197,10 @@ struct SynthIce40Pass : public ScriptPass
 				vpr = true;
 				continue;
 			}
+			if (args[argidx] == "-abc9") {
+				abc = "abc9";
+				continue;
+			}
 			break;
 		}
 		extra_args(args, argidx, design);
@@ -249,7 +257,7 @@ struct SynthIce40Pass : public ScriptPass
 			else
 				run("techmap -map +/techmap.v -map +/ice40/arith_map.v");
 			if (retime || help_mode)
-				run("abc -dff", "(only if -retime)");
+				run(abc + " -dff", "(only if -retime)");
 			run("ice40_opt");
 		}
 
@@ -273,7 +281,7 @@ struct SynthIce40Pass : public ScriptPass
 		if (check_label("map_luts"))
 		{
 			if (abc2 || help_mode) {
-				run("abc", "      (only if -abc2)");
+				run(abc, "      (only if -abc2)");
 				run("ice40_opt", "(only if -abc2)");
 			}
 			run("techmap -map +/ice40/latches_map.v");
@@ -282,7 +290,7 @@ struct SynthIce40Pass : public ScriptPass
 				run("techmap -map +/gate2lut.v -D LUT_WIDTH=4", "(only if -noabc)");
 			}
 			if (!noabc) {
-				run("abc -lut 4", "(skip if -noabc)");
+				run(abc + " -lut 4", "(skip if -noabc)");
 			}
 			run("clean");
 			if (relut || help_mode) {
-- 
cgit v1.2.3


From 62493c91b24c1775f82e64712bf42b175944fe08 Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Tue, 19 Feb 2019 13:42:21 +0100
Subject: Add first draft of functional SB_MAC16 model

Signed-off-by: Clifford Wolf <clifford@clifford.at>
---
 techlibs/ice40/cells_sim.v               | 228 ++++++++++++++++++++++++-------
 techlibs/ice40/tests/test_dsp_model.gtkw |  87 ++++++++++++
 techlibs/ice40/tests/test_dsp_model.sh   |   6 +
 techlibs/ice40/tests/test_dsp_model.v    | 199 +++++++++++++++++++++++++++
 4 files changed, 467 insertions(+), 53 deletions(-)
 create mode 100644 techlibs/ice40/tests/test_dsp_model.gtkw
 create mode 100644 techlibs/ice40/tests/test_dsp_model.sh
 create mode 100644 techlibs/ice40/tests/test_dsp_model.v

(limited to 'techlibs/ice40')

diff --git a/techlibs/ice40/cells_sim.v b/techlibs/ice40/cells_sim.v
index 38ed45981..4a92fccdf 100644
--- a/techlibs/ice40/cells_sim.v
+++ b/techlibs/ice40/cells_sim.v
@@ -886,59 +886,6 @@ module SB_WARMBOOT (
 );
 endmodule
 
-// UltraPlus feature cells
-(* blackbox *)
-module SB_MAC16 (
-	input CLK,
-	input CE,
-	input [15:0] C,
-	input [15:0] A,
-	input [15:0] B,
-	input [15:0] D,
-	input AHOLD,
-	input BHOLD,
-	input CHOLD,
-	input DHOLD,
-	input IRSTTOP,
-	input IRSTBOT,
-	input ORSTTOP,
-	input ORSTBOT,
-	input OLOADTOP,
-	input OLOADBOT,
-	input ADDSUBTOP,
-	input ADDSUBBOT,
-	input OHOLDTOP,
-	input OHOLDBOT,
-	input CI,
-	input ACCUMCI,
-	input SIGNEXTIN,
-	output [31:0] O,
-	output CO,
-	output ACCUMCO,
-	output SIGNEXTOUT
-);
-parameter NEG_TRIGGER = 1'b0;
-parameter C_REG = 1'b0;
-parameter A_REG = 1'b0;
-parameter B_REG = 1'b0;
-parameter D_REG = 1'b0;
-parameter TOP_8x8_MULT_REG = 1'b0;
-parameter BOT_8x8_MULT_REG = 1'b0;
-parameter PIPELINE_16x16_MULT_REG1 = 1'b0;
-parameter PIPELINE_16x16_MULT_REG2 = 1'b0;
-parameter TOPOUTPUT_SELECT =  2'b00;
-parameter TOPADDSUB_LOWERINPUT = 2'b00;
-parameter TOPADDSUB_UPPERINPUT = 1'b0;
-parameter TOPADDSUB_CARRYSELECT = 2'b00;
-parameter BOTOUTPUT_SELECT =  2'b00;
-parameter BOTADDSUB_LOWERINPUT = 2'b00;
-parameter BOTADDSUB_UPPERINPUT = 1'b0;
-parameter BOTADDSUB_CARRYSELECT = 2'b00;
-parameter MODE_8x8 = 1'b0;
-parameter A_SIGNED = 1'b0;
-parameter B_SIGNED = 1'b0;
-endmodule
-
 module SB_SPRAM256KA (
 	input [13:0] ADDRESS,
 	input [15:0] DATAIN,
@@ -1273,3 +1220,178 @@ module SB_IO_OD (
 	endgenerate
 `endif
 endmodule
+
+module SB_MAC16 (
+	input CLK, CE,
+	input [15:0] C, A, B, D,
+	input AHOLD, BHOLD, CHOLD, DHOLD,
+	input IRSTTOP, IRSTBOT,
+	input ORSTTOP, ORSTBOT,
+	input OLOADTOP, OLOADBOT,
+	input ADDSUBTOP, ADDSUBBOT,
+	input OHOLDTOP, OHOLDBOT,
+	input CI, ACCUMCI, SIGNEXTIN,
+	output [31:0] O,
+	output CO, ACCUMCO, SIGNEXTOUT
+);
+	parameter [0:0] NEG_TRIGGER = 0;
+	parameter [0:0] C_REG = 0;
+	parameter [0:0] A_REG = 0;
+	parameter [0:0] B_REG = 0;
+	parameter [0:0] D_REG = 0;
+	parameter [0:0] TOP_8x8_MULT_REG = 0;
+	parameter [0:0] BOT_8x8_MULT_REG = 0;
+	parameter [0:0] PIPELINE_16x16_MULT_REG1 = 0;
+	parameter [0:0] PIPELINE_16x16_MULT_REG2 = 0;
+	parameter [1:0] TOPOUTPUT_SELECT = 0;
+	parameter [1:0] TOPADDSUB_LOWERINPUT = 0;
+	parameter [0:0] TOPADDSUB_UPPERINPUT = 0;
+	parameter [1:0] TOPADDSUB_CARRYSELECT = 0;
+	parameter [1:0] BOTOUTPUT_SELECT = 0;
+	parameter [1:0] BOTADDSUB_LOWERINPUT = 0;
+	parameter [0:0] BOTADDSUB_UPPERINPUT = 0;
+	parameter [1:0] BOTADDSUB_CARRYSELECT = 0;
+	parameter [0:0] MODE_8x8 = 0;
+	parameter [0:0] A_SIGNED = 0;
+	parameter [0:0] B_SIGNED = 0;
+
+	wire clock = CLK ^ NEG_TRIGGER;
+
+	// internal wires, compare Figure on page 133 of ICE Technology Library 3.0 and Fig 2 on page 2 of Lattice TN1295-DSP
+	// http://www.latticesemi.com/~/media/LatticeSemi/Documents/TechnicalBriefs/SBTICETechnologyLibrary201608.pdf
+	// https://www.latticesemi.com/-/media/LatticeSemi/Documents/ApplicationNotes/AD/DSPFunctionUsageGuideforICE40Devices.ashx
+	wire [15:0] iA, iB, iC, iD;
+	wire [15:0] iF, iJ, iK, iG;
+	wire [31:0] iL, iH;
+	wire [15:0] iW, iX, iP, iQ;
+	wire [15:0] iY, iZ, iR, iS;
+	wire HCI, LCI, LCO;
+
+	// Regs C and A
+	reg [15:0] rC, rA;
+	always @(posedge clock, posedge IRSTTOP) begin
+		if (IRSTTOP) begin
+			rC <= 0;
+			rA <= 0;
+		end else if (CE) begin
+			if (!CHOLD) rC <= C;
+			if (!AHOLD) rA <= A;
+		end
+	end
+	assign iC = C_REG ? rC : C;
+	assign iA = A_REG ? rA : A;
+
+	// Regs B and D
+	reg [15:0] rB, rD;
+	always @(posedge clock, posedge IRSTTOP) begin
+		if (IRSTBOT) begin
+			rB <= 0;
+			rD <= 0;
+		end else if (CE) begin
+			if (!BHOLD) rB <= B;
+			if (!DHOLD) rD <= D;
+		end
+	end
+	assign iB = B_REG ? rB : B;
+	assign iD = D_REG ? rD : D;
+
+	// Multiplier Stage
+	wire [15:0] p_Ah_Bh, p_Al_Bh, p_Ah_Bl, p_Al_Bl;
+	wire [15:0] Ah, Al, Bh, Bl;
+	assign Ah = A_SIGNED ? {{8{iA[15]}}, iA[15: 8]} : iA[15: 8];
+	assign Al = A_SIGNED ? {{8{iA[ 7]}}, iA[ 7: 0]} : iA[15: 8];
+	assign Bh = B_SIGNED ? {{8{iB[15]}}, iB[15: 8]} : iB[15: 8];
+	assign Bl = B_SIGNED ? {{8{iB[ 7]}}, iB[ 7: 0]} : iB[15: 8];
+	assign p_Ah_Bh = Ah * Bh;
+	assign p_Al_Bh = Al * Bh;
+	assign p_Ah_Bl = Ah * Bl;
+	assign p_Al_Bl = Al * Bl;
+
+	// Regs F and J
+	reg [15:0] rF, rJ;
+	always @(posedge clock, posedge IRSTTOP) begin
+		if (IRSTTOP) begin
+			rF <= 0;
+			rJ <= 0;
+		end else if (CE) begin
+			rF <= p_Ah_Bh;
+			if (!MODE_8x8) rJ <= p_Al_Bh;
+		end
+	end
+	assign iF = TOP_8x8_MULT_REG ? rF : p_Ah_Bh;
+	assign iJ = PIPELINE_16x16_MULT_REG1 ? rJ : p_Al_Bh;
+
+	// Regs K and G
+	reg [15:0] rK, rG;
+	always @(posedge clock, posedge IRSTBOT) begin
+		if (IRSTBOT) begin
+			rK <= 0;
+			rG <= 0;
+		end else if (CE) begin
+			if (!MODE_8x8) rK <= p_Ah_Bl;
+			rG <= p_Al_Bl;
+		end
+	end
+	assign iK = PIPELINE_16x16_MULT_REG1 ? rK : p_Ah_Bl;
+	assign iG = BOT_8x8_MULT_REG ? rG : p_Al_Bl;
+
+	// Adder Stage
+	reg [31:0] P;
+	always @* begin
+		P = iG[7:0];
+		P = P + (iG[15:8] + iK[7:0]) << 8;
+		P = P + (iK[15:8] + iJ[7:0]) << 16;
+		P = P + (iJ[15:8] + iF[7:0]) << 24;
+	end
+	assign iL = P;
+
+	// Reg H
+	reg [15:0] rH;
+	always @(posedge clock, posedge IRSTBOT) begin
+		if (IRSTBOT) begin
+			rH <= 0;
+		end else if (CE) begin
+			if (!MODE_8x8) rH <= iL;
+		end
+	end
+	assign iH = PIPELINE_16x16_MULT_REG2 ? rH : iL;
+
+	// Hi Output Stage
+	wire [15:0] XW, Oh;
+	reg [15:0] rQ;
+	assign iW = TOPADDSUB_UPPERINPUT ? iC : iQ[31:16];
+	assign iX = (TOPADDSUB_LOWERINPUT == 0) ? iA : (TOPADDSUB_LOWERINPUT == 1) ? iF : (TOPADDSUB_LOWERINPUT == 2) ? iH[31:16] : {16{iZ[15]}};
+	assign {ACCUMCO, XW} = iX + (iW ^ {16{ADDSUBTOP}}) + HCI;
+	assign CO = ACCUMCO ^ ADDSUBTOP;
+	assign iP = OLOADTOP ? iC : XW ^ {16{ADDSUBTOP}};
+	always @(posedge clock, posedge ORSTTOP) begin
+		if (ORSTTOP) begin
+			rQ <= 0;
+		end else if (CE) begin
+			if (!OHOLDTOP) rQ <= iP;
+		end
+	end
+	assign iQ = rQ;
+	assign Oh = (TOPOUTPUT_SELECT == 0) ? iP : (TOPOUTPUT_SELECT == 1) ? iQ : (TOPOUTPUT_SELECT == 2) ? iF : iH[31:16];
+	assign HCI = (TOPADDSUB_CARRYSELECT == 0) ? 1'b0 : (TOPADDSUB_CARRYSELECT == 1) ? 1'b1 : (TOPADDSUB_CARRYSELECT == 2) ? LCO : LCO ^ ADDSUBBOT;
+	assign SIGNEXTOUT = iX[15];
+
+	// Lo Output Stage
+	wire [15:0] YZ, Ol;
+	reg [15:0] rS;
+	assign iY = BOTADDSUB_UPPERINPUT ? iD : iQ[15:0];
+	assign iZ = (BOTADDSUB_LOWERINPUT == 0) ? iB : (BOTADDSUB_LOWERINPUT == 1) ? iG : (BOTADDSUB_LOWERINPUT == 2) ? iH[15:0] : {16{SIGNEXTIN}};
+	assign {LCO, YZ} = iZ + (iY ^ {16{ADDSUBBOT}}) + LCI;
+	assign iR = OLOADBOT ? iD : YZ ^ {16{ADDSUBBOT}};
+	always @(posedge clock, posedge ORSTBOT) begin
+		if (ORSTBOT) begin
+			rS <= 0;
+		end else if (CE) begin
+			if (!OHOLDTOP) rS <= iR;
+		end
+	end
+	assign iS = rS;
+	assign Ol = (BOTOUTPUT_SELECT == 0) ? iR : (BOTOUTPUT_SELECT == 1) ? iS : (BOTOUTPUT_SELECT == 2) ? iG : iH[15:0];
+	assign LCI = (BOTADDSUB_CARRYSELECT == 0) ? 1'b0 : (BOTADDSUB_CARRYSELECT == 1) ? 1'b1 : (BOTADDSUB_CARRYSELECT == 2) ? ACCUMCI : CI;
+	assign O = {Oh, Ol};
+endmodule
diff --git a/techlibs/ice40/tests/test_dsp_model.gtkw b/techlibs/ice40/tests/test_dsp_model.gtkw
new file mode 100644
index 000000000..dafe8916f
--- /dev/null
+++ b/techlibs/ice40/tests/test_dsp_model.gtkw
@@ -0,0 +1,87 @@
+[*]
+[*] GTKWave Analyzer v3.3.86 (w)1999-2017 BSI
+[*] Tue Feb 19 13:33:31 2019
+[*]
+[dumpfile] "/home/clifford/Work/yosys/techlibs/ice40/tests/test_dsp_model.vcd"
+[dumpfile_mtime] "Tue Feb 19 13:29:34 2019"
+[dumpfile_size] 119605
+[savefile] "/home/clifford/Work/yosys/techlibs/ice40/tests/test_dsp_model.gtkw"
+[timestart] 0
+[size] 1850 1362
+[pos] 1816 32
+*-16.399944 42300 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
+[sst_width] 223
+[signals_width] 142
+[sst_expanded] 1
+[sst_vpaned_height] 420
+@28
+testbench.CLK
+testbench.CE
+@200
+-
+@28
+testbench.REF_ACCUMCO
+testbench.UUT_ACCUMCO
+@200
+-
+@28
+testbench.REF_CO
+testbench.UUT_CO
+@200
+-
+@22
+testbench.REF_O[31:0]
+testbench.UUT_O[31:0]
+@200
+-
+@28
+testbench.REF_SIGNEXTOUT
+testbench.UUT_SIGNEXTOUT
+@200
+-
+@22
+testbench.A[15:0]
+testbench.B[15:0]
+testbench.C[15:0]
+testbench.D[15:0]
+@200
+-
+@28
+testbench.AHOLD
+testbench.BHOLD
+testbench.CHOLD
+testbench.DHOLD
+@200
+-
+@28
+testbench.SIGNEXTIN
+testbench.ACCUMCI
+testbench.CI
+@200
+-
+@28
+testbench.ADDSUBTOP
+testbench.ADDSUBBOT
+@200
+-
+@28
+testbench.IRSTTOP
+testbench.IRSTBOT
+@200
+-
+@29
+testbench.OHOLDTOP
+@28
+testbench.OHOLDBOT
+@200
+-
+@28
+testbench.OLOADTOP
+testbench.OLOADBOT
+@200
+-
+@28
+testbench.ORSTTOP
+testbench.ORSTBOT
+[pattern_trace] 1
+[pattern_trace] 0
diff --git a/techlibs/ice40/tests/test_dsp_model.sh b/techlibs/ice40/tests/test_dsp_model.sh
new file mode 100644
index 000000000..ad079b2b6
--- /dev/null
+++ b/techlibs/ice40/tests/test_dsp_model.sh
@@ -0,0 +1,6 @@
+#!/bin/bash
+set -ex
+sed 's/SB_MAC16/SB_MAC16_UUT/; /SB_MAC16_UUT/,/endmodule/ p; d;' < ../cells_sim.v > test_dsp_model_uut.v
+cat /opt/lscc/iCEcube2.2017.01/verilog/sb_ice_syn.v > test_dsp_model_ref.v
+iverilog -s testbench -o test_dsp_model test_dsp_model.v test_dsp_model_uut.v test_dsp_model_ref.v
+./test_dsp_model
diff --git a/techlibs/ice40/tests/test_dsp_model.v b/techlibs/ice40/tests/test_dsp_model.v
new file mode 100644
index 000000000..919bb7917
--- /dev/null
+++ b/techlibs/ice40/tests/test_dsp_model.v
@@ -0,0 +1,199 @@
+`timescale 1ns / 1ps
+
+module testbench;
+	parameter [0:0] NEG_TRIGGER = 0;
+	parameter [0:0] C_REG = 0;
+	parameter [0:0] A_REG = 0;
+	parameter [0:0] B_REG = 0;
+	parameter [0:0] D_REG = 0;
+	parameter [0:0] TOP_8x8_MULT_REG = 0;
+	parameter [0:0] BOT_8x8_MULT_REG = 0;
+	parameter [0:0] PIPELINE_16x16_MULT_REG1 = 0;
+	parameter [0:0] PIPELINE_16x16_MULT_REG2 = 0;
+	parameter [1:0] TOPOUTPUT_SELECT = 0;
+	parameter [1:0] TOPADDSUB_LOWERINPUT = 2;
+	parameter [0:0] TOPADDSUB_UPPERINPUT = 1;
+	parameter [1:0] TOPADDSUB_CARRYSELECT = 2;
+	parameter [1:0] BOTOUTPUT_SELECT = 0;
+	parameter [1:0] BOTADDSUB_LOWERINPUT = 2;
+	parameter [0:0] BOTADDSUB_UPPERINPUT = 1;
+	parameter [1:0] BOTADDSUB_CARRYSELECT = 2;
+	parameter [0:0] MODE_8x8 = 0;
+	parameter [0:0] A_SIGNED = 0;
+	parameter [0:0] B_SIGNED = 0;
+
+	reg CLK, CE;
+	reg [15:0] C, A, B, D;
+	reg AHOLD, BHOLD, CHOLD, DHOLD;
+	reg IRSTTOP, IRSTBOT;
+	reg ORSTTOP, ORSTBOT;
+	reg OLOADTOP, OLOADBOT;
+	reg ADDSUBTOP, ADDSUBBOT;
+	reg OHOLDTOP, OHOLDBOT;
+	reg CI, ACCUMCI, SIGNEXTIN;
+
+	output [31:0] REF_O, UUT_O;
+	output REF_CO, REF_ACCUMCO, REF_SIGNEXTOUT;
+	output UUT_CO, UUT_ACCUMCO, UUT_SIGNEXTOUT;
+
+	integer errcount = 0;
+
+	task clkcycle;
+		begin
+			#5;
+			CLK = ~CLK;
+			#10;
+			CLK = ~CLK;
+			#2;
+			if (REF_O !== UUT_O) begin
+				$display("ERROR at %1t: REF_O=%b UUT_O=%b", $time, REF_O, UUT_O);
+				errcount = errcount + 1;
+			end
+			if (REF_CO !== UUT_CO) begin
+				$display("ERROR at %1t: REF_CO=%b UUT_CO=%b", $time, REF_CO, UUT_CO);
+				errcount = errcount + 1;
+			end
+			if (REF_ACCUMCO !== UUT_ACCUMCO) begin
+				$display("ERROR at %1t: REF_ACCUMCO=%b UUT_ACCUMCO=%b", $time, REF_ACCUMCO, UUT_ACCUMCO);
+				errcount = errcount + 1;
+			end
+			if (REF_SIGNEXTOUT !== UUT_SIGNEXTOUT) begin
+				$display("ERROR at %1t: REF_SIGNEXTOUT=%b UUT_SIGNEXTOUT=%b", $time, REF_SIGNEXTOUT, UUT_SIGNEXTOUT);
+				errcount = errcount + 1;
+			end
+			#3;
+		end
+	endtask
+
+	initial begin
+		$dumpfile("test_dsp_model.vcd");
+		$dumpvars(0, testbench);
+
+		#5;
+		CLK = NEG_TRIGGER;
+		CE = 1;
+		{C, A, B, D} = 0;
+		{AHOLD, BHOLD, CHOLD, DHOLD} = 0;
+		{IRSTTOP, IRSTBOT} = 0;
+		{ORSTTOP, ORSTBOT} = 0;
+		{OLOADTOP, OLOADBOT} = 0;
+		{ADDSUBTOP, ADDSUBBOT} = 0;
+		{OHOLDTOP, OHOLDBOT} = 0;
+		{CI, ACCUMCI, SIGNEXTIN} = 0;
+
+		// C = 10;
+		// A = 15;
+		// B = 22;
+		// D = 27;
+
+		repeat (10) clkcycle;
+
+		if (errcount == 0) begin
+			$display("All tests passed.");
+		end else begin
+			$display("Caught %1d errors.", errcount);
+		end
+	end
+
+	SB_MAC16 #(
+		.NEG_TRIGGER              (NEG_TRIGGER             ),
+		.C_REG                    (C_REG                   ),
+		.A_REG                    (A_REG                   ),
+		.B_REG                    (B_REG                   ),
+		.D_REG                    (D_REG                   ),
+		.TOP_8x8_MULT_REG         (TOP_8x8_MULT_REG        ),
+		.BOT_8x8_MULT_REG         (BOT_8x8_MULT_REG        ),
+		.PIPELINE_16x16_MULT_REG1 (PIPELINE_16x16_MULT_REG1),
+		.PIPELINE_16x16_MULT_REG2 (PIPELINE_16x16_MULT_REG2),
+		.TOPOUTPUT_SELECT         (TOPOUTPUT_SELECT        ),
+		.TOPADDSUB_LOWERINPUT     (TOPADDSUB_LOWERINPUT    ),
+		.TOPADDSUB_UPPERINPUT     (TOPADDSUB_UPPERINPUT    ),
+		.TOPADDSUB_CARRYSELECT    (TOPADDSUB_CARRYSELECT   ),
+		.BOTOUTPUT_SELECT         (BOTOUTPUT_SELECT        ),
+		.BOTADDSUB_LOWERINPUT     (BOTADDSUB_LOWERINPUT    ),
+		.BOTADDSUB_UPPERINPUT     (BOTADDSUB_UPPERINPUT    ),
+		.BOTADDSUB_CARRYSELECT    (BOTADDSUB_CARRYSELECT   ),
+		.MODE_8x8                 (MODE_8x8                ),
+		.A_SIGNED                 (A_SIGNED                ),
+		.B_SIGNED                 (B_SIGNED                )
+	) ref (
+		.CLK        (CLK           ),
+		.CE         (CE            ),
+		.C          (C             ),
+		.A          (A             ),
+		.B          (B             ),
+		.D          (D             ),
+		.AHOLD      (AHOLD         ),
+		.BHOLD      (BHOLD         ),
+		.CHOLD      (CHOLD         ),
+		.DHOLD      (DHOLD         ),
+		.IRSTTOP    (IRSTTOP       ),
+		.IRSTBOT    (IRSTBOT       ),
+		.ORSTTOP    (ORSTTOP       ),
+		.ORSTBOT    (ORSTBOT       ),
+		.OLOADTOP   (OLOADTOP      ),
+		.OLOADBOT   (OLOADBOT      ),
+		.ADDSUBTOP  (ADDSUBTOP     ),
+		.ADDSUBBOT  (ADDSUBBOT     ),
+		.OHOLDTOP   (OHOLDTOP      ),
+		.OHOLDBOT   (OHOLDBOT      ),
+		.CI         (CI            ),
+		.ACCUMCI    (ACCUMCI       ),
+		.SIGNEXTIN  (SIGNEXTIN     ),
+		.O          (REF_O         ),
+		.CO         (REF_CO        ),
+		.ACCUMCO    (REF_ACCUMCO   ),
+		.SIGNEXTOUT (REF_SIGNEXTOUT)
+	);
+
+	SB_MAC16_UUT #(
+		.NEG_TRIGGER              (NEG_TRIGGER             ),
+		.C_REG                    (C_REG                   ),
+		.A_REG                    (A_REG                   ),
+		.B_REG                    (B_REG                   ),
+		.D_REG                    (D_REG                   ),
+		.TOP_8x8_MULT_REG         (TOP_8x8_MULT_REG        ),
+		.BOT_8x8_MULT_REG         (BOT_8x8_MULT_REG        ),
+		.PIPELINE_16x16_MULT_REG1 (PIPELINE_16x16_MULT_REG1),
+		.PIPELINE_16x16_MULT_REG2 (PIPELINE_16x16_MULT_REG2),
+		.TOPOUTPUT_SELECT         (TOPOUTPUT_SELECT        ),
+		.TOPADDSUB_LOWERINPUT     (TOPADDSUB_LOWERINPUT    ),
+		.TOPADDSUB_UPPERINPUT     (TOPADDSUB_UPPERINPUT    ),
+		.TOPADDSUB_CARRYSELECT    (TOPADDSUB_CARRYSELECT   ),
+		.BOTOUTPUT_SELECT         (BOTOUTPUT_SELECT        ),
+		.BOTADDSUB_LOWERINPUT     (BOTADDSUB_LOWERINPUT    ),
+		.BOTADDSUB_UPPERINPUT     (BOTADDSUB_UPPERINPUT    ),
+		.BOTADDSUB_CARRYSELECT    (BOTADDSUB_CARRYSELECT   ),
+		.MODE_8x8                 (MODE_8x8                ),
+		.A_SIGNED                 (A_SIGNED                ),
+		.B_SIGNED                 (B_SIGNED                )
+	) uut (
+		.CLK        (CLK           ),
+		.CE         (CE            ),
+		.C          (C             ),
+		.A          (A             ),
+		.B          (B             ),
+		.D          (D             ),
+		.AHOLD      (AHOLD         ),
+		.BHOLD      (BHOLD         ),
+		.CHOLD      (CHOLD         ),
+		.DHOLD      (DHOLD         ),
+		.IRSTTOP    (IRSTTOP       ),
+		.IRSTBOT    (IRSTBOT       ),
+		.ORSTTOP    (ORSTTOP       ),
+		.ORSTBOT    (ORSTBOT       ),
+		.OLOADTOP   (OLOADTOP      ),
+		.OLOADBOT   (OLOADBOT      ),
+		.ADDSUBTOP  (ADDSUBTOP     ),
+		.ADDSUBBOT  (ADDSUBBOT     ),
+		.OHOLDTOP   (OHOLDTOP      ),
+		.OHOLDBOT   (OHOLDBOT      ),
+		.CI         (CI            ),
+		.ACCUMCI    (ACCUMCI       ),
+		.SIGNEXTIN  (SIGNEXTIN     ),
+		.O          (UUT_O         ),
+		.CO         (UUT_CO        ),
+		.ACCUMCO    (UUT_ACCUMCO   ),
+		.SIGNEXTOUT (UUT_SIGNEXTOUT)
+	);
+endmodule
-- 
cgit v1.2.3


From 7bf4e4a1855df442191e3d1cc28eeda7e01d051c Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Wed, 20 Feb 2019 12:55:20 +0100
Subject: Improve iCE40 SB_MAC16 model

Signed-off-by: Clifford Wolf <clifford@clifford.at>
---
 techlibs/ice40/cells_sim.v               |  27 ++---
 techlibs/ice40/tests/.gitignore          |   8 +-
 techlibs/ice40/tests/test_dsp_model.gtkw |  87 ----------------
 techlibs/ice40/tests/test_dsp_model.sh   |   9 +-
 techlibs/ice40/tests/test_dsp_model.v    | 169 ++++++++++++++++++++++++++++---
 5 files changed, 179 insertions(+), 121 deletions(-)
 delete mode 100644 techlibs/ice40/tests/test_dsp_model.gtkw

(limited to 'techlibs/ice40')

diff --git a/techlibs/ice40/cells_sim.v b/techlibs/ice40/cells_sim.v
index 4a92fccdf..2041693cc 100644
--- a/techlibs/ice40/cells_sim.v
+++ b/techlibs/ice40/cells_sim.v
@@ -1283,7 +1283,7 @@ module SB_MAC16 (
 
 	// Regs B and D
 	reg [15:0] rB, rD;
-	always @(posedge clock, posedge IRSTTOP) begin
+	always @(posedge clock, posedge IRSTBOT) begin
 		if (IRSTBOT) begin
 			rB <= 0;
 			rD <= 0;
@@ -1298,10 +1298,10 @@ module SB_MAC16 (
 	// Multiplier Stage
 	wire [15:0] p_Ah_Bh, p_Al_Bh, p_Ah_Bl, p_Al_Bl;
 	wire [15:0] Ah, Al, Bh, Bl;
-	assign Ah = A_SIGNED ? {{8{iA[15]}}, iA[15: 8]} : iA[15: 8];
-	assign Al = A_SIGNED ? {{8{iA[ 7]}}, iA[ 7: 0]} : iA[15: 8];
-	assign Bh = B_SIGNED ? {{8{iB[15]}}, iB[15: 8]} : iB[15: 8];
-	assign Bl = B_SIGNED ? {{8{iB[ 7]}}, iB[ 7: 0]} : iB[15: 8];
+	assign Ah = {A_SIGNED ? {8{iA[15]}} : 8'b0, iA[15: 8]};
+	assign Al = {A_SIGNED ? {8{iA[ 7]}} : 8'b0, iA[ 7: 0]};
+	assign Bh = {B_SIGNED ? {8{iB[15]}} : 8'b0, iB[15: 8]};
+	assign Bl = {B_SIGNED ? {8{iB[ 7]}} : 8'b0, iB[ 7: 0]};
 	assign p_Ah_Bh = Ah * Bh;
 	assign p_Al_Bh = Al * Bh;
 	assign p_Ah_Bl = Ah * Bl;
@@ -1336,17 +1336,10 @@ module SB_MAC16 (
 	assign iG = BOT_8x8_MULT_REG ? rG : p_Al_Bl;
 
 	// Adder Stage
-	reg [31:0] P;
-	always @* begin
-		P = iG[7:0];
-		P = P + (iG[15:8] + iK[7:0]) << 8;
-		P = P + (iK[15:8] + iJ[7:0]) << 16;
-		P = P + (iJ[15:8] + iF[7:0]) << 24;
-	end
-	assign iL = P;
+	assign iL = iG + (iK << 8) + (iJ << 8) + (iF << 16);
 
 	// Reg H
-	reg [15:0] rH;
+	reg [31:0] rH;
 	always @(posedge clock, posedge IRSTBOT) begin
 		if (IRSTBOT) begin
 			rH <= 0;
@@ -1359,7 +1352,7 @@ module SB_MAC16 (
 	// Hi Output Stage
 	wire [15:0] XW, Oh;
 	reg [15:0] rQ;
-	assign iW = TOPADDSUB_UPPERINPUT ? iC : iQ[31:16];
+	assign iW = TOPADDSUB_UPPERINPUT ? iC : iQ;
 	assign iX = (TOPADDSUB_LOWERINPUT == 0) ? iA : (TOPADDSUB_LOWERINPUT == 1) ? iF : (TOPADDSUB_LOWERINPUT == 2) ? iH[31:16] : {16{iZ[15]}};
 	assign {ACCUMCO, XW} = iX + (iW ^ {16{ADDSUBTOP}}) + HCI;
 	assign CO = ACCUMCO ^ ADDSUBTOP;
@@ -1379,7 +1372,7 @@ module SB_MAC16 (
 	// Lo Output Stage
 	wire [15:0] YZ, Ol;
 	reg [15:0] rS;
-	assign iY = BOTADDSUB_UPPERINPUT ? iD : iQ[15:0];
+	assign iY = BOTADDSUB_UPPERINPUT ? iD : iS;
 	assign iZ = (BOTADDSUB_LOWERINPUT == 0) ? iB : (BOTADDSUB_LOWERINPUT == 1) ? iG : (BOTADDSUB_LOWERINPUT == 2) ? iH[15:0] : {16{SIGNEXTIN}};
 	assign {LCO, YZ} = iZ + (iY ^ {16{ADDSUBBOT}}) + LCI;
 	assign iR = OLOADBOT ? iD : YZ ^ {16{ADDSUBBOT}};
@@ -1387,7 +1380,7 @@ module SB_MAC16 (
 		if (ORSTBOT) begin
 			rS <= 0;
 		end else if (CE) begin
-			if (!OHOLDTOP) rS <= iR;
+			if (!OHOLDBOT) rS <= iR;
 		end
 	end
 	assign iS = rS;
diff --git a/techlibs/ice40/tests/.gitignore b/techlibs/ice40/tests/.gitignore
index b58f9ad4a..9795152c2 100644
--- a/techlibs/ice40/tests/.gitignore
+++ b/techlibs/ice40/tests/.gitignore
@@ -1,2 +1,6 @@
-test_ffs_[01][01][01][01][01]_*
-test_bram_[0-9]*
+/test_ffs_[01][01][01][01][01]_*
+/test_bram_[0-9]*
+/test_dsp_model
+/test_dsp_model.vcd
+/test_dsp_model_ref.v
+/test_dsp_model_uut.v
diff --git a/techlibs/ice40/tests/test_dsp_model.gtkw b/techlibs/ice40/tests/test_dsp_model.gtkw
deleted file mode 100644
index dafe8916f..000000000
--- a/techlibs/ice40/tests/test_dsp_model.gtkw
+++ /dev/null
@@ -1,87 +0,0 @@
-[*]
-[*] GTKWave Analyzer v3.3.86 (w)1999-2017 BSI
-[*] Tue Feb 19 13:33:31 2019
-[*]
-[dumpfile] "/home/clifford/Work/yosys/techlibs/ice40/tests/test_dsp_model.vcd"
-[dumpfile_mtime] "Tue Feb 19 13:29:34 2019"
-[dumpfile_size] 119605
-[savefile] "/home/clifford/Work/yosys/techlibs/ice40/tests/test_dsp_model.gtkw"
-[timestart] 0
-[size] 1850 1362
-[pos] 1816 32
-*-16.399944 42300 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
-[sst_width] 223
-[signals_width] 142
-[sst_expanded] 1
-[sst_vpaned_height] 420
-@28
-testbench.CLK
-testbench.CE
-@200
--
-@28
-testbench.REF_ACCUMCO
-testbench.UUT_ACCUMCO
-@200
--
-@28
-testbench.REF_CO
-testbench.UUT_CO
-@200
--
-@22
-testbench.REF_O[31:0]
-testbench.UUT_O[31:0]
-@200
--
-@28
-testbench.REF_SIGNEXTOUT
-testbench.UUT_SIGNEXTOUT
-@200
--
-@22
-testbench.A[15:0]
-testbench.B[15:0]
-testbench.C[15:0]
-testbench.D[15:0]
-@200
--
-@28
-testbench.AHOLD
-testbench.BHOLD
-testbench.CHOLD
-testbench.DHOLD
-@200
--
-@28
-testbench.SIGNEXTIN
-testbench.ACCUMCI
-testbench.CI
-@200
--
-@28
-testbench.ADDSUBTOP
-testbench.ADDSUBBOT
-@200
--
-@28
-testbench.IRSTTOP
-testbench.IRSTBOT
-@200
--
-@29
-testbench.OHOLDTOP
-@28
-testbench.OHOLDBOT
-@200
--
-@28
-testbench.OLOADTOP
-testbench.OLOADBOT
-@200
--
-@28
-testbench.ORSTTOP
-testbench.ORSTBOT
-[pattern_trace] 1
-[pattern_trace] 0
diff --git a/techlibs/ice40/tests/test_dsp_model.sh b/techlibs/ice40/tests/test_dsp_model.sh
index ad079b2b6..1bc0cc688 100644
--- a/techlibs/ice40/tests/test_dsp_model.sh
+++ b/techlibs/ice40/tests/test_dsp_model.sh
@@ -2,5 +2,10 @@
 set -ex
 sed 's/SB_MAC16/SB_MAC16_UUT/; /SB_MAC16_UUT/,/endmodule/ p; d;' < ../cells_sim.v > test_dsp_model_uut.v
 cat /opt/lscc/iCEcube2.2017.01/verilog/sb_ice_syn.v > test_dsp_model_ref.v
-iverilog -s testbench -o test_dsp_model test_dsp_model.v test_dsp_model_uut.v test_dsp_model_ref.v
-./test_dsp_model
+for tb in testbench \
+		testbench_comb_8x8_A testbench_comb_8x8_B testbench_comb_16x16 \
+		testbench_seq_16x16_A testbench_seq_16x16_B
+do
+	iverilog -s $tb -o test_dsp_model test_dsp_model.v test_dsp_model_uut.v test_dsp_model_ref.v
+	vvp -N ./test_dsp_model
+done
diff --git a/techlibs/ice40/tests/test_dsp_model.v b/techlibs/ice40/tests/test_dsp_model.v
index 919bb7917..594bd4ad3 100644
--- a/techlibs/ice40/tests/test_dsp_model.v
+++ b/techlibs/ice40/tests/test_dsp_model.v
@@ -11,13 +11,13 @@ module testbench;
 	parameter [0:0] PIPELINE_16x16_MULT_REG1 = 0;
 	parameter [0:0] PIPELINE_16x16_MULT_REG2 = 0;
 	parameter [1:0] TOPOUTPUT_SELECT = 0;
-	parameter [1:0] TOPADDSUB_LOWERINPUT = 2;
+	parameter [1:0] TOPADDSUB_LOWERINPUT = 0;
 	parameter [0:0] TOPADDSUB_UPPERINPUT = 1;
-	parameter [1:0] TOPADDSUB_CARRYSELECT = 2;
+	parameter [1:0] TOPADDSUB_CARRYSELECT = 0;
 	parameter [1:0] BOTOUTPUT_SELECT = 0;
-	parameter [1:0] BOTADDSUB_LOWERINPUT = 2;
+	parameter [1:0] BOTADDSUB_LOWERINPUT = 0;
 	parameter [0:0] BOTADDSUB_UPPERINPUT = 1;
-	parameter [1:0] BOTADDSUB_CARRYSELECT = 2;
+	parameter [1:0] BOTADDSUB_CARRYSELECT = 0;
 	parameter [0:0] MODE_8x8 = 0;
 	parameter [0:0] A_SIGNED = 0;
 	parameter [0:0] B_SIGNED = 0;
@@ -46,7 +46,7 @@ module testbench;
 			CLK = ~CLK;
 			#2;
 			if (REF_O !== UUT_O) begin
-				$display("ERROR at %1t: REF_O=%b UUT_O=%b", $time, REF_O, UUT_O);
+				$display("ERROR at %1t: REF_O=%b UUT_O=%b DIFF=%b", $time, REF_O, UUT_O, REF_O ^ UUT_O);
 				errcount = errcount + 1;
 			end
 			if (REF_CO !== UUT_CO) begin
@@ -69,29 +69,47 @@ module testbench;
 		$dumpfile("test_dsp_model.vcd");
 		$dumpvars(0, testbench);
 
-		#5;
+		#2;
 		CLK = NEG_TRIGGER;
 		CE = 1;
 		{C, A, B, D} = 0;
 		{AHOLD, BHOLD, CHOLD, DHOLD} = 0;
-		{IRSTTOP, IRSTBOT} = 0;
-		{ORSTTOP, ORSTBOT} = 0;
 		{OLOADTOP, OLOADBOT} = 0;
 		{ADDSUBTOP, ADDSUBBOT} = 0;
 		{OHOLDTOP, OHOLDBOT} = 0;
 		{CI, ACCUMCI, SIGNEXTIN} = 0;
 
-		// C = 10;
-		// A = 15;
-		// B = 22;
-		// D = 27;
+		{IRSTTOP, IRSTBOT} = ~0;
+		{ORSTTOP, ORSTBOT} = ~0;
+
+		#3;
+		{IRSTTOP, IRSTBOT} = 0;
+		{ORSTTOP, ORSTBOT} = 0;
+
+		repeat (300) begin
+			clkcycle;
+
+			A = $urandom;
+			B = $urandom;
+			C = $urandom;
+			D = $urandom;
 
-		repeat (10) clkcycle;
+			{AHOLD, BHOLD, CHOLD, DHOLD} = $urandom & $urandom & $urandom;
+			{OLOADTOP, OLOADBOT} = $urandom & $urandom & $urandom;
+			{ADDSUBTOP, ADDSUBBOT} = $urandom & $urandom & $urandom;
+			{OHOLDTOP, OHOLDBOT} = $urandom & $urandom & $urandom;
+			{CI, ACCUMCI, SIGNEXTIN} = $urandom & $urandom & $urandom;
+
+			{IRSTTOP, IRSTBOT} = $urandom & $urandom & $urandom;
+			{ORSTTOP, ORSTBOT} = $urandom & $urandom & $urandom;
+		end
 
 		if (errcount == 0) begin
 			$display("All tests passed.");
+			$finish;
 		end else begin
 			$display("Caught %1d errors.", errcount);
+			$stop;
 		end
 	end
 
@@ -197,3 +215,128 @@ module testbench;
 		.SIGNEXTOUT (UUT_SIGNEXTOUT)
 	);
 endmodule
+
+module testbench_comb_8x8_A;
+	testbench #(
+		.NEG_TRIGGER               (0),
+		.C_REG                     (0),
+		.A_REG                     (0),
+		.B_REG                     (0),
+		.D_REG                     (0),
+		.TOP_8x8_MULT_REG          (0),
+		.BOT_8x8_MULT_REG          (0),
+		.PIPELINE_16x16_MULT_REG1  (0),
+		.PIPELINE_16x16_MULT_REG2  (0),
+		.TOPOUTPUT_SELECT          (2),   // 0=P, 1=Q, 2=8x8, 3=16x16
+		.TOPADDSUB_LOWERINPUT      (0),   // 0=A, 1=8x8, 2=16x16, 3=S-EXT
+		.TOPADDSUB_UPPERINPUT      (0),   // 0=Q, 1=C
+		.TOPADDSUB_CARRYSELECT     (0),   // 0=0, 1=1, 2=ACI, 3=CI
+		.BOTOUTPUT_SELECT          (2),   // 0=R, 1=S, 2=8x8, 3=16x16
+		.BOTADDSUB_LOWERINPUT      (0),   // 0=B, 1=8x8, 2=16x16, 3=S-EXT
+		.BOTADDSUB_UPPERINPUT      (0),   // 0=S, 1=D
+		.BOTADDSUB_CARRYSELECT     (0),   // 0=0, 1=1, 2=ACI, 3=CI
+		.MODE_8x8                  (0),
+		.A_SIGNED                  (0),
+		.B_SIGNED                  (0)
+	) testbench ();
+endmodule
+
+module testbench_comb_8x8_B;
+	testbench #(
+		.NEG_TRIGGER               (0),
+		.C_REG                     (0),
+		.A_REG                     (0),
+		.B_REG                     (0),
+		.D_REG                     (0),
+		.TOP_8x8_MULT_REG          (0),
+		.BOT_8x8_MULT_REG          (0),
+		.PIPELINE_16x16_MULT_REG1  (0),
+		.PIPELINE_16x16_MULT_REG2  (0),
+		.TOPOUTPUT_SELECT          (0),   // 0=P, 1=Q, 2=8x8, 3=16x16
+		.TOPADDSUB_LOWERINPUT      (1),   // 0=A, 1=8x8, 2=16x16, 3=S-EXT
+		.TOPADDSUB_UPPERINPUT      (1),   // 0=Q, 1=C
+		.TOPADDSUB_CARRYSELECT     (0),   // 0=0, 1=1, 2=ACI, 3=CI
+		.BOTOUTPUT_SELECT          (0),   // 0=R, 1=S, 2=8x8, 3=16x16
+		.BOTADDSUB_LOWERINPUT      (1),   // 0=B, 1=8x8, 2=16x16, 3=S-EXT
+		.BOTADDSUB_UPPERINPUT      (1),   // 0=S, 1=D
+		.BOTADDSUB_CARRYSELECT     (0),   // 0=0, 1=1, 2=ACI, 3=CI
+		.MODE_8x8                  (0),
+		.A_SIGNED                  (0),
+		.B_SIGNED                  (0)
+	) testbench ();
+endmodule
+
+module testbench_comb_16x16;
+	testbench #(
+		.NEG_TRIGGER               (0),
+		.C_REG                     (0),
+		.A_REG                     (0),
+		.B_REG                     (0),
+		.D_REG                     (0),
+		.TOP_8x8_MULT_REG          (0),
+		.BOT_8x8_MULT_REG          (0),
+		.PIPELINE_16x16_MULT_REG1  (0),
+		.PIPELINE_16x16_MULT_REG2  (0),
+		.TOPOUTPUT_SELECT          (0),   // 0=P, 1=Q, 2=8x8, 3=16x16
+		.TOPADDSUB_LOWERINPUT      (2),   // 0=A, 1=8x8, 2=16x16, 3=S-EXT
+		.TOPADDSUB_UPPERINPUT      (1),   // 0=Q, 1=C
+		.TOPADDSUB_CARRYSELECT     (2),   // 0=0, 1=1, 2=ACI, 3=CI
+		.BOTOUTPUT_SELECT          (0),   // 0=R, 1=S, 2=8x8, 3=16x16
+		.BOTADDSUB_LOWERINPUT      (2),   // 0=B, 1=8x8, 2=16x16, 3=S-EXT
+		.BOTADDSUB_UPPERINPUT      (1),   // 0=S, 1=D
+		.BOTADDSUB_CARRYSELECT     (2),   // 0=0, 1=1, 2=ACI, 3=CI
+		.MODE_8x8                  (0),
+		.A_SIGNED                  (0),
+		.B_SIGNED                  (0)
+	) testbench ();
+endmodule
+
+module testbench_seq_16x16_A;
+	testbench #(
+		.NEG_TRIGGER               (0),
+		.C_REG                     (1),
+		.A_REG                     (1),
+		.B_REG                     (1),
+		.D_REG                     (1),
+		.TOP_8x8_MULT_REG          (1),
+		.BOT_8x8_MULT_REG          (1),
+		.PIPELINE_16x16_MULT_REG1  (1),
+		.PIPELINE_16x16_MULT_REG2  (1),
+		.TOPOUTPUT_SELECT          (0),   // 0=P, 1=Q, 2=8x8, 3=16x16
+		.TOPADDSUB_LOWERINPUT      (2),   // 0=A, 1=8x8, 2=16x16, 3=S-EXT
+		.TOPADDSUB_UPPERINPUT      (1),   // 0=Q, 1=C
+		.TOPADDSUB_CARRYSELECT     (2),   // 0=0, 1=1, 2=ACI, 3=CI
+		.BOTOUTPUT_SELECT          (0),   // 0=R, 1=S, 2=8x8, 3=16x16
+		.BOTADDSUB_LOWERINPUT      (2),   // 0=B, 1=8x8, 2=16x16, 3=S-EXT
+		.BOTADDSUB_UPPERINPUT      (1),   // 0=S, 1=D
+		.BOTADDSUB_CARRYSELECT     (2),   // 0=0, 1=1, 2=ACI, 3=CI
+		.MODE_8x8                  (0),
+		.A_SIGNED                  (0),
+		.B_SIGNED                  (0)
+	) testbench ();
+endmodule
+
+module testbench_seq_16x16_B;
+	testbench #(
+		.NEG_TRIGGER               (0),
+		.C_REG                     (1),
+		.A_REG                     (1),
+		.B_REG                     (1),
+		.D_REG                     (1),
+		.TOP_8x8_MULT_REG          (1),
+		.BOT_8x8_MULT_REG          (1),
+		.PIPELINE_16x16_MULT_REG1  (1),
+		.PIPELINE_16x16_MULT_REG2  (0),
+		.TOPOUTPUT_SELECT          (1),   // 0=P, 1=Q, 2=8x8, 3=16x16
+		.TOPADDSUB_LOWERINPUT      (2),   // 0=A, 1=8x8, 2=16x16, 3=S-EXT
+		.TOPADDSUB_UPPERINPUT      (0),   // 0=Q, 1=C
+		.TOPADDSUB_CARRYSELECT     (2),   // 0=0, 1=1, 2=ACI, 3=CI
+		.BOTOUTPUT_SELECT          (1),   // 0=R, 1=S, 2=8x8, 3=16x16
+		.BOTADDSUB_LOWERINPUT      (2),   // 0=B, 1=8x8, 2=16x16, 3=S-EXT
+		.BOTADDSUB_UPPERINPUT      (0),   // 0=S, 1=D
+		.BOTADDSUB_CARRYSELECT     (2),   // 0=0, 1=1, 2=ACI, 3=CI
+		.MODE_8x8                  (0),
+		.A_SIGNED                  (0),
+		.B_SIGNED                  (0)
+	) testbench ();
+endmodule
-- 
cgit v1.2.3


From 218e9051bbdbbd00620a21e6918e6a4b9bc07867 Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Wed, 20 Feb 2019 16:42:27 +0100
Subject: Add "synth_ice40 -dsp"

Signed-off-by: Clifford Wolf <clifford@clifford.at>
---
 techlibs/ice40/synth_ice40.cc | 30 +++++++++++++++++++++++++++---
 1 file changed, 27 insertions(+), 3 deletions(-)

(limited to 'techlibs/ice40')

diff --git a/techlibs/ice40/synth_ice40.cc b/techlibs/ice40/synth_ice40.cc
index f900453e8..d6d047fe7 100644
--- a/techlibs/ice40/synth_ice40.cc
+++ b/techlibs/ice40/synth_ice40.cc
@@ -79,6 +79,9 @@ struct SynthIce40Pass : public ScriptPass
 		log("    -nobram\n");
 		log("        do not use SB_RAM40_4K* cells in output netlist\n");
 		log("\n");
+		log("    -dsp\n");
+		log("        use iCE40 UltraPlus DSP cells for large arithmetic\n");
+		log("\n");
 		log("    -noabc\n");
 		log("        use built-in Yosys LUT techmapping instead of abc\n");
 		log("\n");
@@ -96,7 +99,7 @@ struct SynthIce40Pass : public ScriptPass
 	}
 
 	string top_opt, blif_file, edif_file, json_file;
-	bool nocarry, nodffe, nobram, flatten, retime, relut, noabc, abc2, vpr;
+	bool nocarry, nodffe, nobram, dsp, flatten, retime, relut, noabc, abc2, vpr;
 	int min_ce_use;
 
 	void clear_flags() YS_OVERRIDE
@@ -109,6 +112,7 @@ struct SynthIce40Pass : public ScriptPass
 		nodffe = false;
 		min_ce_use = -1;
 		nobram = false;
+		dsp = false;
 		flatten = true;
 		retime = false;
 		relut = false;
@@ -181,6 +185,10 @@ struct SynthIce40Pass : public ScriptPass
 				nobram = true;
 				continue;
 			}
+			if (args[argidx] == "-dsp") {
+				dsp = true;
+				continue;
+			}
 			if (args[argidx] == "-noabc") {
 				noabc = true;
 				continue;
@@ -214,11 +222,11 @@ struct SynthIce40Pass : public ScriptPass
 		{
 			run("read_verilog -lib +/ice40/cells_sim.v");
 			run(stringf("hierarchy -check %s", help_mode ? "-top <top>" : top_opt.c_str()));
+			run("proc");
 		}
 
 		if (flatten && check_label("flatten", "(unless -noflatten)"))
 		{
-			run("proc");
 			run("flatten");
 			run("tribuf -logic");
 			run("deminout");
@@ -226,7 +234,23 @@ struct SynthIce40Pass : public ScriptPass
 
 		if (check_label("coarse"))
 		{
-			run("synth -lut 4 -run coarse");
+			run("opt_expr");
+			run("opt_clean");
+			run("check");
+			run("opt");
+			run("wreduce");
+			run("share");
+			run("techmap -map +/cmp2lut.v -D LUT_WIDTH=4");
+			run("opt_expr");
+			run("opt_clean");
+			if (help_mode || dsp)
+				run("ice40_dsp", "(if -dsp)");
+			run("alumacc");
+			run("opt");
+			run("fsm");
+			run("opt -fast");
+			run("memory -nomap");
+			run("opt_clean");
 		}
 
 		if (!nobram && check_label("bram", "(skip if -nobram)"))
-- 
cgit v1.2.3


From 84999a7e680648dff674ce55f634a675852b7dc3 Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Wed, 20 Feb 2019 17:18:59 +0100
Subject: Add ice40 test_dsp_map test case generator

Signed-off-by: Clifford Wolf <clifford@clifford.at>
---
 techlibs/ice40/tests/.gitignore      |  4 ++
 techlibs/ice40/tests/test_dsp_map.sh | 95 ++++++++++++++++++++++++++++++++++++
 2 files changed, 99 insertions(+)
 create mode 100644 techlibs/ice40/tests/test_dsp_map.sh

(limited to 'techlibs/ice40')

diff --git a/techlibs/ice40/tests/.gitignore b/techlibs/ice40/tests/.gitignore
index 9795152c2..300ce9aa6 100644
--- a/techlibs/ice40/tests/.gitignore
+++ b/techlibs/ice40/tests/.gitignore
@@ -4,3 +4,7 @@
 /test_dsp_model.vcd
 /test_dsp_model_ref.v
 /test_dsp_model_uut.v
+/test_dsp_map
+/test_dsp_map_tb.v
+/test_dsp_map_top.v
+/test_dsp_map_syn.v
diff --git a/techlibs/ice40/tests/test_dsp_map.sh b/techlibs/ice40/tests/test_dsp_map.sh
new file mode 100644
index 000000000..5982e5b34
--- /dev/null
+++ b/techlibs/ice40/tests/test_dsp_map.sh
@@ -0,0 +1,95 @@
+#!/bin/bash
+set -ex
+
+SZA=$(( 3 + $RANDOM % 13 ))
+SZB=$(( 3 + $RANDOM % 13 ))
+SZO=$(( 3 + $RANDOM % 29 ))
+
+C0=clk$(( $RANDOM & 1))
+C1=clk$(( $RANDOM & 1))
+C2=clk$(( $RANDOM & 1))
+C3=clk$(( $RANDOM & 1))
+
+E0=$( test $(( $RANDOM & 1 )) -eq 0 && echo posedge || echo negedge )
+E1=$( test $(( $RANDOM & 1 )) -eq 0 && echo posedge || echo negedge )
+E2=$( test $(( $RANDOM & 1 )) -eq 0 && echo posedge || echo negedge )
+E3=$( test $(( $RANDOM & 1 )) -eq 0 && echo posedge || echo negedge )
+
+SP=$( test $(( $RANDOM & 1 )) -eq 0 && echo S || echo P )
+
+RC=$( test $(( $RANDOM & 1 )) -eq 0 && echo "reset" || echo "!reset" )
+RV="32'h$( echo $RANDOM | md5sum | cut -c1-8 )"
+
+cat > test_dsp_map_top.v << EOT
+module top (
+	input clk0, clk1, reset,
+	input  [$SZA:0] A,
+	input  [$SZB:0] B,
+	output [$SZO:0] O
+);
+	reg [15:0] AA, BB;
+	reg [31:0] P, S;
+
+	always @($E0 $C0) AA <= A;
+	always @($E1 $C1) BB <= B;
+	always @($E2 $C2) P <= AA * BB;
+	always @($E3 $C3) S <= $RC ? $RV : S + P;
+	assign O = $SP;
+endmodule
+EOT
+
+cat > test_dsp_map_tb.v << EOT
+\`timescale 1ns / 1ps
+module testbench;
+	reg clk1, clk0, reset;
+	reg [$SZA:0] A;
+	reg [$SZB:0] B;
+
+	wire [$SZO:0] O_top, O_syn;
+
+	top top_inst (.clk0(clk0), .clk1(clk1), .reset(reset), .A(A), .B(B), .O(O_top));
+	syn syn_inst (.clk0(clk0), .clk1(clk1), .reset(reset), .A(A), .B(B), .O(O_syn));
+
+	initial begin
+		#2;
+		clk0 = 0;
+		clk1 = 0;
+		reset = 1;
+		A = 0;
+		B = 0;
+
+		repeat (3) begin
+			#2; clk0 = ~clk0;
+			#2; clk0 = ~clk0;
+			#2; clk1 = ~clk1;
+			#2; clk1 = ~clk1;
+		end
+
+		repeat (100) begin
+			#2;
+			A = \$urandom;
+			B = \$urandom;
+			reset = \$urandom & \$urandom & \$urandom & \$urandom;
+			if (\$urandom & 1) begin
+				#2; clk0 = ~clk0;
+				#2; clk0 = ~clk0;
+			end else begin
+				#2; clk1 = ~clk1;
+				#2; clk1 = ~clk1;
+			end
+			#2;
+			if (O_top !== O_syn) begin
+				\$display("ERROR: O_top=%b O_syn=%b", O_top, O_syn);
+				\$stop;
+			end
+			\$display("OK O_top=O_syn=%b", O_top);
+		end
+
+		\$finish;
+	end
+endmodule
+EOT
+
+../../../yosys -p 'read_verilog test_dsp_map_top.v; synth_ice40 -dsp; rename top syn; write_verilog test_dsp_map_syn.v'
+iverilog -o test_dsp_map -s testbench test_dsp_map_tb.v test_dsp_map_top.v test_dsp_map_syn.v ../cells_sim.v
+vvp -N test_dsp_map
-- 
cgit v1.2.3


From 2fe1c830eb8aea783c75529b42cab04208cea690 Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Thu, 21 Feb 2019 13:28:46 +0100
Subject: Bugfix in ice40_dsp

Signed-off-by: Clifford Wolf <clifford@clifford.at>
---
 techlibs/ice40/tests/.gitignore      |  1 +
 techlibs/ice40/tests/test_dsp_map.sh | 52 ++++++++++++++++++++++--------------
 2 files changed, 33 insertions(+), 20 deletions(-)

(limited to 'techlibs/ice40')

diff --git a/techlibs/ice40/tests/.gitignore b/techlibs/ice40/tests/.gitignore
index 300ce9aa6..120286550 100644
--- a/techlibs/ice40/tests/.gitignore
+++ b/techlibs/ice40/tests/.gitignore
@@ -5,6 +5,7 @@
 /test_dsp_model_ref.v
 /test_dsp_model_uut.v
 /test_dsp_map
+/test_dsp_map.vcd
 /test_dsp_map_tb.v
 /test_dsp_map_top.v
 /test_dsp_map_syn.v
diff --git a/techlibs/ice40/tests/test_dsp_map.sh b/techlibs/ice40/tests/test_dsp_map.sh
index 5982e5b34..3f7f134e4 100644
--- a/techlibs/ice40/tests/test_dsp_map.sh
+++ b/techlibs/ice40/tests/test_dsp_map.sh
@@ -1,26 +1,28 @@
 #!/bin/bash
 set -ex
 
-SZA=$(( 3 + $RANDOM % 13 ))
-SZB=$(( 3 + $RANDOM % 13 ))
-SZO=$(( 3 + $RANDOM % 29 ))
+for iter in {1..100}
+do
+	SZA=$(( 3 + $RANDOM % 13 ))
+	SZB=$(( 3 + $RANDOM % 13 ))
+	SZO=$(( 3 + $RANDOM % 29 ))
 
-C0=clk$(( $RANDOM & 1))
-C1=clk$(( $RANDOM & 1))
-C2=clk$(( $RANDOM & 1))
-C3=clk$(( $RANDOM & 1))
+	C0=clk$(( $RANDOM & 1))
+	C1=clk$(( $RANDOM & 1))
+	C2=clk$(( $RANDOM & 1))
+	C3=clk$(( $RANDOM & 1))
 
-E0=$( test $(( $RANDOM & 1 )) -eq 0 && echo posedge || echo negedge )
-E1=$( test $(( $RANDOM & 1 )) -eq 0 && echo posedge || echo negedge )
-E2=$( test $(( $RANDOM & 1 )) -eq 0 && echo posedge || echo negedge )
-E3=$( test $(( $RANDOM & 1 )) -eq 0 && echo posedge || echo negedge )
+	E0=$( test $(( $RANDOM & 1 )) -eq 0 && echo posedge || echo negedge )
+	E1=$( test $(( $RANDOM & 1 )) -eq 0 && echo posedge || echo negedge )
+	E2=$( test $(( $RANDOM & 1 )) -eq 0 && echo posedge || echo negedge )
+	E3=$( test $(( $RANDOM & 1 )) -eq 0 && echo posedge || echo negedge )
 
-SP=$( test $(( $RANDOM & 1 )) -eq 0 && echo S || echo P )
+	SP=$( test $(( $RANDOM & 1 )) -eq 0 && echo S || echo P )
 
-RC=$( test $(( $RANDOM & 1 )) -eq 0 && echo "reset" || echo "!reset" )
-RV="32'h$( echo $RANDOM | md5sum | cut -c1-8 )"
+	RC=$( test $(( $RANDOM & 1 )) -eq 0 && echo "reset" || echo "!reset" )
+	RV="32'h$( echo $RANDOM | md5sum | cut -c1-8 )"
 
-cat > test_dsp_map_top.v << EOT
+	cat > test_dsp_map_top.v << EOT
 module top (
 	input clk0, clk1, reset,
 	input  [$SZA:0] A,
@@ -38,7 +40,7 @@ module top (
 endmodule
 EOT
 
-cat > test_dsp_map_tb.v << EOT
+	cat > test_dsp_map_tb.v << EOT
 \`timescale 1ns / 1ps
 module testbench;
 	reg clk1, clk0, reset;
@@ -51,10 +53,14 @@ module testbench;
 	syn syn_inst (.clk0(clk0), .clk1(clk1), .reset(reset), .A(A), .B(B), .O(O_syn));
 
 	initial begin
+		// \$dumpfile("test_dsp_map.vcd");
+		// \$dumpvars(0, testbench);
+
 		#2;
 		clk0 = 0;
 		clk1 = 0;
 		reset = 1;
+		reset = $RC;
 		A = 0;
 		B = 0;
 
@@ -82,14 +88,20 @@ module testbench;
 				\$display("ERROR: O_top=%b O_syn=%b", O_top, O_syn);
 				\$stop;
 			end
-			\$display("OK O_top=O_syn=%b", O_top);
+			// \$display("OK O_top=O_syn=%b", O_top);
 		end
 
+		\$display("Test passed.");
 		\$finish;
 	end
 endmodule
 EOT
 
-../../../yosys -p 'read_verilog test_dsp_map_top.v; synth_ice40 -dsp; rename top syn; write_verilog test_dsp_map_syn.v'
-iverilog -o test_dsp_map -s testbench test_dsp_map_tb.v test_dsp_map_top.v test_dsp_map_syn.v ../cells_sim.v
-vvp -N test_dsp_map
+	../../../yosys -p 'read_verilog test_dsp_map_top.v; synth_ice40 -dsp; rename top syn; write_verilog test_dsp_map_syn.v'
+	iverilog -o test_dsp_map -s testbench test_dsp_map_tb.v test_dsp_map_top.v test_dsp_map_syn.v ../cells_sim.v
+	vvp -N test_dsp_map
+done
+
+: ""
+: "####  All tests passed.  ####"
+: ""
-- 
cgit v1.2.3


From cd2902ab1fec57503320e32ba5620c6487f9cb85 Mon Sep 17 00:00:00 2001
From: Elms <elms@freshred.net>
Date: Thu, 28 Feb 2019 16:22:24 -0800
Subject: ice40: use 2 bits for READ/WRITE MODE for SB_RAM map

EBLIF output .param will only use necessary 2 bits

Signed-off-by: Elms <elms@freshred.net>
---
 techlibs/ice40/brams_map.v | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

(limited to 'techlibs/ice40')

diff --git a/techlibs/ice40/brams_map.v b/techlibs/ice40/brams_map.v
index 19a61d73b..ad3bccd21 100644
--- a/techlibs/ice40/brams_map.v
+++ b/techlibs/ice40/brams_map.v
@@ -7,8 +7,8 @@ module \$__ICE40_RAM4K (
 	input  [10:0] WADDR,
 	input  [15:0] MASK, WDATA
 );
-	parameter integer READ_MODE = 0;
-	parameter integer WRITE_MODE = 0;
+	parameter [1:0] READ_MODE = 0;
+	parameter [1:0] WRITE_MODE = 0;
 	parameter [0:0] NEGCLK_R = 0;
 	parameter [0:0] NEGCLK_W = 0;
 
-- 
cgit v1.2.3


From e71055cfe8f3d90e157174b1fd83a06487a0a6a2 Mon Sep 17 00:00:00 2001
From: Sylvain Munaut <tnt@246tNt.com>
Date: Thu, 7 Mar 2019 23:48:10 +0100
Subject: ice40: Add ice40_braminit pass to allow initialization of BRAM from
 file

This adds a INIT_FILE attribute to the SB_RAM40_4K blocks that will
initialize content from a hex file. Same behavior is imlemented in the
simulation model and in a new pass for actual synthesis

Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
---
 techlibs/ice40/Makefile.inc      |   1 +
 techlibs/ice40/cells_sim.v       |  88 +++++++++++++---------
 techlibs/ice40/ice40_braminit.cc | 159 +++++++++++++++++++++++++++++++++++++++
 3 files changed, 211 insertions(+), 37 deletions(-)
 create mode 100644 techlibs/ice40/ice40_braminit.cc

(limited to 'techlibs/ice40')

diff --git a/techlibs/ice40/Makefile.inc b/techlibs/ice40/Makefile.inc
index 2750901c8..723b59d6f 100644
--- a/techlibs/ice40/Makefile.inc
+++ b/techlibs/ice40/Makefile.inc
@@ -1,5 +1,6 @@
 
 OBJS += techlibs/ice40/synth_ice40.o
+OBJS += techlibs/ice40/ice40_braminit.o
 OBJS += techlibs/ice40/ice40_ffssr.o
 OBJS += techlibs/ice40/ice40_ffinit.o
 OBJS += techlibs/ice40/ice40_opt.o
diff --git a/techlibs/ice40/cells_sim.v b/techlibs/ice40/cells_sim.v
index 2041693cc..bc36cdd14 100644
--- a/techlibs/ice40/cells_sim.v
+++ b/techlibs/ice40/cells_sim.v
@@ -326,6 +326,8 @@ module SB_RAM40_4K (
 	parameter INIT_E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
 	parameter INIT_F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
 
+	parameter INIT_FILE = "";
+
 `ifndef BLACKBOX
 	wire [15:0] WMASK_I;
 	wire [15:0] RMASK_I;
@@ -408,43 +410,46 @@ module SB_RAM40_4K (
 	reg [15:0] memory [0:255];
 
 	initial begin
-		for (i=0; i<16; i=i+1) begin
+		if (INIT_FILE != "")
+			$readmemh(INIT_FILE, memory);
+		else
+			for (i=0; i<16; i=i+1) begin
 `ifdef YOSYS
-			memory[ 0*16 + i] <= INIT_0[16*i +: 16];
-			memory[ 1*16 + i] <= INIT_1[16*i +: 16];
-			memory[ 2*16 + i] <= INIT_2[16*i +: 16];
-			memory[ 3*16 + i] <= INIT_3[16*i +: 16];
-			memory[ 4*16 + i] <= INIT_4[16*i +: 16];
-			memory[ 5*16 + i] <= INIT_5[16*i +: 16];
-			memory[ 6*16 + i] <= INIT_6[16*i +: 16];
-			memory[ 7*16 + i] <= INIT_7[16*i +: 16];
-			memory[ 8*16 + i] <= INIT_8[16*i +: 16];
-			memory[ 9*16 + i] <= INIT_9[16*i +: 16];
-			memory[10*16 + i] <= INIT_A[16*i +: 16];
-			memory[11*16 + i] <= INIT_B[16*i +: 16];
-			memory[12*16 + i] <= INIT_C[16*i +: 16];
-			memory[13*16 + i] <= INIT_D[16*i +: 16];
-			memory[14*16 + i] <= INIT_E[16*i +: 16];
-			memory[15*16 + i] <= INIT_F[16*i +: 16];
+				memory[ 0*16 + i] <= INIT_0[16*i +: 16];
+				memory[ 1*16 + i] <= INIT_1[16*i +: 16];
+				memory[ 2*16 + i] <= INIT_2[16*i +: 16];
+				memory[ 3*16 + i] <= INIT_3[16*i +: 16];
+				memory[ 4*16 + i] <= INIT_4[16*i +: 16];
+				memory[ 5*16 + i] <= INIT_5[16*i +: 16];
+				memory[ 6*16 + i] <= INIT_6[16*i +: 16];
+				memory[ 7*16 + i] <= INIT_7[16*i +: 16];
+				memory[ 8*16 + i] <= INIT_8[16*i +: 16];
+				memory[ 9*16 + i] <= INIT_9[16*i +: 16];
+				memory[10*16 + i] <= INIT_A[16*i +: 16];
+				memory[11*16 + i] <= INIT_B[16*i +: 16];
+				memory[12*16 + i] <= INIT_C[16*i +: 16];
+				memory[13*16 + i] <= INIT_D[16*i +: 16];
+				memory[14*16 + i] <= INIT_E[16*i +: 16];
+				memory[15*16 + i] <= INIT_F[16*i +: 16];
 `else
-			memory[ 0*16 + i] = INIT_0[16*i +: 16];
-			memory[ 1*16 + i] = INIT_1[16*i +: 16];
-			memory[ 2*16 + i] = INIT_2[16*i +: 16];
-			memory[ 3*16 + i] = INIT_3[16*i +: 16];
-			memory[ 4*16 + i] = INIT_4[16*i +: 16];
-			memory[ 5*16 + i] = INIT_5[16*i +: 16];
-			memory[ 6*16 + i] = INIT_6[16*i +: 16];
-			memory[ 7*16 + i] = INIT_7[16*i +: 16];
-			memory[ 8*16 + i] = INIT_8[16*i +: 16];
-			memory[ 9*16 + i] = INIT_9[16*i +: 16];
-			memory[10*16 + i] = INIT_A[16*i +: 16];
-			memory[11*16 + i] = INIT_B[16*i +: 16];
-			memory[12*16 + i] = INIT_C[16*i +: 16];
-			memory[13*16 + i] = INIT_D[16*i +: 16];
-			memory[14*16 + i] = INIT_E[16*i +: 16];
-			memory[15*16 + i] = INIT_F[16*i +: 16];
+				memory[ 0*16 + i] = INIT_0[16*i +: 16];
+				memory[ 1*16 + i] = INIT_1[16*i +: 16];
+				memory[ 2*16 + i] = INIT_2[16*i +: 16];
+				memory[ 3*16 + i] = INIT_3[16*i +: 16];
+				memory[ 4*16 + i] = INIT_4[16*i +: 16];
+				memory[ 5*16 + i] = INIT_5[16*i +: 16];
+				memory[ 6*16 + i] = INIT_6[16*i +: 16];
+				memory[ 7*16 + i] = INIT_7[16*i +: 16];
+				memory[ 8*16 + i] = INIT_8[16*i +: 16];
+				memory[ 9*16 + i] = INIT_9[16*i +: 16];
+				memory[10*16 + i] = INIT_A[16*i +: 16];
+				memory[11*16 + i] = INIT_B[16*i +: 16];
+				memory[12*16 + i] = INIT_C[16*i +: 16];
+				memory[13*16 + i] = INIT_D[16*i +: 16];
+				memory[14*16 + i] = INIT_E[16*i +: 16];
+				memory[15*16 + i] = INIT_F[16*i +: 16];
 `endif
-		end
+			end
 	end
 
 	always @(posedge WCLK) begin
@@ -504,6 +509,8 @@ module SB_RAM40_4KNR (
 	parameter INIT_E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
 	parameter INIT_F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
 
+	parameter INIT_FILE = "";
+
 	SB_RAM40_4K #(
 		.WRITE_MODE(WRITE_MODE),
 		.READ_MODE (READ_MODE ),
@@ -522,7 +529,8 @@ module SB_RAM40_4KNR (
 		.INIT_C    (INIT_C    ),
 		.INIT_D    (INIT_D    ),
 		.INIT_E    (INIT_E    ),
-		.INIT_F    (INIT_F    )
+		.INIT_F    (INIT_F    ),
+		.INIT_FILE (INIT_FILE )
 	) RAM (
 		.RDATA(RDATA),
 		.RCLK (~RCLKN),
@@ -566,6 +574,8 @@ module SB_RAM40_4KNW (
 	parameter INIT_E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
 	parameter INIT_F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
 
+	parameter INIT_FILE = "";
+
 	SB_RAM40_4K #(
 		.WRITE_MODE(WRITE_MODE),
 		.READ_MODE (READ_MODE ),
@@ -584,7 +594,8 @@ module SB_RAM40_4KNW (
 		.INIT_C    (INIT_C    ),
 		.INIT_D    (INIT_D    ),
 		.INIT_E    (INIT_E    ),
-		.INIT_F    (INIT_F    )
+		.INIT_F    (INIT_F    ),
+		.INIT_FILE (INIT_FILE )
 	) RAM (
 		.RDATA(RDATA),
 		.RCLK (RCLK ),
@@ -628,6 +639,8 @@ module SB_RAM40_4KNRNW (
 	parameter INIT_E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
 	parameter INIT_F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
 
+	parameter INIT_FILE = "";
+
 	SB_RAM40_4K #(
 		.WRITE_MODE(WRITE_MODE),
 		.READ_MODE (READ_MODE ),
@@ -646,7 +659,8 @@ module SB_RAM40_4KNRNW (
 		.INIT_C    (INIT_C    ),
 		.INIT_D    (INIT_D    ),
 		.INIT_E    (INIT_E    ),
-		.INIT_F    (INIT_F    )
+		.INIT_F    (INIT_F    ),
+		.INIT_FILE (INIT_FILE )
 	) RAM (
 		.RDATA(RDATA),
 		.RCLK (~RCLKN),
diff --git a/techlibs/ice40/ice40_braminit.cc b/techlibs/ice40/ice40_braminit.cc
new file mode 100644
index 000000000..bf12f9148
--- /dev/null
+++ b/techlibs/ice40/ice40_braminit.cc
@@ -0,0 +1,159 @@
+/*
+ *  yosys -- Yosys Open SYnthesis Suite
+ *
+ *  Copyright (C) 2012  Clifford Wolf <clifford@clifford.at>
+ *
+ *  Permission to use, copy, modify, and/or distribute this software for any
+ *  purpose with or without fee is hereby granted, provided that the above
+ *  copyright notice and this permission notice appear in all copies.
+ *
+ *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ */
+
+#include "kernel/yosys.h"
+#include "kernel/sigtools.h"
+#include <stdlib.h>
+#include <stdio.h>
+#include <bitset>
+
+USING_YOSYS_NAMESPACE
+PRIVATE_NAMESPACE_BEGIN
+
+static void run_ice40_braminit(Module *module)
+{
+	for (auto cell : module->selected_cells())
+	{
+		uint16_t mem[256];
+
+		/* Only consider cells we're interested in */
+		if (cell->type != "\\SB_RAM40_4K" &&
+		    cell->type != "\\SB_RAM40_4KNR" &&
+		    cell->type != "\\SB_RAM40_4KNW" &&
+		    cell->type != "\\SB_RAM40_4KNRNW")
+			continue;
+		if (!cell->hasParam("\\INIT_FILE"))
+			continue;
+		std::string init_file = cell->getParam("\\INIT_FILE").decode_string();
+		cell->unsetParam("\\INIT_FILE");
+		if (init_file == "")
+			continue;
+
+		/* Open file */
+		log("Processing %s : %s\n", RTLIL::id2cstr(cell->name), init_file.c_str());
+
+		std::ifstream f;
+		f.open(init_file.c_str());
+		if (f.fail()) {
+			log("Can not open file `%s`.\n", init_file.c_str());
+			continue;
+		}
+
+		/* Defaults to 0 */
+		memset(mem, 0x00, sizeof(mem));
+
+		/* Process each line */
+		bool in_comment = false;
+		int cursor = 0;
+
+		while (!f.eof())
+		{
+			std::string line, token;
+			std::getline(f, line);
+
+			for (int i = 0; i < GetSize(line); i++)
+			{
+				if (in_comment && line.substr(i, 2) == "*/") {
+					line[i] = ' ';
+					line[i+1] = ' ';
+					in_comment = false;
+					continue;
+				}
+				if (!in_comment && line.substr(i, 2) == "/*")
+					in_comment = true;
+				if (in_comment)
+					line[i] = ' ';
+			}
+
+			while (1)
+			{
+				bool set_cursor = false;
+				long value;
+
+				token = next_token(line, " \t\r\n");
+				if (token.empty() || token.substr(0, 2) == "//")
+					break;
+
+				if (token[0] == '@') {
+					token = token.substr(1);
+					set_cursor = true;
+				}
+
+				const char *nptr = token.c_str();
+				char *endptr;
+				value = strtol(nptr, &endptr, 16);
+				if (!*nptr || *endptr) {
+					log("Can not parse %s `%s` for %s.\n",
+						set_cursor ? "address" : "value",
+						nptr, token.c_str()
+					);
+					continue;
+				}
+
+				if (set_cursor)
+					cursor = value;
+				else if (cursor >= 0 && cursor < 256)
+					mem[cursor++] = value;
+				else
+					log("Attempt to initialize non existent address %d\n", cursor);
+			}
+		}
+
+		/* Set attributes */
+		const char *hex = "0123456789ABCDEF";
+		for (int i=0; i<16; i++) {
+			std::string val = "";
+			for (int j=15; j>=0; j--)
+				val += std::bitset<16>(mem[i*16+j]).to_string();
+			cell->setParam("\\INIT_" + std::string(1, hex[i]), RTLIL::Const::from_string(val));
+		}
+	}
+}
+
+struct Ice40BRAMInitPass : public Pass {
+	Ice40BRAMInitPass() : Pass("ice40_braminit", "iCE40: perform SB_RAM40_4K initialization from file") { }
+	void help() YS_OVERRIDE
+	{
+		//   |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
+		log("\n");
+		log("    ice40_braminit\n");
+		log("\n");
+		log("This command processes all SB_RAM40_4K blocks with a non-empty INIT_FILE\n");
+		log("parameter and converts it inti the required INIT_x attributes\n");
+		log("\n");
+	}
+	void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
+	{
+		log_header(design, "Executing ICE40_BRAMINIT pass.\n");
+
+		size_t argidx;
+		for (argidx = 1; argidx < args.size(); argidx++) {
+			// if (args[argidx] == "-???") {
+			//  continue;
+			// }
+			break;
+		}
+		extra_args(args, argidx, design);
+
+		for (auto module : design->selected_modules())
+			run_ice40_braminit(module);
+	}
+} Ice40BRAMInitPass;
+
+PRIVATE_NAMESPACE_END
-- 
cgit v1.2.3


From 5b6f59103374413e9c64c4f228853ce06b03ce29 Mon Sep 17 00:00:00 2001
From: Sylvain Munaut <tnt@246tNt.com>
Date: Fri, 8 Mar 2019 00:11:17 +0100
Subject: ice40: Run ice40_braminit pass by default

Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
---
 techlibs/ice40/synth_ice40.cc | 1 +
 1 file changed, 1 insertion(+)

(limited to 'techlibs/ice40')

diff --git a/techlibs/ice40/synth_ice40.cc b/techlibs/ice40/synth_ice40.cc
index 34501b335..8899bfcc4 100644
--- a/techlibs/ice40/synth_ice40.cc
+++ b/techlibs/ice40/synth_ice40.cc
@@ -257,6 +257,7 @@ struct SynthIce40Pass : public ScriptPass
 		{
 			run("memory_bram -rules +/ice40/brams.txt");
 			run("techmap -map +/ice40/brams_map.v");
+			run("ice40_braminit");
 		}
 
 		if (check_label("map"))
-- 
cgit v1.2.3


From ff4c2a14ae34eeb899c3cf0ca1109f0106b41679 Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Sat, 9 Mar 2019 13:24:55 -0800
Subject: Fix typo in ice40_braminit help msg

Signed-off-by: Clifford Wolf <clifford@clifford.at>
---
 techlibs/ice40/ice40_braminit.cc | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'techlibs/ice40')

diff --git a/techlibs/ice40/ice40_braminit.cc b/techlibs/ice40/ice40_braminit.cc
index bf12f9148..4fa6b0792 100644
--- a/techlibs/ice40/ice40_braminit.cc
+++ b/techlibs/ice40/ice40_braminit.cc
@@ -135,7 +135,7 @@ struct Ice40BRAMInitPass : public Pass {
 		log("    ice40_braminit\n");
 		log("\n");
 		log("This command processes all SB_RAM40_4K blocks with a non-empty INIT_FILE\n");
-		log("parameter and converts it inti the required INIT_x attributes\n");
+		log("parameter and converts it into the required INIT_x attributes\n");
 		log("\n");
 	}
 	void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
-- 
cgit v1.2.3


From 9284cf92b8dcb510a2a9511965e587e42944c543 Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Tue, 12 Mar 2019 20:14:18 +0100
Subject: Remove ice40/cells_sim.v hack to avoid warning for blocking memory
 writes

Signed-off-by: Clifford Wolf <clifford@clifford.at>
---
 techlibs/ice40/cells_sim.v | 19 -------------------
 1 file changed, 19 deletions(-)

(limited to 'techlibs/ice40')

diff --git a/techlibs/ice40/cells_sim.v b/techlibs/ice40/cells_sim.v
index bc36cdd14..62a28364b 100644
--- a/techlibs/ice40/cells_sim.v
+++ b/techlibs/ice40/cells_sim.v
@@ -414,24 +414,6 @@ module SB_RAM40_4K (
 			$readmemh(INIT_FILE, memory);
 		else
 			for (i=0; i<16; i=i+1) begin
-`ifdef YOSYS
-				memory[ 0*16 + i] <= INIT_0[16*i +: 16];
-				memory[ 1*16 + i] <= INIT_1[16*i +: 16];
-				memory[ 2*16 + i] <= INIT_2[16*i +: 16];
-				memory[ 3*16 + i] <= INIT_3[16*i +: 16];
-				memory[ 4*16 + i] <= INIT_4[16*i +: 16];
-				memory[ 5*16 + i] <= INIT_5[16*i +: 16];
-				memory[ 6*16 + i] <= INIT_6[16*i +: 16];
-				memory[ 7*16 + i] <= INIT_7[16*i +: 16];
-				memory[ 8*16 + i] <= INIT_8[16*i +: 16];
-				memory[ 9*16 + i] <= INIT_9[16*i +: 16];
-				memory[10*16 + i] <= INIT_A[16*i +: 16];
-				memory[11*16 + i] <= INIT_B[16*i +: 16];
-				memory[12*16 + i] <= INIT_C[16*i +: 16];
-				memory[13*16 + i] <= INIT_D[16*i +: 16];
-				memory[14*16 + i] <= INIT_E[16*i +: 16];
-				memory[15*16 + i] <= INIT_F[16*i +: 16];
-`else
 				memory[ 0*16 + i] = INIT_0[16*i +: 16];
 				memory[ 1*16 + i] = INIT_1[16*i +: 16];
 				memory[ 2*16 + i] = INIT_2[16*i +: 16];
@@ -448,7 +430,6 @@ module SB_RAM40_4K (
 				memory[13*16 + i] = INIT_D[16*i +: 16];
 				memory[14*16 + i] = INIT_E[16*i +: 16];
 				memory[15*16 + i] = INIT_F[16*i +: 16];
-`endif
 			end
 	end
 
-- 
cgit v1.2.3


From 7980118d74aae04479be3b9e9b59f95bf3bfbfe5 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Tue, 16 Apr 2019 16:39:30 -0700
Subject: Add ice40 box files

---
 techlibs/ice40/Makefile.inc   | 3 +++
 techlibs/ice40/cells.box      | 6 ++++++
 techlibs/ice40/cells_box.v    | 5 +++++
 techlibs/ice40/cells_sim.v    | 1 +
 techlibs/ice40/lut.lut        | 4 ++++
 techlibs/ice40/synth_ice40.cc | 9 ++++++++-
 6 files changed, 27 insertions(+), 1 deletion(-)
 create mode 100644 techlibs/ice40/cells.box
 create mode 100644 techlibs/ice40/cells_box.v
 create mode 100644 techlibs/ice40/lut.lut

(limited to 'techlibs/ice40')

diff --git a/techlibs/ice40/Makefile.inc b/techlibs/ice40/Makefile.inc
index 723b59d6f..cd992bb24 100644
--- a/techlibs/ice40/Makefile.inc
+++ b/techlibs/ice40/Makefile.inc
@@ -28,6 +28,9 @@ $(eval $(call add_share_file,share/ice40,techlibs/ice40/cells_sim.v))
 $(eval $(call add_share_file,share/ice40,techlibs/ice40/latches_map.v))
 $(eval $(call add_share_file,share/ice40,techlibs/ice40/brams.txt))
 $(eval $(call add_share_file,share/ice40,techlibs/ice40/brams_map.v))
+$(eval $(call add_share_file,share/ice40,techlibs/ice40/cells.box))
+$(eval $(call add_share_file,share/ice40,techlibs/ice40/cells_box.v))
+$(eval $(call add_share_file,share/ice40,techlibs/ice40/lut.lut))
 
 $(eval $(call add_gen_share_file,share/ice40,techlibs/ice40/brams_init1.vh))
 $(eval $(call add_gen_share_file,share/ice40,techlibs/ice40/brams_init2.vh))
diff --git a/techlibs/ice40/cells.box b/techlibs/ice40/cells.box
new file mode 100644
index 000000000..e4cfb71e6
--- /dev/null
+++ b/techlibs/ice40/cells.box
@@ -0,0 +1,6 @@
+# NB: Inputs/Outputs must be ordered alphabetically
+
+# Inputs: CI I0 I1
+# Outputs: CO
+SB_CARRY 1 1 3 1
+126 259 231
diff --git a/techlibs/ice40/cells_box.v b/techlibs/ice40/cells_box.v
new file mode 100644
index 000000000..cca88f9aa
--- /dev/null
+++ b/techlibs/ice40/cells_box.v
@@ -0,0 +1,5 @@
+(* abc_box_id = 1 *)
+module SB_CARRY (output CO, input CI, I0, I1);
+	assign CO = (I0 && I1) || ((I0 || I1) && CI);
+endmodule
+
diff --git a/techlibs/ice40/cells_sim.v b/techlibs/ice40/cells_sim.v
index 62a28364b..322c1e5c7 100644
--- a/techlibs/ice40/cells_sim.v
+++ b/techlibs/ice40/cells_sim.v
@@ -881,6 +881,7 @@ module SB_WARMBOOT (
 );
 endmodule
 
+(* nomem2reg *)
 module SB_SPRAM256KA (
 	input [13:0] ADDRESS,
 	input [15:0] DATAIN,
diff --git a/techlibs/ice40/lut.lut b/techlibs/ice40/lut.lut
new file mode 100644
index 000000000..48da89f46
--- /dev/null
+++ b/techlibs/ice40/lut.lut
@@ -0,0 +1,4 @@
+1	1	316
+2	1	316 379
+3	1	316 379 400
+4	1	316	379	400	449
diff --git a/techlibs/ice40/synth_ice40.cc b/techlibs/ice40/synth_ice40.cc
index 6c77e5482..3faa10b4f 100644
--- a/techlibs/ice40/synth_ice40.cc
+++ b/techlibs/ice40/synth_ice40.cc
@@ -316,7 +316,14 @@ struct SynthIce40Pass : public ScriptPass
 				run("techmap -map +/gate2lut.v -D LUT_WIDTH=4", "(only if -noabc)");
 			}
 			if (!noabc) {
-				run(abc + " -dress -lut 4", "(skip if -noabc)");
+				if (abc == "abc9") {
+					run("read_verilog +/ice40/cells_box.v");
+					run("techmap -map +/techmap.v A:abc_box_id");
+					run(abc + " -dress -lut +/ice40/lut.lut -box +/ice40/cells.box", "(skip if -noabc)");
+					run("blackbox A:abc_box_id");
+				}
+				else
+					run(abc + " -lut 4", "(skip if -noabc)");
 			}
 			run("clean");
 			if (relut || help_mode) {
-- 
cgit v1.2.3


From 743c164eee06abb44601e00304db18cdb36a180f Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Tue, 16 Apr 2019 17:34:11 -0700
Subject: Add SB_LUT4 to box library

---
 techlibs/ice40/cells.box   | 7 +++++++
 techlibs/ice40/cells_box.v | 7 +++++++
 techlibs/ice40/lut.lut     | 2 ++
 3 files changed, 16 insertions(+)

(limited to 'techlibs/ice40')

diff --git a/techlibs/ice40/cells.box b/techlibs/ice40/cells.box
index e4cfb71e6..d775efa78 100644
--- a/techlibs/ice40/cells.box
+++ b/techlibs/ice40/cells.box
@@ -1,6 +1,13 @@
+# From https://github.com/cliffordwolf/icestorm/blob/81c33a3/icefuzz/timings_hx8k.txt
+
 # NB: Inputs/Outputs must be ordered alphabetically
 
 # Inputs: CI I0 I1
 # Outputs: CO
 SB_CARRY 1 1 3 1
 126 259 231
+
+# Inputs: I0 I1 I2 I3
+# Outputs: O
+SB_LUT4 2 1 4 1
+316 379 400 449
diff --git a/techlibs/ice40/cells_box.v b/techlibs/ice40/cells_box.v
index cca88f9aa..e2a54a42c 100644
--- a/techlibs/ice40/cells_box.v
+++ b/techlibs/ice40/cells_box.v
@@ -3,3 +3,10 @@ module SB_CARRY (output CO, input CI, I0, I1);
 	assign CO = (I0 && I1) || ((I0 || I1) && CI);
 endmodule
 
+(* abc_box_id = 2 *)
+module SB_LUT4 (output O, input I0, I1, I2, I3);
+	parameter [15:0] LUT_INIT = 0;
+	// Indicate this is a black-box
+	assign O = 1'b0;
+endmodule
+
diff --git a/techlibs/ice40/lut.lut b/techlibs/ice40/lut.lut
index 48da89f46..6fa0682da 100644
--- a/techlibs/ice40/lut.lut
+++ b/techlibs/ice40/lut.lut
@@ -1,3 +1,5 @@
+# From https://github.com/cliffordwolf/icestorm/blob/81c33a3/icefuzz/timings_hx8k.txt
+
 1	1	316
 2	1	316 379
 3	1	316 379 400
-- 
cgit v1.2.3


From 17fb6c35229bddc636021def319547e4d8fdf271 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Wed, 17 Apr 2019 08:40:50 -0700
Subject: Fix spacing

---
 techlibs/ice40/lut.lut | 10 +++++-----
 1 file changed, 5 insertions(+), 5 deletions(-)

(limited to 'techlibs/ice40')

diff --git a/techlibs/ice40/lut.lut b/techlibs/ice40/lut.lut
index 6fa0682da..eef997869 100644
--- a/techlibs/ice40/lut.lut
+++ b/techlibs/ice40/lut.lut
@@ -1,6 +1,6 @@
 # From https://github.com/cliffordwolf/icestorm/blob/81c33a3/icefuzz/timings_hx8k.txt
-
-1	1	316
-2	1	316 379
-3	1	316 379 400
-4	1	316	379	400	449
+#       I3  I2  I1  I0
+1   1   316
+2   1   316 379
+3   1   316 379 400
+4   1   316 379 400 449
-- 
cgit v1.2.3


From a7632ab3326c5247b8152a53808413b259c13253 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Wed, 17 Apr 2019 11:10:04 -0700
Subject: Try using an ICE40_CARRY_LUT primitive to avoid ABC issues

---
 techlibs/ice40/arith_map.v    | 37 ++++++++++++++++++++++---------------
 techlibs/ice40/cells.box      | 12 ++++--------
 techlibs/ice40/cells_box.v    | 24 +++++++++++++++---------
 techlibs/ice40/cells_map.v    | 24 ++++++++++++++++++++++++
 techlibs/ice40/cells_sim.v    | 22 ++++++++++++++++++++++
 techlibs/ice40/ice40_opt.cc   | 16 ++++++++++++++--
 techlibs/ice40/synth_ice40.cc |  2 +-
 7 files changed, 102 insertions(+), 35 deletions(-)

(limited to 'techlibs/ice40')

diff --git a/techlibs/ice40/arith_map.v b/techlibs/ice40/arith_map.v
index 4449fdc1b..eefc375dd 100644
--- a/techlibs/ice40/arith_map.v
+++ b/techlibs/ice40/arith_map.v
@@ -44,25 +44,32 @@ module _80_ice40_alu (A, B, CI, BI, X, Y, CO);
 
 	genvar i;
 	generate for (i = 0; i < Y_WIDTH; i = i + 1) begin:slice
-		SB_CARRY carry (
-			.I0(AA[i]),
-			.I1(BB[i]),
-			.CI(C[i]),
-			.CO(CO[i])
-		);
-		SB_LUT4 #(
-			//         I0: 1010 1010 1010 1010
-			//         I1: 1100 1100 1100 1100
-			//         I2: 1111 0000 1111 0000
-			//         I3: 1111 1111 0000 0000
-			.LUT_INIT(16'b 0110_1001_1001_0110)
-		) adder (
-			.I0(1'b0),
+		ICE40_CARRY_LUT carry_lut (
 			.I1(AA[i]),
 			.I2(BB[i]),
-			.I3(C[i]),
+			.CI(C[i]),
+			.CO(CO[i]),
 			.O(Y[i])
 		);
+//		SB_CARRY carry (
+//			.I0(AA[i]),
+//			.I1(BB[i]),
+//			.CI(C[i]),
+//			.CO(CO[i])
+//		);
+//		SB_LUT4 #(
+//			//         I0: 1010 1010 1010 1010
+//			//         I1: 1100 1100 1100 1100
+//			//         I2: 1111 0000 1111 0000
+//			//         I3: 1111 1111 0000 0000
+//			.LUT_INIT(16'b 0110_1001_1001_0110)
+//		) adder (
+//			.I0(1'b0),
+//			.I1(AA[i]),
+//			.I2(BB[i]),
+//			.I3(C[i]),
+//			.O(Y[i])
+//		);
 	end endgenerate
 
 	assign X = AA ^ BB;
diff --git a/techlibs/ice40/cells.box b/techlibs/ice40/cells.box
index d775efa78..34d1f372e 100644
--- a/techlibs/ice40/cells.box
+++ b/techlibs/ice40/cells.box
@@ -2,12 +2,8 @@
 
 # NB: Inputs/Outputs must be ordered alphabetically
 
-# Inputs: CI I0 I1
-# Outputs: CO
-SB_CARRY 1 1 3 1
+# Inputs: CI I1 I2
+# Outputs: CO O
+ICE40_CARRY_LUT 1 1 3 2
 126 259 231
-
-# Inputs: I0 I1 I2 I3
-# Outputs: O
-SB_LUT4 2 1 4 1
-316 379 400 449
+316 400 379
diff --git a/techlibs/ice40/cells_box.v b/techlibs/ice40/cells_box.v
index e2a54a42c..d0eb8708c 100644
--- a/techlibs/ice40/cells_box.v
+++ b/techlibs/ice40/cells_box.v
@@ -1,12 +1,18 @@
 (* abc_box_id = 1 *)
-module SB_CARRY (output CO, input CI, I0, I1);
-	assign CO = (I0 && I1) || ((I0 || I1) && CI);
-endmodule
+module ICE40_CARRY_LUT (output CO, O, input CI, I1, I2);
+	assign CO = (I1 && I2) || ((I1 || I2) && CI);
 
-(* abc_box_id = 2 *)
-module SB_LUT4 (output O, input I0, I1, I2, I3);
-	parameter [15:0] LUT_INIT = 0;
-	// Indicate this is a black-box
-	assign O = 1'b0;
-endmodule
+	wire I0, I3;
+	assign I0 = 1'b0;
+	assign I3 = CI;
 
+	//                            I0: 1010 1010 1010 1010
+	//                            I1: 1100 1100 1100 1100
+	//                            I2: 1111 0000 1111 0000
+	//                            I3: 1111 1111 0000 0000
+	localparam [15:0] LUT_INIT = 16'b 0110_1001_1001_0110;
+	wire [7:0] s3 = I3 ? LUT_INIT[15:8] : LUT_INIT[7:0];
+	wire [3:0] s2 = I2 ?       s3[ 7:4] :       s3[3:0];
+	wire [1:0] s1 = I1 ?       s2[ 3:2] :       s2[1:0];
+	assign O = I0 ? s1[1] : s1[0];
+endmodule
diff --git a/techlibs/ice40/cells_map.v b/techlibs/ice40/cells_map.v
index d0ddfd02e..d4c611686 100644
--- a/techlibs/ice40/cells_map.v
+++ b/techlibs/ice40/cells_map.v
@@ -57,3 +57,27 @@ module \$lut (A, Y);
   endgenerate
 endmodule
 `endif
+
+`ifndef NO_CARRY
+module ICE40_CARRY_LUT (output CO, O, input CI, I1, I2);
+	SB_CARRY carry (
+		.I0(I1),
+		.I1(I2),
+		.CI(CI),
+		.CO(CO),
+	);
+	SB_LUT4 #(
+		//         I0: 1010 1010 1010 1010
+		//         I1: 1100 1100 1100 1100
+		//         I2: 1111 0000 1111 0000
+		//         I3: 1111 1111 0000 0000
+		.LUT_INIT(16'b 0110_1001_1001_0110)
+	) adder (
+		.I0(1'b0),
+		.I1(I1),
+		.I2(I2),
+		.I3(CI),
+		.O(O)
+	);
+endmodule
+`endif
diff --git a/techlibs/ice40/cells_sim.v b/techlibs/ice40/cells_sim.v
index 322c1e5c7..b5a739a63 100644
--- a/techlibs/ice40/cells_sim.v
+++ b/techlibs/ice40/cells_sim.v
@@ -1384,3 +1384,25 @@ module SB_MAC16 (
 	assign LCI = (BOTADDSUB_CARRYSELECT == 0) ? 1'b0 : (BOTADDSUB_CARRYSELECT == 1) ? 1'b1 : (BOTADDSUB_CARRYSELECT == 2) ? ACCUMCI : CI;
 	assign O = {Oh, Ol};
 endmodule
+
+module ICE40_CARRY_LUT (input CI, input I1, input I2, output CO, output O);
+	SB_CARRY carry (
+		.I0(I1),
+		.I1(I2),
+		.CI(CI),
+		.CO(CO),
+	);
+	SB_LUT4 #(
+		//         I0: 1010 1010 1010 1010
+		//         I1: 1100 1100 1100 1100
+		//         I2: 1111 0000 1111 0000
+		//         I3: 1111 1111 0000 0000
+		.LUT_INIT(16'b 0110_1001_1001_0110)
+	) adder (
+		.I0(1'b0),
+		.I1(I1),
+		.I2(I2),
+		.I3(CI),
+		.O(O)
+	);
+endmodule
diff --git a/techlibs/ice40/ice40_opt.cc b/techlibs/ice40/ice40_opt.cc
index f528607d6..edb293b93 100644
--- a/techlibs/ice40/ice40_opt.cc
+++ b/techlibs/ice40/ice40_opt.cc
@@ -47,16 +47,20 @@ static void run_ice40_opts(Module *module)
 			continue;
 		}
 
-		if (cell->type == "\\SB_CARRY")
+		if (cell->type.in("\\SB_CARRY", "\\ICE40_CARRY_LUT"))
 		{
 			SigSpec non_const_inputs, replacement_output;
 			int count_zeros = 0, count_ones = 0;
 
 			SigBit inbit[3] = {
-				get_bit_or_zero(cell->getPort("\\I0")),
 				get_bit_or_zero(cell->getPort("\\I1")),
 				get_bit_or_zero(cell->getPort("\\CI"))
 			};
+			if (cell->type == "\\SB_CARRY")
+				inbit[2] = get_bit_or_zero(cell->getPort("\\I0"));
+			else if (cell->type == "\\ICE40_CARRY_LUT")
+				inbit[2] = get_bit_or_zero(cell->getPort("\\I2"));
+			else log_abort();
 			for (int i = 0; i < 3; i++)
 				if (inbit[i].wire == nullptr) {
 					if (inbit[i] == State::S1)
@@ -79,6 +83,14 @@ static void run_ice40_opts(Module *module)
 				module->design->scratchpad_set_bool("opt.did_something", true);
 				log("Optimized away SB_CARRY cell %s.%s: CO=%s\n",
 						log_id(module), log_id(cell), log_signal(replacement_output));
+
+				if (cell->type == "\\ICE40_CARRY_LUT")
+					module->addLut(NEW_ID,
+						{ RTLIL::S0, cell->getPort("\\I1"), cell->getPort("\\I2"), cell->getPort("\\CI") },
+						cell->getPort("\\O"),
+						RTLIL::Const("0110_1001_1001_0110"),
+						cell->get_src_attribute());
+
 				module->remove(cell);
 			}
 			continue;
diff --git a/techlibs/ice40/synth_ice40.cc b/techlibs/ice40/synth_ice40.cc
index 3faa10b4f..d09a1184c 100644
--- a/techlibs/ice40/synth_ice40.cc
+++ b/techlibs/ice40/synth_ice40.cc
@@ -296,7 +296,7 @@ struct SynthIce40Pass : public ScriptPass
 				run("opt_merge");
 				run(stringf("dff2dffe -unmap-mince %d", min_ce_use));
 			}
-			run("techmap -D NO_LUT -map +/ice40/cells_map.v");
+			run("techmap -D NO_LUT -D NO_CARRY -map +/ice40/cells_map.v");
 			run("opt_expr -mux_undef");
 			run("simplemap");
 			run("ice40_ffinit");
-- 
cgit v1.2.3


From c1ebe51a75ef8ce47d6b1406fa87b15bd8f97760 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Wed, 17 Apr 2019 11:10:20 -0700
Subject: Revert "Try using an ICE40_CARRY_LUT primitive to avoid ABC issues"

This reverts commit a7632ab3326c5247b8152a53808413b259c13253.
---
 techlibs/ice40/arith_map.v    | 37 +++++++++++++++----------------------
 techlibs/ice40/cells.box      | 12 ++++++++----
 techlibs/ice40/cells_box.v    | 24 +++++++++---------------
 techlibs/ice40/cells_map.v    | 24 ------------------------
 techlibs/ice40/cells_sim.v    | 22 ----------------------
 techlibs/ice40/ice40_opt.cc   | 16 ++--------------
 techlibs/ice40/synth_ice40.cc |  2 +-
 7 files changed, 35 insertions(+), 102 deletions(-)

(limited to 'techlibs/ice40')

diff --git a/techlibs/ice40/arith_map.v b/techlibs/ice40/arith_map.v
index eefc375dd..4449fdc1b 100644
--- a/techlibs/ice40/arith_map.v
+++ b/techlibs/ice40/arith_map.v
@@ -44,32 +44,25 @@ module _80_ice40_alu (A, B, CI, BI, X, Y, CO);
 
 	genvar i;
 	generate for (i = 0; i < Y_WIDTH; i = i + 1) begin:slice
-		ICE40_CARRY_LUT carry_lut (
+		SB_CARRY carry (
+			.I0(AA[i]),
+			.I1(BB[i]),
+			.CI(C[i]),
+			.CO(CO[i])
+		);
+		SB_LUT4 #(
+			//         I0: 1010 1010 1010 1010
+			//         I1: 1100 1100 1100 1100
+			//         I2: 1111 0000 1111 0000
+			//         I3: 1111 1111 0000 0000
+			.LUT_INIT(16'b 0110_1001_1001_0110)
+		) adder (
+			.I0(1'b0),
 			.I1(AA[i]),
 			.I2(BB[i]),
-			.CI(C[i]),
-			.CO(CO[i]),
+			.I3(C[i]),
 			.O(Y[i])
 		);
-//		SB_CARRY carry (
-//			.I0(AA[i]),
-//			.I1(BB[i]),
-//			.CI(C[i]),
-//			.CO(CO[i])
-//		);
-//		SB_LUT4 #(
-//			//         I0: 1010 1010 1010 1010
-//			//         I1: 1100 1100 1100 1100
-//			//         I2: 1111 0000 1111 0000
-//			//         I3: 1111 1111 0000 0000
-//			.LUT_INIT(16'b 0110_1001_1001_0110)
-//		) adder (
-//			.I0(1'b0),
-//			.I1(AA[i]),
-//			.I2(BB[i]),
-//			.I3(C[i]),
-//			.O(Y[i])
-//		);
 	end endgenerate
 
 	assign X = AA ^ BB;
diff --git a/techlibs/ice40/cells.box b/techlibs/ice40/cells.box
index 34d1f372e..d775efa78 100644
--- a/techlibs/ice40/cells.box
+++ b/techlibs/ice40/cells.box
@@ -2,8 +2,12 @@
 
 # NB: Inputs/Outputs must be ordered alphabetically
 
-# Inputs: CI I1 I2
-# Outputs: CO O
-ICE40_CARRY_LUT 1 1 3 2
+# Inputs: CI I0 I1
+# Outputs: CO
+SB_CARRY 1 1 3 1
 126 259 231
-316 400 379
+
+# Inputs: I0 I1 I2 I3
+# Outputs: O
+SB_LUT4 2 1 4 1
+316 379 400 449
diff --git a/techlibs/ice40/cells_box.v b/techlibs/ice40/cells_box.v
index d0eb8708c..e2a54a42c 100644
--- a/techlibs/ice40/cells_box.v
+++ b/techlibs/ice40/cells_box.v
@@ -1,18 +1,12 @@
 (* abc_box_id = 1 *)
-module ICE40_CARRY_LUT (output CO, O, input CI, I1, I2);
-	assign CO = (I1 && I2) || ((I1 || I2) && CI);
-
-	wire I0, I3;
-	assign I0 = 1'b0;
-	assign I3 = CI;
+module SB_CARRY (output CO, input CI, I0, I1);
+	assign CO = (I0 && I1) || ((I0 || I1) && CI);
+endmodule
 
-	//                            I0: 1010 1010 1010 1010
-	//                            I1: 1100 1100 1100 1100
-	//                            I2: 1111 0000 1111 0000
-	//                            I3: 1111 1111 0000 0000
-	localparam [15:0] LUT_INIT = 16'b 0110_1001_1001_0110;
-	wire [7:0] s3 = I3 ? LUT_INIT[15:8] : LUT_INIT[7:0];
-	wire [3:0] s2 = I2 ?       s3[ 7:4] :       s3[3:0];
-	wire [1:0] s1 = I1 ?       s2[ 3:2] :       s2[1:0];
-	assign O = I0 ? s1[1] : s1[0];
+(* abc_box_id = 2 *)
+module SB_LUT4 (output O, input I0, I1, I2, I3);
+	parameter [15:0] LUT_INIT = 0;
+	// Indicate this is a black-box
+	assign O = 1'b0;
 endmodule
+
diff --git a/techlibs/ice40/cells_map.v b/techlibs/ice40/cells_map.v
index d4c611686..d0ddfd02e 100644
--- a/techlibs/ice40/cells_map.v
+++ b/techlibs/ice40/cells_map.v
@@ -57,27 +57,3 @@ module \$lut (A, Y);
   endgenerate
 endmodule
 `endif
-
-`ifndef NO_CARRY
-module ICE40_CARRY_LUT (output CO, O, input CI, I1, I2);
-	SB_CARRY carry (
-		.I0(I1),
-		.I1(I2),
-		.CI(CI),
-		.CO(CO),
-	);
-	SB_LUT4 #(
-		//         I0: 1010 1010 1010 1010
-		//         I1: 1100 1100 1100 1100
-		//         I2: 1111 0000 1111 0000
-		//         I3: 1111 1111 0000 0000
-		.LUT_INIT(16'b 0110_1001_1001_0110)
-	) adder (
-		.I0(1'b0),
-		.I1(I1),
-		.I2(I2),
-		.I3(CI),
-		.O(O)
-	);
-endmodule
-`endif
diff --git a/techlibs/ice40/cells_sim.v b/techlibs/ice40/cells_sim.v
index b5a739a63..322c1e5c7 100644
--- a/techlibs/ice40/cells_sim.v
+++ b/techlibs/ice40/cells_sim.v
@@ -1384,25 +1384,3 @@ module SB_MAC16 (
 	assign LCI = (BOTADDSUB_CARRYSELECT == 0) ? 1'b0 : (BOTADDSUB_CARRYSELECT == 1) ? 1'b1 : (BOTADDSUB_CARRYSELECT == 2) ? ACCUMCI : CI;
 	assign O = {Oh, Ol};
 endmodule
-
-module ICE40_CARRY_LUT (input CI, input I1, input I2, output CO, output O);
-	SB_CARRY carry (
-		.I0(I1),
-		.I1(I2),
-		.CI(CI),
-		.CO(CO),
-	);
-	SB_LUT4 #(
-		//         I0: 1010 1010 1010 1010
-		//         I1: 1100 1100 1100 1100
-		//         I2: 1111 0000 1111 0000
-		//         I3: 1111 1111 0000 0000
-		.LUT_INIT(16'b 0110_1001_1001_0110)
-	) adder (
-		.I0(1'b0),
-		.I1(I1),
-		.I2(I2),
-		.I3(CI),
-		.O(O)
-	);
-endmodule
diff --git a/techlibs/ice40/ice40_opt.cc b/techlibs/ice40/ice40_opt.cc
index edb293b93..f528607d6 100644
--- a/techlibs/ice40/ice40_opt.cc
+++ b/techlibs/ice40/ice40_opt.cc
@@ -47,20 +47,16 @@ static void run_ice40_opts(Module *module)
 			continue;
 		}
 
-		if (cell->type.in("\\SB_CARRY", "\\ICE40_CARRY_LUT"))
+		if (cell->type == "\\SB_CARRY")
 		{
 			SigSpec non_const_inputs, replacement_output;
 			int count_zeros = 0, count_ones = 0;
 
 			SigBit inbit[3] = {
+				get_bit_or_zero(cell->getPort("\\I0")),
 				get_bit_or_zero(cell->getPort("\\I1")),
 				get_bit_or_zero(cell->getPort("\\CI"))
 			};
-			if (cell->type == "\\SB_CARRY")
-				inbit[2] = get_bit_or_zero(cell->getPort("\\I0"));
-			else if (cell->type == "\\ICE40_CARRY_LUT")
-				inbit[2] = get_bit_or_zero(cell->getPort("\\I2"));
-			else log_abort();
 			for (int i = 0; i < 3; i++)
 				if (inbit[i].wire == nullptr) {
 					if (inbit[i] == State::S1)
@@ -83,14 +79,6 @@ static void run_ice40_opts(Module *module)
 				module->design->scratchpad_set_bool("opt.did_something", true);
 				log("Optimized away SB_CARRY cell %s.%s: CO=%s\n",
 						log_id(module), log_id(cell), log_signal(replacement_output));
-
-				if (cell->type == "\\ICE40_CARRY_LUT")
-					module->addLut(NEW_ID,
-						{ RTLIL::S0, cell->getPort("\\I1"), cell->getPort("\\I2"), cell->getPort("\\CI") },
-						cell->getPort("\\O"),
-						RTLIL::Const("0110_1001_1001_0110"),
-						cell->get_src_attribute());
-
 				module->remove(cell);
 			}
 			continue;
diff --git a/techlibs/ice40/synth_ice40.cc b/techlibs/ice40/synth_ice40.cc
index d09a1184c..3faa10b4f 100644
--- a/techlibs/ice40/synth_ice40.cc
+++ b/techlibs/ice40/synth_ice40.cc
@@ -296,7 +296,7 @@ struct SynthIce40Pass : public ScriptPass
 				run("opt_merge");
 				run(stringf("dff2dffe -unmap-mince %d", min_ce_use));
 			}
-			run("techmap -D NO_LUT -D NO_CARRY -map +/ice40/cells_map.v");
+			run("techmap -D NO_LUT -map +/ice40/cells_map.v");
 			run("opt_expr -mux_undef");
 			run("simplemap");
 			run("ice40_ffinit");
-- 
cgit v1.2.3


From 42c33db22caeffa05bde59d915a4433b756929a1 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Wed, 17 Apr 2019 12:15:34 -0700
Subject: Rename to abc.*

---
 techlibs/ice40/abc.box     | 13 +++++++++++++
 techlibs/ice40/abc.lut     |  6 ++++++
 techlibs/ice40/abc.v       | 12 ++++++++++++
 techlibs/ice40/cells.box   | 13 -------------
 techlibs/ice40/cells_box.v | 12 ------------
 techlibs/ice40/lut.lut     |  6 ------
 6 files changed, 31 insertions(+), 31 deletions(-)
 create mode 100644 techlibs/ice40/abc.box
 create mode 100644 techlibs/ice40/abc.lut
 create mode 100644 techlibs/ice40/abc.v
 delete mode 100644 techlibs/ice40/cells.box
 delete mode 100644 techlibs/ice40/cells_box.v
 delete mode 100644 techlibs/ice40/lut.lut

(limited to 'techlibs/ice40')

diff --git a/techlibs/ice40/abc.box b/techlibs/ice40/abc.box
new file mode 100644
index 000000000..d775efa78
--- /dev/null
+++ b/techlibs/ice40/abc.box
@@ -0,0 +1,13 @@
+# From https://github.com/cliffordwolf/icestorm/blob/81c33a3/icefuzz/timings_hx8k.txt
+
+# NB: Inputs/Outputs must be ordered alphabetically
+
+# Inputs: CI I0 I1
+# Outputs: CO
+SB_CARRY 1 1 3 1
+126 259 231
+
+# Inputs: I0 I1 I2 I3
+# Outputs: O
+SB_LUT4 2 1 4 1
+316 379 400 449
diff --git a/techlibs/ice40/abc.lut b/techlibs/ice40/abc.lut
new file mode 100644
index 000000000..eef997869
--- /dev/null
+++ b/techlibs/ice40/abc.lut
@@ -0,0 +1,6 @@
+# From https://github.com/cliffordwolf/icestorm/blob/81c33a3/icefuzz/timings_hx8k.txt
+#       I3  I2  I1  I0
+1   1   316
+2   1   316 379
+3   1   316 379 400
+4   1   316 379 400 449
diff --git a/techlibs/ice40/abc.v b/techlibs/ice40/abc.v
new file mode 100644
index 000000000..e2a54a42c
--- /dev/null
+++ b/techlibs/ice40/abc.v
@@ -0,0 +1,12 @@
+(* abc_box_id = 1 *)
+module SB_CARRY (output CO, input CI, I0, I1);
+	assign CO = (I0 && I1) || ((I0 || I1) && CI);
+endmodule
+
+(* abc_box_id = 2 *)
+module SB_LUT4 (output O, input I0, I1, I2, I3);
+	parameter [15:0] LUT_INIT = 0;
+	// Indicate this is a black-box
+	assign O = 1'b0;
+endmodule
+
diff --git a/techlibs/ice40/cells.box b/techlibs/ice40/cells.box
deleted file mode 100644
index d775efa78..000000000
--- a/techlibs/ice40/cells.box
+++ /dev/null
@@ -1,13 +0,0 @@
-# From https://github.com/cliffordwolf/icestorm/blob/81c33a3/icefuzz/timings_hx8k.txt
-
-# NB: Inputs/Outputs must be ordered alphabetically
-
-# Inputs: CI I0 I1
-# Outputs: CO
-SB_CARRY 1 1 3 1
-126 259 231
-
-# Inputs: I0 I1 I2 I3
-# Outputs: O
-SB_LUT4 2 1 4 1
-316 379 400 449
diff --git a/techlibs/ice40/cells_box.v b/techlibs/ice40/cells_box.v
deleted file mode 100644
index e2a54a42c..000000000
--- a/techlibs/ice40/cells_box.v
+++ /dev/null
@@ -1,12 +0,0 @@
-(* abc_box_id = 1 *)
-module SB_CARRY (output CO, input CI, I0, I1);
-	assign CO = (I0 && I1) || ((I0 || I1) && CI);
-endmodule
-
-(* abc_box_id = 2 *)
-module SB_LUT4 (output O, input I0, I1, I2, I3);
-	parameter [15:0] LUT_INIT = 0;
-	// Indicate this is a black-box
-	assign O = 1'b0;
-endmodule
-
diff --git a/techlibs/ice40/lut.lut b/techlibs/ice40/lut.lut
deleted file mode 100644
index eef997869..000000000
--- a/techlibs/ice40/lut.lut
+++ /dev/null
@@ -1,6 +0,0 @@
-# From https://github.com/cliffordwolf/icestorm/blob/81c33a3/icefuzz/timings_hx8k.txt
-#       I3  I2  I1  I0
-1   1   316
-2   1   316 379
-3   1   316 379 400
-4   1   316 379 400 449
-- 
cgit v1.2.3


From 4fb9ccfcd81db6d2e574bea3d142b714126d1123 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Wed, 17 Apr 2019 12:22:03 -0700
Subject: synth_ice40 to use renamed files

---
 techlibs/ice40/synth_ice40.cc | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

(limited to 'techlibs/ice40')

diff --git a/techlibs/ice40/synth_ice40.cc b/techlibs/ice40/synth_ice40.cc
index 3faa10b4f..91cd063a2 100644
--- a/techlibs/ice40/synth_ice40.cc
+++ b/techlibs/ice40/synth_ice40.cc
@@ -317,9 +317,9 @@ struct SynthIce40Pass : public ScriptPass
 			}
 			if (!noabc) {
 				if (abc == "abc9") {
-					run("read_verilog +/ice40/cells_box.v");
+					run("read_verilog +/ice40/abc.v");
 					run("techmap -map +/techmap.v A:abc_box_id");
-					run(abc + " -dress -lut +/ice40/lut.lut -box +/ice40/cells.box", "(skip if -noabc)");
+					run(abc + " -dress -lut +/ice40/abc.lut -box +/ice40/abc.box", "(skip if -noabc)");
 					run("blackbox A:abc_box_id");
 				}
 				else
-- 
cgit v1.2.3


From 1eade0667102b50afa927f64e22968dd28365167 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Wed, 17 Apr 2019 12:27:02 -0700
Subject: Also update Makefile.inc

---
 techlibs/ice40/Makefile.inc | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

(limited to 'techlibs/ice40')

diff --git a/techlibs/ice40/Makefile.inc b/techlibs/ice40/Makefile.inc
index cd992bb24..abfede011 100644
--- a/techlibs/ice40/Makefile.inc
+++ b/techlibs/ice40/Makefile.inc
@@ -28,9 +28,9 @@ $(eval $(call add_share_file,share/ice40,techlibs/ice40/cells_sim.v))
 $(eval $(call add_share_file,share/ice40,techlibs/ice40/latches_map.v))
 $(eval $(call add_share_file,share/ice40,techlibs/ice40/brams.txt))
 $(eval $(call add_share_file,share/ice40,techlibs/ice40/brams_map.v))
-$(eval $(call add_share_file,share/ice40,techlibs/ice40/cells.box))
-$(eval $(call add_share_file,share/ice40,techlibs/ice40/cells_box.v))
-$(eval $(call add_share_file,share/ice40,techlibs/ice40/lut.lut))
+$(eval $(call add_share_file,share/ice40,techlibs/ice40/abc.box))
+$(eval $(call add_share_file,share/ice40,techlibs/ice40/abc.v))
+$(eval $(call add_share_file,share/ice40,techlibs/ice40/abc.lut))
 
 $(eval $(call add_gen_share_file,share/ice40,techlibs/ice40/brams_init1.vh))
 $(eval $(call add_gen_share_file,share/ice40,techlibs/ice40/brams_init2.vh))
-- 
cgit v1.2.3


From 58847df1b94d2caaa1fe959acb04425397f3567f Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Wed, 17 Apr 2019 12:27:45 -0700
Subject: Mark seq output ports with "abc_flop_q" attr

---
 techlibs/ice40/cells_sim.v | 48 +++++++++++++++++++++++-----------------------
 1 file changed, 24 insertions(+), 24 deletions(-)

(limited to 'techlibs/ice40')

diff --git a/techlibs/ice40/cells_sim.v b/techlibs/ice40/cells_sim.v
index 322c1e5c7..cf7b9d252 100644
--- a/techlibs/ice40/cells_sim.v
+++ b/techlibs/ice40/cells_sim.v
@@ -132,18 +132,18 @@ endmodule
 
 // Positive Edge SiliconBlue FF Cells
 
-module SB_DFF (output `SB_DFF_REG, input C, D);
+module SB_DFF ((* abc_flop_q *) output `SB_DFF_REG, input C, D);
 	always @(posedge C)
 		Q <= D;
 endmodule
 
-module SB_DFFE (output `SB_DFF_REG, input C, E, D);
+module SB_DFFE ((* abc_flop_q *) output `SB_DFF_REG, input C, E, D);
 	always @(posedge C)
 		if (E)
 			Q <= D;
 endmodule
 
-module SB_DFFSR (output `SB_DFF_REG, input C, R, D);
+module SB_DFFSR ((* abc_flop_q *) output `SB_DFF_REG, input C, R, D);
 	always @(posedge C)
 		if (R)
 			Q <= 0;
@@ -151,7 +151,7 @@ module SB_DFFSR (output `SB_DFF_REG, input C, R, D);
 			Q <= D;
 endmodule
 
-module SB_DFFR (output `SB_DFF_REG, input C, R, D);
+module SB_DFFR ((* abc_flop_q *) output `SB_DFF_REG, input C, R, D);
 	always @(posedge C, posedge R)
 		if (R)
 			Q <= 0;
@@ -159,7 +159,7 @@ module SB_DFFR (output `SB_DFF_REG, input C, R, D);
 			Q <= D;
 endmodule
 
-module SB_DFFSS (output `SB_DFF_REG, input C, S, D);
+module SB_DFFSS ((* abc_flop_q *) output `SB_DFF_REG, input C, S, D);
 	always @(posedge C)
 		if (S)
 			Q <= 1;
@@ -167,7 +167,7 @@ module SB_DFFSS (output `SB_DFF_REG, input C, S, D);
 			Q <= D;
 endmodule
 
-module SB_DFFS (output `SB_DFF_REG, input C, S, D);
+module SB_DFFS ((* abc_flop_q *) output `SB_DFF_REG, input C, S, D);
 	always @(posedge C, posedge S)
 		if (S)
 			Q <= 1;
@@ -175,7 +175,7 @@ module SB_DFFS (output `SB_DFF_REG, input C, S, D);
 			Q <= D;
 endmodule
 
-module SB_DFFESR (output `SB_DFF_REG, input C, E, R, D);
+module SB_DFFESR ((* abc_flop_q *) output `SB_DFF_REG, input C, E, R, D);
 	always @(posedge C)
 		if (E) begin
 			if (R)
@@ -185,7 +185,7 @@ module SB_DFFESR (output `SB_DFF_REG, input C, E, R, D);
 		end
 endmodule
 
-module SB_DFFER (output `SB_DFF_REG, input C, E, R, D);
+module SB_DFFER ((* abc_flop_q *) output `SB_DFF_REG, input C, E, R, D);
 	always @(posedge C, posedge R)
 		if (R)
 			Q <= 0;
@@ -193,7 +193,7 @@ module SB_DFFER (output `SB_DFF_REG, input C, E, R, D);
 			Q <= D;
 endmodule
 
-module SB_DFFESS (output `SB_DFF_REG, input C, E, S, D);
+module SB_DFFESS ((* abc_flop_q *) output `SB_DFF_REG, input C, E, S, D);
 	always @(posedge C)
 		if (E) begin
 			if (S)
@@ -203,7 +203,7 @@ module SB_DFFESS (output `SB_DFF_REG, input C, E, S, D);
 		end
 endmodule
 
-module SB_DFFES (output `SB_DFF_REG, input C, E, S, D);
+module SB_DFFES ((* abc_flop_q *) output `SB_DFF_REG, input C, E, S, D);
 	always @(posedge C, posedge S)
 		if (S)
 			Q <= 1;
@@ -213,18 +213,18 @@ endmodule
 
 // Negative Edge SiliconBlue FF Cells
 
-module SB_DFFN (output `SB_DFF_REG, input C, D);
+module SB_DFFN ((* abc_flop_q *) output `SB_DFF_REG, input C, D);
 	always @(negedge C)
 		Q <= D;
 endmodule
 
-module SB_DFFNE (output `SB_DFF_REG, input C, E, D);
+module SB_DFFNE ((* abc_flop_q *) output `SB_DFF_REG, input C, E, D);
 	always @(negedge C)
 		if (E)
 			Q <= D;
 endmodule
 
-module SB_DFFNSR (output `SB_DFF_REG, input C, R, D);
+module SB_DFFNSR ((* abc_flop_q *) output `SB_DFF_REG, input C, R, D);
 	always @(negedge C)
 		if (R)
 			Q <= 0;
@@ -232,7 +232,7 @@ module SB_DFFNSR (output `SB_DFF_REG, input C, R, D);
 			Q <= D;
 endmodule
 
-module SB_DFFNR (output `SB_DFF_REG, input C, R, D);
+module SB_DFFNR ((* abc_flop_q *) output `SB_DFF_REG, input C, R, D);
 	always @(negedge C, posedge R)
 		if (R)
 			Q <= 0;
@@ -240,7 +240,7 @@ module SB_DFFNR (output `SB_DFF_REG, input C, R, D);
 			Q <= D;
 endmodule
 
-module SB_DFFNSS (output `SB_DFF_REG, input C, S, D);
+module SB_DFFNSS ((* abc_flop_q *) output `SB_DFF_REG, input C, S, D);
 	always @(negedge C)
 		if (S)
 			Q <= 1;
@@ -248,7 +248,7 @@ module SB_DFFNSS (output `SB_DFF_REG, input C, S, D);
 			Q <= D;
 endmodule
 
-module SB_DFFNS (output `SB_DFF_REG, input C, S, D);
+module SB_DFFNS ((* abc_flop_q *) output `SB_DFF_REG, input C, S, D);
 	always @(negedge C, posedge S)
 		if (S)
 			Q <= 1;
@@ -256,7 +256,7 @@ module SB_DFFNS (output `SB_DFF_REG, input C, S, D);
 			Q <= D;
 endmodule
 
-module SB_DFFNESR (output `SB_DFF_REG, input C, E, R, D);
+module SB_DFFNESR ((* abc_flop_q *) output `SB_DFF_REG, input C, E, R, D);
 	always @(negedge C)
 		if (E) begin
 			if (R)
@@ -266,7 +266,7 @@ module SB_DFFNESR (output `SB_DFF_REG, input C, E, R, D);
 		end
 endmodule
 
-module SB_DFFNER (output `SB_DFF_REG, input C, E, R, D);
+module SB_DFFNER ((* abc_flop_q *) output `SB_DFF_REG, input C, E, R, D);
 	always @(negedge C, posedge R)
 		if (R)
 			Q <= 0;
@@ -274,7 +274,7 @@ module SB_DFFNER (output `SB_DFF_REG, input C, E, R, D);
 			Q <= D;
 endmodule
 
-module SB_DFFNESS (output `SB_DFF_REG, input C, E, S, D);
+module SB_DFFNESS ((* abc_flop_q *) output `SB_DFF_REG, input C, E, S, D);
 	always @(negedge C)
 		if (E) begin
 			if (S)
@@ -284,7 +284,7 @@ module SB_DFFNESS (output `SB_DFF_REG, input C, E, S, D);
 		end
 endmodule
 
-module SB_DFFNES (output `SB_DFF_REG, input C, E, S, D);
+module SB_DFFNES ((* abc_flop_q *) output `SB_DFF_REG, input C, E, S, D);
 	always @(negedge C, posedge S)
 		if (S)
 			Q <= 1;
@@ -295,7 +295,7 @@ endmodule
 // SiliconBlue RAM Cells
 
 module SB_RAM40_4K (
-	output [15:0] RDATA,
+	(* abc_flop_q *) output [15:0] RDATA,
 	input         RCLK, RCLKE, RE,
 	input  [10:0] RADDR,
 	input         WCLK, WCLKE, WE,
@@ -463,7 +463,7 @@ module SB_RAM40_4K (
 endmodule
 
 module SB_RAM40_4KNR (
-	output [15:0] RDATA,
+	(* abc_flop_q *) output [15:0] RDATA,
 	input         RCLKN, RCLKE, RE,
 	input  [10:0] RADDR,
 	input         WCLK, WCLKE, WE,
@@ -528,7 +528,7 @@ module SB_RAM40_4KNR (
 endmodule
 
 module SB_RAM40_4KNW (
-	output [15:0] RDATA,
+	(* abc_flop_q *) output [15:0] RDATA,
 	input         RCLK, RCLKE, RE,
 	input  [10:0] RADDR,
 	input         WCLKN, WCLKE, WE,
@@ -593,7 +593,7 @@ module SB_RAM40_4KNW (
 endmodule
 
 module SB_RAM40_4KNRNW (
-	output [15:0] RDATA,
+	(* abc_flop_q *) output [15:0] RDATA,
 	input         RCLKN, RCLKE, RE,
 	input  [10:0] RADDR,
 	input         WCLKN, WCLKE, WE,
-- 
cgit v1.2.3


From 437fec0d88b4a2ad172edf0d1a861a38845f3b1d Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Wed, 17 Apr 2019 13:01:17 -0700
Subject: Map to SB_LUT4 from fastest input first

---
 techlibs/ice40/cells_map.v | 18 +++++++++++-------
 1 file changed, 11 insertions(+), 7 deletions(-)

(limited to 'techlibs/ice40')

diff --git a/techlibs/ice40/cells_map.v b/techlibs/ice40/cells_map.v
index d0ddfd02e..287c48b11 100644
--- a/techlibs/ice40/cells_map.v
+++ b/techlibs/ice40/cells_map.v
@@ -37,20 +37,24 @@ module \$lut (A, Y);
 
   generate
     if (WIDTH == 1) begin
-      SB_LUT4 #(.LUT_INIT(LUT)) _TECHMAP_REPLACE_ (.O(Y),
-        .I0(A[0]), .I1(1'b0), .I2(1'b0), .I3(1'b0));
+      localparam [15:0] INIT = {{8{LUT[1]}}, {8{LUT[0]}}};
+      SB_LUT4 #(.LUT_INIT(INIT)) _TECHMAP_REPLACE_ (.O(Y),
+        .I0(1'b0), .I1(1'b0), .I2(1'b0), .I3(A[0]));
     end else
     if (WIDTH == 2) begin
-      SB_LUT4 #(.LUT_INIT(LUT)) _TECHMAP_REPLACE_ (.O(Y),
-        .I0(A[0]), .I1(A[1]), .I2(1'b0), .I3(1'b0));
+      localparam [15:0] INIT = {{4{LUT[3]}}, {4{LUT[1]}}, {4{LUT[2]}}, {4{LUT[0]}}};
+      SB_LUT4 #(.LUT_INIT(INIT)) _TECHMAP_REPLACE_ (.O(Y),
+        .I0(1'b0), .I1(1'b0), .I2(A[1]), .I3(A[0]));
     end else
     if (WIDTH == 3) begin
-      SB_LUT4 #(.LUT_INIT(LUT)) _TECHMAP_REPLACE_ (.O(Y),
-        .I0(A[0]), .I1(A[1]), .I2(A[2]), .I3(1'b0));
+      localparam [15:0] INIT = {{2{LUT[7]}}, {2{LUT[3]}}, {2{LUT[5]}}, {2{LUT[1]}}, {2{LUT[6]}}, {2{LUT[2]}}, {2{LUT[4]}}, {2{LUT[0]}}};
+      SB_LUT4 #(.LUT_INIT(INIT)) _TECHMAP_REPLACE_ (.O(Y),
+        .I0(1'b0), .I1(A[2]), .I2(A[1]), .I3(A[0]));
     end else
     if (WIDTH == 4) begin
+      localparam [15:0] INIT = {LUT[15], LUT[7], LUT[11], LUT[3], LUT[13], LUT[5], LUT[9], LUT[1], LUT[14], LUT[6], LUT[10], LUT[2], LUT[12], LUT[4], LUT[8], LUT[0]};
       SB_LUT4 #(.LUT_INIT(LUT)) _TECHMAP_REPLACE_ (.O(Y),
-        .I0(A[0]), .I1(A[1]), .I2(A[2]), .I3(A[3]));
+        .I0(A[3]), .I1(A[2]), .I2(A[1]), .I3(A[0]));
     end else begin
       wire _TECHMAP_FAIL_ = 1;
     end
-- 
cgit v1.2.3


From 671cca59a9f63f9fb7102727eb4dee1b18fe3ef6 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Wed, 17 Apr 2019 14:44:08 -0700
Subject: Missing abc_flop_q attribute on SPRAM

---
 techlibs/ice40/cells_sim.v | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'techlibs/ice40')

diff --git a/techlibs/ice40/cells_sim.v b/techlibs/ice40/cells_sim.v
index cf7b9d252..70cd51ed1 100644
--- a/techlibs/ice40/cells_sim.v
+++ b/techlibs/ice40/cells_sim.v
@@ -887,7 +887,7 @@ module SB_SPRAM256KA (
 	input [15:0] DATAIN,
 	input [3:0] MASKWREN,
 	input WREN, CHIPSELECT, CLOCK, STANDBY, SLEEP, POWEROFF,
-	output reg [15:0] DATAOUT
+	(* abc_flop_q *) output reg [15:0] DATAOUT
 );
 `ifndef BLACKBOX
 `ifndef EQUIV
-- 
cgit v1.2.3


From 6f3e5297dbf1a0b28e6bfa51990f957939d722d7 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Wed, 17 Apr 2019 15:04:46 -0700
Subject: Add "-device" argument to synth_ice40

---
 techlibs/ice40/Makefile.inc   |  6 ++++--
 techlibs/ice40/abc.box        | 13 -------------
 techlibs/ice40/abc.lut        |  6 ------
 techlibs/ice40/hx8k.box       | 13 +++++++++++++
 techlibs/ice40/hx8k.lut       |  6 ++++++
 techlibs/ice40/synth_ice40.cc | 15 +++++++++++++--
 6 files changed, 36 insertions(+), 23 deletions(-)
 delete mode 100644 techlibs/ice40/abc.box
 delete mode 100644 techlibs/ice40/abc.lut
 create mode 100644 techlibs/ice40/hx8k.box
 create mode 100644 techlibs/ice40/hx8k.lut

(limited to 'techlibs/ice40')

diff --git a/techlibs/ice40/Makefile.inc b/techlibs/ice40/Makefile.inc
index abfede011..efcea6e98 100644
--- a/techlibs/ice40/Makefile.inc
+++ b/techlibs/ice40/Makefile.inc
@@ -28,9 +28,11 @@ $(eval $(call add_share_file,share/ice40,techlibs/ice40/cells_sim.v))
 $(eval $(call add_share_file,share/ice40,techlibs/ice40/latches_map.v))
 $(eval $(call add_share_file,share/ice40,techlibs/ice40/brams.txt))
 $(eval $(call add_share_file,share/ice40,techlibs/ice40/brams_map.v))
-$(eval $(call add_share_file,share/ice40,techlibs/ice40/abc.box))
 $(eval $(call add_share_file,share/ice40,techlibs/ice40/abc.v))
-$(eval $(call add_share_file,share/ice40,techlibs/ice40/abc.lut))
+$(eval $(call add_share_file,share/ice40,techlibs/ice40/hx8k.box))
+$(eval $(call add_share_file,share/ice40,techlibs/ice40/hx8k.lut))
+$(eval $(call add_share_file,share/ice40,techlibs/ice40/up5k.box))
+$(eval $(call add_share_file,share/ice40,techlibs/ice40/up5k.lut))
 
 $(eval $(call add_gen_share_file,share/ice40,techlibs/ice40/brams_init1.vh))
 $(eval $(call add_gen_share_file,share/ice40,techlibs/ice40/brams_init2.vh))
diff --git a/techlibs/ice40/abc.box b/techlibs/ice40/abc.box
deleted file mode 100644
index d775efa78..000000000
--- a/techlibs/ice40/abc.box
+++ /dev/null
@@ -1,13 +0,0 @@
-# From https://github.com/cliffordwolf/icestorm/blob/81c33a3/icefuzz/timings_hx8k.txt
-
-# NB: Inputs/Outputs must be ordered alphabetically
-
-# Inputs: CI I0 I1
-# Outputs: CO
-SB_CARRY 1 1 3 1
-126 259 231
-
-# Inputs: I0 I1 I2 I3
-# Outputs: O
-SB_LUT4 2 1 4 1
-316 379 400 449
diff --git a/techlibs/ice40/abc.lut b/techlibs/ice40/abc.lut
deleted file mode 100644
index eef997869..000000000
--- a/techlibs/ice40/abc.lut
+++ /dev/null
@@ -1,6 +0,0 @@
-# From https://github.com/cliffordwolf/icestorm/blob/81c33a3/icefuzz/timings_hx8k.txt
-#       I3  I2  I1  I0
-1   1   316
-2   1   316 379
-3   1   316 379 400
-4   1   316 379 400 449
diff --git a/techlibs/ice40/hx8k.box b/techlibs/ice40/hx8k.box
new file mode 100644
index 000000000..c31f7bf39
--- /dev/null
+++ b/techlibs/ice40/hx8k.box
@@ -0,0 +1,13 @@
+# From https://github.com/cliffordwolf/icestorm/blob/be0bca0/icefuzz/timings_hx8k.txt
+
+# NB: Inputs/Outputs must be ordered alphabetically
+
+# Inputs: CI I0 I1
+# Outputs: CO
+SB_CARRY 1 1 3 1
+126 259 231
+
+# Inputs: I0 I1 I2 I3
+# Outputs: O
+SB_LUT4 2 1 4 1
+449 400 379 316
diff --git a/techlibs/ice40/hx8k.lut b/techlibs/ice40/hx8k.lut
new file mode 100644
index 000000000..3b3bb11e2
--- /dev/null
+++ b/techlibs/ice40/hx8k.lut
@@ -0,0 +1,6 @@
+# From https://github.com/cliffordwolf/icestorm/blob/be0bca0/icefuzz/timings_hx8k.txt
+#       I3  I2  I1  I0
+1   1   316
+2   1   316 379
+3   1   316 379 400
+4   1   316 379 400 449
diff --git a/techlibs/ice40/synth_ice40.cc b/techlibs/ice40/synth_ice40.cc
index 91cd063a2..2981875eb 100644
--- a/techlibs/ice40/synth_ice40.cc
+++ b/techlibs/ice40/synth_ice40.cc
@@ -37,6 +37,10 @@ struct SynthIce40Pass : public ScriptPass
 		log("\n");
 		log("This command runs synthesis for iCE40 FPGAs.\n");
 		log("\n");
+		log("    -device < hx1k | lp384 | lp1k | lp8k | hx8k | u4k | up5k >\n");
+		log("        optimise the synthesis netlist for the specified device.\n");
+		log("        HX1K is the default target if no device argument specified.\n");
+		log("\n");
 		log("    -top <module>\n");
 		log("        use the specified module as top module\n");
 		log("\n");
@@ -102,7 +106,7 @@ struct SynthIce40Pass : public ScriptPass
 	}
 
 
-	string top_opt, blif_file, edif_file, json_file, abc;
+	string top_opt, blif_file, edif_file, json_file, abc, device_opt;
 	bool nocarry, nodffe, nobram, dsp, flatten, retime, relut, noabc, abc2, vpr;
 	int min_ce_use;
 
@@ -124,6 +128,7 @@ struct SynthIce40Pass : public ScriptPass
 		abc2 = false;
 		vpr = false;
 		abc = "abc";
+		device_opt = "hx1k";
 	}
 
 	void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
@@ -210,12 +215,18 @@ struct SynthIce40Pass : public ScriptPass
 				abc = "abc9";
 				continue;
 			}
+			if (args[argidx] == "-device" && argidx+1 < args.size()) {
+				device_opt = args[++argidx];
+				continue;
+			}
 			break;
 		}
 		extra_args(args, argidx, design);
 
 		if (!design->full_selection())
 			log_cmd_error("This command only operates on fully selected designs!\n");
+		if (device_opt != "hx1k" && device_opt !="lp384" && device_opt != "lp1k" && device_opt !="lp8k" && device_opt !="hx8k" && device_opt != "u4k" && device_opt != "up5k")
+			log_cmd_error("Invalid or no family specified: '%s'\n", device_opt.c_str());
 
 		log_header(design, "Executing SYNTH_ICE40 pass.\n");
 		log_push();
@@ -319,7 +330,7 @@ struct SynthIce40Pass : public ScriptPass
 				if (abc == "abc9") {
 					run("read_verilog +/ice40/abc.v");
 					run("techmap -map +/techmap.v A:abc_box_id");
-					run(abc + " -dress -lut +/ice40/abc.lut -box +/ice40/abc.box", "(skip if -noabc)");
+					run(abc + stringf(" -dress -lut +/ice40/%s.lut -box +/ice40/%s.box", device_opt.c_str(), device_opt.c_str()), "(skip if -noabc)");
 					run("blackbox A:abc_box_id");
 				}
 				else
-- 
cgit v1.2.3


From 3105a8a6531545efefe228fb4fc4b7b09ae127e8 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Wed, 17 Apr 2019 15:07:44 -0700
Subject: Update error message

---
 techlibs/ice40/synth_ice40.cc | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'techlibs/ice40')

diff --git a/techlibs/ice40/synth_ice40.cc b/techlibs/ice40/synth_ice40.cc
index 2981875eb..62589ad87 100644
--- a/techlibs/ice40/synth_ice40.cc
+++ b/techlibs/ice40/synth_ice40.cc
@@ -226,7 +226,7 @@ struct SynthIce40Pass : public ScriptPass
 		if (!design->full_selection())
 			log_cmd_error("This command only operates on fully selected designs!\n");
 		if (device_opt != "hx1k" && device_opt !="lp384" && device_opt != "lp1k" && device_opt !="lp8k" && device_opt !="hx8k" && device_opt != "u4k" && device_opt != "up5k")
-			log_cmd_error("Invalid or no family specified: '%s'\n", device_opt.c_str());
+			log_cmd_error("Invalid or no device specified: '%s'\n", device_opt.c_str());
 
 		log_header(design, "Executing SYNTH_ICE40 pass.\n");
 		log_push();
-- 
cgit v1.2.3


From 5c0853fc518bbbad77b819a5c916e438d0e33cb0 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Wed, 17 Apr 2019 15:10:39 -0700
Subject: Add up5k timings

---
 techlibs/ice40/up5k.box | 13 +++++++++++++
 techlibs/ice40/up5k.lut |  6 ++++++
 2 files changed, 19 insertions(+)
 create mode 100644 techlibs/ice40/up5k.box
 create mode 100644 techlibs/ice40/up5k.lut

(limited to 'techlibs/ice40')

diff --git a/techlibs/ice40/up5k.box b/techlibs/ice40/up5k.box
new file mode 100644
index 000000000..94df1df8f
--- /dev/null
+++ b/techlibs/ice40/up5k.box
@@ -0,0 +1,13 @@
+# From https://github.com/cliffordwolf/icestorm/blob/be0bca0/icefuzz/timings_up5k.txt
+
+# NB: Inputs/Outputs must be ordered alphabetically
+
+# Inputs: CI I0 I1
+# Outputs: CO
+SB_CARRY 1 1 3 1
+278 675 609
+
+# Inputs: I0 I1 I2 I3
+# Outputs: O
+SB_LUT4 2 1 4 1
+1285 1231 1205 874
diff --git a/techlibs/ice40/up5k.lut b/techlibs/ice40/up5k.lut
new file mode 100644
index 000000000..1e4fcadb6
--- /dev/null
+++ b/techlibs/ice40/up5k.lut
@@ -0,0 +1,6 @@
+# From https://github.com/cliffordwolf/icestorm/blob/be0bca0/icefuzz/timings_up5k.txt
+#       I3  I2  I1  I0
+1   1   874
+2   1   874 1205
+3   1   874 1205 1231
+4   1   874 1205 1231 1285
-- 
cgit v1.2.3


From c795e14d25b42ae28bd4b8f7e259e969442437b3 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Wed, 17 Apr 2019 15:19:02 -0700
Subject: Reduce to three devices: hx, lp, u

---
 techlibs/ice40/hx.box         | 13 +++++++++++++
 techlibs/ice40/hx.lut         |  6 ++++++
 techlibs/ice40/hx8k.box       | 13 -------------
 techlibs/ice40/hx8k.lut       |  6 ------
 techlibs/ice40/lp.box         | 13 +++++++++++++
 techlibs/ice40/lp.lut         |  6 ++++++
 techlibs/ice40/synth_ice40.cc |  8 ++++----
 techlibs/ice40/u.box          | 13 +++++++++++++
 techlibs/ice40/u.lut          |  6 ++++++
 techlibs/ice40/up5k.box       | 13 -------------
 techlibs/ice40/up5k.lut       |  6 ------
 11 files changed, 61 insertions(+), 42 deletions(-)
 create mode 100644 techlibs/ice40/hx.box
 create mode 100644 techlibs/ice40/hx.lut
 delete mode 100644 techlibs/ice40/hx8k.box
 delete mode 100644 techlibs/ice40/hx8k.lut
 create mode 100644 techlibs/ice40/lp.box
 create mode 100644 techlibs/ice40/lp.lut
 create mode 100644 techlibs/ice40/u.box
 create mode 100644 techlibs/ice40/u.lut
 delete mode 100644 techlibs/ice40/up5k.box
 delete mode 100644 techlibs/ice40/up5k.lut

(limited to 'techlibs/ice40')

diff --git a/techlibs/ice40/hx.box b/techlibs/ice40/hx.box
new file mode 100644
index 000000000..c31f7bf39
--- /dev/null
+++ b/techlibs/ice40/hx.box
@@ -0,0 +1,13 @@
+# From https://github.com/cliffordwolf/icestorm/blob/be0bca0/icefuzz/timings_hx8k.txt
+
+# NB: Inputs/Outputs must be ordered alphabetically
+
+# Inputs: CI I0 I1
+# Outputs: CO
+SB_CARRY 1 1 3 1
+126 259 231
+
+# Inputs: I0 I1 I2 I3
+# Outputs: O
+SB_LUT4 2 1 4 1
+449 400 379 316
diff --git a/techlibs/ice40/hx.lut b/techlibs/ice40/hx.lut
new file mode 100644
index 000000000..3b3bb11e2
--- /dev/null
+++ b/techlibs/ice40/hx.lut
@@ -0,0 +1,6 @@
+# From https://github.com/cliffordwolf/icestorm/blob/be0bca0/icefuzz/timings_hx8k.txt
+#       I3  I2  I1  I0
+1   1   316
+2   1   316 379
+3   1   316 379 400
+4   1   316 379 400 449
diff --git a/techlibs/ice40/hx8k.box b/techlibs/ice40/hx8k.box
deleted file mode 100644
index c31f7bf39..000000000
--- a/techlibs/ice40/hx8k.box
+++ /dev/null
@@ -1,13 +0,0 @@
-# From https://github.com/cliffordwolf/icestorm/blob/be0bca0/icefuzz/timings_hx8k.txt
-
-# NB: Inputs/Outputs must be ordered alphabetically
-
-# Inputs: CI I0 I1
-# Outputs: CO
-SB_CARRY 1 1 3 1
-126 259 231
-
-# Inputs: I0 I1 I2 I3
-# Outputs: O
-SB_LUT4 2 1 4 1
-449 400 379 316
diff --git a/techlibs/ice40/hx8k.lut b/techlibs/ice40/hx8k.lut
deleted file mode 100644
index 3b3bb11e2..000000000
--- a/techlibs/ice40/hx8k.lut
+++ /dev/null
@@ -1,6 +0,0 @@
-# From https://github.com/cliffordwolf/icestorm/blob/be0bca0/icefuzz/timings_hx8k.txt
-#       I3  I2  I1  I0
-1   1   316
-2   1   316 379
-3   1   316 379 400
-4   1   316 379 400 449
diff --git a/techlibs/ice40/lp.box b/techlibs/ice40/lp.box
new file mode 100644
index 000000000..7eb8e86e0
--- /dev/null
+++ b/techlibs/ice40/lp.box
@@ -0,0 +1,13 @@
+# From https://github.com/cliffordwolf/icestorm/blob/be0bca0/icefuzz/timings_lp8k.txt
+
+# NB: Inputs/Outputs must be ordered alphabetically
+
+# Inputs: CI I0 I1
+# Outputs: CO
+SB_CARRY 1 1 3 1
+186 675 609
+
+# Inputs: I0 I1 I2 I3
+# Outputs: O
+SB_LUT4 2 1 4 1
+465 558 589 661
diff --git a/techlibs/ice40/lp.lut b/techlibs/ice40/lp.lut
new file mode 100644
index 000000000..e72f760a2
--- /dev/null
+++ b/techlibs/ice40/lp.lut
@@ -0,0 +1,6 @@
+# From https://github.com/cliffordwolf/icestorm/blob/be0bca0/icefuzz/timings_lp8k.txt
+#       I3  I2  I1  I0
+1   1   465
+2   1   465 558
+3   1   465 558 589
+4   1   465 558 589 661
diff --git a/techlibs/ice40/synth_ice40.cc b/techlibs/ice40/synth_ice40.cc
index 62589ad87..7c95588e4 100644
--- a/techlibs/ice40/synth_ice40.cc
+++ b/techlibs/ice40/synth_ice40.cc
@@ -37,9 +37,9 @@ struct SynthIce40Pass : public ScriptPass
 		log("\n");
 		log("This command runs synthesis for iCE40 FPGAs.\n");
 		log("\n");
-		log("    -device < hx1k | lp384 | lp1k | lp8k | hx8k | u4k | up5k >\n");
+		log("    -device < hx | lp | u >\n");
 		log("        optimise the synthesis netlist for the specified device.\n");
-		log("        HX1K is the default target if no device argument specified.\n");
+		log("        HX is the default target if no device argument specified.\n");
 		log("\n");
 		log("    -top <module>\n");
 		log("        use the specified module as top module\n");
@@ -128,7 +128,7 @@ struct SynthIce40Pass : public ScriptPass
 		abc2 = false;
 		vpr = false;
 		abc = "abc";
-		device_opt = "hx1k";
+		device_opt = "hx";
 	}
 
 	void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
@@ -225,7 +225,7 @@ struct SynthIce40Pass : public ScriptPass
 
 		if (!design->full_selection())
 			log_cmd_error("This command only operates on fully selected designs!\n");
-		if (device_opt != "hx1k" && device_opt !="lp384" && device_opt != "lp1k" && device_opt !="lp8k" && device_opt !="hx8k" && device_opt != "u4k" && device_opt != "up5k")
+		if (device_opt != "hx" && device_opt != "lp" && device_opt !="u")
 			log_cmd_error("Invalid or no device specified: '%s'\n", device_opt.c_str());
 
 		log_header(design, "Executing SYNTH_ICE40 pass.\n");
diff --git a/techlibs/ice40/u.box b/techlibs/ice40/u.box
new file mode 100644
index 000000000..94df1df8f
--- /dev/null
+++ b/techlibs/ice40/u.box
@@ -0,0 +1,13 @@
+# From https://github.com/cliffordwolf/icestorm/blob/be0bca0/icefuzz/timings_up5k.txt
+
+# NB: Inputs/Outputs must be ordered alphabetically
+
+# Inputs: CI I0 I1
+# Outputs: CO
+SB_CARRY 1 1 3 1
+278 675 609
+
+# Inputs: I0 I1 I2 I3
+# Outputs: O
+SB_LUT4 2 1 4 1
+1285 1231 1205 874
diff --git a/techlibs/ice40/u.lut b/techlibs/ice40/u.lut
new file mode 100644
index 000000000..1e4fcadb6
--- /dev/null
+++ b/techlibs/ice40/u.lut
@@ -0,0 +1,6 @@
+# From https://github.com/cliffordwolf/icestorm/blob/be0bca0/icefuzz/timings_up5k.txt
+#       I3  I2  I1  I0
+1   1   874
+2   1   874 1205
+3   1   874 1205 1231
+4   1   874 1205 1231 1285
diff --git a/techlibs/ice40/up5k.box b/techlibs/ice40/up5k.box
deleted file mode 100644
index 94df1df8f..000000000
--- a/techlibs/ice40/up5k.box
+++ /dev/null
@@ -1,13 +0,0 @@
-# From https://github.com/cliffordwolf/icestorm/blob/be0bca0/icefuzz/timings_up5k.txt
-
-# NB: Inputs/Outputs must be ordered alphabetically
-
-# Inputs: CI I0 I1
-# Outputs: CO
-SB_CARRY 1 1 3 1
-278 675 609
-
-# Inputs: I0 I1 I2 I3
-# Outputs: O
-SB_LUT4 2 1 4 1
-1285 1231 1205 874
diff --git a/techlibs/ice40/up5k.lut b/techlibs/ice40/up5k.lut
deleted file mode 100644
index 1e4fcadb6..000000000
--- a/techlibs/ice40/up5k.lut
+++ /dev/null
@@ -1,6 +0,0 @@
-# From https://github.com/cliffordwolf/icestorm/blob/be0bca0/icefuzz/timings_up5k.txt
-#       I3  I2  I1  I0
-1   1   874
-2   1   874 1205
-3   1   874 1205 1231
-4   1   874 1205 1231 1285
-- 
cgit v1.2.3


From 8fd455c91070e1e4cf05cbece79999fef04bb9b9 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Wed, 17 Apr 2019 15:19:48 -0700
Subject: Update Makefile.inc too

---
 techlibs/ice40/Makefile.inc | 10 ++++++----
 1 file changed, 6 insertions(+), 4 deletions(-)

(limited to 'techlibs/ice40')

diff --git a/techlibs/ice40/Makefile.inc b/techlibs/ice40/Makefile.inc
index efcea6e98..cb2121a11 100644
--- a/techlibs/ice40/Makefile.inc
+++ b/techlibs/ice40/Makefile.inc
@@ -29,10 +29,12 @@ $(eval $(call add_share_file,share/ice40,techlibs/ice40/latches_map.v))
 $(eval $(call add_share_file,share/ice40,techlibs/ice40/brams.txt))
 $(eval $(call add_share_file,share/ice40,techlibs/ice40/brams_map.v))
 $(eval $(call add_share_file,share/ice40,techlibs/ice40/abc.v))
-$(eval $(call add_share_file,share/ice40,techlibs/ice40/hx8k.box))
-$(eval $(call add_share_file,share/ice40,techlibs/ice40/hx8k.lut))
-$(eval $(call add_share_file,share/ice40,techlibs/ice40/up5k.box))
-$(eval $(call add_share_file,share/ice40,techlibs/ice40/up5k.lut))
+$(eval $(call add_share_file,share/ice40,techlibs/ice40/hx.box))
+$(eval $(call add_share_file,share/ice40,techlibs/ice40/hx.lut))
+$(eval $(call add_share_file,share/ice40,techlibs/ice40/lp.box))
+$(eval $(call add_share_file,share/ice40,techlibs/ice40/lp.lut))
+$(eval $(call add_share_file,share/ice40,techlibs/ice40/u.box))
+$(eval $(call add_share_file,share/ice40,techlibs/ice40/u.lut))
 
 $(eval $(call add_gen_share_file,share/ice40,techlibs/ice40/brams_init1.vh))
 $(eval $(call add_gen_share_file,share/ice40,techlibs/ice40/brams_init2.vh))
-- 
cgit v1.2.3


From ed5e75ed7d5a4515e23a496570c7eb03f48742b0 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Thu, 18 Apr 2019 09:02:58 -0700
Subject: Rename to abc_*.{box,lut}

---
 techlibs/ice40/abc_hx.box  | 13 +++++++++++++
 techlibs/ice40/abc_lp.box  | 13 +++++++++++++
 techlibs/ice40/abc_lp.lut  |  6 ++++++
 techlibs/ice40/abc_lut.box |  6 ++++++
 techlibs/ice40/abc_u.box   | 13 +++++++++++++
 techlibs/ice40/abc_u.lut   |  6 ++++++
 techlibs/ice40/hx.box      | 13 -------------
 techlibs/ice40/hx.lut      |  6 ------
 techlibs/ice40/lp.box      | 13 -------------
 techlibs/ice40/lp.lut      |  6 ------
 techlibs/ice40/u.box       | 13 -------------
 techlibs/ice40/u.lut       |  6 ------
 12 files changed, 57 insertions(+), 57 deletions(-)
 create mode 100644 techlibs/ice40/abc_hx.box
 create mode 100644 techlibs/ice40/abc_lp.box
 create mode 100644 techlibs/ice40/abc_lp.lut
 create mode 100644 techlibs/ice40/abc_lut.box
 create mode 100644 techlibs/ice40/abc_u.box
 create mode 100644 techlibs/ice40/abc_u.lut
 delete mode 100644 techlibs/ice40/hx.box
 delete mode 100644 techlibs/ice40/hx.lut
 delete mode 100644 techlibs/ice40/lp.box
 delete mode 100644 techlibs/ice40/lp.lut
 delete mode 100644 techlibs/ice40/u.box
 delete mode 100644 techlibs/ice40/u.lut

(limited to 'techlibs/ice40')

diff --git a/techlibs/ice40/abc_hx.box b/techlibs/ice40/abc_hx.box
new file mode 100644
index 000000000..c31f7bf39
--- /dev/null
+++ b/techlibs/ice40/abc_hx.box
@@ -0,0 +1,13 @@
+# From https://github.com/cliffordwolf/icestorm/blob/be0bca0/icefuzz/timings_hx8k.txt
+
+# NB: Inputs/Outputs must be ordered alphabetically
+
+# Inputs: CI I0 I1
+# Outputs: CO
+SB_CARRY 1 1 3 1
+126 259 231
+
+# Inputs: I0 I1 I2 I3
+# Outputs: O
+SB_LUT4 2 1 4 1
+449 400 379 316
diff --git a/techlibs/ice40/abc_lp.box b/techlibs/ice40/abc_lp.box
new file mode 100644
index 000000000..7eb8e86e0
--- /dev/null
+++ b/techlibs/ice40/abc_lp.box
@@ -0,0 +1,13 @@
+# From https://github.com/cliffordwolf/icestorm/blob/be0bca0/icefuzz/timings_lp8k.txt
+
+# NB: Inputs/Outputs must be ordered alphabetically
+
+# Inputs: CI I0 I1
+# Outputs: CO
+SB_CARRY 1 1 3 1
+186 675 609
+
+# Inputs: I0 I1 I2 I3
+# Outputs: O
+SB_LUT4 2 1 4 1
+465 558 589 661
diff --git a/techlibs/ice40/abc_lp.lut b/techlibs/ice40/abc_lp.lut
new file mode 100644
index 000000000..e72f760a2
--- /dev/null
+++ b/techlibs/ice40/abc_lp.lut
@@ -0,0 +1,6 @@
+# From https://github.com/cliffordwolf/icestorm/blob/be0bca0/icefuzz/timings_lp8k.txt
+#       I3  I2  I1  I0
+1   1   465
+2   1   465 558
+3   1   465 558 589
+4   1   465 558 589 661
diff --git a/techlibs/ice40/abc_lut.box b/techlibs/ice40/abc_lut.box
new file mode 100644
index 000000000..3b3bb11e2
--- /dev/null
+++ b/techlibs/ice40/abc_lut.box
@@ -0,0 +1,6 @@
+# From https://github.com/cliffordwolf/icestorm/blob/be0bca0/icefuzz/timings_hx8k.txt
+#       I3  I2  I1  I0
+1   1   316
+2   1   316 379
+3   1   316 379 400
+4   1   316 379 400 449
diff --git a/techlibs/ice40/abc_u.box b/techlibs/ice40/abc_u.box
new file mode 100644
index 000000000..94df1df8f
--- /dev/null
+++ b/techlibs/ice40/abc_u.box
@@ -0,0 +1,13 @@
+# From https://github.com/cliffordwolf/icestorm/blob/be0bca0/icefuzz/timings_up5k.txt
+
+# NB: Inputs/Outputs must be ordered alphabetically
+
+# Inputs: CI I0 I1
+# Outputs: CO
+SB_CARRY 1 1 3 1
+278 675 609
+
+# Inputs: I0 I1 I2 I3
+# Outputs: O
+SB_LUT4 2 1 4 1
+1285 1231 1205 874
diff --git a/techlibs/ice40/abc_u.lut b/techlibs/ice40/abc_u.lut
new file mode 100644
index 000000000..1e4fcadb6
--- /dev/null
+++ b/techlibs/ice40/abc_u.lut
@@ -0,0 +1,6 @@
+# From https://github.com/cliffordwolf/icestorm/blob/be0bca0/icefuzz/timings_up5k.txt
+#       I3  I2  I1  I0
+1   1   874
+2   1   874 1205
+3   1   874 1205 1231
+4   1   874 1205 1231 1285
diff --git a/techlibs/ice40/hx.box b/techlibs/ice40/hx.box
deleted file mode 100644
index c31f7bf39..000000000
--- a/techlibs/ice40/hx.box
+++ /dev/null
@@ -1,13 +0,0 @@
-# From https://github.com/cliffordwolf/icestorm/blob/be0bca0/icefuzz/timings_hx8k.txt
-
-# NB: Inputs/Outputs must be ordered alphabetically
-
-# Inputs: CI I0 I1
-# Outputs: CO
-SB_CARRY 1 1 3 1
-126 259 231
-
-# Inputs: I0 I1 I2 I3
-# Outputs: O
-SB_LUT4 2 1 4 1
-449 400 379 316
diff --git a/techlibs/ice40/hx.lut b/techlibs/ice40/hx.lut
deleted file mode 100644
index 3b3bb11e2..000000000
--- a/techlibs/ice40/hx.lut
+++ /dev/null
@@ -1,6 +0,0 @@
-# From https://github.com/cliffordwolf/icestorm/blob/be0bca0/icefuzz/timings_hx8k.txt
-#       I3  I2  I1  I0
-1   1   316
-2   1   316 379
-3   1   316 379 400
-4   1   316 379 400 449
diff --git a/techlibs/ice40/lp.box b/techlibs/ice40/lp.box
deleted file mode 100644
index 7eb8e86e0..000000000
--- a/techlibs/ice40/lp.box
+++ /dev/null
@@ -1,13 +0,0 @@
-# From https://github.com/cliffordwolf/icestorm/blob/be0bca0/icefuzz/timings_lp8k.txt
-
-# NB: Inputs/Outputs must be ordered alphabetically
-
-# Inputs: CI I0 I1
-# Outputs: CO
-SB_CARRY 1 1 3 1
-186 675 609
-
-# Inputs: I0 I1 I2 I3
-# Outputs: O
-SB_LUT4 2 1 4 1
-465 558 589 661
diff --git a/techlibs/ice40/lp.lut b/techlibs/ice40/lp.lut
deleted file mode 100644
index e72f760a2..000000000
--- a/techlibs/ice40/lp.lut
+++ /dev/null
@@ -1,6 +0,0 @@
-# From https://github.com/cliffordwolf/icestorm/blob/be0bca0/icefuzz/timings_lp8k.txt
-#       I3  I2  I1  I0
-1   1   465
-2   1   465 558
-3   1   465 558 589
-4   1   465 558 589 661
diff --git a/techlibs/ice40/u.box b/techlibs/ice40/u.box
deleted file mode 100644
index 94df1df8f..000000000
--- a/techlibs/ice40/u.box
+++ /dev/null
@@ -1,13 +0,0 @@
-# From https://github.com/cliffordwolf/icestorm/blob/be0bca0/icefuzz/timings_up5k.txt
-
-# NB: Inputs/Outputs must be ordered alphabetically
-
-# Inputs: CI I0 I1
-# Outputs: CO
-SB_CARRY 1 1 3 1
-278 675 609
-
-# Inputs: I0 I1 I2 I3
-# Outputs: O
-SB_LUT4 2 1 4 1
-1285 1231 1205 874
diff --git a/techlibs/ice40/u.lut b/techlibs/ice40/u.lut
deleted file mode 100644
index 1e4fcadb6..000000000
--- a/techlibs/ice40/u.lut
+++ /dev/null
@@ -1,6 +0,0 @@
-# From https://github.com/cliffordwolf/icestorm/blob/be0bca0/icefuzz/timings_up5k.txt
-#       I3  I2  I1  I0
-1   1   874
-2   1   874 1205
-3   1   874 1205 1231
-4   1   874 1205 1231 1285
-- 
cgit v1.2.3


From 8024f4189738af196f7ce432d95c73efd1f02955 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Thu, 18 Apr 2019 09:04:34 -0700
Subject: Fix rename

---
 techlibs/ice40/abc_hx.lut  | 6 ++++++
 techlibs/ice40/abc_lut.box | 6 ------
 2 files changed, 6 insertions(+), 6 deletions(-)
 create mode 100644 techlibs/ice40/abc_hx.lut
 delete mode 100644 techlibs/ice40/abc_lut.box

(limited to 'techlibs/ice40')

diff --git a/techlibs/ice40/abc_hx.lut b/techlibs/ice40/abc_hx.lut
new file mode 100644
index 000000000..3b3bb11e2
--- /dev/null
+++ b/techlibs/ice40/abc_hx.lut
@@ -0,0 +1,6 @@
+# From https://github.com/cliffordwolf/icestorm/blob/be0bca0/icefuzz/timings_hx8k.txt
+#       I3  I2  I1  I0
+1   1   316
+2   1   316 379
+3   1   316 379 400
+4   1   316 379 400 449
diff --git a/techlibs/ice40/abc_lut.box b/techlibs/ice40/abc_lut.box
deleted file mode 100644
index 3b3bb11e2..000000000
--- a/techlibs/ice40/abc_lut.box
+++ /dev/null
@@ -1,6 +0,0 @@
-# From https://github.com/cliffordwolf/icestorm/blob/be0bca0/icefuzz/timings_hx8k.txt
-#       I3  I2  I1  I0
-1   1   316
-2   1   316 379
-3   1   316 379 400
-4   1   316 379 400 449
-- 
cgit v1.2.3


From 7b6ab937c14ae30d331527c71dffbc050aaba13c Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Thu, 18 Apr 2019 09:05:22 -0700
Subject: Make SB_LUT4 a blackbox

---
 techlibs/ice40/abc_hx.box | 2 +-
 techlibs/ice40/abc_lp.box | 2 +-
 techlibs/ice40/abc_u.box  | 2 +-
 3 files changed, 3 insertions(+), 3 deletions(-)

(limited to 'techlibs/ice40')

diff --git a/techlibs/ice40/abc_hx.box b/techlibs/ice40/abc_hx.box
index c31f7bf39..5a18a8423 100644
--- a/techlibs/ice40/abc_hx.box
+++ b/techlibs/ice40/abc_hx.box
@@ -9,5 +9,5 @@ SB_CARRY 1 1 3 1
 
 # Inputs: I0 I1 I2 I3
 # Outputs: O
-SB_LUT4 2 1 4 1
+SB_LUT4 2 0 4 1
 449 400 379 316
diff --git a/techlibs/ice40/abc_lp.box b/techlibs/ice40/abc_lp.box
index 7eb8e86e0..87fe81585 100644
--- a/techlibs/ice40/abc_lp.box
+++ b/techlibs/ice40/abc_lp.box
@@ -9,5 +9,5 @@ SB_CARRY 1 1 3 1
 
 # Inputs: I0 I1 I2 I3
 # Outputs: O
-SB_LUT4 2 1 4 1
+SB_LUT4 2 0 4 1
 465 558 589 661
diff --git a/techlibs/ice40/abc_u.box b/techlibs/ice40/abc_u.box
index 94df1df8f..5035a4169 100644
--- a/techlibs/ice40/abc_u.box
+++ b/techlibs/ice40/abc_u.box
@@ -9,5 +9,5 @@ SB_CARRY 1 1 3 1
 
 # Inputs: I0 I1 I2 I3
 # Outputs: O
-SB_LUT4 2 1 4 1
+SB_LUT4 2 0 4 1
 1285 1231 1205 874
-- 
cgit v1.2.3


From 9278192efe5ae6382f4e011abaf417b45a6abfef Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Thu, 18 Apr 2019 09:58:34 -0700
Subject: Also update Makefile.inc

---
 techlibs/ice40/Makefile.inc | 13 ++++++-------
 1 file changed, 6 insertions(+), 7 deletions(-)

(limited to 'techlibs/ice40')

diff --git a/techlibs/ice40/Makefile.inc b/techlibs/ice40/Makefile.inc
index cb2121a11..d258d5a5d 100644
--- a/techlibs/ice40/Makefile.inc
+++ b/techlibs/ice40/Makefile.inc
@@ -28,13 +28,12 @@ $(eval $(call add_share_file,share/ice40,techlibs/ice40/cells_sim.v))
 $(eval $(call add_share_file,share/ice40,techlibs/ice40/latches_map.v))
 $(eval $(call add_share_file,share/ice40,techlibs/ice40/brams.txt))
 $(eval $(call add_share_file,share/ice40,techlibs/ice40/brams_map.v))
-$(eval $(call add_share_file,share/ice40,techlibs/ice40/abc.v))
-$(eval $(call add_share_file,share/ice40,techlibs/ice40/hx.box))
-$(eval $(call add_share_file,share/ice40,techlibs/ice40/hx.lut))
-$(eval $(call add_share_file,share/ice40,techlibs/ice40/lp.box))
-$(eval $(call add_share_file,share/ice40,techlibs/ice40/lp.lut))
-$(eval $(call add_share_file,share/ice40,techlibs/ice40/u.box))
-$(eval $(call add_share_file,share/ice40,techlibs/ice40/u.lut))
+$(eval $(call add_share_file,share/ice40,techlibs/ice40/abc_hx.box))
+$(eval $(call add_share_file,share/ice40,techlibs/ice40/abc_hx.lut))
+$(eval $(call add_share_file,share/ice40,techlibs/ice40/abc_lp.box))
+$(eval $(call add_share_file,share/ice40,techlibs/ice40/abc_lp.lut))
+$(eval $(call add_share_file,share/ice40,techlibs/ice40/abc_u.box))
+$(eval $(call add_share_file,share/ice40,techlibs/ice40/abc_u.lut))
 
 $(eval $(call add_gen_share_file,share/ice40,techlibs/ice40/brams_init1.vh))
 $(eval $(call add_gen_share_file,share/ice40,techlibs/ice40/brams_init2.vh))
-- 
cgit v1.2.3


From 4c327cf316404fbedb1d26b0aebecaaf01d46f6b Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Thu, 18 Apr 2019 10:32:41 -0700
Subject: Use new -wb flag for ABC flow

---
 techlibs/ice40/abc.v          | 12 ------------
 techlibs/ice40/cells_sim.v    |  2 ++
 techlibs/ice40/synth_ice40.cc | 10 +++-------
 3 files changed, 5 insertions(+), 19 deletions(-)
 delete mode 100644 techlibs/ice40/abc.v

(limited to 'techlibs/ice40')

diff --git a/techlibs/ice40/abc.v b/techlibs/ice40/abc.v
deleted file mode 100644
index e2a54a42c..000000000
--- a/techlibs/ice40/abc.v
+++ /dev/null
@@ -1,12 +0,0 @@
-(* abc_box_id = 1 *)
-module SB_CARRY (output CO, input CI, I0, I1);
-	assign CO = (I0 && I1) || ((I0 || I1) && CI);
-endmodule
-
-(* abc_box_id = 2 *)
-module SB_LUT4 (output O, input I0, I1, I2, I3);
-	parameter [15:0] LUT_INIT = 0;
-	// Indicate this is a black-box
-	assign O = 1'b0;
-endmodule
-
diff --git a/techlibs/ice40/cells_sim.v b/techlibs/ice40/cells_sim.v
index 70cd51ed1..dba563e37 100644
--- a/techlibs/ice40/cells_sim.v
+++ b/techlibs/ice40/cells_sim.v
@@ -118,6 +118,7 @@ endmodule
 
 // SiliconBlue Logic Cells
 
+(* abc_box_id = 2 *)
 module SB_LUT4 (output O, input I0, I1, I2, I3);
 	parameter [15:0] LUT_INIT = 0;
 	wire [7:0] s3 = I3 ? LUT_INIT[15:8] : LUT_INIT[7:0];
@@ -126,6 +127,7 @@ module SB_LUT4 (output O, input I0, I1, I2, I3);
 	assign O = I0 ? s1[1] : s1[0];
 endmodule
 
+(* abc_box_id = 1, whitebox *)
 module SB_CARRY (output CO, input I0, I1, CI);
 	assign CO = (I0 && I1) || ((I0 || I1) && CI);
 endmodule
diff --git a/techlibs/ice40/synth_ice40.cc b/techlibs/ice40/synth_ice40.cc
index 7c95588e4..84abf7181 100644
--- a/techlibs/ice40/synth_ice40.cc
+++ b/techlibs/ice40/synth_ice40.cc
@@ -240,7 +240,7 @@ struct SynthIce40Pass : public ScriptPass
 	{
 		if (check_label("begin"))
 		{
-			run("read_verilog -lib +/ice40/cells_sim.v");
+			run("read_verilog -wb +/ice40/cells_sim.v");
 			run(stringf("hierarchy -check %s", help_mode ? "-top <top>" : top_opt.c_str()));
 			run("proc");
 		}
@@ -327,12 +327,8 @@ struct SynthIce40Pass : public ScriptPass
 				run("techmap -map +/gate2lut.v -D LUT_WIDTH=4", "(only if -noabc)");
 			}
 			if (!noabc) {
-				if (abc == "abc9") {
-					run("read_verilog +/ice40/abc.v");
-					run("techmap -map +/techmap.v A:abc_box_id");
-					run(abc + stringf(" -dress -lut +/ice40/%s.lut -box +/ice40/%s.box", device_opt.c_str(), device_opt.c_str()), "(skip if -noabc)");
-					run("blackbox A:abc_box_id");
-				}
+				if (abc == "abc9")
+					run(abc + stringf(" -dress -lut +/ice40/abc_%s.lut -box +/ice40/abc_%s.box", device_opt.c_str(), device_opt.c_str()), "(skip if -noabc)");
 				else
 					run(abc + " -lut 4", "(skip if -noabc)");
 			}
-- 
cgit v1.2.3


From ca1eb98a975e1d95629f8e55bfdd021221edf0b7 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Thu, 18 Apr 2019 17:46:32 -0700
Subject: Add SB_DFF* to boxes

---
 techlibs/ice40/abc_hx.box | 104 +++++++++++++++++++++++++++++++++++++++++++++-
 techlibs/ice40/abc_lp.box | 104 +++++++++++++++++++++++++++++++++++++++++++++-
 techlibs/ice40/abc_u.box  | 104 +++++++++++++++++++++++++++++++++++++++++++++-
 3 files changed, 306 insertions(+), 6 deletions(-)

(limited to 'techlibs/ice40')

diff --git a/techlibs/ice40/abc_hx.box b/techlibs/ice40/abc_hx.box
index 5a18a8423..9ebdae18b 100644
--- a/techlibs/ice40/abc_hx.box
+++ b/techlibs/ice40/abc_hx.box
@@ -2,12 +2,112 @@
 
 # NB: Inputs/Outputs must be ordered alphabetically
 
+# Inputs: C D
+# Outputs: Q
+SB_DFF 1 0 2 1
+- -
+
+# Inputs: C D E
+# Outputs: Q
+SB_DFFE 2 0 3 1
+- - -
+
+# Inputs: C D R
+# Outputs: Q
+SB_DFFSR 3 0 3 1
+- - -
+
+# Inputs: C D R
+# Outputs: Q
+SB_DFFR 4 0 3 1
+- - -
+
+# Inputs: C D S
+# Outputs: Q
+SB_DFFSS 5 0 3 1
+- - -
+
+# Inputs: C D S
+# Outputs: Q
+SB_DFFS 6 0 3 1
+- - -
+
+# Inputs: C D E R
+# Outputs: Q
+SB_DFFESR 7 0 4 1
+- - - -
+
+# Inputs: C D E R
+# Outputs: Q
+SB_DFFER 8 0 4 1
+- - - -
+
+# Inputs: C D E S
+# Outputs: Q
+SB_DFFESS 9 0 4 1
+- - - -
+
+# Inputs: C D E S
+# Outputs: Q
+SB_DFFES 10 0 4 1
+- - - -
+
+# Inputs: C D
+# Outputs: Q
+SB_DFFN 11 0 2 1
+- -
+
+# Inputs: C D E
+# Outputs: Q
+SB_DFFNE 12 0 3 1
+- - -
+
+# Inputs: C D R
+# Outputs: Q
+SB_DFFNSR 13 0 3 1
+- - -
+
+# Inputs: C D R
+# Outputs: Q
+SB_DFFNR 14 0 3 1
+- - -
+
+# Inputs: C D S
+# Outputs: Q
+SB_DFFNSS 15 0 3 1
+- - -
+
+# Inputs: C D S
+# Outputs: Q
+SB_DFFNS 16 0 3 1
+- - -
+
+# Inputs: C D E R
+# Outputs: Q
+SB_DFFNESR 17 0 4 1
+- - - -
+
+# Inputs: C D E R
+# Outputs: Q
+SB_DFFNER 18 0 4 1
+- - - -
+
+# Inputs: C D E S
+# Outputs: Q
+SB_DFFNESS 19 0 4 1
+- - - -
+
+# Inputs: C D E S
+# Outputs: Q
+SB_DFFNES 20 0 4 1
+- - - -
+
 # Inputs: CI I0 I1
 # Outputs: CO
-SB_CARRY 1 1 3 1
+SB_CARRY 21 1 3 1
 126 259 231
 
 # Inputs: I0 I1 I2 I3
 # Outputs: O
-SB_LUT4 2 0 4 1
+SB_LUT4 22 0 4 1
 449 400 379 316
diff --git a/techlibs/ice40/abc_lp.box b/techlibs/ice40/abc_lp.box
index 87fe81585..464821dac 100644
--- a/techlibs/ice40/abc_lp.box
+++ b/techlibs/ice40/abc_lp.box
@@ -2,12 +2,112 @@
 
 # NB: Inputs/Outputs must be ordered alphabetically
 
+# Inputs: C D
+# Outputs: Q
+SB_DFF 1 0 2 1
+- -
+
+# Inputs: C D E
+# Outputs: Q
+SB_DFFE 2 0 3 1
+- - -
+
+# Inputs: C D R
+# Outputs: Q
+SB_DFFSR 3 0 3 1
+- - -
+
+# Inputs: C D R
+# Outputs: Q
+SB_DFFR 4 0 3 1
+- - -
+
+# Inputs: C D S
+# Outputs: Q
+SB_DFFSS 5 0 3 1
+- - -
+
+# Inputs: C D S
+# Outputs: Q
+SB_DFFS 6 0 3 1
+- - -
+
+# Inputs: C D E R
+# Outputs: Q
+SB_DFFESR 7 0 4 1
+- - - -
+
+# Inputs: C D E R
+# Outputs: Q
+SB_DFFER 8 0 4 1
+- - - -
+
+# Inputs: C D E S
+# Outputs: Q
+SB_DFFESS 9 0 4 1
+- - - -
+
+# Inputs: C D E S
+# Outputs: Q
+SB_DFFES 10 0 4 1
+- - - -
+
+# Inputs: C D
+# Outputs: Q
+SB_DFFN 11 0 2 1
+- -
+
+# Inputs: C D E
+# Outputs: Q
+SB_DFFNE 12 0 3 1
+- - -
+
+# Inputs: C D R
+# Outputs: Q
+SB_DFFNSR 13 0 3 1
+- - -
+
+# Inputs: C D R
+# Outputs: Q
+SB_DFFNR 14 0 3 1
+- - -
+
+# Inputs: C D S
+# Outputs: Q
+SB_DFFNSS 15 0 3 1
+- - -
+
+# Inputs: C D S
+# Outputs: Q
+SB_DFFNS 16 0 3 1
+- - -
+
+# Inputs: C D E R
+# Outputs: Q
+SB_DFFNESR 17 0 4 1
+- - - -
+
+# Inputs: C D E R
+# Outputs: Q
+SB_DFFNER 18 0 4 1
+- - - -
+
+# Inputs: C D E S
+# Outputs: Q
+SB_DFFNESS 19 0 4 1
+- - - -
+
+# Inputs: C D E S
+# Outputs: Q
+SB_DFFNES 20 0 4 1
+- - - -
+
 # Inputs: CI I0 I1
 # Outputs: CO
-SB_CARRY 1 1 3 1
+SB_CARRY 21 1 3 1
 186 675 609
 
 # Inputs: I0 I1 I2 I3
 # Outputs: O
-SB_LUT4 2 0 4 1
+SB_LUT4 22 0 4 1
 465 558 589 661
diff --git a/techlibs/ice40/abc_u.box b/techlibs/ice40/abc_u.box
index 5035a4169..314bff401 100644
--- a/techlibs/ice40/abc_u.box
+++ b/techlibs/ice40/abc_u.box
@@ -2,12 +2,112 @@
 
 # NB: Inputs/Outputs must be ordered alphabetically
 
+# Inputs: C D
+# Outputs: Q
+SB_DFF 1 0 2 1
+- -
+
+# Inputs: C D E
+# Outputs: Q
+SB_DFFE 2 0 3 1
+- - -
+
+# Inputs: C D R
+# Outputs: Q
+SB_DFFSR 3 0 3 1
+- - -
+
+# Inputs: C D R
+# Outputs: Q
+SB_DFFR 4 0 3 1
+- - -
+
+# Inputs: C D S
+# Outputs: Q
+SB_DFFSS 5 0 3 1
+- - -
+
+# Inputs: C D S
+# Outputs: Q
+SB_DFFS 6 0 3 1
+- - -
+
+# Inputs: C D E R
+# Outputs: Q
+SB_DFFESR 7 0 4 1
+- - - -
+
+# Inputs: C D E R
+# Outputs: Q
+SB_DFFER 8 0 4 1
+- - - -
+
+# Inputs: C D E S
+# Outputs: Q
+SB_DFFESS 9 0 4 1
+- - - -
+
+# Inputs: C D E S
+# Outputs: Q
+SB_DFFES 10 0 4 1
+- - - -
+
+# Inputs: C D
+# Outputs: Q
+SB_DFFN 11 0 2 1
+- -
+
+# Inputs: C D E
+# Outputs: Q
+SB_DFFNE 12 0 3 1
+- - -
+
+# Inputs: C D R
+# Outputs: Q
+SB_DFFNSR 13 0 3 1
+- - -
+
+# Inputs: C D R
+# Outputs: Q
+SB_DFFNR 14 0 3 1
+- - -
+
+# Inputs: C D S
+# Outputs: Q
+SB_DFFNSS 15 0 3 1
+- - -
+
+# Inputs: C D S
+# Outputs: Q
+SB_DFFNS 16 0 3 1
+- - -
+
+# Inputs: C D E R
+# Outputs: Q
+SB_DFFNESR 17 0 4 1
+- - - -
+
+# Inputs: C D E R
+# Outputs: Q
+SB_DFFNER 18 0 4 1
+- - - -
+
+# Inputs: C D E S
+# Outputs: Q
+SB_DFFNESS 19 0 4 1
+- - - -
+
+# Inputs: C D E S
+# Outputs: Q
+SB_DFFNES 20 0 4 1
+- - - -
+
 # Inputs: CI I0 I1
 # Outputs: CO
-SB_CARRY 1 1 3 1
+SB_CARRY 21 1 3 1
 278 675 609
 
 # Inputs: I0 I1 I2 I3
 # Outputs: O
-SB_LUT4 2 0 4 1
+SB_LUT4 22 0 4 1
 1285 1231 1205 874
-- 
cgit v1.2.3


From cf66416110f60b7dce10a78960898ceb52f51626 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Thu, 18 Apr 2019 17:46:53 -0700
Subject: Annotate SB_DFF* with abc_flop and abc_box_id

---
 techlibs/ice40/cells_sim.v | 71 ++++++++++++++++++++++++++++++++--------------
 1 file changed, 49 insertions(+), 22 deletions(-)

(limited to 'techlibs/ice40')

diff --git a/techlibs/ice40/cells_sim.v b/techlibs/ice40/cells_sim.v
index dba563e37..a6f1fc9de 100644
--- a/techlibs/ice40/cells_sim.v
+++ b/techlibs/ice40/cells_sim.v
@@ -118,7 +118,7 @@ endmodule
 
 // SiliconBlue Logic Cells
 
-(* abc_box_id = 2 *)
+(* abc_box_id = 22 *
 module SB_LUT4 (output O, input I0, I1, I2, I3);
 	parameter [15:0] LUT_INIT = 0;
 	wire [7:0] s3 = I3 ? LUT_INIT[15:8] : LUT_INIT[7:0];
@@ -127,25 +127,35 @@ module SB_LUT4 (output O, input I0, I1, I2, I3);
 	assign O = I0 ? s1[1] : s1[0];
 endmodule
 
-(* abc_box_id = 1, whitebox *)
+(* abc_box_id = 21, whitebox *)
 module SB_CARRY (output CO, input I0, I1, CI);
 	assign CO = (I0 && I1) || ((I0 || I1) && CI);
 endmodule
 
 // Positive Edge SiliconBlue FF Cells
 
-module SB_DFF ((* abc_flop_q *) output `SB_DFF_REG, input C, D);
+(* abc_box_id = 1, abc_flop *)
+`ifdef ABC_FLOPS
+    (* whitebox *)
+`endif
+module SB_DFF ((* abc_flop_q *) output `SB_DFF_REG, input C, (* abc_flop_d *) input D);
+`ifndef ABC_FLOPS
 	always @(posedge C)
 		Q <= D;
+`else
+    assign Q = D;
+`endif
 endmodule
 
-module SB_DFFE ((* abc_flop_q *) output `SB_DFF_REG, input C, E, D);
+//(* abc_box_id = 2, abc_flop *)
+module SB_DFFE ((* abc_flop_q *) output `SB_DFF_REG, input C, E, (* abc_flop_d *) input D);
 	always @(posedge C)
 		if (E)
 			Q <= D;
 endmodule
 
-module SB_DFFSR ((* abc_flop_q *) output `SB_DFF_REG, input C, R, D);
+//(* abc_box_id = 3, abc_flop *)
+module SB_DFFSR ((* abc_flop_q *) output `SB_DFF_REG, input C, R, (* abc_flop_d *) input D);
 	always @(posedge C)
 		if (R)
 			Q <= 0;
@@ -153,7 +163,8 @@ module SB_DFFSR ((* abc_flop_q *) output `SB_DFF_REG, input C, R, D);
 			Q <= D;
 endmodule
 
-module SB_DFFR ((* abc_flop_q *) output `SB_DFF_REG, input C, R, D);
+//(* abc_box_id = 4, abc_flop *)
+module SB_DFFR ((* abc_flop_q *) output `SB_DFF_REG, input C, R, (* abc_flop_d *) input D);
 	always @(posedge C, posedge R)
 		if (R)
 			Q <= 0;
@@ -161,7 +172,8 @@ module SB_DFFR ((* abc_flop_q *) output `SB_DFF_REG, input C, R, D);
 			Q <= D;
 endmodule
 
-module SB_DFFSS ((* abc_flop_q *) output `SB_DFF_REG, input C, S, D);
+//(* abc_box_id = 5, abc_flop *)
+module SB_DFFSS ((* abc_flop_q *) output `SB_DFF_REG, input C, S, (* abc_flop_d *) input D);
 	always @(posedge C)
 		if (S)
 			Q <= 1;
@@ -169,7 +181,8 @@ module SB_DFFSS ((* abc_flop_q *) output `SB_DFF_REG, input C, S, D);
 			Q <= D;
 endmodule
 
-module SB_DFFS ((* abc_flop_q *) output `SB_DFF_REG, input C, S, D);
+//(* abc_box_id = 6, abc_flop *)
+module SB_DFFS ((* abc_flop_q *) output `SB_DFF_REG, input C, S, (* abc_flop_d *) input D);
 	always @(posedge C, posedge S)
 		if (S)
 			Q <= 1;
@@ -177,7 +190,8 @@ module SB_DFFS ((* abc_flop_q *) output `SB_DFF_REG, input C, S, D);
 			Q <= D;
 endmodule
 
-module SB_DFFESR ((* abc_flop_q *) output `SB_DFF_REG, input C, E, R, D);
+//(* abc_box_id = 7, abc_flop *)
+module SB_DFFESR ((* abc_flop_q *) output `SB_DFF_REG, input C, E, R, (* abc_flop_d *) input D);
 	always @(posedge C)
 		if (E) begin
 			if (R)
@@ -187,7 +201,8 @@ module SB_DFFESR ((* abc_flop_q *) output `SB_DFF_REG, input C, E, R, D);
 		end
 endmodule
 
-module SB_DFFER ((* abc_flop_q *) output `SB_DFF_REG, input C, E, R, D);
+//(* abc_box_id = 8, abc_flop *)
+module SB_DFFER ((* abc_flop_q *) output `SB_DFF_REG, input C, E, R, (* abc_flop_d *) input D);
 	always @(posedge C, posedge R)
 		if (R)
 			Q <= 0;
@@ -195,7 +210,8 @@ module SB_DFFER ((* abc_flop_q *) output `SB_DFF_REG, input C, E, R, D);
 			Q <= D;
 endmodule
 
-module SB_DFFESS ((* abc_flop_q *) output `SB_DFF_REG, input C, E, S, D);
+//(* abc_box_id = 9, abc_flop *)
+module SB_DFFESS ((* abc_flop_q *) output `SB_DFF_REG, input C, E, S, (* abc_flop_d *) input D);
 	always @(posedge C)
 		if (E) begin
 			if (S)
@@ -205,7 +221,8 @@ module SB_DFFESS ((* abc_flop_q *) output `SB_DFF_REG, input C, E, S, D);
 		end
 endmodule
 
-module SB_DFFES ((* abc_flop_q *) output `SB_DFF_REG, input C, E, S, D);
+//(* abc_box_id = 10, abc_flop *)
+module SB_DFFES ((* abc_flop_q *) output `SB_DFF_REG, input C, E, S, (* abc_flop_d *) input D);
 	always @(posedge C, posedge S)
 		if (S)
 			Q <= 1;
@@ -215,18 +232,21 @@ endmodule
 
 // Negative Edge SiliconBlue FF Cells
 
-module SB_DFFN ((* abc_flop_q *) output `SB_DFF_REG, input C, D);
+//(* abc_box_id = 11, abc_flop *)
+module SB_DFFN ((* abc_flop_q *) output `SB_DFF_REG, input C, (* abc_flop_d *) input D);
 	always @(negedge C)
 		Q <= D;
 endmodule
 
-module SB_DFFNE ((* abc_flop_q *) output `SB_DFF_REG, input C, E, D);
+//(* abc_box_id = 12, abc_flop *)
+module SB_DFFNE ((* abc_flop_q *) output `SB_DFF_REG, input C, E, (* abc_flop_d *) input D);
 	always @(negedge C)
 		if (E)
 			Q <= D;
 endmodule
 
-module SB_DFFNSR ((* abc_flop_q *) output `SB_DFF_REG, input C, R, D);
+//(* abc_box_id = 13, abc_flop *)
+module SB_DFFNSR ((* abc_flop_q *) output `SB_DFF_REG, input C, R, (* abc_flop_d *) input D);
 	always @(negedge C)
 		if (R)
 			Q <= 0;
@@ -234,7 +254,8 @@ module SB_DFFNSR ((* abc_flop_q *) output `SB_DFF_REG, input C, R, D);
 			Q <= D;
 endmodule
 
-module SB_DFFNR ((* abc_flop_q *) output `SB_DFF_REG, input C, R, D);
+//(* abc_box_id = 14, abc_flop *)
+module SB_DFFNR ((* abc_flop_q *) output `SB_DFF_REG, input C, R, (* abc_flop_d *) input D);
 	always @(negedge C, posedge R)
 		if (R)
 			Q <= 0;
@@ -242,7 +263,8 @@ module SB_DFFNR ((* abc_flop_q *) output `SB_DFF_REG, input C, R, D);
 			Q <= D;
 endmodule
 
-module SB_DFFNSS ((* abc_flop_q *) output `SB_DFF_REG, input C, S, D);
+//(* abc_box_id = 15, abc_flop *)
+module SB_DFFNSS ((* abc_flop_q *) output `SB_DFF_REG, input C, S, (* abc_flop_d *) input D);
 	always @(negedge C)
 		if (S)
 			Q <= 1;
@@ -250,7 +272,8 @@ module SB_DFFNSS ((* abc_flop_q *) output `SB_DFF_REG, input C, S, D);
 			Q <= D;
 endmodule
 
-module SB_DFFNS ((* abc_flop_q *) output `SB_DFF_REG, input C, S, D);
+//(* abc_box_id = 16, abc_flop *)
+module SB_DFFNS ((* abc_flop_q *) output `SB_DFF_REG, input C, S, (* abc_flop_d *) input D);
 	always @(negedge C, posedge S)
 		if (S)
 			Q <= 1;
@@ -258,7 +281,8 @@ module SB_DFFNS ((* abc_flop_q *) output `SB_DFF_REG, input C, S, D);
 			Q <= D;
 endmodule
 
-module SB_DFFNESR ((* abc_flop_q *) output `SB_DFF_REG, input C, E, R, D);
+//(* abc_box_id = 17, abc_flop *)
+module SB_DFFNESR ((* abc_flop_q *) output `SB_DFF_REG, input C, E, R, (* abc_flop_d *) input D);
 	always @(negedge C)
 		if (E) begin
 			if (R)
@@ -268,7 +292,8 @@ module SB_DFFNESR ((* abc_flop_q *) output `SB_DFF_REG, input C, E, R, D);
 		end
 endmodule
 
-module SB_DFFNER ((* abc_flop_q *) output `SB_DFF_REG, input C, E, R, D);
+//(* abc_box_id = 18, abc_flop *)
+module SB_DFFNER ((* abc_flop_q *) output `SB_DFF_REG, input C, E, R, (* abc_flop_d *) input D);
 	always @(negedge C, posedge R)
 		if (R)
 			Q <= 0;
@@ -276,7 +301,8 @@ module SB_DFFNER ((* abc_flop_q *) output `SB_DFF_REG, input C, E, R, D);
 			Q <= D;
 endmodule
 
-module SB_DFFNESS ((* abc_flop_q *) output `SB_DFF_REG, input C, E, S, D);
+//(* abc_box_id = 19, abc_flop *)
+module SB_DFFNESS ((* abc_flop_q *) output `SB_DFF_REG, input C, E, S, (* abc_flop_d *) input D);
 	always @(negedge C)
 		if (E) begin
 			if (S)
@@ -286,7 +312,8 @@ module SB_DFFNESS ((* abc_flop_q *) output `SB_DFF_REG, input C, E, S, D);
 		end
 endmodule
 
-module SB_DFFNES ((* abc_flop_q *) output `SB_DFF_REG, input C, E, S, D);
+//(* abc_box_id = 20, abc_flop *)
+module SB_DFFNES ((* abc_flop_q *) output `SB_DFF_REG, input C, E, S, (* abc_flop_d *) input D);
 	always @(negedge C, posedge S)
 		if (S)
 			Q <= 1;
-- 
cgit v1.2.3


From 0919f36b88bed88e6dbfa23381540dc8ee035962 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Thu, 18 Apr 2019 17:50:11 -0700
Subject: Missing close bracket

---
 techlibs/ice40/cells_sim.v | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'techlibs/ice40')

diff --git a/techlibs/ice40/cells_sim.v b/techlibs/ice40/cells_sim.v
index a6f1fc9de..1d104c5d7 100644
--- a/techlibs/ice40/cells_sim.v
+++ b/techlibs/ice40/cells_sim.v
@@ -118,7 +118,7 @@ endmodule
 
 // SiliconBlue Logic Cells
 
-(* abc_box_id = 22 *
+(* abc_box_id = 22 *)
 module SB_LUT4 (output O, input I0, I1, I2, I3);
 	parameter [15:0] LUT_INIT = 0;
 	wire [7:0] s3 = I3 ? LUT_INIT[15:8] : LUT_INIT[7:0];
-- 
cgit v1.2.3


From 19b660ff6e8b493ff3de43ce59e393c56b9a6b3b Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Thu, 18 Apr 2019 23:07:16 -0700
Subject: Fix SB_DFF comb model

---
 techlibs/ice40/cells_sim.v    | 2 +-
 techlibs/ice40/synth_ice40.cc | 4 ++--
 2 files changed, 3 insertions(+), 3 deletions(-)

(limited to 'techlibs/ice40')

diff --git a/techlibs/ice40/cells_sim.v b/techlibs/ice40/cells_sim.v
index 1d104c5d7..c49b29ab3 100644
--- a/techlibs/ice40/cells_sim.v
+++ b/techlibs/ice40/cells_sim.v
@@ -143,7 +143,7 @@ module SB_DFF ((* abc_flop_q *) output `SB_DFF_REG, input C, (* abc_flop_d *) in
 	always @(posedge C)
 		Q <= D;
 `else
-    assign Q = D;
+    always @* Q = D;
 `endif
 endmodule
 
diff --git a/techlibs/ice40/synth_ice40.cc b/techlibs/ice40/synth_ice40.cc
index 84abf7181..d5d354701 100644
--- a/techlibs/ice40/synth_ice40.cc
+++ b/techlibs/ice40/synth_ice40.cc
@@ -240,7 +240,7 @@ struct SynthIce40Pass : public ScriptPass
 	{
 		if (check_label("begin"))
 		{
-			run("read_verilog -wb +/ice40/cells_sim.v");
+			run("read_verilog -wb -D ABC_FLOPS +/ice40/cells_sim.v");
 			run(stringf("hierarchy -check %s", help_mode ? "-top <top>" : top_opt.c_str()));
 			run("proc");
 		}
@@ -293,7 +293,7 @@ struct SynthIce40Pass : public ScriptPass
 				run("techmap");
 			else
 				run("techmap -map +/techmap.v -map +/ice40/arith_map.v");
-			if (retime || help_mode)
+			if ((retime || help_mode) && abc != "abc9")
 				run(abc + " -dff", "(only if -retime)");
 			run("ice40_opt");
 		}
-- 
cgit v1.2.3


From 2776925bcf04e67d1c33812e102d1195dca393bf Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Fri, 19 Apr 2019 08:36:38 -0700
Subject: Make SB_DFF whitebox

---
 techlibs/ice40/abc_hx.box | 2 +-
 techlibs/ice40/abc_lp.box | 2 +-
 techlibs/ice40/abc_u.box  | 2 +-
 3 files changed, 3 insertions(+), 3 deletions(-)

(limited to 'techlibs/ice40')

diff --git a/techlibs/ice40/abc_hx.box b/techlibs/ice40/abc_hx.box
index 9ebdae18b..994f3091d 100644
--- a/techlibs/ice40/abc_hx.box
+++ b/techlibs/ice40/abc_hx.box
@@ -4,7 +4,7 @@
 
 # Inputs: C D
 # Outputs: Q
-SB_DFF 1 0 2 1
+SB_DFF 1 1 2 1
 - -
 
 # Inputs: C D E
diff --git a/techlibs/ice40/abc_lp.box b/techlibs/ice40/abc_lp.box
index 464821dac..002b7bba4 100644
--- a/techlibs/ice40/abc_lp.box
+++ b/techlibs/ice40/abc_lp.box
@@ -4,7 +4,7 @@
 
 # Inputs: C D
 # Outputs: Q
-SB_DFF 1 0 2 1
+SB_DFF 1 1 2 1
 - -
 
 # Inputs: C D E
diff --git a/techlibs/ice40/abc_u.box b/techlibs/ice40/abc_u.box
index 314bff401..cb336181c 100644
--- a/techlibs/ice40/abc_u.box
+++ b/techlibs/ice40/abc_u.box
@@ -4,7 +4,7 @@
 
 # Inputs: C D
 # Outputs: Q
-SB_DFF 1 0 2 1
+SB_DFF 1 1 2 1
 - -
 
 # Inputs: C D E
-- 
cgit v1.2.3


From af4652522fd01aaec84664e65d7fe1474c578c49 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Fri, 19 Apr 2019 21:09:55 -0700
Subject: ABC_FLOPS -> ABC_MODEL -- only whitebox if ABC_MODEL set

---
 techlibs/ice40/cells_sim.v    | 9 ++++++---
 techlibs/ice40/synth_ice40.cc | 2 +-
 2 files changed, 7 insertions(+), 4 deletions(-)

(limited to 'techlibs/ice40')

diff --git a/techlibs/ice40/cells_sim.v b/techlibs/ice40/cells_sim.v
index c49b29ab3..a98bc30d9 100644
--- a/techlibs/ice40/cells_sim.v
+++ b/techlibs/ice40/cells_sim.v
@@ -127,7 +127,10 @@ module SB_LUT4 (output O, input I0, I1, I2, I3);
 	assign O = I0 ? s1[1] : s1[0];
 endmodule
 
-(* abc_box_id = 21, whitebox *)
+(* abc_box_id = 21 *)
+`ifdef ABC_MODEL
+    (* whitebox *)
+`endif
 module SB_CARRY (output CO, input I0, I1, CI);
 	assign CO = (I0 && I1) || ((I0 || I1) && CI);
 endmodule
@@ -135,11 +138,11 @@ endmodule
 // Positive Edge SiliconBlue FF Cells
 
 (* abc_box_id = 1, abc_flop *)
-`ifdef ABC_FLOPS
+`ifdef ABC_MODEL
     (* whitebox *)
 `endif
 module SB_DFF ((* abc_flop_q *) output `SB_DFF_REG, input C, (* abc_flop_d *) input D);
-`ifndef ABC_FLOPS
+`ifndef ABC_MODEL
 	always @(posedge C)
 		Q <= D;
 `else
diff --git a/techlibs/ice40/synth_ice40.cc b/techlibs/ice40/synth_ice40.cc
index d5d354701..7cedecdff 100644
--- a/techlibs/ice40/synth_ice40.cc
+++ b/techlibs/ice40/synth_ice40.cc
@@ -240,7 +240,7 @@ struct SynthIce40Pass : public ScriptPass
 	{
 		if (check_label("begin"))
 		{
-			run("read_verilog -wb -D ABC_FLOPS +/ice40/cells_sim.v");
+			run("read_verilog -wb -D ABC_MODEL +/ice40/cells_sim.v");
 			run(stringf("hierarchy -check %s", help_mode ? "-top <top>" : top_opt.c_str()));
 			run("proc");
 		}
-- 
cgit v1.2.3


From 71da8363008159fed399ec74318d83e34642d1f2 Mon Sep 17 00:00:00 2001
From: Luke Wren <wren6991@gmail.com>
Date: Wed, 17 Apr 2019 22:56:41 +0100
Subject: ice40 cells_sim.v: SB_IO: update clock enable behaviour based on
 hardware experiments

---
 techlibs/ice40/cells_sim.v | 29 +++++++++++++++++++----------
 1 file changed, 19 insertions(+), 10 deletions(-)

(limited to 'techlibs/ice40')

diff --git a/techlibs/ice40/cells_sim.v b/techlibs/ice40/cells_sim.v
index 62a28364b..00843b97c 100644
--- a/techlibs/ice40/cells_sim.v
+++ b/techlibs/ice40/cells_sim.v
@@ -27,18 +27,27 @@ module SB_IO (
 	reg dout_q_0, dout_q_1;
 	reg outena_q;
 
+	// IO tile generates a constant 1'b1 internally if global_cen is not connected
+	wire clken_pulled = CLOCK_ENABLE || CLOCK_ENABLE === 1'bz;
+	reg  clken_pulled_ri;
+	reg  clken_pulled_ro;
+
 	generate if (!NEG_TRIGGER) begin
-		always @(posedge INPUT_CLK)  if (CLOCK_ENABLE) din_q_0  <= PACKAGE_PIN;
-		always @(negedge INPUT_CLK)  if (CLOCK_ENABLE) din_q_1  <= PACKAGE_PIN;
-		always @(posedge OUTPUT_CLK) if (CLOCK_ENABLE) dout_q_0 <= D_OUT_0;
-		always @(negedge OUTPUT_CLK) if (CLOCK_ENABLE) dout_q_1 <= D_OUT_1;
-		always @(posedge OUTPUT_CLK) if (CLOCK_ENABLE) outena_q <= OUTPUT_ENABLE;
+		always @(posedge INPUT_CLK)                       clken_pulled_ri <= clken_pulled;
+		always @(posedge INPUT_CLK)  if (clken_pulled)    din_q_0         <= PACKAGE_PIN;
+		always @(negedge INPUT_CLK)  if (clken_pulled_ri) din_q_1         <= PACKAGE_PIN;
+		always @(posedge OUTPUT_CLK)                      clken_pulled_ro <= clken_pulled;
+		always @(posedge OUTPUT_CLK) if (clken_pulled)    dout_q_0        <= D_OUT_0;
+		always @(negedge OUTPUT_CLK) if (clken_pulled_ro) dout_q_1        <= D_OUT_1;
+		always @(posedge OUTPUT_CLK) if (clken_pulled)    outena_q        <= OUTPUT_ENABLE;
 	end else begin
-		always @(negedge INPUT_CLK)  if (CLOCK_ENABLE) din_q_0  <= PACKAGE_PIN;
-		always @(posedge INPUT_CLK)  if (CLOCK_ENABLE) din_q_1  <= PACKAGE_PIN;
-		always @(negedge OUTPUT_CLK) if (CLOCK_ENABLE) dout_q_0 <= D_OUT_0;
-		always @(posedge OUTPUT_CLK) if (CLOCK_ENABLE) dout_q_1 <= D_OUT_1;
-		always @(negedge OUTPUT_CLK) if (CLOCK_ENABLE) outena_q <= OUTPUT_ENABLE;
+		always @(negedge INPUT_CLK)                       clken_pulled_ri <= clken_pulled;
+		always @(negedge INPUT_CLK)  if (clken_pulled)    din_q_0         <= PACKAGE_PIN;
+		always @(posedge INPUT_CLK)  if (clken_pulled_ri) din_q_1         <= PACKAGE_PIN;
+		always @(negedge OUTPUT_CLK)                      clken_pulled_ro <= clken_pulled;
+		always @(negedge OUTPUT_CLK) if (clken_pulled)    dout_q_0        <= D_OUT_0;
+		always @(posedge OUTPUT_CLK) if (clken_pulled_ro) dout_q_1        <= D_OUT_1;
+		always @(negedge OUTPUT_CLK) if (clken_pulled)    outena_q        <= OUTPUT_ENABLE;
 	end endgenerate
 
 	always @* begin
-- 
cgit v1.2.3


From d7f0700bae9785a55353ca76fe9f354ee4ffe03e Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Sun, 21 Apr 2019 15:19:02 -0700
Subject: Convert to use #945

---
 techlibs/ice40/cells_sim.v    | 10 ++--------
 techlibs/ice40/synth_ice40.cc |  2 +-
 2 files changed, 3 insertions(+), 9 deletions(-)

(limited to 'techlibs/ice40')

diff --git a/techlibs/ice40/cells_sim.v b/techlibs/ice40/cells_sim.v
index a98bc30d9..93d970762 100644
--- a/techlibs/ice40/cells_sim.v
+++ b/techlibs/ice40/cells_sim.v
@@ -127,20 +127,14 @@ module SB_LUT4 (output O, input I0, I1, I2, I3);
 	assign O = I0 ? s1[1] : s1[0];
 endmodule
 
-(* abc_box_id = 21 *)
-`ifdef ABC_MODEL
-    (* whitebox *)
-`endif
+(* abc_box_id = 21, lib_whitebox *)
 module SB_CARRY (output CO, input I0, I1, CI);
 	assign CO = (I0 && I1) || ((I0 || I1) && CI);
 endmodule
 
 // Positive Edge SiliconBlue FF Cells
 
-(* abc_box_id = 1, abc_flop *)
-`ifdef ABC_MODEL
-    (* whitebox *)
-`endif
+(* abc_box_id = 1, abc_flop, lib_whitebox *)
 module SB_DFF ((* abc_flop_q *) output `SB_DFF_REG, input C, (* abc_flop_d *) input D);
 `ifndef ABC_MODEL
 	always @(posedge C)
diff --git a/techlibs/ice40/synth_ice40.cc b/techlibs/ice40/synth_ice40.cc
index 7cedecdff..718f9d9e0 100644
--- a/techlibs/ice40/synth_ice40.cc
+++ b/techlibs/ice40/synth_ice40.cc
@@ -240,7 +240,7 @@ struct SynthIce40Pass : public ScriptPass
 	{
 		if (check_label("begin"))
 		{
-			run("read_verilog -wb -D ABC_MODEL +/ice40/cells_sim.v");
+			run("read_verilog -lib -D ABC_MODEL +/ice40/cells_sim.v");
 			run(stringf("hierarchy -check %s", help_mode ? "-top <top>" : top_opt.c_str()));
 			run("proc");
 		}
-- 
cgit v1.2.3


From 91c3afcab723d85d3c6931561cb13ad7b70e7e5c Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Tue, 23 Apr 2019 13:42:06 -0700
Subject: Use nonblocking

---
 techlibs/ice40/cells_sim.v | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'techlibs/ice40')

diff --git a/techlibs/ice40/cells_sim.v b/techlibs/ice40/cells_sim.v
index 40e54f9f0..40972766d 100644
--- a/techlibs/ice40/cells_sim.v
+++ b/techlibs/ice40/cells_sim.v
@@ -149,7 +149,7 @@ module SB_DFF ((* abc_flop_q *) output `SB_DFF_REG, input C, (* abc_flop_d *) in
 	always @(posedge C)
 		Q <= D;
 `else
-    always @* Q = D;
+    always @* Q <= D;
 `endif
 endmodule
 
-- 
cgit v1.2.3


From 1ea6d7920f14dc07b97adf48b166216d2be171d3 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Fri, 26 Apr 2019 14:31:59 -0700
Subject: Cleanup ice40

---
 techlibs/ice40/synth_ice40.cc | 10 ++++++----
 1 file changed, 6 insertions(+), 4 deletions(-)

(limited to 'techlibs/ice40')

diff --git a/techlibs/ice40/synth_ice40.cc b/techlibs/ice40/synth_ice40.cc
index 8899bfcc4..5de33110a 100644
--- a/techlibs/ice40/synth_ice40.cc
+++ b/techlibs/ice40/synth_ice40.cc
@@ -225,11 +225,13 @@ struct SynthIce40Pass : public ScriptPass
 			run("proc");
 		}
 
-		if (flatten && check_label("flatten", "(unless -noflatten)"))
+		if (check_label("flatten", "(unless -noflatten)"))
 		{
-			run("flatten");
-			run("tribuf -logic");
-			run("deminout");
+			if (flatten) {
+				run("flatten");
+				run("tribuf -logic");
+				run("deminout");
+			}
 		}
 
 		if (check_label("coarse"))
-- 
cgit v1.2.3


From d2d402e62567abe15873c0357b4e34b8f83d03cd Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Tue, 30 Apr 2019 08:10:37 +0200
Subject: Run "peepopt" in generic "synth" pass and "synth_ice40"

Signed-off-by: Clifford Wolf <clifford@clifford.at>
---
 techlibs/ice40/synth_ice40.cc | 2 ++
 1 file changed, 2 insertions(+)

(limited to 'techlibs/ice40')

diff --git a/techlibs/ice40/synth_ice40.cc b/techlibs/ice40/synth_ice40.cc
index 8899bfcc4..f5249e567 100644
--- a/techlibs/ice40/synth_ice40.cc
+++ b/techlibs/ice40/synth_ice40.cc
@@ -239,6 +239,8 @@ struct SynthIce40Pass : public ScriptPass
 			run("check");
 			run("opt");
 			run("wreduce");
+			run("peepopt");
+			run("opt_clean");
 			run("share");
 			run("techmap -map +/cmp2lut.v -D LUT_WIDTH=4");
 			run("opt_expr");
-- 
cgit v1.2.3


From 4f9183d10747c6889ea7d1468dbb6f69844714e6 Mon Sep 17 00:00:00 2001
From: Sylvain Munaut <tnt@246tNt.com>
Date: Mon, 13 May 2019 12:51:06 +0200
Subject: ice40/cells_sim.v: Add support for TRIM input to SB_HFOSC

Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
---
 techlibs/ice40/cells_sim.v | 11 +++++++++++
 1 file changed, 11 insertions(+)

(limited to 'techlibs/ice40')

diff --git a/techlibs/ice40/cells_sim.v b/techlibs/ice40/cells_sim.v
index 00843b97c..e89405b22 100644
--- a/techlibs/ice40/cells_sim.v
+++ b/techlibs/ice40/cells_sim.v
@@ -930,10 +930,21 @@ endmodule
 
 (* blackbox *)
 module SB_HFOSC(
+	input TRIM0,
+	input TRIM1,
+	input TRIM2,
+	input TRIM3,
+	input TRIM4,
+	input TRIM5,
+	input TRIM6,
+	input TRIM7,
+	input TRIM8,
+	input TRIM9,
 	input CLKHFPU,
 	input CLKHFEN,
 	output CLKHF
 );
+parameter TRIM_EN = "0b0";
 parameter CLKHF_DIV = "0b00";
 endmodule
 
-- 
cgit v1.2.3


From 9f44a7171528b90e85b2f33ef8823660fbd95609 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Mon, 3 Jun 2019 09:23:43 -0700
Subject: Consistent with xilinx

---
 techlibs/ice40/abc_hx.box     | 2 +-
 techlibs/ice40/cells_sim.v    | 2 +-
 techlibs/ice40/synth_ice40.cc | 4 ++--
 3 files changed, 4 insertions(+), 4 deletions(-)

(limited to 'techlibs/ice40')

diff --git a/techlibs/ice40/abc_hx.box b/techlibs/ice40/abc_hx.box
index 994f3091d..9ebdae18b 100644
--- a/techlibs/ice40/abc_hx.box
+++ b/techlibs/ice40/abc_hx.box
@@ -4,7 +4,7 @@
 
 # Inputs: C D
 # Outputs: Q
-SB_DFF 1 1 2 1
+SB_DFF 1 0 2 1
 - -
 
 # Inputs: C D E
diff --git a/techlibs/ice40/cells_sim.v b/techlibs/ice40/cells_sim.v
index b5e10fb20..6897aeeb4 100644
--- a/techlibs/ice40/cells_sim.v
+++ b/techlibs/ice40/cells_sim.v
@@ -145,7 +145,7 @@ endmodule
 
 (* abc_box_id = 1, abc_flop, lib_whitebox *)
 module SB_DFF ((* abc_flop_q *) output `SB_DFF_REG, input C, (* abc_flop_d *) input D);
-`ifndef ABC_MODEL
+`ifndef _ABC
 	always @(posedge C)
 		Q <= D;
 `else
diff --git a/techlibs/ice40/synth_ice40.cc b/techlibs/ice40/synth_ice40.cc
index 168161a90..5afa042b0 100644
--- a/techlibs/ice40/synth_ice40.cc
+++ b/techlibs/ice40/synth_ice40.cc
@@ -240,7 +240,7 @@ struct SynthIce40Pass : public ScriptPass
 	{
 		if (check_label("begin"))
 		{
-			run("read_verilog -lib -D ABC_MODEL +/ice40/cells_sim.v");
+			run("read_verilog -lib -D_ABC +/ice40/cells_sim.v");
 			run(stringf("hierarchy -check %s", help_mode ? "-top <top>" : top_opt.c_str()));
 			run("proc");
 		}
@@ -334,7 +334,7 @@ struct SynthIce40Pass : public ScriptPass
 				if (abc == "abc9")
 					run(abc + stringf(" -dress -lut +/ice40/abc_%s.lut -box +/ice40/abc_%s.box", device_opt.c_str(), device_opt.c_str()), "(skip if -noabc)");
 				else
-					run(abc + " -lut 4", "(skip if -noabc)");
+					run(abc + " -dress -lut 4", "(skip if -noabc)");
 			}
 			run("clean");
 			if (relut || help_mode) {
-- 
cgit v1.2.3


From 4da25c76b365b7c90a368c36def81d1122434b95 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Mon, 3 Jun 2019 09:33:42 -0700
Subject: Ooopsie

---
 techlibs/ice40/cells_map.v | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'techlibs/ice40')

diff --git a/techlibs/ice40/cells_map.v b/techlibs/ice40/cells_map.v
index 287c48b11..759549e30 100644
--- a/techlibs/ice40/cells_map.v
+++ b/techlibs/ice40/cells_map.v
@@ -53,7 +53,7 @@ module \$lut (A, Y);
     end else
     if (WIDTH == 4) begin
       localparam [15:0] INIT = {LUT[15], LUT[7], LUT[11], LUT[3], LUT[13], LUT[5], LUT[9], LUT[1], LUT[14], LUT[6], LUT[10], LUT[2], LUT[12], LUT[4], LUT[8], LUT[0]};
-      SB_LUT4 #(.LUT_INIT(LUT)) _TECHMAP_REPLACE_ (.O(Y),
+      SB_LUT4 #(.LUT_INIT(INIT)) _TECHMAP_REPLACE_ (.O(Y),
         .I0(A[3]), .I1(A[2]), .I2(A[1]), .I3(A[0]));
     end else begin
       wire _TECHMAP_FAIL_ = 1;
-- 
cgit v1.2.3


From 00927703177d01ad27559aad827b72068b80b12a Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Mon, 3 Jun 2019 12:34:55 -0700
Subject: Make SB_LUT4 a whitebox, SB_DFF a blackbox (for now)

---
 techlibs/ice40/abc_hx.box  | 2 +-
 techlibs/ice40/abc_lp.box  | 4 ++--
 techlibs/ice40/abc_u.box   | 4 ++--
 techlibs/ice40/cells_sim.v | 6 +++---
 4 files changed, 8 insertions(+), 8 deletions(-)

(limited to 'techlibs/ice40')

diff --git a/techlibs/ice40/abc_hx.box b/techlibs/ice40/abc_hx.box
index 9ebdae18b..a0655643d 100644
--- a/techlibs/ice40/abc_hx.box
+++ b/techlibs/ice40/abc_hx.box
@@ -109,5 +109,5 @@ SB_CARRY 21 1 3 1
 
 # Inputs: I0 I1 I2 I3
 # Outputs: O
-SB_LUT4 22 0 4 1
+SB_LUT4 22 1 4 1
 449 400 379 316
diff --git a/techlibs/ice40/abc_lp.box b/techlibs/ice40/abc_lp.box
index 002b7bba4..dbc98d0c4 100644
--- a/techlibs/ice40/abc_lp.box
+++ b/techlibs/ice40/abc_lp.box
@@ -4,7 +4,7 @@
 
 # Inputs: C D
 # Outputs: Q
-SB_DFF 1 1 2 1
+SB_DFF 1 0 2 1
 - -
 
 # Inputs: C D E
@@ -109,5 +109,5 @@ SB_CARRY 21 1 3 1
 
 # Inputs: I0 I1 I2 I3
 # Outputs: O
-SB_LUT4 22 0 4 1
+SB_LUT4 22 1 4 1
 465 558 589 661
diff --git a/techlibs/ice40/abc_u.box b/techlibs/ice40/abc_u.box
index cb336181c..3b5834e40 100644
--- a/techlibs/ice40/abc_u.box
+++ b/techlibs/ice40/abc_u.box
@@ -4,7 +4,7 @@
 
 # Inputs: C D
 # Outputs: Q
-SB_DFF 1 1 2 1
+SB_DFF 1 0 2 1
 - -
 
 # Inputs: C D E
@@ -109,5 +109,5 @@ SB_CARRY 21 1 3 1
 
 # Inputs: I0 I1 I2 I3
 # Outputs: O
-SB_LUT4 22 0 4 1
+SB_LUT4 22 1 4 1
 1285 1231 1205 874
diff --git a/techlibs/ice40/cells_sim.v b/techlibs/ice40/cells_sim.v
index 6897aeeb4..b9f381266 100644
--- a/techlibs/ice40/cells_sim.v
+++ b/techlibs/ice40/cells_sim.v
@@ -127,7 +127,7 @@ endmodule
 
 // SiliconBlue Logic Cells
 
-(* abc_box_id = 22 *)
+(* abc_box_id = 22, lib_whitebox *)
 module SB_LUT4 (output O, input I0, I1, I2, I3);
 	parameter [15:0] LUT_INIT = 0;
 	wire [7:0] s3 = I3 ? LUT_INIT[15:8] : LUT_INIT[7:0];
@@ -136,8 +136,8 @@ module SB_LUT4 (output O, input I0, I1, I2, I3);
 	assign O = I0 ? s1[1] : s1[0];
 endmodule
 
-(* abc_box_id = 21, lib_whitebox *)
-module SB_CARRY (output CO, input I0, I1, CI);
+(* abc_box_id = 21, abc_carry, lib_whitebox *)
+module SB_CARRY ((* abc_carry_out *) output CO, input I0, I1, (* abc_carry_in *) input CI);
 	assign CO = (I0 && I1) || ((I0 || I1) && CI);
 endmodule
 
-- 
cgit v1.2.3


From abf90b040331f9fd48c9e4bdb4bbb952db4c2d04 Mon Sep 17 00:00:00 2001
From: Simon Schubert <2@0x2c.org>
Date: Mon, 10 Jun 2019 11:49:08 +0200
Subject: ice40/cells_sim.v: Add support for RGB_DRV/LED_DRV_CUR for u4k

---
 techlibs/ice40/cells_sim.v | 24 ++++++++++++++++++++++++
 1 file changed, 24 insertions(+)

(limited to 'techlibs/ice40')

diff --git a/techlibs/ice40/cells_sim.v b/techlibs/ice40/cells_sim.v
index e89405b22..f9945b2b5 100644
--- a/techlibs/ice40/cells_sim.v
+++ b/techlibs/ice40/cells_sim.v
@@ -973,6 +973,30 @@ parameter RGB1_CURRENT = "0b000000";
 parameter RGB2_CURRENT = "0b000000";
 endmodule
 
+(* blackbox *)
+module SB_LED_DRV_CUR(
+	input EN,
+	output LEDPU
+);
+endmodule
+
+(* blackbox *)
+module SB_RGB_DRV(
+	input RGBLEDEN,
+	input RGB0PWM,
+	input RGB1PWM,
+	input RGB2PWM,
+	input RGBPU,
+	output RGB0,
+	output RGB1,
+	output RGB2
+);
+parameter CURRENT_MODE = "0b0";
+parameter RGB0_CURRENT = "0b000000";
+parameter RGB1_CURRENT = "0b000000";
+parameter RGB2_CURRENT = "0b000000";
+endmodule
+
 (* blackbox *)
 module SB_I2C(
 	input  SBCLKI,
-- 
cgit v1.2.3


From f9433cc34bd52d4807c318a6b26f63cdd15d35c0 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Wed, 12 Jun 2019 09:29:30 -0700
Subject: Remove abc_flop{,_d} attributes from ice40/cells_sim.v

---
 techlibs/ice40/cells_sim.v | 60 ++++++++++++++++------------------------------
 1 file changed, 20 insertions(+), 40 deletions(-)

(limited to 'techlibs/ice40')

diff --git a/techlibs/ice40/cells_sim.v b/techlibs/ice40/cells_sim.v
index 523dd8cbe..55b4d98c9 100644
--- a/techlibs/ice40/cells_sim.v
+++ b/techlibs/ice40/cells_sim.v
@@ -143,8 +143,7 @@ endmodule
 
 // Positive Edge SiliconBlue FF Cells
 
-(* abc_box_id = 1, abc_flop, lib_whitebox *)
-module SB_DFF ((* abc_flop_q *) output `SB_DFF_REG, input C, (* abc_flop_d *) input D);
+module SB_DFF ((* abc_flop_q *) output `SB_DFF_REG, input C, D);
 `ifndef _ABC
 	always @(posedge C)
 		Q <= D;
@@ -153,15 +152,13 @@ module SB_DFF ((* abc_flop_q *) output `SB_DFF_REG, input C, (* abc_flop_d *) in
 `endif
 endmodule
 
-//(* abc_box_id = 2, abc_flop *)
-module SB_DFFE ((* abc_flop_q *) output `SB_DFF_REG, input C, E, (* abc_flop_d *) input D);
+module SB_DFFE ((* abc_flop_q *) output `SB_DFF_REG, input C, E, D);
 	always @(posedge C)
 		if (E)
 			Q <= D;
 endmodule
 
-//(* abc_box_id = 3, abc_flop *)
-module SB_DFFSR ((* abc_flop_q *) output `SB_DFF_REG, input C, R, (* abc_flop_d *) input D);
+module SB_DFFSR ((* abc_flop_q *) output `SB_DFF_REG, input C, R, D);
 	always @(posedge C)
 		if (R)
 			Q <= 0;
@@ -169,8 +166,7 @@ module SB_DFFSR ((* abc_flop_q *) output `SB_DFF_REG, input C, R, (* abc_flop_d
 			Q <= D;
 endmodule
 
-//(* abc_box_id = 4, abc_flop *)
-module SB_DFFR ((* abc_flop_q *) output `SB_DFF_REG, input C, R, (* abc_flop_d *) input D);
+module SB_DFFR ((* abc_flop_q *) output `SB_DFF_REG, input C, R, D);
 	always @(posedge C, posedge R)
 		if (R)
 			Q <= 0;
@@ -178,8 +174,7 @@ module SB_DFFR ((* abc_flop_q *) output `SB_DFF_REG, input C, R, (* abc_flop_d *
 			Q <= D;
 endmodule
 
-//(* abc_box_id = 5, abc_flop *)
-module SB_DFFSS ((* abc_flop_q *) output `SB_DFF_REG, input C, S, (* abc_flop_d *) input D);
+module SB_DFFSS ((* abc_flop_q *) output `SB_DFF_REG, input C, S, D);
 	always @(posedge C)
 		if (S)
 			Q <= 1;
@@ -187,8 +182,7 @@ module SB_DFFSS ((* abc_flop_q *) output `SB_DFF_REG, input C, S, (* abc_flop_d
 			Q <= D;
 endmodule
 
-//(* abc_box_id = 6, abc_flop *)
-module SB_DFFS ((* abc_flop_q *) output `SB_DFF_REG, input C, S, (* abc_flop_d *) input D);
+module SB_DFFS ((* abc_flop_q *) output `SB_DFF_REG, input C, S, D);
 	always @(posedge C, posedge S)
 		if (S)
 			Q <= 1;
@@ -196,8 +190,7 @@ module SB_DFFS ((* abc_flop_q *) output `SB_DFF_REG, input C, S, (* abc_flop_d *
 			Q <= D;
 endmodule
 
-//(* abc_box_id = 7, abc_flop *)
-module SB_DFFESR ((* abc_flop_q *) output `SB_DFF_REG, input C, E, R, (* abc_flop_d *) input D);
+module SB_DFFESR ((* abc_flop_q *) output `SB_DFF_REG, input C, E, R, D);
 	always @(posedge C)
 		if (E) begin
 			if (R)
@@ -207,8 +200,7 @@ module SB_DFFESR ((* abc_flop_q *) output `SB_DFF_REG, input C, E, R, (* abc_flo
 		end
 endmodule
 
-//(* abc_box_id = 8, abc_flop *)
-module SB_DFFER ((* abc_flop_q *) output `SB_DFF_REG, input C, E, R, (* abc_flop_d *) input D);
+module SB_DFFER ((* abc_flop_q *) output `SB_DFF_REG, input C, E, R, D);
 	always @(posedge C, posedge R)
 		if (R)
 			Q <= 0;
@@ -216,8 +208,7 @@ module SB_DFFER ((* abc_flop_q *) output `SB_DFF_REG, input C, E, R, (* abc_flop
 			Q <= D;
 endmodule
 
-//(* abc_box_id = 9, abc_flop *)
-module SB_DFFESS ((* abc_flop_q *) output `SB_DFF_REG, input C, E, S, (* abc_flop_d *) input D);
+module SB_DFFESS ((* abc_flop_q *) output `SB_DFF_REG, input C, E, S, D);
 	always @(posedge C)
 		if (E) begin
 			if (S)
@@ -227,8 +218,7 @@ module SB_DFFESS ((* abc_flop_q *) output `SB_DFF_REG, input C, E, S, (* abc_flo
 		end
 endmodule
 
-//(* abc_box_id = 10, abc_flop *)
-module SB_DFFES ((* abc_flop_q *) output `SB_DFF_REG, input C, E, S, (* abc_flop_d *) input D);
+module SB_DFFES ((* abc_flop_q *) output `SB_DFF_REG, input C, E, S, D);
 	always @(posedge C, posedge S)
 		if (S)
 			Q <= 1;
@@ -238,21 +228,18 @@ endmodule
 
 // Negative Edge SiliconBlue FF Cells
 
-//(* abc_box_id = 11, abc_flop *)
-module SB_DFFN ((* abc_flop_q *) output `SB_DFF_REG, input C, (* abc_flop_d *) input D);
+module SB_DFFN ((* abc_flop_q *) output `SB_DFF_REG, input C, D);
 	always @(negedge C)
 		Q <= D;
 endmodule
 
-//(* abc_box_id = 12, abc_flop *)
-module SB_DFFNE ((* abc_flop_q *) output `SB_DFF_REG, input C, E, (* abc_flop_d *) input D);
+module SB_DFFNE ((* abc_flop_q *) output `SB_DFF_REG, input C, E, D);
 	always @(negedge C)
 		if (E)
 			Q <= D;
 endmodule
 
-//(* abc_box_id = 13, abc_flop *)
-module SB_DFFNSR ((* abc_flop_q *) output `SB_DFF_REG, input C, R, (* abc_flop_d *) input D);
+module SB_DFFNSR ((* abc_flop_q *) output `SB_DFF_REG, input C, R, D);
 	always @(negedge C)
 		if (R)
 			Q <= 0;
@@ -260,8 +247,7 @@ module SB_DFFNSR ((* abc_flop_q *) output `SB_DFF_REG, input C, R, (* abc_flop_d
 			Q <= D;
 endmodule
 
-//(* abc_box_id = 14, abc_flop *)
-module SB_DFFNR ((* abc_flop_q *) output `SB_DFF_REG, input C, R, (* abc_flop_d *) input D);
+module SB_DFFNR ((* abc_flop_q *) output `SB_DFF_REG, input C, R, D);
 	always @(negedge C, posedge R)
 		if (R)
 			Q <= 0;
@@ -269,8 +255,7 @@ module SB_DFFNR ((* abc_flop_q *) output `SB_DFF_REG, input C, R, (* abc_flop_d
 			Q <= D;
 endmodule
 
-//(* abc_box_id = 15, abc_flop *)
-module SB_DFFNSS ((* abc_flop_q *) output `SB_DFF_REG, input C, S, (* abc_flop_d *) input D);
+module SB_DFFNSS ((* abc_flop_q *) output `SB_DFF_REG, input C, S, D);
 	always @(negedge C)
 		if (S)
 			Q <= 1;
@@ -278,8 +263,7 @@ module SB_DFFNSS ((* abc_flop_q *) output `SB_DFF_REG, input C, S, (* abc_flop_d
 			Q <= D;
 endmodule
 
-//(* abc_box_id = 16, abc_flop *)
-module SB_DFFNS ((* abc_flop_q *) output `SB_DFF_REG, input C, S, (* abc_flop_d *) input D);
+module SB_DFFNS ((* abc_flop_q *) output `SB_DFF_REG, input C, S, D);
 	always @(negedge C, posedge S)
 		if (S)
 			Q <= 1;
@@ -287,8 +271,7 @@ module SB_DFFNS ((* abc_flop_q *) output `SB_DFF_REG, input C, S, (* abc_flop_d
 			Q <= D;
 endmodule
 
-//(* abc_box_id = 17, abc_flop *)
-module SB_DFFNESR ((* abc_flop_q *) output `SB_DFF_REG, input C, E, R, (* abc_flop_d *) input D);
+module SB_DFFNESR ((* abc_flop_q *) output `SB_DFF_REG, input C, E, R, D);
 	always @(negedge C)
 		if (E) begin
 			if (R)
@@ -298,8 +281,7 @@ module SB_DFFNESR ((* abc_flop_q *) output `SB_DFF_REG, input C, E, R, (* abc_fl
 		end
 endmodule
 
-//(* abc_box_id = 18, abc_flop *)
-module SB_DFFNER ((* abc_flop_q *) output `SB_DFF_REG, input C, E, R, (* abc_flop_d *) input D);
+module SB_DFFNER ((* abc_flop_q *) output `SB_DFF_REG, input C, E, R, D);
 	always @(negedge C, posedge R)
 		if (R)
 			Q <= 0;
@@ -307,8 +289,7 @@ module SB_DFFNER ((* abc_flop_q *) output `SB_DFF_REG, input C, E, R, (* abc_flo
 			Q <= D;
 endmodule
 
-//(* abc_box_id = 19, abc_flop *)
-module SB_DFFNESS ((* abc_flop_q *) output `SB_DFF_REG, input C, E, S, (* abc_flop_d *) input D);
+module SB_DFFNESS ((* abc_flop_q *) output `SB_DFF_REG, input C, E, S, D);
 	always @(negedge C)
 		if (E) begin
 			if (S)
@@ -318,8 +299,7 @@ module SB_DFFNESS ((* abc_flop_q *) output `SB_DFF_REG, input C, E, S, (* abc_fl
 		end
 endmodule
 
-//(* abc_box_id = 20, abc_flop *)
-module SB_DFFNES ((* abc_flop_q *) output `SB_DFF_REG, input C, E, S, (* abc_flop_d *) input D);
+module SB_DFFNES ((* abc_flop_q *) output `SB_DFF_REG, input C, E, S, D);
 	always @(negedge C, posedge S)
 		if (S)
 			Q <= 1;
-- 
cgit v1.2.3


From 2052806d3361dca8a866aee0665af223db51bdbd Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Thu, 13 Jun 2019 08:24:33 -0700
Subject: Fix LP SB_LUT4 timing

---
 techlibs/ice40/abc_lp.box | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'techlibs/ice40')

diff --git a/techlibs/ice40/abc_lp.box b/techlibs/ice40/abc_lp.box
index dbc98d0c4..eb1cd0937 100644
--- a/techlibs/ice40/abc_lp.box
+++ b/techlibs/ice40/abc_lp.box
@@ -110,4 +110,4 @@ SB_CARRY 21 1 3 1
 # Inputs: I0 I1 I2 I3
 # Outputs: O
 SB_LUT4 22 1 4 1
-465 558 589 661
+661 589 558 465
-- 
cgit v1.2.3


From 627a62a797ef9e676ba9d89f53f927d0c2463585 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Fri, 14 Jun 2019 10:32:46 -0700
Subject: Make doc consistent

---
 techlibs/ice40/synth_ice40.cc | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'techlibs/ice40')

diff --git a/techlibs/ice40/synth_ice40.cc b/techlibs/ice40/synth_ice40.cc
index 5afa042b0..a60829764 100644
--- a/techlibs/ice40/synth_ice40.cc
+++ b/techlibs/ice40/synth_ice40.cc
@@ -97,7 +97,7 @@ struct SynthIce40Pass : public ScriptPass
 		log("        (this feature is experimental and incomplete)\n");
 		log("\n");
 		log("    -abc9\n");
-		log("        use abc9 instead of abc\n");
+		log("        use new ABC9 flow (EXPERIMENTAL)\n");
 		log("\n");
 		log("\n");
 		log("The following commands are executed by this synthesis command:\n");
-- 
cgit v1.2.3


From ee428f73abdbbde95601e583db186d86a8fa6b91 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Fri, 14 Jun 2019 10:37:52 -0700
Subject: Remove WIP ABC9 flop support

---
 techlibs/ice40/cells_sim.v | 50 +++++++++++++++++++++++-----------------------
 1 file changed, 25 insertions(+), 25 deletions(-)

(limited to 'techlibs/ice40')

diff --git a/techlibs/ice40/cells_sim.v b/techlibs/ice40/cells_sim.v
index 55b4d98c9..031afa85c 100644
--- a/techlibs/ice40/cells_sim.v
+++ b/techlibs/ice40/cells_sim.v
@@ -143,7 +143,7 @@ endmodule
 
 // Positive Edge SiliconBlue FF Cells
 
-module SB_DFF ((* abc_flop_q *) output `SB_DFF_REG, input C, D);
+module SB_DFF (output `SB_DFF_REG, input C, D);
 `ifndef _ABC
 	always @(posedge C)
 		Q <= D;
@@ -152,13 +152,13 @@ module SB_DFF ((* abc_flop_q *) output `SB_DFF_REG, input C, D);
 `endif
 endmodule
 
-module SB_DFFE ((* abc_flop_q *) output `SB_DFF_REG, input C, E, D);
+module SB_DFFE (output `SB_DFF_REG, input C, E, D);
 	always @(posedge C)
 		if (E)
 			Q <= D;
 endmodule
 
-module SB_DFFSR ((* abc_flop_q *) output `SB_DFF_REG, input C, R, D);
+module SB_DFFSR (output `SB_DFF_REG, input C, R, D);
 	always @(posedge C)
 		if (R)
 			Q <= 0;
@@ -166,7 +166,7 @@ module SB_DFFSR ((* abc_flop_q *) output `SB_DFF_REG, input C, R, D);
 			Q <= D;
 endmodule
 
-module SB_DFFR ((* abc_flop_q *) output `SB_DFF_REG, input C, R, D);
+module SB_DFFR (output `SB_DFF_REG, input C, R, D);
 	always @(posedge C, posedge R)
 		if (R)
 			Q <= 0;
@@ -174,7 +174,7 @@ module SB_DFFR ((* abc_flop_q *) output `SB_DFF_REG, input C, R, D);
 			Q <= D;
 endmodule
 
-module SB_DFFSS ((* abc_flop_q *) output `SB_DFF_REG, input C, S, D);
+module SB_DFFSS (output `SB_DFF_REG, input C, S, D);
 	always @(posedge C)
 		if (S)
 			Q <= 1;
@@ -182,7 +182,7 @@ module SB_DFFSS ((* abc_flop_q *) output `SB_DFF_REG, input C, S, D);
 			Q <= D;
 endmodule
 
-module SB_DFFS ((* abc_flop_q *) output `SB_DFF_REG, input C, S, D);
+module SB_DFFS (output `SB_DFF_REG, input C, S, D);
 	always @(posedge C, posedge S)
 		if (S)
 			Q <= 1;
@@ -190,7 +190,7 @@ module SB_DFFS ((* abc_flop_q *) output `SB_DFF_REG, input C, S, D);
 			Q <= D;
 endmodule
 
-module SB_DFFESR ((* abc_flop_q *) output `SB_DFF_REG, input C, E, R, D);
+module SB_DFFESR (output `SB_DFF_REG, input C, E, R, D);
 	always @(posedge C)
 		if (E) begin
 			if (R)
@@ -200,7 +200,7 @@ module SB_DFFESR ((* abc_flop_q *) output `SB_DFF_REG, input C, E, R, D);
 		end
 endmodule
 
-module SB_DFFER ((* abc_flop_q *) output `SB_DFF_REG, input C, E, R, D);
+module SB_DFFER (output `SB_DFF_REG, input C, E, R, D);
 	always @(posedge C, posedge R)
 		if (R)
 			Q <= 0;
@@ -208,7 +208,7 @@ module SB_DFFER ((* abc_flop_q *) output `SB_DFF_REG, input C, E, R, D);
 			Q <= D;
 endmodule
 
-module SB_DFFESS ((* abc_flop_q *) output `SB_DFF_REG, input C, E, S, D);
+module SB_DFFESS (output `SB_DFF_REG, input C, E, S, D);
 	always @(posedge C)
 		if (E) begin
 			if (S)
@@ -218,7 +218,7 @@ module SB_DFFESS ((* abc_flop_q *) output `SB_DFF_REG, input C, E, S, D);
 		end
 endmodule
 
-module SB_DFFES ((* abc_flop_q *) output `SB_DFF_REG, input C, E, S, D);
+module SB_DFFES (output `SB_DFF_REG, input C, E, S, D);
 	always @(posedge C, posedge S)
 		if (S)
 			Q <= 1;
@@ -228,18 +228,18 @@ endmodule
 
 // Negative Edge SiliconBlue FF Cells
 
-module SB_DFFN ((* abc_flop_q *) output `SB_DFF_REG, input C, D);
+module SB_DFFN (output `SB_DFF_REG, input C, D);
 	always @(negedge C)
 		Q <= D;
 endmodule
 
-module SB_DFFNE ((* abc_flop_q *) output `SB_DFF_REG, input C, E, D);
+module SB_DFFNE (output `SB_DFF_REG, input C, E, D);
 	always @(negedge C)
 		if (E)
 			Q <= D;
 endmodule
 
-module SB_DFFNSR ((* abc_flop_q *) output `SB_DFF_REG, input C, R, D);
+module SB_DFFNSR (output `SB_DFF_REG, input C, R, D);
 	always @(negedge C)
 		if (R)
 			Q <= 0;
@@ -247,7 +247,7 @@ module SB_DFFNSR ((* abc_flop_q *) output `SB_DFF_REG, input C, R, D);
 			Q <= D;
 endmodule
 
-module SB_DFFNR ((* abc_flop_q *) output `SB_DFF_REG, input C, R, D);
+module SB_DFFNR (output `SB_DFF_REG, input C, R, D);
 	always @(negedge C, posedge R)
 		if (R)
 			Q <= 0;
@@ -255,7 +255,7 @@ module SB_DFFNR ((* abc_flop_q *) output `SB_DFF_REG, input C, R, D);
 			Q <= D;
 endmodule
 
-module SB_DFFNSS ((* abc_flop_q *) output `SB_DFF_REG, input C, S, D);
+module SB_DFFNSS (output `SB_DFF_REG, input C, S, D);
 	always @(negedge C)
 		if (S)
 			Q <= 1;
@@ -263,7 +263,7 @@ module SB_DFFNSS ((* abc_flop_q *) output `SB_DFF_REG, input C, S, D);
 			Q <= D;
 endmodule
 
-module SB_DFFNS ((* abc_flop_q *) output `SB_DFF_REG, input C, S, D);
+module SB_DFFNS (output `SB_DFF_REG, input C, S, D);
 	always @(negedge C, posedge S)
 		if (S)
 			Q <= 1;
@@ -271,7 +271,7 @@ module SB_DFFNS ((* abc_flop_q *) output `SB_DFF_REG, input C, S, D);
 			Q <= D;
 endmodule
 
-module SB_DFFNESR ((* abc_flop_q *) output `SB_DFF_REG, input C, E, R, D);
+module SB_DFFNESR (output `SB_DFF_REG, input C, E, R, D);
 	always @(negedge C)
 		if (E) begin
 			if (R)
@@ -281,7 +281,7 @@ module SB_DFFNESR ((* abc_flop_q *) output `SB_DFF_REG, input C, E, R, D);
 		end
 endmodule
 
-module SB_DFFNER ((* abc_flop_q *) output `SB_DFF_REG, input C, E, R, D);
+module SB_DFFNER (output `SB_DFF_REG, input C, E, R, D);
 	always @(negedge C, posedge R)
 		if (R)
 			Q <= 0;
@@ -289,7 +289,7 @@ module SB_DFFNER ((* abc_flop_q *) output `SB_DFF_REG, input C, E, R, D);
 			Q <= D;
 endmodule
 
-module SB_DFFNESS ((* abc_flop_q *) output `SB_DFF_REG, input C, E, S, D);
+module SB_DFFNESS (output `SB_DFF_REG, input C, E, S, D);
 	always @(negedge C)
 		if (E) begin
 			if (S)
@@ -299,7 +299,7 @@ module SB_DFFNESS ((* abc_flop_q *) output `SB_DFF_REG, input C, E, S, D);
 		end
 endmodule
 
-module SB_DFFNES ((* abc_flop_q *) output `SB_DFF_REG, input C, E, S, D);
+module SB_DFFNES (output `SB_DFF_REG, input C, E, S, D);
 	always @(negedge C, posedge S)
 		if (S)
 			Q <= 1;
@@ -310,7 +310,7 @@ endmodule
 // SiliconBlue RAM Cells
 
 module SB_RAM40_4K (
-	(* abc_flop_q *) output [15:0] RDATA,
+	output [15:0] RDATA,
 	input         RCLK, RCLKE, RE,
 	input  [10:0] RADDR,
 	input         WCLK, WCLKE, WE,
@@ -478,7 +478,7 @@ module SB_RAM40_4K (
 endmodule
 
 module SB_RAM40_4KNR (
-	(* abc_flop_q *) output [15:0] RDATA,
+	output [15:0] RDATA,
 	input         RCLKN, RCLKE, RE,
 	input  [10:0] RADDR,
 	input         WCLK, WCLKE, WE,
@@ -543,7 +543,7 @@ module SB_RAM40_4KNR (
 endmodule
 
 module SB_RAM40_4KNW (
-	(* abc_flop_q *) output [15:0] RDATA,
+	output [15:0] RDATA,
 	input         RCLK, RCLKE, RE,
 	input  [10:0] RADDR,
 	input         WCLKN, WCLKE, WE,
@@ -608,7 +608,7 @@ module SB_RAM40_4KNW (
 endmodule
 
 module SB_RAM40_4KNRNW (
-	(* abc_flop_q *) output [15:0] RDATA,
+	output [15:0] RDATA,
 	input         RCLKN, RCLKE, RE,
 	input  [10:0] RADDR,
 	input         WCLKN, WCLKE, WE,
@@ -902,7 +902,7 @@ module SB_SPRAM256KA (
 	input [15:0] DATAIN,
 	input [3:0] MASKWREN,
 	input WREN, CHIPSELECT, CLOCK, STANDBY, SLEEP, POWEROFF,
-	(* abc_flop_q *) output reg [15:0] DATAOUT
+	output reg [15:0] DATAOUT
 );
 `ifndef BLACKBOX
 `ifndef EQUIV
-- 
cgit v1.2.3


From 97d265637505a239e3d328a3ee7e26c6fd5d6744 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Fri, 14 Jun 2019 12:00:02 -0700
Subject: Resolve comments from @daveshah1

---
 techlibs/ice40/synth_ice40.cc | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'techlibs/ice40')

diff --git a/techlibs/ice40/synth_ice40.cc b/techlibs/ice40/synth_ice40.cc
index a60829764..d8e9786c5 100644
--- a/techlibs/ice40/synth_ice40.cc
+++ b/techlibs/ice40/synth_ice40.cc
@@ -332,7 +332,7 @@ struct SynthIce40Pass : public ScriptPass
 			}
 			if (!noabc) {
 				if (abc == "abc9")
-					run(abc + stringf(" -dress -lut +/ice40/abc_%s.lut -box +/ice40/abc_%s.box", device_opt.c_str(), device_opt.c_str()), "(skip if -noabc)");
+					run(abc + stringf(" -lut +/ice40/abc_%s.lut -box +/ice40/abc_%s.box", device_opt.c_str(), device_opt.c_str()), "(skip if -noabc)");
 				else
 					run(abc + " -dress -lut 4", "(skip if -noabc)");
 			}
-- 
cgit v1.2.3


From 0d888ee7edada1349b76360f85124a81d0766cd2 Mon Sep 17 00:00:00 2001
From: acw1251 <acwright@mit.edu>
Date: Wed, 19 Jun 2019 15:27:04 -0400
Subject: Fixed the help summary line for a few commands

---
 techlibs/ice40/ice40_unlut.cc | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'techlibs/ice40')

diff --git a/techlibs/ice40/ice40_unlut.cc b/techlibs/ice40/ice40_unlut.cc
index 2428a8e78..bec3c4c96 100644
--- a/techlibs/ice40/ice40_unlut.cc
+++ b/techlibs/ice40/ice40_unlut.cc
@@ -74,7 +74,7 @@ static void run_ice40_unlut(Module *module)
 }
 
 struct Ice40UnlutPass : public Pass {
-	Ice40UnlutPass() : Pass("ice40_unlut", "iCE40: perform simple optimizations") { }
+	Ice40UnlutPass() : Pass("ice40_unlut", "iCE40: transform SBLUT4 cells to $lut cells") { }
 	void help() YS_OVERRIDE
 	{
 		//   |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
-- 
cgit v1.2.3


From ce29ede801e4cbfa430c56833f3f0bf98b18063f Mon Sep 17 00:00:00 2001
From: acw1251 <acwright@mit.edu>
Date: Wed, 19 Jun 2019 16:39:46 -0400
Subject: Fixed small typo in ice40_unlut help summary

---
 techlibs/ice40/ice40_unlut.cc | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'techlibs/ice40')

diff --git a/techlibs/ice40/ice40_unlut.cc b/techlibs/ice40/ice40_unlut.cc
index bec3c4c96..d16e6e6a3 100644
--- a/techlibs/ice40/ice40_unlut.cc
+++ b/techlibs/ice40/ice40_unlut.cc
@@ -74,7 +74,7 @@ static void run_ice40_unlut(Module *module)
 }
 
 struct Ice40UnlutPass : public Pass {
-	Ice40UnlutPass() : Pass("ice40_unlut", "iCE40: transform SBLUT4 cells to $lut cells") { }
+	Ice40UnlutPass() : Pass("ice40_unlut", "iCE40: transform SB_LUT4 cells to $lut cells") { }
 	void help() YS_OVERRIDE
 	{
 		//   |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
-- 
cgit v1.2.3


From 63182ed57d3a62c8c5e316cea48216024afb38a4 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Sat, 22 Jun 2019 14:27:41 -0700
Subject: Fix and cleanup ice40 boxes for carry in/out

---
 techlibs/ice40/abc_hx.box  | 112 ++++-----------------------------------------
 techlibs/ice40/abc_lp.box  | 110 +++-----------------------------------------
 techlibs/ice40/abc_u.box   | 112 ++++-----------------------------------------
 techlibs/ice40/cells_sim.v |   4 +-
 4 files changed, 25 insertions(+), 313 deletions(-)

(limited to 'techlibs/ice40')

diff --git a/techlibs/ice40/abc_hx.box b/techlibs/ice40/abc_hx.box
index a0655643d..f8e12b527 100644
--- a/techlibs/ice40/abc_hx.box
+++ b/techlibs/ice40/abc_hx.box
@@ -1,113 +1,17 @@
 # From https://github.com/cliffordwolf/icestorm/blob/be0bca0/icefuzz/timings_hx8k.txt
 
 # NB: Inputs/Outputs must be ordered alphabetically
+#     (with exceptions for carry in/out)
 
-# Inputs: C D
-# Outputs: Q
-SB_DFF 1 0 2 1
-- -
-
-# Inputs: C D E
-# Outputs: Q
-SB_DFFE 2 0 3 1
-- - -
-
-# Inputs: C D R
-# Outputs: Q
-SB_DFFSR 3 0 3 1
-- - -
-
-# Inputs: C D R
-# Outputs: Q
-SB_DFFR 4 0 3 1
-- - -
-
-# Inputs: C D S
-# Outputs: Q
-SB_DFFSS 5 0 3 1
-- - -
-
-# Inputs: C D S
-# Outputs: Q
-SB_DFFS 6 0 3 1
-- - -
-
-# Inputs: C D E R
-# Outputs: Q
-SB_DFFESR 7 0 4 1
-- - - -
-
-# Inputs: C D E R
-# Outputs: Q
-SB_DFFER 8 0 4 1
-- - - -
-
-# Inputs: C D E S
-# Outputs: Q
-SB_DFFESS 9 0 4 1
-- - - -
-
-# Inputs: C D E S
-# Outputs: Q
-SB_DFFES 10 0 4 1
-- - - -
-
-# Inputs: C D
-# Outputs: Q
-SB_DFFN 11 0 2 1
-- -
-
-# Inputs: C D E
-# Outputs: Q
-SB_DFFNE 12 0 3 1
-- - -
-
-# Inputs: C D R
-# Outputs: Q
-SB_DFFNSR 13 0 3 1
-- - -
-
-# Inputs: C D R
-# Outputs: Q
-SB_DFFNR 14 0 3 1
-- - -
-
-# Inputs: C D S
-# Outputs: Q
-SB_DFFNSS 15 0 3 1
-- - -
-
-# Inputs: C D S
-# Outputs: Q
-SB_DFFNS 16 0 3 1
-- - -
-
-# Inputs: C D E R
-# Outputs: Q
-SB_DFFNESR 17 0 4 1
-- - - -
-
-# Inputs: C D E R
-# Outputs: Q
-SB_DFFNER 18 0 4 1
-- - - -
-
-# Inputs: C D E S
-# Outputs: Q
-SB_DFFNESS 19 0 4 1
-- - - -
-
-# Inputs: C D E S
-# Outputs: Q
-SB_DFFNES 20 0 4 1
-- - - -
-
-# Inputs: CI I0 I1
+# Inputs: I0 I1 CI
 # Outputs: CO
-SB_CARRY 21 1 3 1
-126 259 231
+#   (NB: carry chain input/output must be last
+#        input/output and have been moved there
+#        overriding the alphabetical ordering)
+SB_CARRY 1 1 3 1
+259 231 126
 
 # Inputs: I0 I1 I2 I3
 # Outputs: O
-SB_LUT4 22 1 4 1
+SB_LUT4 2 1 4 1
 449 400 379 316
diff --git a/techlibs/ice40/abc_lp.box b/techlibs/ice40/abc_lp.box
index eb1cd0937..fbe4c56e6 100644
--- a/techlibs/ice40/abc_lp.box
+++ b/techlibs/ice40/abc_lp.box
@@ -1,113 +1,17 @@
 # From https://github.com/cliffordwolf/icestorm/blob/be0bca0/icefuzz/timings_lp8k.txt
 
 # NB: Inputs/Outputs must be ordered alphabetically
-
-# Inputs: C D
-# Outputs: Q
-SB_DFF 1 0 2 1
-- -
-
-# Inputs: C D E
-# Outputs: Q
-SB_DFFE 2 0 3 1
-- - -
-
-# Inputs: C D R
-# Outputs: Q
-SB_DFFSR 3 0 3 1
-- - -
-
-# Inputs: C D R
-# Outputs: Q
-SB_DFFR 4 0 3 1
-- - -
-
-# Inputs: C D S
-# Outputs: Q
-SB_DFFSS 5 0 3 1
-- - -
-
-# Inputs: C D S
-# Outputs: Q
-SB_DFFS 6 0 3 1
-- - -
-
-# Inputs: C D E R
-# Outputs: Q
-SB_DFFESR 7 0 4 1
-- - - -
-
-# Inputs: C D E R
-# Outputs: Q
-SB_DFFER 8 0 4 1
-- - - -
-
-# Inputs: C D E S
-# Outputs: Q
-SB_DFFESS 9 0 4 1
-- - - -
-
-# Inputs: C D E S
-# Outputs: Q
-SB_DFFES 10 0 4 1
-- - - -
-
-# Inputs: C D
-# Outputs: Q
-SB_DFFN 11 0 2 1
-- -
-
-# Inputs: C D E
-# Outputs: Q
-SB_DFFNE 12 0 3 1
-- - -
-
-# Inputs: C D R
-# Outputs: Q
-SB_DFFNSR 13 0 3 1
-- - -
-
-# Inputs: C D R
-# Outputs: Q
-SB_DFFNR 14 0 3 1
-- - -
-
-# Inputs: C D S
-# Outputs: Q
-SB_DFFNSS 15 0 3 1
-- - -
-
-# Inputs: C D S
-# Outputs: Q
-SB_DFFNS 16 0 3 1
-- - -
-
-# Inputs: C D E R
-# Outputs: Q
-SB_DFFNESR 17 0 4 1
-- - - -
-
-# Inputs: C D E R
-# Outputs: Q
-SB_DFFNER 18 0 4 1
-- - - -
-
-# Inputs: C D E S
-# Outputs: Q
-SB_DFFNESS 19 0 4 1
-- - - -
-
-# Inputs: C D E S
-# Outputs: Q
-SB_DFFNES 20 0 4 1
-- - - -
+#     (with exceptions for carry in/out)
 
 # Inputs: CI I0 I1
 # Outputs: CO
-SB_CARRY 21 1 3 1
-186 675 609
+#   (NB: carry chain input/output must be last
+#        input/output and have been moved there
+#        overriding the alphabetical ordering)
+SB_CARRY 1 1 3 1
+675 609 186 
 
 # Inputs: I0 I1 I2 I3
 # Outputs: O
-SB_LUT4 22 1 4 1
+SB_LUT4 2 1 4 1
 661 589 558 465
diff --git a/techlibs/ice40/abc_u.box b/techlibs/ice40/abc_u.box
index 3b5834e40..f44deabc4 100644
--- a/techlibs/ice40/abc_u.box
+++ b/techlibs/ice40/abc_u.box
@@ -1,113 +1,17 @@
 # From https://github.com/cliffordwolf/icestorm/blob/be0bca0/icefuzz/timings_up5k.txt
 
 # NB: Inputs/Outputs must be ordered alphabetically
+#     (with exceptions for carry in/out)
 
-# Inputs: C D
-# Outputs: Q
-SB_DFF 1 0 2 1
-- -
-
-# Inputs: C D E
-# Outputs: Q
-SB_DFFE 2 0 3 1
-- - -
-
-# Inputs: C D R
-# Outputs: Q
-SB_DFFSR 3 0 3 1
-- - -
-
-# Inputs: C D R
-# Outputs: Q
-SB_DFFR 4 0 3 1
-- - -
-
-# Inputs: C D S
-# Outputs: Q
-SB_DFFSS 5 0 3 1
-- - -
-
-# Inputs: C D S
-# Outputs: Q
-SB_DFFS 6 0 3 1
-- - -
-
-# Inputs: C D E R
-# Outputs: Q
-SB_DFFESR 7 0 4 1
-- - - -
-
-# Inputs: C D E R
-# Outputs: Q
-SB_DFFER 8 0 4 1
-- - - -
-
-# Inputs: C D E S
-# Outputs: Q
-SB_DFFESS 9 0 4 1
-- - - -
-
-# Inputs: C D E S
-# Outputs: Q
-SB_DFFES 10 0 4 1
-- - - -
-
-# Inputs: C D
-# Outputs: Q
-SB_DFFN 11 0 2 1
-- -
-
-# Inputs: C D E
-# Outputs: Q
-SB_DFFNE 12 0 3 1
-- - -
-
-# Inputs: C D R
-# Outputs: Q
-SB_DFFNSR 13 0 3 1
-- - -
-
-# Inputs: C D R
-# Outputs: Q
-SB_DFFNR 14 0 3 1
-- - -
-
-# Inputs: C D S
-# Outputs: Q
-SB_DFFNSS 15 0 3 1
-- - -
-
-# Inputs: C D S
-# Outputs: Q
-SB_DFFNS 16 0 3 1
-- - -
-
-# Inputs: C D E R
-# Outputs: Q
-SB_DFFNESR 17 0 4 1
-- - - -
-
-# Inputs: C D E R
-# Outputs: Q
-SB_DFFNER 18 0 4 1
-- - - -
-
-# Inputs: C D E S
-# Outputs: Q
-SB_DFFNESS 19 0 4 1
-- - - -
-
-# Inputs: C D E S
-# Outputs: Q
-SB_DFFNES 20 0 4 1
-- - - -
-
-# Inputs: CI I0 I1
+# Inputs: I0 I1 CI
 # Outputs: CO
-SB_CARRY 21 1 3 1
-278 675 609
+#   (NB: carry chain input/output must be last
+#        input/output and have been moved there
+#        overriding the alphabetical ordering)
+SB_CARRY 1 1 3 1
+675 609 278
 
 # Inputs: I0 I1 I2 I3
 # Outputs: O
-SB_LUT4 22 1 4 1
+SB_LUT4 2 1 4 1
 1285 1231 1205 874
diff --git a/techlibs/ice40/cells_sim.v b/techlibs/ice40/cells_sim.v
index 031afa85c..317ae2c1f 100644
--- a/techlibs/ice40/cells_sim.v
+++ b/techlibs/ice40/cells_sim.v
@@ -127,7 +127,7 @@ endmodule
 
 // SiliconBlue Logic Cells
 
-(* abc_box_id = 22, lib_whitebox *)
+(* abc_box_id = 2, lib_whitebox *)
 module SB_LUT4 (output O, input I0, I1, I2, I3);
 	parameter [15:0] LUT_INIT = 0;
 	wire [7:0] s3 = I3 ? LUT_INIT[15:8] : LUT_INIT[7:0];
@@ -136,7 +136,7 @@ module SB_LUT4 (output O, input I0, I1, I2, I3);
 	assign O = I0 ? s1[1] : s1[0];
 endmodule
 
-(* abc_box_id = 21, abc_carry, lib_whitebox *)
+(* abc_box_id = 1, abc_carry, lib_whitebox *)
 module SB_CARRY ((* abc_carry_out *) output CO, input I0, I1, (* abc_carry_in *) input CI);
 	assign CO = (I0 && I1) || ((I0 || I1) && CI);
 endmodule
-- 
cgit v1.2.3


From 0dd850e6552a74430559ed63c3a9a67aa1c84512 Mon Sep 17 00:00:00 2001
From: David Shah <dave@ds0.me>
Date: Wed, 26 Jun 2019 11:39:44 +0100
Subject: abc9: Add wire delays to synth_ice40

Signed-off-by: David Shah <dave@ds0.me>
---
 techlibs/ice40/synth_ice40.cc | 12 ++++++++++--
 1 file changed, 10 insertions(+), 2 deletions(-)

(limited to 'techlibs/ice40')

diff --git a/techlibs/ice40/synth_ice40.cc b/techlibs/ice40/synth_ice40.cc
index d8e9786c5..a782f00b9 100644
--- a/techlibs/ice40/synth_ice40.cc
+++ b/techlibs/ice40/synth_ice40.cc
@@ -331,8 +331,16 @@ struct SynthIce40Pass : public ScriptPass
 				run("techmap -map +/gate2lut.v -D LUT_WIDTH=4", "(only if -noabc)");
 			}
 			if (!noabc) {
-				if (abc == "abc9")
-					run(abc + stringf(" -lut +/ice40/abc_%s.lut -box +/ice40/abc_%s.box", device_opt.c_str(), device_opt.c_str()), "(skip if -noabc)");
+				if (abc == "abc9") {
+					int wire_delay;
+					if (device_opt == "lp")
+						wire_delay = 400;
+					else if (device_opt == "u")
+						wire_delay = 750;
+					else
+						wire_delay = 250;
+					run(abc + stringf(" -W %d -lut +/ice40/abc_%s.lut -box +/ice40/abc_%s.box", wire_delay, device_opt.c_str(), device_opt.c_str()), "(skip if -noabc)");
+				}
 				else
 					run(abc + " -dress -lut 4", "(skip if -noabc)");
 			}
-- 
cgit v1.2.3


From 9398921af1d21b47aa291d240a1f274418adcaf2 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Thu, 27 Jun 2019 16:07:14 -0700
Subject: Refactor for one "abc_carry" attribute on module

---
 techlibs/ice40/cells_sim.v | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

(limited to 'techlibs/ice40')

diff --git a/techlibs/ice40/cells_sim.v b/techlibs/ice40/cells_sim.v
index 317ae2c1f..c7e4101e1 100644
--- a/techlibs/ice40/cells_sim.v
+++ b/techlibs/ice40/cells_sim.v
@@ -136,8 +136,8 @@ module SB_LUT4 (output O, input I0, I1, I2, I3);
 	assign O = I0 ? s1[1] : s1[0];
 endmodule
 
-(* abc_box_id = 1, abc_carry, lib_whitebox *)
-module SB_CARRY ((* abc_carry_out *) output CO, input I0, I1, (* abc_carry_in *) input CI);
+(* abc_box_id = 1, abc_carry="CI,CO", lib_whitebox *)
+module SB_CARRY (output CO, input I0, I1, CI);
 	assign CO = (I0 && I1) || ((I0 || I1) && CI);
 endmodule
 
-- 
cgit v1.2.3


From 4daa74679779a45542b36c1f3630bd1fbae9ec7b Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Thu, 27 Jun 2019 16:11:39 -0700
Subject: Remove noise from ice40/cells_sim.v

---
 techlibs/ice40/cells_sim.v | 5 -----
 1 file changed, 5 deletions(-)

(limited to 'techlibs/ice40')

diff --git a/techlibs/ice40/cells_sim.v b/techlibs/ice40/cells_sim.v
index c7e4101e1..b746ba4e5 100644
--- a/techlibs/ice40/cells_sim.v
+++ b/techlibs/ice40/cells_sim.v
@@ -144,12 +144,8 @@ endmodule
 // Positive Edge SiliconBlue FF Cells
 
 module SB_DFF (output `SB_DFF_REG, input C, D);
-`ifndef _ABC
 	always @(posedge C)
 		Q <= D;
-`else
-    always @* Q <= D;
-`endif
 endmodule
 
 module SB_DFFE (output `SB_DFF_REG, input C, E, D);
@@ -896,7 +892,6 @@ module SB_WARMBOOT (
 );
 endmodule
 
-(* nomem2reg *)
 module SB_SPRAM256KA (
 	input [13:0] ADDRESS,
 	input [15:0] DATAIN,
-- 
cgit v1.2.3


From af8a5ae5fe35d65742eb17db8cd2bacda93e916e Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Thu, 27 Jun 2019 16:12:20 -0700
Subject: Extraneous newline

---
 techlibs/ice40/synth_ice40.cc | 1 -
 1 file changed, 1 deletion(-)

(limited to 'techlibs/ice40')

diff --git a/techlibs/ice40/synth_ice40.cc b/techlibs/ice40/synth_ice40.cc
index a782f00b9..caef420d4 100644
--- a/techlibs/ice40/synth_ice40.cc
+++ b/techlibs/ice40/synth_ice40.cc
@@ -105,7 +105,6 @@ struct SynthIce40Pass : public ScriptPass
 		log("\n");
 	}
 
-
 	string top_opt, blif_file, edif_file, json_file, abc, device_opt;
 	bool nocarry, nodffe, nobram, dsp, flatten, retime, relut, noabc, abc2, vpr;
 	int min_ce_use;
-- 
cgit v1.2.3


From 03705f69f4e7fbd19181297cd4de68472a5f4ba3 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Fri, 28 Jun 2019 09:49:01 -0700
Subject: Update synth_ice40 -device doc to be relevant for -abc9 only

---
 techlibs/ice40/synth_ice40.cc | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

(limited to 'techlibs/ice40')

diff --git a/techlibs/ice40/synth_ice40.cc b/techlibs/ice40/synth_ice40.cc
index caef420d4..9dd5d81f7 100644
--- a/techlibs/ice40/synth_ice40.cc
+++ b/techlibs/ice40/synth_ice40.cc
@@ -38,8 +38,8 @@ struct SynthIce40Pass : public ScriptPass
 		log("This command runs synthesis for iCE40 FPGAs.\n");
 		log("\n");
 		log("    -device < hx | lp | u >\n");
-		log("        optimise the synthesis netlist for the specified device.\n");
-		log("        HX is the default target if no device argument specified.\n");
+		log("        relevant only for '-abc9' flow, optimise timing for the specified device.\n");
+		log("        default: hx\n");
 		log("\n");
 		log("    -top <module>\n");
 		log("        use the specified module as top module\n");
-- 
cgit v1.2.3


From 6bbd286e033ed25bb49684316a86d6227dec4cd7 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Wed, 10 Jul 2019 12:47:48 -0700
Subject: Error out if -abc9 and -retime specified

---
 techlibs/ice40/synth_ice40.cc | 5 ++++-
 1 file changed, 4 insertions(+), 1 deletion(-)

(limited to 'techlibs/ice40')

diff --git a/techlibs/ice40/synth_ice40.cc b/techlibs/ice40/synth_ice40.cc
index 9dd5d81f7..2c75215cb 100644
--- a/techlibs/ice40/synth_ice40.cc
+++ b/techlibs/ice40/synth_ice40.cc
@@ -227,6 +227,9 @@ struct SynthIce40Pass : public ScriptPass
 		if (device_opt != "hx" && device_opt != "lp" && device_opt !="u")
 			log_cmd_error("Invalid or no device specified: '%s'\n", device_opt.c_str());
 
+		if (abc == "abc9" && retime)
+			log_cmd_error("-retime option not currently compatible with -abc9!\n");
+
 		log_header(design, "Executing SYNTH_ICE40 pass.\n");
 		log_push();
 
@@ -296,7 +299,7 @@ struct SynthIce40Pass : public ScriptPass
 				run("techmap");
 			else
 				run("techmap -map +/techmap.v -map +/ice40/arith_map.v");
-			if ((retime || help_mode) && abc != "abc9")
+			if (retime || help_mode)
 				run(abc + " -dff", "(only if -retime)");
 			run("ice40_opt");
 		}
-- 
cgit v1.2.3


From a8c5f7f41ec0c829c29ae425b0074eb33fa2a30c Mon Sep 17 00:00:00 2001
From: whitequark <whitequark@whitequark.org>
Date: Thu, 11 Jul 2019 10:46:45 +0000
Subject: synth_ice40: fix help text typo. NFC.

---
 techlibs/ice40/synth_ice40.cc | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'techlibs/ice40')

diff --git a/techlibs/ice40/synth_ice40.cc b/techlibs/ice40/synth_ice40.cc
index 2c75215cb..78c62213e 100644
--- a/techlibs/ice40/synth_ice40.cc
+++ b/techlibs/ice40/synth_ice40.cc
@@ -78,7 +78,7 @@ struct SynthIce40Pass : public ScriptPass
 		log("\n");
 		log("    -dffe_min_ce_use <min_ce_use>\n");
 		log("        do not use SB_DFFE* cells if the resulting CE line would go to less\n");
-		log("        than min_ce_use SB_DFFE*in output netlist\n");
+		log("        than min_ce_use SB_DFFE* in output netlist\n");
 		log("\n");
 		log("    -nobram\n");
 		log("        do not use SB_RAM40_4K* cells in output netlist\n");
-- 
cgit v1.2.3


From b700a4b1c5dd086874c7024edb10674cf3c3a7c4 Mon Sep 17 00:00:00 2001
From: whitequark <whitequark@whitequark.org>
Date: Thu, 11 Jul 2019 10:46:30 +0000
Subject: synth_ice40: switch -relut to be always on.

---
 techlibs/ice40/synth_ice40.cc | 14 ++++----------
 1 file changed, 4 insertions(+), 10 deletions(-)

(limited to 'techlibs/ice40')

diff --git a/techlibs/ice40/synth_ice40.cc b/techlibs/ice40/synth_ice40.cc
index 78c62213e..0474e76e9 100644
--- a/techlibs/ice40/synth_ice40.cc
+++ b/techlibs/ice40/synth_ice40.cc
@@ -67,9 +67,6 @@ struct SynthIce40Pass : public ScriptPass
 		log("    -retime\n");
 		log("        run 'abc' with -dff option\n");
 		log("\n");
-		log("    -relut\n");
-		log("        combine LUTs after synthesis\n");
-		log("\n");
 		log("    -nocarry\n");
 		log("        do not use SB_CARRY cells in output netlist\n");
 		log("\n");
@@ -106,7 +103,7 @@ struct SynthIce40Pass : public ScriptPass
 	}
 
 	string top_opt, blif_file, edif_file, json_file, abc, device_opt;
-	bool nocarry, nodffe, nobram, dsp, flatten, retime, relut, noabc, abc2, vpr;
+	bool nocarry, nodffe, nobram, dsp, flatten, retime, noabc, abc2, vpr;
 	int min_ce_use;
 
 	void clear_flags() YS_OVERRIDE
@@ -122,7 +119,6 @@ struct SynthIce40Pass : public ScriptPass
 		dsp = false;
 		flatten = true;
 		retime = false;
-		relut = false;
 		noabc = false;
 		abc2 = false;
 		vpr = false;
@@ -175,7 +171,7 @@ struct SynthIce40Pass : public ScriptPass
 				continue;
 			}
 			if (args[argidx] == "-relut") {
-				relut = true;
+				// removed, opt_lut is always run
 				continue;
 			}
 			if (args[argidx] == "-nocarry") {
@@ -347,10 +343,8 @@ struct SynthIce40Pass : public ScriptPass
 					run(abc + " -dress -lut 4", "(skip if -noabc)");
 			}
 			run("clean");
-			if (relut || help_mode) {
-				run("ice40_unlut", "                            (only if -relut)");
-				run("opt_lut -dlogic SB_CARRY:I0=1:I1=2:CI=3", "(only if -relut)");
-			}
+			run("ice40_unlut");
+			run("opt_lut -dlogic SB_CARRY:I0=1:I1=2:CI=3");
 		}
 
 		if (check_label("map_cells"))
-- 
cgit v1.2.3


From fc3d74616f284eaccdc7d105cd77572953602d7f Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Fri, 12 Jul 2019 00:50:42 -0700
Subject: Combine SB_CARRY+SB_LUT into one $__ICE40_CARRY_LUT4 box

---
 techlibs/ice40/abc_hx.box | 12 ++++--------
 techlibs/ice40/abc_lp.box | 12 ++++--------
 techlibs/ice40/abc_u.box  | 14 +++++---------
 3 files changed, 13 insertions(+), 25 deletions(-)

(limited to 'techlibs/ice40')

diff --git a/techlibs/ice40/abc_hx.box b/techlibs/ice40/abc_hx.box
index f8e12b527..4b55297dd 100644
--- a/techlibs/ice40/abc_hx.box
+++ b/techlibs/ice40/abc_hx.box
@@ -3,15 +3,11 @@
 # NB: Inputs/Outputs must be ordered alphabetically
 #     (with exceptions for carry in/out)
 
-# Inputs: I0 I1 CI
-# Outputs: CO
+# Inputs: A B CI
+# Outputs: O CO
 #   (NB: carry chain input/output must be last
 #        input/output and have been moved there
 #        overriding the alphabetical ordering)
-SB_CARRY 1 1 3 1
+$__ICE40_CARRY_LUT4 1 1 3 2
+400 379 316
 259 231 126
-
-# Inputs: I0 I1 I2 I3
-# Outputs: O
-SB_LUT4 2 1 4 1
-449 400 379 316
diff --git a/techlibs/ice40/abc_lp.box b/techlibs/ice40/abc_lp.box
index fbe4c56e6..b85346370 100644
--- a/techlibs/ice40/abc_lp.box
+++ b/techlibs/ice40/abc_lp.box
@@ -3,15 +3,11 @@
 # NB: Inputs/Outputs must be ordered alphabetically
 #     (with exceptions for carry in/out)
 
-# Inputs: CI I0 I1
-# Outputs: CO
+# Inputs: A B CI
+# Outputs: O CO
 #   (NB: carry chain input/output must be last
 #        input/output and have been moved there
 #        overriding the alphabetical ordering)
-SB_CARRY 1 1 3 1
+$__ICE40_CARRY_LUT4 1 1 3 2
+589 558 465
 675 609 186 
-
-# Inputs: I0 I1 I2 I3
-# Outputs: O
-SB_LUT4 2 1 4 1
-661 589 558 465
diff --git a/techlibs/ice40/abc_u.box b/techlibs/ice40/abc_u.box
index f44deabc4..3a71addef 100644
--- a/techlibs/ice40/abc_u.box
+++ b/techlibs/ice40/abc_u.box
@@ -3,15 +3,11 @@
 # NB: Inputs/Outputs must be ordered alphabetically
 #     (with exceptions for carry in/out)
 
-# Inputs: I0 I1 CI
-# Outputs: CO
+# Inputs: A B CI
+# Outputs: O CO
 #   (NB: carry chain input/output must be last
 #        input/output and have been moved there
 #        overriding the alphabetical ordering)
-SB_CARRY 1 1 3 1
-675 609 278
-
-# Inputs: I0 I1 I2 I3
-# Outputs: O
-SB_LUT4 2 1 4 1
-1285 1231 1205 874
+$__ICE40_CARRY_LUT4 1 1 3 2
+1231 1205 875
+675  609  278
-- 
cgit v1.2.3


From c6e16e1334dcbd8bb556ab566130cc7936f06a69 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Fri, 12 Jul 2019 00:51:37 -0700
Subject: _ABC macro will map and unmap to this new box

---
 techlibs/ice40/arith_map.v | 10 ++++++++++
 techlibs/ice40/cells_map.v | 24 ++++++++++++++++++++++++
 2 files changed, 34 insertions(+)

(limited to 'techlibs/ice40')

diff --git a/techlibs/ice40/arith_map.v b/techlibs/ice40/arith_map.v
index 4449fdc1b..6d45e4a6b 100644
--- a/techlibs/ice40/arith_map.v
+++ b/techlibs/ice40/arith_map.v
@@ -44,6 +44,15 @@ module _80_ice40_alu (A, B, CI, BI, X, Y, CO);
 
 	genvar i;
 	generate for (i = 0; i < Y_WIDTH; i = i + 1) begin:slice
+`ifdef _ABC
+		\$__ICE40_CARRY_LUT4 carry (
+			.A(AA[i]),
+			.B(BB[i]),
+			.CI(C[i]),
+			.CO(CO[i]),
+            .O(Y[i])
+		);
+`else
 		SB_CARRY carry (
 			.I0(AA[i]),
 			.I1(BB[i]),
@@ -63,6 +72,7 @@ module _80_ice40_alu (A, B, CI, BI, X, Y, CO);
 			.I3(C[i]),
 			.O(Y[i])
 		);
+`endif
 	end endgenerate
 
 	assign X = AA ^ BB;
diff --git a/techlibs/ice40/cells_map.v b/techlibs/ice40/cells_map.v
index 759549e30..5dca63e19 100644
--- a/techlibs/ice40/cells_map.v
+++ b/techlibs/ice40/cells_map.v
@@ -61,3 +61,27 @@ module \$lut (A, Y);
   endgenerate
 endmodule
 `endif
+
+`ifdef _ABC
+module \$__ICE40_CARRY_LUT4 (output CO, O, input A, B, CI);
+  SB_CARRY carry (
+    .I0(A),
+    .I1(B),
+    .CI(CI),
+    .CO(CO)
+  );
+  SB_LUT4 #(
+    //         I0: 1010 1010 1010 1010
+    //         I1: 1100 1100 1100 1100
+    //         I2: 1111 0000 1111 0000
+    //         I3: 1111 1111 0000 0000
+    .LUT_INIT(16'b 0110_1001_1001_0110)
+  ) adder (
+    .I0(1'b0),
+    .I1(A),
+    .I2(B),
+    .I3(CI),
+    .O(O)
+  );
+endmodule
+`endif
-- 
cgit v1.2.3


From a79ff2501e7b73b4af958d23d247951b107bb054 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Fri, 12 Jul 2019 00:52:19 -0700
Subject: Add new box to cells_sim.v

---
 techlibs/ice40/cells_sim.v | 27 +++++++++++++++++++++++++--
 1 file changed, 25 insertions(+), 2 deletions(-)

(limited to 'techlibs/ice40')

diff --git a/techlibs/ice40/cells_sim.v b/techlibs/ice40/cells_sim.v
index b746ba4e5..cf36f5cfb 100644
--- a/techlibs/ice40/cells_sim.v
+++ b/techlibs/ice40/cells_sim.v
@@ -127,7 +127,7 @@ endmodule
 
 // SiliconBlue Logic Cells
 
-(* abc_box_id = 2, lib_whitebox *)
+(* lib_whitebox *)
 module SB_LUT4 (output O, input I0, I1, I2, I3);
 	parameter [15:0] LUT_INIT = 0;
 	wire [7:0] s3 = I3 ? LUT_INIT[15:8] : LUT_INIT[7:0];
@@ -136,11 +136,34 @@ module SB_LUT4 (output O, input I0, I1, I2, I3);
 	assign O = I0 ? s1[1] : s1[0];
 endmodule
 
-(* abc_box_id = 1, abc_carry="CI,CO", lib_whitebox *)
+(* lib_whitebox *)
 module SB_CARRY (output CO, input I0, I1, CI);
 	assign CO = (I0 && I1) || ((I0 || I1) && CI);
 endmodule
 
+(* abc_box_id = 1, abc_carry="CI,CO", lib_whitebox *)
+module \$__ICE40_CARRY_LUT4 (output CO, O, input A, B, CI);
+	SB_CARRY carry (
+		.I0(A),
+		.I1(B),
+		.CI(CI),
+		.CO(CO)
+	);
+	SB_LUT4 #(
+		//         I0: 1010 1010 1010 1010
+		//         I1: 1100 1100 1100 1100
+		//         I2: 1111 0000 1111 0000
+		//         I3: 1111 1111 0000 0000
+		.LUT_INIT(16'b 0110_1001_1001_0110)
+	) adder (
+		.I0(1'b0),
+		.I1(A),
+		.I2(B),
+		.I3(CI),
+		.O(O)
+	);
+endmodule
+
 // Positive Edge SiliconBlue FF Cells
 
 module SB_DFF (output `SB_DFF_REG, input C, D);
-- 
cgit v1.2.3


From 0f5bddcd792ed2da2b9a3eb12e775537f394e771 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Fri, 12 Jul 2019 00:52:31 -0700
Subject: ice40_opt to handle this box and opt back to SB_LUT4

---
 techlibs/ice40/ice40_opt.cc | 48 +++++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 48 insertions(+)

(limited to 'techlibs/ice40')

diff --git a/techlibs/ice40/ice40_opt.cc b/techlibs/ice40/ice40_opt.cc
index f528607d6..b22fc83fe 100644
--- a/techlibs/ice40/ice40_opt.cc
+++ b/techlibs/ice40/ice40_opt.cc
@@ -83,6 +83,54 @@ static void run_ice40_opts(Module *module)
 			}
 			continue;
 		}
+
+		if (cell->type == "$__ICE40_CARRY_LUT4")
+		{
+			SigSpec non_const_inputs, replacement_output;
+			int count_zeros = 0, count_ones = 0;
+
+			SigBit inbit[3] = {
+				cell->getPort("\\A"),
+				cell->getPort("\\B"),
+				cell->getPort("\\CI")
+			};
+			for (int i = 0; i < 3; i++)
+				if (inbit[i].wire == nullptr) {
+					if (inbit[i] == State::S1)
+						count_ones++;
+					else
+						count_zeros++;
+				} else
+					non_const_inputs.append(inbit[i]);
+
+			if (count_zeros >= 2)
+				replacement_output = State::S0;
+			else if (count_ones >= 2)
+				replacement_output = State::S1;
+			else if (GetSize(non_const_inputs) == 1)
+				replacement_output = non_const_inputs;
+
+			if (GetSize(replacement_output)) {
+				optimized_co.insert(sigmap(cell->getPort("\\CO")[0]));
+				module->connect(cell->getPort("\\CO")[0], replacement_output);
+				module->design->scratchpad_set_bool("opt.did_something", true);
+				log("Optimized SB_CARRY from $__ICE40_CARRY_LUT4 cell (leaving behind SB_LUT4) %s.%s: CO=%s\n",
+						log_id(module), log_id(cell), log_signal(replacement_output));
+				cell->type = "\\SB_LUT4";
+				sb_lut_cells.push_back(cell);
+				cell->setPort("\\I0", RTLIL::S0);
+				cell->setPort("\\I1", inbit[0]);
+				cell->setPort("\\I2", inbit[1]);
+				cell->setPort("\\I3", inbit[2]);
+				cell->unsetPort("\\A");
+				cell->unsetPort("\\B");
+				cell->unsetPort("\\CI");
+				cell->unsetPort("\\CO");
+				cell->setParam("\\LUT_INIT", std::string("0110100110010110"));
+				sb_lut_cells.push_back(cell);
+			}
+			continue;
+		}
 	}
 
 	for (auto cell : sb_lut_cells)
-- 
cgit v1.2.3


From 62ac5ebd02e18add18a11f4c19002f4059b091b7 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Fri, 12 Jul 2019 00:53:01 -0700
Subject: Map to and from this box if -abc9

---
 techlibs/ice40/synth_ice40.cc | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

(limited to 'techlibs/ice40')

diff --git a/techlibs/ice40/synth_ice40.cc b/techlibs/ice40/synth_ice40.cc
index 2c75215cb..59f6d1863 100644
--- a/techlibs/ice40/synth_ice40.cc
+++ b/techlibs/ice40/synth_ice40.cc
@@ -242,7 +242,7 @@ struct SynthIce40Pass : public ScriptPass
 	{
 		if (check_label("begin"))
 		{
-			run("read_verilog -lib -D_ABC +/ice40/cells_sim.v");
+			run("read_verilog -icells -lib -D_ABC +/ice40/cells_sim.v");
 			run(stringf("hierarchy -check %s", help_mode ? "-top <top>" : top_opt.c_str()));
 			run("proc");
 		}
@@ -298,7 +298,7 @@ struct SynthIce40Pass : public ScriptPass
 			if (nocarry)
 				run("techmap");
 			else
-				run("techmap -map +/techmap.v -map +/ice40/arith_map.v");
+				run("techmap -map +/techmap.v -map +/ice40/arith_map.v" + std::string(abc == "abc9" ? " -D _ABC" : ""));
 			if (retime || help_mode)
 				run(abc + " -dff", "(only if -retime)");
 			run("ice40_opt");
@@ -342,6 +342,7 @@ struct SynthIce40Pass : public ScriptPass
 					else
 						wire_delay = 250;
 					run(abc + stringf(" -W %d -lut +/ice40/abc_%s.lut -box +/ice40/abc_%s.box", wire_delay, device_opt.c_str(), device_opt.c_str()), "(skip if -noabc)");
+					run("techmap -D NO_LUT -D _ABC -map +/ice40/cells_map.v");
 				}
 				else
 					run(abc + " -dress -lut 4", "(skip if -noabc)");
-- 
cgit v1.2.3


From 4de03bd5e6cd72b3eb2a70d5735e7526d7a6f8a8 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Fri, 12 Jul 2019 01:08:48 -0700
Subject: Remove double push

---
 techlibs/ice40/ice40_opt.cc | 1 -
 1 file changed, 1 deletion(-)

(limited to 'techlibs/ice40')

diff --git a/techlibs/ice40/ice40_opt.cc b/techlibs/ice40/ice40_opt.cc
index b22fc83fe..4e50b250e 100644
--- a/techlibs/ice40/ice40_opt.cc
+++ b/techlibs/ice40/ice40_opt.cc
@@ -117,7 +117,6 @@ static void run_ice40_opts(Module *module)
 				log("Optimized SB_CARRY from $__ICE40_CARRY_LUT4 cell (leaving behind SB_LUT4) %s.%s: CO=%s\n",
 						log_id(module), log_id(cell), log_signal(replacement_output));
 				cell->type = "\\SB_LUT4";
-				sb_lut_cells.push_back(cell);
 				cell->setPort("\\I0", RTLIL::S0);
 				cell->setPort("\\I1", inbit[0]);
 				cell->setPort("\\I2", inbit[1]);
-- 
cgit v1.2.3


From e0e5d7d68eee0d1a83b048d9d9fde94673ff5673 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Fri, 12 Jul 2019 01:15:22 -0700
Subject: Fix spacing

---
 techlibs/ice40/arith_map.v | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'techlibs/ice40')

diff --git a/techlibs/ice40/arith_map.v b/techlibs/ice40/arith_map.v
index 6d45e4a6b..abba18c37 100644
--- a/techlibs/ice40/arith_map.v
+++ b/techlibs/ice40/arith_map.v
@@ -50,7 +50,7 @@ module _80_ice40_alu (A, B, CI, BI, X, Y, CO);
 			.B(BB[i]),
 			.CI(C[i]),
 			.CO(CO[i]),
-            .O(Y[i])
+			.O(Y[i])
 		);
 `else
 		SB_CARRY carry (
-- 
cgit v1.2.3


From 28274dfb09fb48637f82949ce601a417eb3d0b82 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Fri, 12 Jul 2019 01:17:53 -0700
Subject: Off by one

---
 techlibs/ice40/abc_u.box | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'techlibs/ice40')

diff --git a/techlibs/ice40/abc_u.box b/techlibs/ice40/abc_u.box
index 3a71addef..95c2c3d81 100644
--- a/techlibs/ice40/abc_u.box
+++ b/techlibs/ice40/abc_u.box
@@ -9,5 +9,5 @@
 #        input/output and have been moved there
 #        overriding the alphabetical ordering)
 $__ICE40_CARRY_LUT4 1 1 3 2
-1231 1205 875
+1231 1205 874
 675  609  278
-- 
cgit v1.2.3


From 7a912f22b2c3976d72a25ffd605a1cf598b67983 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Fri, 12 Jul 2019 01:32:10 -0700
Subject: Use Const::from_string() not its constructor...

---
 techlibs/ice40/ice40_opt.cc | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'techlibs/ice40')

diff --git a/techlibs/ice40/ice40_opt.cc b/techlibs/ice40/ice40_opt.cc
index 4e50b250e..67e8771b4 100644
--- a/techlibs/ice40/ice40_opt.cc
+++ b/techlibs/ice40/ice40_opt.cc
@@ -125,7 +125,7 @@ static void run_ice40_opts(Module *module)
 				cell->unsetPort("\\B");
 				cell->unsetPort("\\CI");
 				cell->unsetPort("\\CO");
-				cell->setParam("\\LUT_INIT", std::string("0110100110010110"));
+				cell->setParam("\\LUT_INIT", RTLIL::Const::from_string("0110100110010110"));
 				sb_lut_cells.push_back(cell);
 			}
 			continue;
-- 
cgit v1.2.3


From d032198facc05634bd617328e1865e7f0d8d953c Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Sat, 13 Jul 2019 01:11:00 -0700
Subject: ice40_opt to $__ICE40_CARRY_LUT4 into $lut not SB_LUT

---
 techlibs/ice40/ice40_opt.cc | 16 +++++++---------
 1 file changed, 7 insertions(+), 9 deletions(-)

(limited to 'techlibs/ice40')

diff --git a/techlibs/ice40/ice40_opt.cc b/techlibs/ice40/ice40_opt.cc
index 67e8771b4..38910dffa 100644
--- a/techlibs/ice40/ice40_opt.cc
+++ b/techlibs/ice40/ice40_opt.cc
@@ -114,19 +114,17 @@ static void run_ice40_opts(Module *module)
 				optimized_co.insert(sigmap(cell->getPort("\\CO")[0]));
 				module->connect(cell->getPort("\\CO")[0], replacement_output);
 				module->design->scratchpad_set_bool("opt.did_something", true);
-				log("Optimized SB_CARRY from $__ICE40_CARRY_LUT4 cell (leaving behind SB_LUT4) %s.%s: CO=%s\n",
+				log("Optimized $__ICE40_CARRY_LUT4 cell into $lut (without SB_CARRY) %s.%s: CO=%s\n",
 						log_id(module), log_id(cell), log_signal(replacement_output));
-				cell->type = "\\SB_LUT4";
-				cell->setPort("\\I0", RTLIL::S0);
-				cell->setPort("\\I1", inbit[0]);
-				cell->setPort("\\I2", inbit[1]);
-				cell->setPort("\\I3", inbit[2]);
-				cell->unsetPort("\\A");
+				cell->type = "$lut";
+				cell->setPort("\\A", { RTLIL::S0, inbit[0], inbit[1], inbit[2] });
+				cell->setPort("\\Y", cell->getPort("\\O"));
 				cell->unsetPort("\\B");
 				cell->unsetPort("\\CI");
 				cell->unsetPort("\\CO");
-				cell->setParam("\\LUT_INIT", RTLIL::Const::from_string("0110100110010110"));
-				sb_lut_cells.push_back(cell);
+				cell->unsetPort("\\O");
+				cell->setParam("\\LUT", RTLIL::Const::from_string("0110100110010110"));
+				cell->setParam("\\WIDTH", 4);
 			}
 			continue;
 		}
-- 
cgit v1.2.3


From 5fb27c071bb072644dbb38cf8a516628c2afe15b Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Mon, 15 Jul 2019 12:03:51 -0700
Subject: $__ICE40_CARRY_LUT4 -> $__ICE40_FULL_ADDER as per @whitequark

---
 techlibs/ice40/abc_hx.box   | 2 +-
 techlibs/ice40/abc_lp.box   | 2 +-
 techlibs/ice40/abc_u.box    | 2 +-
 techlibs/ice40/arith_map.v  | 2 +-
 techlibs/ice40/cells_map.v  | 2 +-
 techlibs/ice40/cells_sim.v  | 2 +-
 techlibs/ice40/ice40_opt.cc | 4 ++--
 7 files changed, 8 insertions(+), 8 deletions(-)

(limited to 'techlibs/ice40')

diff --git a/techlibs/ice40/abc_hx.box b/techlibs/ice40/abc_hx.box
index 4b55297dd..c0ea742e2 100644
--- a/techlibs/ice40/abc_hx.box
+++ b/techlibs/ice40/abc_hx.box
@@ -8,6 +8,6 @@
 #   (NB: carry chain input/output must be last
 #        input/output and have been moved there
 #        overriding the alphabetical ordering)
-$__ICE40_CARRY_LUT4 1 1 3 2
+$__ICE40_FULL_ADDER 1 1 3 2
 400 379 316
 259 231 126
diff --git a/techlibs/ice40/abc_lp.box b/techlibs/ice40/abc_lp.box
index b85346370..d73b6d649 100644
--- a/techlibs/ice40/abc_lp.box
+++ b/techlibs/ice40/abc_lp.box
@@ -8,6 +8,6 @@
 #   (NB: carry chain input/output must be last
 #        input/output and have been moved there
 #        overriding the alphabetical ordering)
-$__ICE40_CARRY_LUT4 1 1 3 2
+$__ICE40_FULL_ADDER 1 1 3 2
 589 558 465
 675 609 186 
diff --git a/techlibs/ice40/abc_u.box b/techlibs/ice40/abc_u.box
index 95c2c3d81..42d666051 100644
--- a/techlibs/ice40/abc_u.box
+++ b/techlibs/ice40/abc_u.box
@@ -8,6 +8,6 @@
 #   (NB: carry chain input/output must be last
 #        input/output and have been moved there
 #        overriding the alphabetical ordering)
-$__ICE40_CARRY_LUT4 1 1 3 2
+$__ICE40_FULL_ADDER 1 1 3 2
 1231 1205 874
 675  609  278
diff --git a/techlibs/ice40/arith_map.v b/techlibs/ice40/arith_map.v
index abba18c37..fe83a8e38 100644
--- a/techlibs/ice40/arith_map.v
+++ b/techlibs/ice40/arith_map.v
@@ -45,7 +45,7 @@ module _80_ice40_alu (A, B, CI, BI, X, Y, CO);
 	genvar i;
 	generate for (i = 0; i < Y_WIDTH; i = i + 1) begin:slice
 `ifdef _ABC
-		\$__ICE40_CARRY_LUT4 carry (
+		\$__ICE40_FULL_ADDER carry (
 			.A(AA[i]),
 			.B(BB[i]),
 			.CI(C[i]),
diff --git a/techlibs/ice40/cells_map.v b/techlibs/ice40/cells_map.v
index 5dca63e19..b4b831165 100644
--- a/techlibs/ice40/cells_map.v
+++ b/techlibs/ice40/cells_map.v
@@ -63,7 +63,7 @@ endmodule
 `endif
 
 `ifdef _ABC
-module \$__ICE40_CARRY_LUT4 (output CO, O, input A, B, CI);
+module \$__ICE40_FULL_ADDER (output CO, O, input A, B, CI);
   SB_CARRY carry (
     .I0(A),
     .I1(B),
diff --git a/techlibs/ice40/cells_sim.v b/techlibs/ice40/cells_sim.v
index cf36f5cfb..609facc93 100644
--- a/techlibs/ice40/cells_sim.v
+++ b/techlibs/ice40/cells_sim.v
@@ -142,7 +142,7 @@ module SB_CARRY (output CO, input I0, I1, CI);
 endmodule
 
 (* abc_box_id = 1, abc_carry="CI,CO", lib_whitebox *)
-module \$__ICE40_CARRY_LUT4 (output CO, O, input A, B, CI);
+module \$__ICE40_FULL_ADDER (output CO, O, input A, B, CI);
 	SB_CARRY carry (
 		.I0(A),
 		.I1(B),
diff --git a/techlibs/ice40/ice40_opt.cc b/techlibs/ice40/ice40_opt.cc
index 38910dffa..e492454fb 100644
--- a/techlibs/ice40/ice40_opt.cc
+++ b/techlibs/ice40/ice40_opt.cc
@@ -84,7 +84,7 @@ static void run_ice40_opts(Module *module)
 			continue;
 		}
 
-		if (cell->type == "$__ICE40_CARRY_LUT4")
+		if (cell->type == "$__ICE40_FULL_ADDER")
 		{
 			SigSpec non_const_inputs, replacement_output;
 			int count_zeros = 0, count_ones = 0;
@@ -114,7 +114,7 @@ static void run_ice40_opts(Module *module)
 				optimized_co.insert(sigmap(cell->getPort("\\CO")[0]));
 				module->connect(cell->getPort("\\CO")[0], replacement_output);
 				module->design->scratchpad_set_bool("opt.did_something", true);
-				log("Optimized $__ICE40_CARRY_LUT4 cell into $lut (without SB_CARRY) %s.%s: CO=%s\n",
+				log("Optimized $__ICE40_FULL_ADDER cell back to logic (without SB_CARRY) %s.%s: CO=%s\n",
 						log_id(module), log_id(cell), log_signal(replacement_output));
 				cell->type = "$lut";
 				cell->setPort("\\A", { RTLIL::S0, inbit[0], inbit[1], inbit[2] });
-- 
cgit v1.2.3


From ba099bfe9befccc42df99d2930fdbc686152187c Mon Sep 17 00:00:00 2001
From: whitequark <whitequark@whitequark.org>
Date: Thu, 11 Jul 2019 10:56:59 +0000
Subject: synth_{ice40,ecp5}: more sensible pass label naming.

---
 techlibs/ice40/synth_ice40.cc | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

(limited to 'techlibs/ice40')

diff --git a/techlibs/ice40/synth_ice40.cc b/techlibs/ice40/synth_ice40.cc
index 0474e76e9..1a20f7049 100644
--- a/techlibs/ice40/synth_ice40.cc
+++ b/techlibs/ice40/synth_ice40.cc
@@ -275,14 +275,14 @@ struct SynthIce40Pass : public ScriptPass
 			run("opt_clean");
 		}
 
-		if (!nobram && check_label("bram", "(skip if -nobram)"))
+		if (!nobram && check_label("map_bram", "(skip if -nobram)"))
 		{
 			run("memory_bram -rules +/ice40/brams.txt");
 			run("techmap -map +/ice40/brams_map.v");
 			run("ice40_braminit");
 		}
 
-		if (check_label("map"))
+		if (check_label("map_ffram"))
 		{
 			run("opt -fast -mux_undef -undriven -fine");
 			run("memory_map");
-- 
cgit v1.2.3


From f28e38de9994151ea4e22608441dbc9e116d7b8c Mon Sep 17 00:00:00 2001
From: Sylvain Munaut <tnt@246tNt.com>
Date: Tue, 16 Jul 2019 23:57:15 +0200
Subject: ice40: Adapt the relut process passes to the new $lut <=> SB_LUT4
 port map

The new mapping introduced in 437fec0d88b4a2ad172edf0d1a861a38845f3b1d
needed matching adaptation when converting and optimizing LUTs during
the relut process

Fixes #1187

(Diagnosis of the issue by @daveshah1 on IRC)

Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
---
 techlibs/ice40/ice40_unlut.cc | 6 +++---
 techlibs/ice40/synth_ice40.cc | 2 +-
 2 files changed, 4 insertions(+), 4 deletions(-)

(limited to 'techlibs/ice40')

diff --git a/techlibs/ice40/ice40_unlut.cc b/techlibs/ice40/ice40_unlut.cc
index d16e6e6a3..f3f70ac1f 100644
--- a/techlibs/ice40/ice40_unlut.cc
+++ b/techlibs/ice40/ice40_unlut.cc
@@ -56,10 +56,10 @@ static void run_ice40_unlut(Module *module)
 			cell->unsetParam("\\LUT_INIT");
 
 			cell->setPort("\\A", SigSpec({
-				get_bit_or_zero(cell->getPort("\\I3")),
-				get_bit_or_zero(cell->getPort("\\I2")),
+				get_bit_or_zero(cell->getPort("\\I0")),
 				get_bit_or_zero(cell->getPort("\\I1")),
-				get_bit_or_zero(cell->getPort("\\I0"))
+				get_bit_or_zero(cell->getPort("\\I2")),
+				get_bit_or_zero(cell->getPort("\\I3"))
 			}));
 			cell->setPort("\\Y", cell->getPort("\\O")[0]);
 			cell->unsetPort("\\I0");
diff --git a/techlibs/ice40/synth_ice40.cc b/techlibs/ice40/synth_ice40.cc
index b3d30791a..78ac5ea13 100644
--- a/techlibs/ice40/synth_ice40.cc
+++ b/techlibs/ice40/synth_ice40.cc
@@ -345,7 +345,7 @@ struct SynthIce40Pass : public ScriptPass
 			}
 			run("clean");
 			run("ice40_unlut");
-			run("opt_lut -dlogic SB_CARRY:I0=1:I1=2:CI=3");
+			run("opt_lut -dlogic SB_CARRY:I0=2:I1=1:CI=0");
 		}
 
 		if (check_label("map_cells"))
-- 
cgit v1.2.3


From f7753720feaf466a089f4b96fca27ed4130b5be8 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Fri, 19 Jul 2019 08:45:35 -0700
Subject: Don't copy ref if exists already

---
 techlibs/ice40/tests/test_dsp_model.sh | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

(limited to 'techlibs/ice40')

diff --git a/techlibs/ice40/tests/test_dsp_model.sh b/techlibs/ice40/tests/test_dsp_model.sh
index 1bc0cc688..2d42c23ad 100644
--- a/techlibs/ice40/tests/test_dsp_model.sh
+++ b/techlibs/ice40/tests/test_dsp_model.sh
@@ -1,7 +1,9 @@
 #!/bin/bash
 set -ex
 sed 's/SB_MAC16/SB_MAC16_UUT/; /SB_MAC16_UUT/,/endmodule/ p; d;' < ../cells_sim.v > test_dsp_model_uut.v
-cat /opt/lscc/iCEcube2.2017.01/verilog/sb_ice_syn.v > test_dsp_model_ref.v
+if [ ! -f "test_dsp_model_ref.v" ]; then
+	cat /opt/lscc/iCEcube2.2017.01/verilog/sb_ice_syn.v > test_dsp_model_ref.v
+fi
 for tb in testbench \
 		testbench_comb_8x8_A testbench_comb_8x8_B testbench_comb_16x16 \
 		testbench_seq_16x16_A testbench_seq_16x16_B
-- 
cgit v1.2.3


From 171cd2ff738cdb8027b9b6efb988bab8744264a9 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Fri, 19 Jul 2019 08:52:49 -0700
Subject: Add tests for all combinations of A and B signedness for comb mul

---
 techlibs/ice40/tests/test_dsp_model.sh |   5 +-
 techlibs/ice40/tests/test_dsp_model.v  | 225 +++++++++++++++++++++++++++++++++
 2 files changed, 229 insertions(+), 1 deletion(-)

(limited to 'techlibs/ice40')

diff --git a/techlibs/ice40/tests/test_dsp_model.sh b/techlibs/ice40/tests/test_dsp_model.sh
index 2d42c23ad..75f95ab29 100644
--- a/techlibs/ice40/tests/test_dsp_model.sh
+++ b/techlibs/ice40/tests/test_dsp_model.sh
@@ -6,7 +6,10 @@ if [ ! -f "test_dsp_model_ref.v" ]; then
 fi
 for tb in testbench \
 		testbench_comb_8x8_A testbench_comb_8x8_B testbench_comb_16x16 \
-		testbench_seq_16x16_A testbench_seq_16x16_B
+		testbench_seq_16x16_A testbench_seq_16x16_B \
+		testbench_comb_8x8_A_signedA testbench_comb_8x8_A_signedB testbench_comb_8x8_A_signedAB \
+		testbench_comb_8x8_B_signedA testbench_comb_8x8_B_signedB testbench_comb_8x8_B_signedAB \
+		testbench_comb_16x16_B_signedA testbench_comb_16x16_B_signedB testbench_comb_16x16_B_signedAB
 do
 	iverilog -s $tb -o test_dsp_model test_dsp_model.v test_dsp_model_uut.v test_dsp_model_ref.v
 	vvp -N ./test_dsp_model
diff --git a/techlibs/ice40/tests/test_dsp_model.v b/techlibs/ice40/tests/test_dsp_model.v
index 594bd4ad3..f4f6858f0 100644
--- a/techlibs/ice40/tests/test_dsp_model.v
+++ b/techlibs/ice40/tests/test_dsp_model.v
@@ -241,6 +241,81 @@ module testbench_comb_8x8_A;
 	) testbench ();
 endmodule
 
+module testbench_comb_8x8_A_signedA;
+	testbench #(
+		.NEG_TRIGGER               (0),
+		.C_REG                     (0),
+		.A_REG                     (0),
+		.B_REG                     (0),
+		.D_REG                     (0),
+		.TOP_8x8_MULT_REG          (0),
+		.BOT_8x8_MULT_REG          (0),
+		.PIPELINE_16x16_MULT_REG1  (0),
+		.PIPELINE_16x16_MULT_REG2  (0),
+		.TOPOUTPUT_SELECT          (2),   // 0=P, 1=Q, 2=8x8, 3=16x16
+		.TOPADDSUB_LOWERINPUT      (0),   // 0=A, 1=8x8, 2=16x16, 3=S-EXT
+		.TOPADDSUB_UPPERINPUT      (0),   // 0=Q, 1=C
+		.TOPADDSUB_CARRYSELECT     (0),   // 0=0, 1=1, 2=ACI, 3=CI
+		.BOTOUTPUT_SELECT          (2),   // 0=R, 1=S, 2=8x8, 3=16x16
+		.BOTADDSUB_LOWERINPUT      (0),   // 0=B, 1=8x8, 2=16x16, 3=S-EXT
+		.BOTADDSUB_UPPERINPUT      (0),   // 0=S, 1=D
+		.BOTADDSUB_CARRYSELECT     (0),   // 0=0, 1=1, 2=ACI, 3=CI
+		.MODE_8x8                  (0),
+		.A_SIGNED                  (1),
+		.B_SIGNED                  (0)
+	) testbench ();
+endmodule
+
+module testbench_comb_8x8_A_signedB;
+	testbench #(
+		.NEG_TRIGGER               (0),
+		.C_REG                     (0),
+		.A_REG                     (0),
+		.B_REG                     (0),
+		.D_REG                     (0),
+		.TOP_8x8_MULT_REG          (0),
+		.BOT_8x8_MULT_REG          (0),
+		.PIPELINE_16x16_MULT_REG1  (0),
+		.PIPELINE_16x16_MULT_REG2  (0),
+		.TOPOUTPUT_SELECT          (2),   // 0=P, 1=Q, 2=8x8, 3=16x16
+		.TOPADDSUB_LOWERINPUT      (0),   // 0=A, 1=8x8, 2=16x16, 3=S-EXT
+		.TOPADDSUB_UPPERINPUT      (0),   // 0=Q, 1=C
+		.TOPADDSUB_CARRYSELECT     (0),   // 0=0, 1=1, 2=ACI, 3=CI
+		.BOTOUTPUT_SELECT          (2),   // 0=R, 1=S, 2=8x8, 3=16x16
+		.BOTADDSUB_LOWERINPUT      (0),   // 0=B, 1=8x8, 2=16x16, 3=S-EXT
+		.BOTADDSUB_UPPERINPUT      (0),   // 0=S, 1=D
+		.BOTADDSUB_CARRYSELECT     (0),   // 0=0, 1=1, 2=ACI, 3=CI
+		.MODE_8x8                  (0),
+		.A_SIGNED                  (0),
+		.B_SIGNED                  (1)
+	) testbench ();
+endmodule
+
+module testbench_comb_8x8_A_signedAB;
+	testbench #(
+		.NEG_TRIGGER               (0),
+		.C_REG                     (0),
+		.A_REG                     (0),
+		.B_REG                     (0),
+		.D_REG                     (0),
+		.TOP_8x8_MULT_REG          (0),
+		.BOT_8x8_MULT_REG          (0),
+		.PIPELINE_16x16_MULT_REG1  (0),
+		.PIPELINE_16x16_MULT_REG2  (0),
+		.TOPOUTPUT_SELECT          (2),   // 0=P, 1=Q, 2=8x8, 3=16x16
+		.TOPADDSUB_LOWERINPUT      (0),   // 0=A, 1=8x8, 2=16x16, 3=S-EXT
+		.TOPADDSUB_UPPERINPUT      (0),   // 0=Q, 1=C
+		.TOPADDSUB_CARRYSELECT     (0),   // 0=0, 1=1, 2=ACI, 3=CI
+		.BOTOUTPUT_SELECT          (2),   // 0=R, 1=S, 2=8x8, 3=16x16
+		.BOTADDSUB_LOWERINPUT      (0),   // 0=B, 1=8x8, 2=16x16, 3=S-EXT
+		.BOTADDSUB_UPPERINPUT      (0),   // 0=S, 1=D
+		.BOTADDSUB_CARRYSELECT     (0),   // 0=0, 1=1, 2=ACI, 3=CI
+		.MODE_8x8                  (0),
+		.A_SIGNED                  (1),
+		.B_SIGNED                  (1)
+	) testbench ();
+endmodule
+
 module testbench_comb_8x8_B;
 	testbench #(
 		.NEG_TRIGGER               (0),
@@ -266,6 +341,81 @@ module testbench_comb_8x8_B;
 	) testbench ();
 endmodule
 
+module testbench_comb_8x8_B_signedA;
+	testbench #(
+		.NEG_TRIGGER               (0),
+		.C_REG                     (0),
+		.A_REG                     (0),
+		.B_REG                     (0),
+		.D_REG                     (0),
+		.TOP_8x8_MULT_REG          (0),
+		.BOT_8x8_MULT_REG          (0),
+		.PIPELINE_16x16_MULT_REG1  (0),
+		.PIPELINE_16x16_MULT_REG2  (0),
+		.TOPOUTPUT_SELECT          (0),   // 0=P, 1=Q, 2=8x8, 3=16x16
+		.TOPADDSUB_LOWERINPUT      (1),   // 0=A, 1=8x8, 2=16x16, 3=S-EXT
+		.TOPADDSUB_UPPERINPUT      (1),   // 0=Q, 1=C
+		.TOPADDSUB_CARRYSELECT     (0),   // 0=0, 1=1, 2=ACI, 3=CI
+		.BOTOUTPUT_SELECT          (0),   // 0=R, 1=S, 2=8x8, 3=16x16
+		.BOTADDSUB_LOWERINPUT      (1),   // 0=B, 1=8x8, 2=16x16, 3=S-EXT
+		.BOTADDSUB_UPPERINPUT      (1),   // 0=S, 1=D
+		.BOTADDSUB_CARRYSELECT     (0),   // 0=0, 1=1, 2=ACI, 3=CI
+		.MODE_8x8                  (0),
+		.A_SIGNED                  (1),
+		.B_SIGNED                  (0)
+	) testbench ();
+endmodule
+
+module testbench_comb_8x8_B_signedB;
+	testbench #(
+		.NEG_TRIGGER               (0),
+		.C_REG                     (0),
+		.A_REG                     (0),
+		.B_REG                     (0),
+		.D_REG                     (0),
+		.TOP_8x8_MULT_REG          (0),
+		.BOT_8x8_MULT_REG          (0),
+		.PIPELINE_16x16_MULT_REG1  (0),
+		.PIPELINE_16x16_MULT_REG2  (0),
+		.TOPOUTPUT_SELECT          (0),   // 0=P, 1=Q, 2=8x8, 3=16x16
+		.TOPADDSUB_LOWERINPUT      (1),   // 0=A, 1=8x8, 2=16x16, 3=S-EXT
+		.TOPADDSUB_UPPERINPUT      (1),   // 0=Q, 1=C
+		.TOPADDSUB_CARRYSELECT     (0),   // 0=0, 1=1, 2=ACI, 3=CI
+		.BOTOUTPUT_SELECT          (0),   // 0=R, 1=S, 2=8x8, 3=16x16
+		.BOTADDSUB_LOWERINPUT      (1),   // 0=B, 1=8x8, 2=16x16, 3=S-EXT
+		.BOTADDSUB_UPPERINPUT      (1),   // 0=S, 1=D
+		.BOTADDSUB_CARRYSELECT     (0),   // 0=0, 1=1, 2=ACI, 3=CI
+		.MODE_8x8                  (0),
+		.A_SIGNED                  (0),
+		.B_SIGNED                  (1)
+	) testbench ();
+endmodule
+
+module testbench_comb_8x8_B_signedAB;
+	testbench #(
+		.NEG_TRIGGER               (0),
+		.C_REG                     (0),
+		.A_REG                     (0),
+		.B_REG                     (0),
+		.D_REG                     (0),
+		.TOP_8x8_MULT_REG          (0),
+		.BOT_8x8_MULT_REG          (0),
+		.PIPELINE_16x16_MULT_REG1  (0),
+		.PIPELINE_16x16_MULT_REG2  (0),
+		.TOPOUTPUT_SELECT          (0),   // 0=P, 1=Q, 2=8x8, 3=16x16
+		.TOPADDSUB_LOWERINPUT      (1),   // 0=A, 1=8x8, 2=16x16, 3=S-EXT
+		.TOPADDSUB_UPPERINPUT      (1),   // 0=Q, 1=C
+		.TOPADDSUB_CARRYSELECT     (0),   // 0=0, 1=1, 2=ACI, 3=CI
+		.BOTOUTPUT_SELECT          (0),   // 0=R, 1=S, 2=8x8, 3=16x16
+		.BOTADDSUB_LOWERINPUT      (1),   // 0=B, 1=8x8, 2=16x16, 3=S-EXT
+		.BOTADDSUB_UPPERINPUT      (1),   // 0=S, 1=D
+		.BOTADDSUB_CARRYSELECT     (0),   // 0=0, 1=1, 2=ACI, 3=CI
+		.MODE_8x8                  (0),
+		.A_SIGNED                  (1),
+		.B_SIGNED                  (1)
+	) testbench ();
+endmodule
+
 module testbench_comb_16x16;
 	testbench #(
 		.NEG_TRIGGER               (0),
@@ -291,6 +441,81 @@ module testbench_comb_16x16;
 	) testbench ();
 endmodule
 
+module testbench_comb_16x16_signedA;
+	testbench #(
+		.NEG_TRIGGER               (0),
+		.C_REG                     (0),
+		.A_REG                     (0),
+		.B_REG                     (0),
+		.D_REG                     (0),
+		.TOP_8x8_MULT_REG          (0),
+		.BOT_8x8_MULT_REG          (0),
+		.PIPELINE_16x16_MULT_REG1  (0),
+		.PIPELINE_16x16_MULT_REG2  (0),
+		.TOPOUTPUT_SELECT          (0),   // 0=P, 1=Q, 2=8x8, 3=16x16
+		.TOPADDSUB_LOWERINPUT      (2),   // 0=A, 1=8x8, 2=16x16, 3=S-EXT
+		.TOPADDSUB_UPPERINPUT      (1),   // 0=Q, 1=C
+		.TOPADDSUB_CARRYSELECT     (2),   // 0=0, 1=1, 2=ACI, 3=CI
+		.BOTOUTPUT_SELECT          (0),   // 0=R, 1=S, 2=8x8, 3=16x16
+		.BOTADDSUB_LOWERINPUT      (2),   // 0=B, 1=8x8, 2=16x16, 3=S-EXT
+		.BOTADDSUB_UPPERINPUT      (1),   // 0=S, 1=D
+		.BOTADDSUB_CARRYSELECT     (2),   // 0=0, 1=1, 2=ACI, 3=CI
+		.MODE_8x8                  (0),
+		.A_SIGNED                  (1),
+		.B_SIGNED                  (0)
+	) testbench ();
+endmodule
+
+module testbench_comb_16x16_signedB;
+	testbench #(
+		.NEG_TRIGGER               (0),
+		.C_REG                     (0),
+		.A_REG                     (0),
+		.B_REG                     (0),
+		.D_REG                     (0),
+		.TOP_8x8_MULT_REG          (0),
+		.BOT_8x8_MULT_REG          (0),
+		.PIPELINE_16x16_MULT_REG1  (0),
+		.PIPELINE_16x16_MULT_REG2  (0),
+		.TOPOUTPUT_SELECT          (0),   // 0=P, 1=Q, 2=8x8, 3=16x16
+		.TOPADDSUB_LOWERINPUT      (2),   // 0=A, 1=8x8, 2=16x16, 3=S-EXT
+		.TOPADDSUB_UPPERINPUT      (1),   // 0=Q, 1=C
+		.TOPADDSUB_CARRYSELECT     (2),   // 0=0, 1=1, 2=ACI, 3=CI
+		.BOTOUTPUT_SELECT          (0),   // 0=R, 1=S, 2=8x8, 3=16x16
+		.BOTADDSUB_LOWERINPUT      (2),   // 0=B, 1=8x8, 2=16x16, 3=S-EXT
+		.BOTADDSUB_UPPERINPUT      (1),   // 0=S, 1=D
+		.BOTADDSUB_CARRYSELECT     (2),   // 0=0, 1=1, 2=ACI, 3=CI
+		.MODE_8x8                  (0),
+		.A_SIGNED                  (0),
+		.B_SIGNED                  (1)
+	) testbench ();
+endmodule
+
+module testbench_comb_16x16_signedAB;
+	testbench #(
+		.NEG_TRIGGER               (0),
+		.C_REG                     (0),
+		.A_REG                     (0),
+		.B_REG                     (0),
+		.D_REG                     (0),
+		.TOP_8x8_MULT_REG          (0),
+		.BOT_8x8_MULT_REG          (0),
+		.PIPELINE_16x16_MULT_REG1  (0),
+		.PIPELINE_16x16_MULT_REG2  (0),
+		.TOPOUTPUT_SELECT          (0),   // 0=P, 1=Q, 2=8x8, 3=16x16
+		.TOPADDSUB_LOWERINPUT      (2),   // 0=A, 1=8x8, 2=16x16, 3=S-EXT
+		.TOPADDSUB_UPPERINPUT      (1),   // 0=Q, 1=C
+		.TOPADDSUB_CARRYSELECT     (2),   // 0=0, 1=1, 2=ACI, 3=CI
+		.BOTOUTPUT_SELECT          (0),   // 0=R, 1=S, 2=8x8, 3=16x16
+		.BOTADDSUB_LOWERINPUT      (2),   // 0=B, 1=8x8, 2=16x16, 3=S-EXT
+		.BOTADDSUB_UPPERINPUT      (1),   // 0=S, 1=D
+		.BOTADDSUB_CARRYSELECT     (2),   // 0=0, 1=1, 2=ACI, 3=CI
+		.MODE_8x8                  (0),
+		.A_SIGNED                  (1),
+		.B_SIGNED                  (1)
+	) testbench ();
+endmodule
+
 module testbench_seq_16x16_A;
 	testbench #(
 		.NEG_TRIGGER               (0),
-- 
cgit v1.2.3


From 3c84271543379a5a3845d5dcdb49a5e6fbafbc66 Mon Sep 17 00:00:00 2001
From: David Shah <dave@ds0.me>
Date: Fri, 19 Jul 2019 17:13:34 +0100
Subject: ice40/cells_sim.v: LSB of A/B only signed in 8x8 mode

Signed-off-by: David Shah <dave@ds0.me>
---
 techlibs/ice40/cells_sim.v | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

(limited to 'techlibs/ice40')

diff --git a/techlibs/ice40/cells_sim.v b/techlibs/ice40/cells_sim.v
index 609facc93..4402f8d36 100644
--- a/techlibs/ice40/cells_sim.v
+++ b/techlibs/ice40/cells_sim.v
@@ -1363,9 +1363,9 @@ module SB_MAC16 (
 	wire [15:0] p_Ah_Bh, p_Al_Bh, p_Ah_Bl, p_Al_Bl;
 	wire [15:0] Ah, Al, Bh, Bl;
 	assign Ah = {A_SIGNED ? {8{iA[15]}} : 8'b0, iA[15: 8]};
-	assign Al = {A_SIGNED ? {8{iA[ 7]}} : 8'b0, iA[ 7: 0]};
+	assign Al = {A_SIGNED && MODE_8x8 ? {8{iA[ 7]}} : 8'b0, iA[ 7: 0]};
 	assign Bh = {B_SIGNED ? {8{iB[15]}} : 8'b0, iB[15: 8]};
-	assign Bl = {B_SIGNED ? {8{iB[ 7]}} : 8'b0, iB[ 7: 0]};
+	assign Bl = {B_SIGNED && MODE_8x8 ? {8{iB[ 7]}} : 8'b0, iB[ 7: 0]};
 	assign p_Ah_Bh = Ah * Bh;
 	assign p_Al_Bh = Al * Bh;
 	assign p_Ah_Bl = Ah * Bl;
-- 
cgit v1.2.3


From 79f14c751417685e7405855a96fc7a37f5bc7fbf Mon Sep 17 00:00:00 2001
From: David Shah <dave@ds0.me>
Date: Fri, 19 Jul 2019 17:33:41 +0100
Subject: ice40/cells_sim.v: Fix sign of J and K partial products

Signed-off-by: David Shah <dave@ds0.me>
---
 techlibs/ice40/cells_sim.v | 12 +++++++-----
 1 file changed, 7 insertions(+), 5 deletions(-)

(limited to 'techlibs/ice40')

diff --git a/techlibs/ice40/cells_sim.v b/techlibs/ice40/cells_sim.v
index 4402f8d36..2205be27d 100644
--- a/techlibs/ice40/cells_sim.v
+++ b/techlibs/ice40/cells_sim.v
@@ -1366,10 +1366,10 @@ module SB_MAC16 (
 	assign Al = {A_SIGNED && MODE_8x8 ? {8{iA[ 7]}} : 8'b0, iA[ 7: 0]};
 	assign Bh = {B_SIGNED ? {8{iB[15]}} : 8'b0, iB[15: 8]};
 	assign Bl = {B_SIGNED && MODE_8x8 ? {8{iB[ 7]}} : 8'b0, iB[ 7: 0]};
-	assign p_Ah_Bh = Ah * Bh;
-	assign p_Al_Bh = Al * Bh;
-	assign p_Ah_Bl = Ah * Bl;
-	assign p_Al_Bl = Al * Bl;
+	assign p_Ah_Bh = Ah * Bh; // F
+	assign p_Al_Bh = {8'b0, Al[7:0]} * Bh; // J
+	assign p_Ah_Bl = Ah * {8'b0, Bl[7:0]}; // K
+	assign p_Al_Bl = Al * Bl; // G
 
 	// Regs F and J
 	reg [15:0] rF, rJ;
@@ -1400,7 +1400,9 @@ module SB_MAC16 (
 	assign iG = BOT_8x8_MULT_REG ? rG : p_Al_Bl;
 
 	// Adder Stage
-	assign iL = iG + (iK << 8) + (iJ << 8) + (iF << 16);
+	wire [23:0] iK_e = {A_SIGNED ? {8{iK[15]}} : 8'b0, iK};
+	wire [23:0] iJ_e = {B_SIGNED ? {8{iJ[15]}} : 8'b0, iJ};
+	assign iL = iG + (iK_e << 8) + (iJ_e << 8) + (iF << 16);
 
 	// Reg H
 	reg [31:0] rH;
-- 
cgit v1.2.3


From 80884d6f7bd10d79e89ad3893ae557aa64af9742 Mon Sep 17 00:00:00 2001
From: David Shah <dave@ds0.me>
Date: Fri, 19 Jul 2019 17:33:57 +0100
Subject: ice40: Fix test_dsp_model.sh

Signed-off-by: David Shah <dave@ds0.me>
---
 techlibs/ice40/tests/test_dsp_model.sh | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'techlibs/ice40')

diff --git a/techlibs/ice40/tests/test_dsp_model.sh b/techlibs/ice40/tests/test_dsp_model.sh
index 75f95ab29..1e564d1b2 100644
--- a/techlibs/ice40/tests/test_dsp_model.sh
+++ b/techlibs/ice40/tests/test_dsp_model.sh
@@ -9,7 +9,7 @@ for tb in testbench \
 		testbench_seq_16x16_A testbench_seq_16x16_B \
 		testbench_comb_8x8_A_signedA testbench_comb_8x8_A_signedB testbench_comb_8x8_A_signedAB \
 		testbench_comb_8x8_B_signedA testbench_comb_8x8_B_signedB testbench_comb_8x8_B_signedAB \
-		testbench_comb_16x16_B_signedA testbench_comb_16x16_B_signedB testbench_comb_16x16_B_signedAB
+		testbench_comb_16x16_signedA testbench_comb_16x16_signedB testbench_comb_16x16_signedAB
 do
 	iverilog -s $tb -o test_dsp_model test_dsp_model.v test_dsp_model_uut.v test_dsp_model_ref.v
 	vvp -N ./test_dsp_model
-- 
cgit v1.2.3


From 48d0f994064557dc0832748e17133ee2eac88cbf Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Wed, 7 Aug 2019 11:09:17 -0700
Subject: stoi -> atoi

---
 techlibs/ice40/synth_ice40.cc | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'techlibs/ice40')

diff --git a/techlibs/ice40/synth_ice40.cc b/techlibs/ice40/synth_ice40.cc
index be60a0071..dc04eed67 100644
--- a/techlibs/ice40/synth_ice40.cc
+++ b/techlibs/ice40/synth_ice40.cc
@@ -183,7 +183,7 @@ struct SynthIce40Pass : public ScriptPass
 				continue;
 			}
 			if (args[argidx] == "-dffe_min_ce_use" && argidx+1 < args.size()) {
-				min_ce_use = std::stoi(args[++argidx]);
+				min_ce_use = atoi(args[++argidx].c_str());
 				continue;
 			}
 			if (args[argidx] == "-nobram") {
-- 
cgit v1.2.3


From 71649969213863b2695f1c51956886fc7879c3e6 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Wed, 7 Aug 2019 11:12:38 -0700
Subject: RTLIL::S{0,1} -> State::S{0,1}

---
 techlibs/ice40/ice40_opt.cc | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'techlibs/ice40')

diff --git a/techlibs/ice40/ice40_opt.cc b/techlibs/ice40/ice40_opt.cc
index e492454fb..d5106b805 100644
--- a/techlibs/ice40/ice40_opt.cc
+++ b/techlibs/ice40/ice40_opt.cc
@@ -117,7 +117,7 @@ static void run_ice40_opts(Module *module)
 				log("Optimized $__ICE40_FULL_ADDER cell back to logic (without SB_CARRY) %s.%s: CO=%s\n",
 						log_id(module), log_id(cell), log_signal(replacement_output));
 				cell->type = "$lut";
-				cell->setPort("\\A", { RTLIL::S0, inbit[0], inbit[1], inbit[2] });
+				cell->setPort("\\A", { State::S0, inbit[0], inbit[1], inbit[2] });
 				cell->setPort("\\Y", cell->getPort("\\O"));
 				cell->unsetPort("\\B");
 				cell->unsetPort("\\CI");
-- 
cgit v1.2.3


From 6d77236f3845cd8785e7bdd4da3c5ef966be6043 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Wed, 7 Aug 2019 12:20:08 -0700
Subject: substr() -> compare()

---
 techlibs/ice40/ice40_braminit.cc | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

(limited to 'techlibs/ice40')

diff --git a/techlibs/ice40/ice40_braminit.cc b/techlibs/ice40/ice40_braminit.cc
index 4fa6b0792..1a139ffea 100644
--- a/techlibs/ice40/ice40_braminit.cc
+++ b/techlibs/ice40/ice40_braminit.cc
@@ -69,13 +69,13 @@ static void run_ice40_braminit(Module *module)
 
 			for (int i = 0; i < GetSize(line); i++)
 			{
-				if (in_comment && line.substr(i, 2) == "*/") {
+				if (in_comment && line.compare(i, 2, "*/") == 0) {
 					line[i] = ' ';
 					line[i+1] = ' ';
 					in_comment = false;
 					continue;
 				}
-				if (!in_comment && line.substr(i, 2) == "/*")
+				if (!in_comment && line.compare(i, 2, "/*") == 0)
 					in_comment = true;
 				if (in_comment)
 					line[i] = ' ';
@@ -87,7 +87,7 @@ static void run_ice40_braminit(Module *module)
 				long value;
 
 				token = next_token(line, " \t\r\n");
-				if (token.empty() || token.substr(0, 2) == "//")
+				if (token.empty() || token.compare(0, 2, "//") == 0)
 					break;
 
 				if (token[0] == '@') {
-- 
cgit v1.2.3


From 6b314c8371bbd8bb999f5ad330aa71c803755d54 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Wed, 7 Aug 2019 14:50:59 -0700
Subject: Wrap SB_CARRY+SB_LUT into $__ICE40_FULL_ADDER

---
 techlibs/ice40/arith_map.v    | 22 ----------------------
 techlibs/ice40/cells_map.v    | 22 ++++++++++------------
 techlibs/ice40/synth_ice40.cc |  9 ++++-----
 3 files changed, 14 insertions(+), 39 deletions(-)

(limited to 'techlibs/ice40')

diff --git a/techlibs/ice40/arith_map.v b/techlibs/ice40/arith_map.v
index fe83a8e38..65f28c585 100644
--- a/techlibs/ice40/arith_map.v
+++ b/techlibs/ice40/arith_map.v
@@ -44,7 +44,6 @@ module _80_ice40_alu (A, B, CI, BI, X, Y, CO);
 
 	genvar i;
 	generate for (i = 0; i < Y_WIDTH; i = i + 1) begin:slice
-`ifdef _ABC
 		\$__ICE40_FULL_ADDER carry (
 			.A(AA[i]),
 			.B(BB[i]),
@@ -52,27 +51,6 @@ module _80_ice40_alu (A, B, CI, BI, X, Y, CO);
 			.CO(CO[i]),
 			.O(Y[i])
 		);
-`else
-		SB_CARRY carry (
-			.I0(AA[i]),
-			.I1(BB[i]),
-			.CI(C[i]),
-			.CO(CO[i])
-		);
-		SB_LUT4 #(
-			//         I0: 1010 1010 1010 1010
-			//         I1: 1100 1100 1100 1100
-			//         I2: 1111 0000 1111 0000
-			//         I3: 1111 1111 0000 0000
-			.LUT_INIT(16'b 0110_1001_1001_0110)
-		) adder (
-			.I0(1'b0),
-			.I1(AA[i]),
-			.I2(BB[i]),
-			.I3(C[i]),
-			.O(Y[i])
-		);
-`endif
 	end endgenerate
 
 	assign X = AA ^ BB;
diff --git a/techlibs/ice40/cells_map.v b/techlibs/ice40/cells_map.v
index b4b831165..511b7f6c6 100644
--- a/techlibs/ice40/cells_map.v
+++ b/techlibs/ice40/cells_map.v
@@ -62,7 +62,7 @@ module \$lut (A, Y);
 endmodule
 `endif
 
-`ifdef _ABC
+`ifndef NO_ADDER
 module \$__ICE40_FULL_ADDER (output CO, O, input A, B, CI);
   SB_CARRY carry (
     .I0(A),
@@ -70,18 +70,16 @@ module \$__ICE40_FULL_ADDER (output CO, O, input A, B, CI);
     .CI(CI),
     .CO(CO)
   );
-  SB_LUT4 #(
-    //         I0: 1010 1010 1010 1010
-    //         I1: 1100 1100 1100 1100
-    //         I2: 1111 0000 1111 0000
-    //         I3: 1111 1111 0000 0000
-    .LUT_INIT(16'b 0110_1001_1001_0110)
+  \$lut #(
+    .WIDTH(4),
+    //    A[0]: 1010 1010 1010 1010
+    //    A[1]: 1100 1100 1100 1100
+    //    A[2]: 1111 0000 1111 0000
+    //    A[3]: 1111 1111 0000 0000
+    .LUT(16'b 0110_1001_1001_0110)
   ) adder (
-    .I0(1'b0),
-    .I1(A),
-    .I2(B),
-    .I3(CI),
-    .O(O)
+    .A({CI,B,A,1'b0}),
+    .Y(O)
   );
 endmodule
 `endif
diff --git a/techlibs/ice40/synth_ice40.cc b/techlibs/ice40/synth_ice40.cc
index be60a0071..93d5dcbd4 100644
--- a/techlibs/ice40/synth_ice40.cc
+++ b/techlibs/ice40/synth_ice40.cc
@@ -238,7 +238,7 @@ struct SynthIce40Pass : public ScriptPass
 	{
 		if (check_label("begin"))
 		{
-			run("read_verilog -icells -lib -D_ABC +/ice40/cells_sim.v");
+			run("read_verilog -icells -lib +/ice40/cells_sim.v");
 			run(stringf("hierarchy -check %s", help_mode ? "-top <top>" : top_opt.c_str()));
 			run("proc");
 		}
@@ -294,7 +294,7 @@ struct SynthIce40Pass : public ScriptPass
 			if (nocarry)
 				run("techmap");
 			else
-				run("techmap -map +/techmap.v -map +/ice40/arith_map.v" + std::string(abc == "abc9" ? " -D _ABC" : ""));
+				run("techmap -map +/techmap.v -map +/ice40/arith_map.v");
 			if (retime || help_mode)
 				run(abc + " -dff", "(only if -retime)");
 			run("ice40_opt");
@@ -309,7 +309,7 @@ struct SynthIce40Pass : public ScriptPass
 				run("opt_merge");
 				run(stringf("dff2dffe -unmap-mince %d", min_ce_use));
 			}
-			run("techmap -D NO_LUT -map +/ice40/cells_map.v");
+			run("techmap -D NO_LUT -D NO_ADDER -map +/ice40/cells_map.v");
 			run("opt_expr -mux_undef");
 			run("simplemap");
 			run("ice40_ffinit");
@@ -338,13 +338,12 @@ struct SynthIce40Pass : public ScriptPass
 					else
 						wire_delay = 250;
 					run(abc + stringf(" -W %d -lut +/ice40/abc_%s.lut -box +/ice40/abc_%s.box", wire_delay, device_opt.c_str(), device_opt.c_str()), "(skip if -noabc)");
-					run("techmap -D NO_LUT -D _ABC -map +/ice40/cells_map.v");
 				}
 				else
 					run(abc + " -dress -lut 4", "(skip if -noabc)");
 			}
+			run("techmap -D NO_LUT -map +/ice40/cells_map.v");
 			run("clean");
-			run("ice40_unlut");
 			run("opt_lut -dlogic SB_CARRY:I0=2:I1=1:CI=0");
 		}
 
-- 
cgit v1.2.3


From ea8ac8fd7484cc7c3b8929ae339f9aeb49403c36 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Wed, 7 Aug 2019 14:52:56 -0700
Subject: Remove ice40_unlut

---
 techlibs/ice40/Makefile.inc   |   1 -
 techlibs/ice40/ice40_unlut.cc | 106 ------------------------------------------
 2 files changed, 107 deletions(-)
 delete mode 100644 techlibs/ice40/ice40_unlut.cc

(limited to 'techlibs/ice40')

diff --git a/techlibs/ice40/Makefile.inc b/techlibs/ice40/Makefile.inc
index d258d5a5d..76a89b107 100644
--- a/techlibs/ice40/Makefile.inc
+++ b/techlibs/ice40/Makefile.inc
@@ -4,7 +4,6 @@ OBJS += techlibs/ice40/ice40_braminit.o
 OBJS += techlibs/ice40/ice40_ffssr.o
 OBJS += techlibs/ice40/ice40_ffinit.o
 OBJS += techlibs/ice40/ice40_opt.o
-OBJS += techlibs/ice40/ice40_unlut.o
 
 GENFILES += techlibs/ice40/brams_init1.vh
 GENFILES += techlibs/ice40/brams_init2.vh
diff --git a/techlibs/ice40/ice40_unlut.cc b/techlibs/ice40/ice40_unlut.cc
deleted file mode 100644
index f3f70ac1f..000000000
--- a/techlibs/ice40/ice40_unlut.cc
+++ /dev/null
@@ -1,106 +0,0 @@
-/*
- *  yosys -- Yosys Open SYnthesis Suite
- *
- *  Copyright (C) 2012  Clifford Wolf <clifford@clifford.at>
- *
- *  Permission to use, copy, modify, and/or distribute this software for any
- *  purpose with or without fee is hereby granted, provided that the above
- *  copyright notice and this permission notice appear in all copies.
- *
- *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
- *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
- *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
- *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
- *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
- *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
- *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
- *
- */
-
-#include "kernel/yosys.h"
-#include "kernel/sigtools.h"
-#include <stdlib.h>
-#include <stdio.h>
-
-USING_YOSYS_NAMESPACE
-PRIVATE_NAMESPACE_BEGIN
-
-static SigBit get_bit_or_zero(const SigSpec &sig)
-{
-	if (GetSize(sig) == 0)
-		return State::S0;
-	return sig[0];
-}
-
-static void run_ice40_unlut(Module *module)
-{
-	SigMap sigmap(module);
-
-	for (auto cell : module->selected_cells())
-	{
-		if (cell->type == "\\SB_LUT4")
-		{
-			SigSpec inbits;
-
-			inbits.append(get_bit_or_zero(cell->getPort("\\I0")));
-			inbits.append(get_bit_or_zero(cell->getPort("\\I1")));
-			inbits.append(get_bit_or_zero(cell->getPort("\\I2")));
-			inbits.append(get_bit_or_zero(cell->getPort("\\I3")));
-			sigmap.apply(inbits);
-
-			log("Mapping SB_LUT4 cell %s.%s to $lut.\n", log_id(module), log_id(cell));
-
-			cell->type ="$lut";
-			cell->setParam("\\WIDTH", 4);
-			cell->setParam("\\LUT", cell->getParam("\\LUT_INIT"));
-			cell->unsetParam("\\LUT_INIT");
-
-			cell->setPort("\\A", SigSpec({
-				get_bit_or_zero(cell->getPort("\\I0")),
-				get_bit_or_zero(cell->getPort("\\I1")),
-				get_bit_or_zero(cell->getPort("\\I2")),
-				get_bit_or_zero(cell->getPort("\\I3"))
-			}));
-			cell->setPort("\\Y", cell->getPort("\\O")[0]);
-			cell->unsetPort("\\I0");
-			cell->unsetPort("\\I1");
-			cell->unsetPort("\\I2");
-			cell->unsetPort("\\I3");
-			cell->unsetPort("\\O");
-
-			cell->check();
-		}
-	}
-}
-
-struct Ice40UnlutPass : public Pass {
-	Ice40UnlutPass() : Pass("ice40_unlut", "iCE40: transform SB_LUT4 cells to $lut cells") { }
-	void help() YS_OVERRIDE
-	{
-		//   |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
-		log("\n");
-		log("    ice40_unlut [options] [selection]\n");
-		log("\n");
-		log("This command transforms all SB_LUT4 cells to generic $lut cells.\n");
-		log("\n");
-	}
-	void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
-	{
-		log_header(design, "Executing ICE40_UNLUT pass (convert SB_LUT4 to $lut).\n");
-		log_push();
-
-		size_t argidx;
-		for (argidx = 1; argidx < args.size(); argidx++) {
-			// if (args[argidx] == "-???") {
-			//  continue;
-			// }
-			break;
-		}
-		extra_args(args, argidx, design);
-
-		for (auto module : design->selected_modules())
-			run_ice40_unlut(module);
-	}
-} Ice40UnlutPass;
-
-PRIVATE_NAMESPACE_END
-- 
cgit v1.2.3


From cc331cf70d9e9f7095e335fc217fd3dbbbe92a93 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Wed, 7 Aug 2019 16:27:07 -0700
Subject: Add test

---
 techlibs/ice40/tests/test_arith.ys | 11 ++++++++++-
 1 file changed, 10 insertions(+), 1 deletion(-)

(limited to 'techlibs/ice40')

diff --git a/techlibs/ice40/tests/test_arith.ys b/techlibs/ice40/tests/test_arith.ys
index 160c767fb..7e928ec78 100644
--- a/techlibs/ice40/tests/test_arith.ys
+++ b/techlibs/ice40/tests/test_arith.ys
@@ -1,6 +1,5 @@
 read_verilog test_arith.v
 synth_ice40
-techmap -map ../cells_sim.v
 rename test gate
 
 read_verilog test_arith.v
@@ -8,3 +7,13 @@ rename test gold
 
 miter -equiv -flatten -make_outputs gold gate miter
 sat -verify -prove trigger 0 -show-ports miter
+
+delete A:whitebox # Necessary since whiteboxes cannot
+                  # be overwritten...
+synth_ice40 -top gate
+
+read_verilog test_arith.v
+rename test gold
+
+miter -equiv -flatten -make_outputs gold gate miter
+sat -verify -prove trigger 0 -show-ports miter
-- 
cgit v1.2.3


From 675c1d42182b871ff4706b992eb005ed9d3d6f02 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Wed, 7 Aug 2019 16:27:24 -0700
Subject: Add ice40_wrapcarry pass, rename $__ICE40_FULL_ADDER -> CARRY_WRAPPER

---
 techlibs/ice40/arith_map.v    | 10 +++++++++-
 techlibs/ice40/cells_map.v    | 13 +++++--------
 techlibs/ice40/synth_ice40.cc |  4 +++-
 3 files changed, 17 insertions(+), 10 deletions(-)

(limited to 'techlibs/ice40')

diff --git a/techlibs/ice40/arith_map.v b/techlibs/ice40/arith_map.v
index 65f28c585..26b24db9e 100644
--- a/techlibs/ice40/arith_map.v
+++ b/techlibs/ice40/arith_map.v
@@ -44,10 +44,18 @@ module _80_ice40_alu (A, B, CI, BI, X, Y, CO);
 
 	genvar i;
 	generate for (i = 0; i < Y_WIDTH; i = i + 1) begin:slice
-		\$__ICE40_FULL_ADDER carry (
+		\$__ICE40_CARRY_WRAPPER #(
+			//    A[0]: 1010 1010 1010 1010
+			//    A[1]: 1100 1100 1100 1100
+			//    A[2]: 1111 0000 1111 0000
+			//    A[3]: 1111 1111 0000 0000
+			.LUT(16'b 0110_1001_1001_0110)
+		) fadd (
 			.A(AA[i]),
 			.B(BB[i]),
 			.CI(C[i]),
+			.I0(1'b0),
+			.I3(C[i]),
 			.CO(CO[i]),
 			.O(Y[i])
 		);
diff --git a/techlibs/ice40/cells_map.v b/techlibs/ice40/cells_map.v
index 511b7f6c6..0c10c9ac4 100644
--- a/techlibs/ice40/cells_map.v
+++ b/techlibs/ice40/cells_map.v
@@ -63,7 +63,8 @@ endmodule
 `endif
 
 `ifndef NO_ADDER
-module \$__ICE40_FULL_ADDER (output CO, O, input A, B, CI);
+module \$__ICE40_CARRY_WRAPPER (output CO, O, input A, B, CI, I0, I3);
+  parameter LUT = 0;
   SB_CARRY carry (
     .I0(A),
     .I1(B),
@@ -72,13 +73,9 @@ module \$__ICE40_FULL_ADDER (output CO, O, input A, B, CI);
   );
   \$lut #(
     .WIDTH(4),
-    //    A[0]: 1010 1010 1010 1010
-    //    A[1]: 1100 1100 1100 1100
-    //    A[2]: 1111 0000 1111 0000
-    //    A[3]: 1111 1111 0000 0000
-    .LUT(16'b 0110_1001_1001_0110)
-  ) adder (
-    .A({CI,B,A,1'b0}),
+    .LUT(LUT)
+  ) lut (
+    .A({I3,B,A,I0}),
     .Y(O)
   );
 endmodule
diff --git a/techlibs/ice40/synth_ice40.cc b/techlibs/ice40/synth_ice40.cc
index 93d5dcbd4..8f4a0f377 100644
--- a/techlibs/ice40/synth_ice40.cc
+++ b/techlibs/ice40/synth_ice40.cc
@@ -293,8 +293,10 @@ struct SynthIce40Pass : public ScriptPass
 		{
 			if (nocarry)
 				run("techmap");
-			else
+			else {
+				run("ice40_wrapcarry");
 				run("techmap -map +/techmap.v -map +/ice40/arith_map.v");
+			}
 			if (retime || help_mode)
 				run(abc + " -dff", "(only if -retime)");
 			run("ice40_opt");
-- 
cgit v1.2.3


From 9776084eda50060594c6609295c7aa540bb400e1 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Wed, 7 Aug 2019 16:40:24 -0700
Subject: Allow whitebox modules to be overwritten

---
 techlibs/ice40/tests/test_arith.ys | 2 --
 1 file changed, 2 deletions(-)

(limited to 'techlibs/ice40')

diff --git a/techlibs/ice40/tests/test_arith.ys b/techlibs/ice40/tests/test_arith.ys
index 7e928ec78..ddb80b700 100644
--- a/techlibs/ice40/tests/test_arith.ys
+++ b/techlibs/ice40/tests/test_arith.ys
@@ -8,8 +8,6 @@ rename test gold
 miter -equiv -flatten -make_outputs gold gate miter
 sat -verify -prove trigger 0 -show-ports miter
 
-delete A:whitebox # Necessary since whiteboxes cannot
-                  # be overwritten...
 synth_ice40 -top gate
 
 read_verilog test_arith.v
-- 
cgit v1.2.3


From f9020ce2b35f2fc205fc71cb095efce1a24fd86d Mon Sep 17 00:00:00 2001
From: David Shah <davey1576@gmail.com>
Date: Sat, 10 Aug 2019 17:14:48 +0100
Subject: Revert "Wrap SB_LUT+SB_CARRY into $__ICE40_CARRY_WRAPPER"

---
 techlibs/ice40/Makefile.inc        |   1 +
 techlibs/ice40/arith_map.v         |  30 ++++++++---
 techlibs/ice40/cells_map.v         |  23 ++++----
 techlibs/ice40/ice40_unlut.cc      | 106 +++++++++++++++++++++++++++++++++++++
 techlibs/ice40/synth_ice40.cc      |  13 +++--
 techlibs/ice40/tests/test_arith.ys |   9 +---
 6 files changed, 150 insertions(+), 32 deletions(-)
 create mode 100644 techlibs/ice40/ice40_unlut.cc

(limited to 'techlibs/ice40')

diff --git a/techlibs/ice40/Makefile.inc b/techlibs/ice40/Makefile.inc
index 76a89b107..d258d5a5d 100644
--- a/techlibs/ice40/Makefile.inc
+++ b/techlibs/ice40/Makefile.inc
@@ -4,6 +4,7 @@ OBJS += techlibs/ice40/ice40_braminit.o
 OBJS += techlibs/ice40/ice40_ffssr.o
 OBJS += techlibs/ice40/ice40_ffinit.o
 OBJS += techlibs/ice40/ice40_opt.o
+OBJS += techlibs/ice40/ice40_unlut.o
 
 GENFILES += techlibs/ice40/brams_init1.vh
 GENFILES += techlibs/ice40/brams_init2.vh
diff --git a/techlibs/ice40/arith_map.v b/techlibs/ice40/arith_map.v
index 26b24db9e..fe83a8e38 100644
--- a/techlibs/ice40/arith_map.v
+++ b/techlibs/ice40/arith_map.v
@@ -44,21 +44,35 @@ module _80_ice40_alu (A, B, CI, BI, X, Y, CO);
 
 	genvar i;
 	generate for (i = 0; i < Y_WIDTH; i = i + 1) begin:slice
-		\$__ICE40_CARRY_WRAPPER #(
-			//    A[0]: 1010 1010 1010 1010
-			//    A[1]: 1100 1100 1100 1100
-			//    A[2]: 1111 0000 1111 0000
-			//    A[3]: 1111 1111 0000 0000
-			.LUT(16'b 0110_1001_1001_0110)
-		) fadd (
+`ifdef _ABC
+		\$__ICE40_FULL_ADDER carry (
 			.A(AA[i]),
 			.B(BB[i]),
 			.CI(C[i]),
+			.CO(CO[i]),
+			.O(Y[i])
+		);
+`else
+		SB_CARRY carry (
+			.I0(AA[i]),
+			.I1(BB[i]),
+			.CI(C[i]),
+			.CO(CO[i])
+		);
+		SB_LUT4 #(
+			//         I0: 1010 1010 1010 1010
+			//         I1: 1100 1100 1100 1100
+			//         I2: 1111 0000 1111 0000
+			//         I3: 1111 1111 0000 0000
+			.LUT_INIT(16'b 0110_1001_1001_0110)
+		) adder (
 			.I0(1'b0),
+			.I1(AA[i]),
+			.I2(BB[i]),
 			.I3(C[i]),
-			.CO(CO[i]),
 			.O(Y[i])
 		);
+`endif
 	end endgenerate
 
 	assign X = AA ^ BB;
diff --git a/techlibs/ice40/cells_map.v b/techlibs/ice40/cells_map.v
index 0c10c9ac4..b4b831165 100644
--- a/techlibs/ice40/cells_map.v
+++ b/techlibs/ice40/cells_map.v
@@ -62,21 +62,26 @@ module \$lut (A, Y);
 endmodule
 `endif
 
-`ifndef NO_ADDER
-module \$__ICE40_CARRY_WRAPPER (output CO, O, input A, B, CI, I0, I3);
-  parameter LUT = 0;
+`ifdef _ABC
+module \$__ICE40_FULL_ADDER (output CO, O, input A, B, CI);
   SB_CARRY carry (
     .I0(A),
     .I1(B),
     .CI(CI),
     .CO(CO)
   );
-  \$lut #(
-    .WIDTH(4),
-    .LUT(LUT)
-  ) lut (
-    .A({I3,B,A,I0}),
-    .Y(O)
+  SB_LUT4 #(
+    //         I0: 1010 1010 1010 1010
+    //         I1: 1100 1100 1100 1100
+    //         I2: 1111 0000 1111 0000
+    //         I3: 1111 1111 0000 0000
+    .LUT_INIT(16'b 0110_1001_1001_0110)
+  ) adder (
+    .I0(1'b0),
+    .I1(A),
+    .I2(B),
+    .I3(CI),
+    .O(O)
   );
 endmodule
 `endif
diff --git a/techlibs/ice40/ice40_unlut.cc b/techlibs/ice40/ice40_unlut.cc
new file mode 100644
index 000000000..f3f70ac1f
--- /dev/null
+++ b/techlibs/ice40/ice40_unlut.cc
@@ -0,0 +1,106 @@
+/*
+ *  yosys -- Yosys Open SYnthesis Suite
+ *
+ *  Copyright (C) 2012  Clifford Wolf <clifford@clifford.at>
+ *
+ *  Permission to use, copy, modify, and/or distribute this software for any
+ *  purpose with or without fee is hereby granted, provided that the above
+ *  copyright notice and this permission notice appear in all copies.
+ *
+ *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ */
+
+#include "kernel/yosys.h"
+#include "kernel/sigtools.h"
+#include <stdlib.h>
+#include <stdio.h>
+
+USING_YOSYS_NAMESPACE
+PRIVATE_NAMESPACE_BEGIN
+
+static SigBit get_bit_or_zero(const SigSpec &sig)
+{
+	if (GetSize(sig) == 0)
+		return State::S0;
+	return sig[0];
+}
+
+static void run_ice40_unlut(Module *module)
+{
+	SigMap sigmap(module);
+
+	for (auto cell : module->selected_cells())
+	{
+		if (cell->type == "\\SB_LUT4")
+		{
+			SigSpec inbits;
+
+			inbits.append(get_bit_or_zero(cell->getPort("\\I0")));
+			inbits.append(get_bit_or_zero(cell->getPort("\\I1")));
+			inbits.append(get_bit_or_zero(cell->getPort("\\I2")));
+			inbits.append(get_bit_or_zero(cell->getPort("\\I3")));
+			sigmap.apply(inbits);
+
+			log("Mapping SB_LUT4 cell %s.%s to $lut.\n", log_id(module), log_id(cell));
+
+			cell->type ="$lut";
+			cell->setParam("\\WIDTH", 4);
+			cell->setParam("\\LUT", cell->getParam("\\LUT_INIT"));
+			cell->unsetParam("\\LUT_INIT");
+
+			cell->setPort("\\A", SigSpec({
+				get_bit_or_zero(cell->getPort("\\I0")),
+				get_bit_or_zero(cell->getPort("\\I1")),
+				get_bit_or_zero(cell->getPort("\\I2")),
+				get_bit_or_zero(cell->getPort("\\I3"))
+			}));
+			cell->setPort("\\Y", cell->getPort("\\O")[0]);
+			cell->unsetPort("\\I0");
+			cell->unsetPort("\\I1");
+			cell->unsetPort("\\I2");
+			cell->unsetPort("\\I3");
+			cell->unsetPort("\\O");
+
+			cell->check();
+		}
+	}
+}
+
+struct Ice40UnlutPass : public Pass {
+	Ice40UnlutPass() : Pass("ice40_unlut", "iCE40: transform SB_LUT4 cells to $lut cells") { }
+	void help() YS_OVERRIDE
+	{
+		//   |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
+		log("\n");
+		log("    ice40_unlut [options] [selection]\n");
+		log("\n");
+		log("This command transforms all SB_LUT4 cells to generic $lut cells.\n");
+		log("\n");
+	}
+	void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
+	{
+		log_header(design, "Executing ICE40_UNLUT pass (convert SB_LUT4 to $lut).\n");
+		log_push();
+
+		size_t argidx;
+		for (argidx = 1; argidx < args.size(); argidx++) {
+			// if (args[argidx] == "-???") {
+			//  continue;
+			// }
+			break;
+		}
+		extra_args(args, argidx, design);
+
+		for (auto module : design->selected_modules())
+			run_ice40_unlut(module);
+	}
+} Ice40UnlutPass;
+
+PRIVATE_NAMESPACE_END
diff --git a/techlibs/ice40/synth_ice40.cc b/techlibs/ice40/synth_ice40.cc
index c6de81bd9..dc04eed67 100644
--- a/techlibs/ice40/synth_ice40.cc
+++ b/techlibs/ice40/synth_ice40.cc
@@ -238,7 +238,7 @@ struct SynthIce40Pass : public ScriptPass
 	{
 		if (check_label("begin"))
 		{
-			run("read_verilog -icells -lib +/ice40/cells_sim.v");
+			run("read_verilog -icells -lib -D_ABC +/ice40/cells_sim.v");
 			run(stringf("hierarchy -check %s", help_mode ? "-top <top>" : top_opt.c_str()));
 			run("proc");
 		}
@@ -293,10 +293,8 @@ struct SynthIce40Pass : public ScriptPass
 		{
 			if (nocarry)
 				run("techmap");
-			else {
-				run("ice40_wrapcarry");
-				run("techmap -map +/techmap.v -map +/ice40/arith_map.v");
-			}
+			else
+				run("techmap -map +/techmap.v -map +/ice40/arith_map.v" + std::string(abc == "abc9" ? " -D _ABC" : ""));
 			if (retime || help_mode)
 				run(abc + " -dff", "(only if -retime)");
 			run("ice40_opt");
@@ -311,7 +309,7 @@ struct SynthIce40Pass : public ScriptPass
 				run("opt_merge");
 				run(stringf("dff2dffe -unmap-mince %d", min_ce_use));
 			}
-			run("techmap -D NO_LUT -D NO_ADDER -map +/ice40/cells_map.v");
+			run("techmap -D NO_LUT -map +/ice40/cells_map.v");
 			run("opt_expr -mux_undef");
 			run("simplemap");
 			run("ice40_ffinit");
@@ -340,12 +338,13 @@ struct SynthIce40Pass : public ScriptPass
 					else
 						wire_delay = 250;
 					run(abc + stringf(" -W %d -lut +/ice40/abc_%s.lut -box +/ice40/abc_%s.box", wire_delay, device_opt.c_str(), device_opt.c_str()), "(skip if -noabc)");
+					run("techmap -D NO_LUT -D _ABC -map +/ice40/cells_map.v");
 				}
 				else
 					run(abc + " -dress -lut 4", "(skip if -noabc)");
 			}
-			run("techmap -D NO_LUT -map +/ice40/cells_map.v");
 			run("clean");
+			run("ice40_unlut");
 			run("opt_lut -dlogic SB_CARRY:I0=2:I1=1:CI=0");
 		}
 
diff --git a/techlibs/ice40/tests/test_arith.ys b/techlibs/ice40/tests/test_arith.ys
index ddb80b700..160c767fb 100644
--- a/techlibs/ice40/tests/test_arith.ys
+++ b/techlibs/ice40/tests/test_arith.ys
@@ -1,5 +1,6 @@
 read_verilog test_arith.v
 synth_ice40
+techmap -map ../cells_sim.v
 rename test gate
 
 read_verilog test_arith.v
@@ -7,11 +8,3 @@ rename test gold
 
 miter -equiv -flatten -make_outputs gold gate miter
 sat -verify -prove trigger 0 -show-ports miter
-
-synth_ice40 -top gate
-
-read_verilog test_arith.v
-rename test gold
-
-miter -equiv -flatten -make_outputs gold gate miter
-sat -verify -prove trigger 0 -show-ports miter
-- 
cgit v1.2.3


From 12c692f6eda7367527fde2a8aad49447a73aa643 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Mon, 12 Aug 2019 12:06:45 -0700
Subject: Revert "Merge pull request #1280 from
 YosysHQ/revert-1266-eddie/ice40_full_adder"

This reverts commit c851dc13108021834533094a8a3236da6d9e0161, reversing
changes made to f54bf1631ff37a83733c162e6ebd188c1d5ea18f.
---
 techlibs/ice40/Makefile.inc        |   1 -
 techlibs/ice40/arith_map.v         |  30 +++--------
 techlibs/ice40/cells_map.v         |  23 ++++----
 techlibs/ice40/ice40_unlut.cc      | 106 -------------------------------------
 techlibs/ice40/synth_ice40.cc      |  13 ++---
 techlibs/ice40/tests/test_arith.ys |   9 +++-
 6 files changed, 32 insertions(+), 150 deletions(-)
 delete mode 100644 techlibs/ice40/ice40_unlut.cc

(limited to 'techlibs/ice40')

diff --git a/techlibs/ice40/Makefile.inc b/techlibs/ice40/Makefile.inc
index d258d5a5d..76a89b107 100644
--- a/techlibs/ice40/Makefile.inc
+++ b/techlibs/ice40/Makefile.inc
@@ -4,7 +4,6 @@ OBJS += techlibs/ice40/ice40_braminit.o
 OBJS += techlibs/ice40/ice40_ffssr.o
 OBJS += techlibs/ice40/ice40_ffinit.o
 OBJS += techlibs/ice40/ice40_opt.o
-OBJS += techlibs/ice40/ice40_unlut.o
 
 GENFILES += techlibs/ice40/brams_init1.vh
 GENFILES += techlibs/ice40/brams_init2.vh
diff --git a/techlibs/ice40/arith_map.v b/techlibs/ice40/arith_map.v
index fe83a8e38..26b24db9e 100644
--- a/techlibs/ice40/arith_map.v
+++ b/techlibs/ice40/arith_map.v
@@ -44,35 +44,21 @@ module _80_ice40_alu (A, B, CI, BI, X, Y, CO);
 
 	genvar i;
 	generate for (i = 0; i < Y_WIDTH; i = i + 1) begin:slice
-`ifdef _ABC
-		\$__ICE40_FULL_ADDER carry (
+		\$__ICE40_CARRY_WRAPPER #(
+			//    A[0]: 1010 1010 1010 1010
+			//    A[1]: 1100 1100 1100 1100
+			//    A[2]: 1111 0000 1111 0000
+			//    A[3]: 1111 1111 0000 0000
+			.LUT(16'b 0110_1001_1001_0110)
+		) fadd (
 			.A(AA[i]),
 			.B(BB[i]),
 			.CI(C[i]),
-			.CO(CO[i]),
-			.O(Y[i])
-		);
-`else
-		SB_CARRY carry (
-			.I0(AA[i]),
-			.I1(BB[i]),
-			.CI(C[i]),
-			.CO(CO[i])
-		);
-		SB_LUT4 #(
-			//         I0: 1010 1010 1010 1010
-			//         I1: 1100 1100 1100 1100
-			//         I2: 1111 0000 1111 0000
-			//         I3: 1111 1111 0000 0000
-			.LUT_INIT(16'b 0110_1001_1001_0110)
-		) adder (
 			.I0(1'b0),
-			.I1(AA[i]),
-			.I2(BB[i]),
 			.I3(C[i]),
+			.CO(CO[i]),
 			.O(Y[i])
 		);
-`endif
 	end endgenerate
 
 	assign X = AA ^ BB;
diff --git a/techlibs/ice40/cells_map.v b/techlibs/ice40/cells_map.v
index b4b831165..0c10c9ac4 100644
--- a/techlibs/ice40/cells_map.v
+++ b/techlibs/ice40/cells_map.v
@@ -62,26 +62,21 @@ module \$lut (A, Y);
 endmodule
 `endif
 
-`ifdef _ABC
-module \$__ICE40_FULL_ADDER (output CO, O, input A, B, CI);
+`ifndef NO_ADDER
+module \$__ICE40_CARRY_WRAPPER (output CO, O, input A, B, CI, I0, I3);
+  parameter LUT = 0;
   SB_CARRY carry (
     .I0(A),
     .I1(B),
     .CI(CI),
     .CO(CO)
   );
-  SB_LUT4 #(
-    //         I0: 1010 1010 1010 1010
-    //         I1: 1100 1100 1100 1100
-    //         I2: 1111 0000 1111 0000
-    //         I3: 1111 1111 0000 0000
-    .LUT_INIT(16'b 0110_1001_1001_0110)
-  ) adder (
-    .I0(1'b0),
-    .I1(A),
-    .I2(B),
-    .I3(CI),
-    .O(O)
+  \$lut #(
+    .WIDTH(4),
+    .LUT(LUT)
+  ) lut (
+    .A({I3,B,A,I0}),
+    .Y(O)
   );
 endmodule
 `endif
diff --git a/techlibs/ice40/ice40_unlut.cc b/techlibs/ice40/ice40_unlut.cc
deleted file mode 100644
index f3f70ac1f..000000000
--- a/techlibs/ice40/ice40_unlut.cc
+++ /dev/null
@@ -1,106 +0,0 @@
-/*
- *  yosys -- Yosys Open SYnthesis Suite
- *
- *  Copyright (C) 2012  Clifford Wolf <clifford@clifford.at>
- *
- *  Permission to use, copy, modify, and/or distribute this software for any
- *  purpose with or without fee is hereby granted, provided that the above
- *  copyright notice and this permission notice appear in all copies.
- *
- *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
- *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
- *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
- *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
- *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
- *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
- *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
- *
- */
-
-#include "kernel/yosys.h"
-#include "kernel/sigtools.h"
-#include <stdlib.h>
-#include <stdio.h>
-
-USING_YOSYS_NAMESPACE
-PRIVATE_NAMESPACE_BEGIN
-
-static SigBit get_bit_or_zero(const SigSpec &sig)
-{
-	if (GetSize(sig) == 0)
-		return State::S0;
-	return sig[0];
-}
-
-static void run_ice40_unlut(Module *module)
-{
-	SigMap sigmap(module);
-
-	for (auto cell : module->selected_cells())
-	{
-		if (cell->type == "\\SB_LUT4")
-		{
-			SigSpec inbits;
-
-			inbits.append(get_bit_or_zero(cell->getPort("\\I0")));
-			inbits.append(get_bit_or_zero(cell->getPort("\\I1")));
-			inbits.append(get_bit_or_zero(cell->getPort("\\I2")));
-			inbits.append(get_bit_or_zero(cell->getPort("\\I3")));
-			sigmap.apply(inbits);
-
-			log("Mapping SB_LUT4 cell %s.%s to $lut.\n", log_id(module), log_id(cell));
-
-			cell->type ="$lut";
-			cell->setParam("\\WIDTH", 4);
-			cell->setParam("\\LUT", cell->getParam("\\LUT_INIT"));
-			cell->unsetParam("\\LUT_INIT");
-
-			cell->setPort("\\A", SigSpec({
-				get_bit_or_zero(cell->getPort("\\I0")),
-				get_bit_or_zero(cell->getPort("\\I1")),
-				get_bit_or_zero(cell->getPort("\\I2")),
-				get_bit_or_zero(cell->getPort("\\I3"))
-			}));
-			cell->setPort("\\Y", cell->getPort("\\O")[0]);
-			cell->unsetPort("\\I0");
-			cell->unsetPort("\\I1");
-			cell->unsetPort("\\I2");
-			cell->unsetPort("\\I3");
-			cell->unsetPort("\\O");
-
-			cell->check();
-		}
-	}
-}
-
-struct Ice40UnlutPass : public Pass {
-	Ice40UnlutPass() : Pass("ice40_unlut", "iCE40: transform SB_LUT4 cells to $lut cells") { }
-	void help() YS_OVERRIDE
-	{
-		//   |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
-		log("\n");
-		log("    ice40_unlut [options] [selection]\n");
-		log("\n");
-		log("This command transforms all SB_LUT4 cells to generic $lut cells.\n");
-		log("\n");
-	}
-	void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
-	{
-		log_header(design, "Executing ICE40_UNLUT pass (convert SB_LUT4 to $lut).\n");
-		log_push();
-
-		size_t argidx;
-		for (argidx = 1; argidx < args.size(); argidx++) {
-			// if (args[argidx] == "-???") {
-			//  continue;
-			// }
-			break;
-		}
-		extra_args(args, argidx, design);
-
-		for (auto module : design->selected_modules())
-			run_ice40_unlut(module);
-	}
-} Ice40UnlutPass;
-
-PRIVATE_NAMESPACE_END
diff --git a/techlibs/ice40/synth_ice40.cc b/techlibs/ice40/synth_ice40.cc
index dc04eed67..c6de81bd9 100644
--- a/techlibs/ice40/synth_ice40.cc
+++ b/techlibs/ice40/synth_ice40.cc
@@ -238,7 +238,7 @@ struct SynthIce40Pass : public ScriptPass
 	{
 		if (check_label("begin"))
 		{
-			run("read_verilog -icells -lib -D_ABC +/ice40/cells_sim.v");
+			run("read_verilog -icells -lib +/ice40/cells_sim.v");
 			run(stringf("hierarchy -check %s", help_mode ? "-top <top>" : top_opt.c_str()));
 			run("proc");
 		}
@@ -293,8 +293,10 @@ struct SynthIce40Pass : public ScriptPass
 		{
 			if (nocarry)
 				run("techmap");
-			else
-				run("techmap -map +/techmap.v -map +/ice40/arith_map.v" + std::string(abc == "abc9" ? " -D _ABC" : ""));
+			else {
+				run("ice40_wrapcarry");
+				run("techmap -map +/techmap.v -map +/ice40/arith_map.v");
+			}
 			if (retime || help_mode)
 				run(abc + " -dff", "(only if -retime)");
 			run("ice40_opt");
@@ -309,7 +311,7 @@ struct SynthIce40Pass : public ScriptPass
 				run("opt_merge");
 				run(stringf("dff2dffe -unmap-mince %d", min_ce_use));
 			}
-			run("techmap -D NO_LUT -map +/ice40/cells_map.v");
+			run("techmap -D NO_LUT -D NO_ADDER -map +/ice40/cells_map.v");
 			run("opt_expr -mux_undef");
 			run("simplemap");
 			run("ice40_ffinit");
@@ -338,13 +340,12 @@ struct SynthIce40Pass : public ScriptPass
 					else
 						wire_delay = 250;
 					run(abc + stringf(" -W %d -lut +/ice40/abc_%s.lut -box +/ice40/abc_%s.box", wire_delay, device_opt.c_str(), device_opt.c_str()), "(skip if -noabc)");
-					run("techmap -D NO_LUT -D _ABC -map +/ice40/cells_map.v");
 				}
 				else
 					run(abc + " -dress -lut 4", "(skip if -noabc)");
 			}
+			run("techmap -D NO_LUT -map +/ice40/cells_map.v");
 			run("clean");
-			run("ice40_unlut");
 			run("opt_lut -dlogic SB_CARRY:I0=2:I1=1:CI=0");
 		}
 
diff --git a/techlibs/ice40/tests/test_arith.ys b/techlibs/ice40/tests/test_arith.ys
index 160c767fb..ddb80b700 100644
--- a/techlibs/ice40/tests/test_arith.ys
+++ b/techlibs/ice40/tests/test_arith.ys
@@ -1,6 +1,5 @@
 read_verilog test_arith.v
 synth_ice40
-techmap -map ../cells_sim.v
 rename test gate
 
 read_verilog test_arith.v
@@ -8,3 +7,11 @@ rename test gold
 
 miter -equiv -flatten -make_outputs gold gate miter
 sat -verify -prove trigger 0 -show-ports miter
+
+synth_ice40 -top gate
+
+read_verilog test_arith.v
+rename test gold
+
+miter -equiv -flatten -make_outputs gold gate miter
+sat -verify -prove trigger 0 -show-ports miter
-- 
cgit v1.2.3


From 8a2480526f2ff80cbdf0f0f4279e8989b53b6e9b Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Mon, 12 Aug 2019 12:19:25 -0700
Subject: Fix $lut pin ordering inside $__ICE40_CARRY_WRAPPER

---
 techlibs/ice40/cells_map.v | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'techlibs/ice40')

diff --git a/techlibs/ice40/cells_map.v b/techlibs/ice40/cells_map.v
index 0c10c9ac4..662423f0a 100644
--- a/techlibs/ice40/cells_map.v
+++ b/techlibs/ice40/cells_map.v
@@ -75,7 +75,7 @@ module \$__ICE40_CARRY_WRAPPER (output CO, O, input A, B, CI, I0, I3);
     .WIDTH(4),
     .LUT(LUT)
   ) lut (
-    .A({I3,B,A,I0}),
+    .A({I0,A,B,I3}),
     .Y(O)
   );
 endmodule
-- 
cgit v1.2.3


From 1c57b1e7ea0128aebef8e78bcf4de9aaf9e42c6a Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Fri, 16 Aug 2019 15:56:57 -0700
Subject: Update abc_* attr in ecp5 and ice40

---
 techlibs/ice40/cells_sim.v | 10 ++++++++--
 1 file changed, 8 insertions(+), 2 deletions(-)

(limited to 'techlibs/ice40')

diff --git a/techlibs/ice40/cells_sim.v b/techlibs/ice40/cells_sim.v
index 2205be27d..5b18fec27 100644
--- a/techlibs/ice40/cells_sim.v
+++ b/techlibs/ice40/cells_sim.v
@@ -141,8 +141,14 @@ module SB_CARRY (output CO, input I0, I1, CI);
 	assign CO = (I0 && I1) || ((I0 || I1) && CI);
 endmodule
 
-(* abc_box_id = 1, abc_carry="CI,CO", lib_whitebox *)
-module \$__ICE40_FULL_ADDER (output CO, O, input A, B, CI);
+(* abc_box_id = 1, lib_whitebox *)
+module \$__ICE40_FULL_ADDER (
+	(* abc_carry_out *) output CO,
+	output O,
+	input A,
+	input B,
+	(* abc_carry_in *) input CI
+);
 	SB_CARRY carry (
 		.I0(A),
 		.I1(B),
-- 
cgit v1.2.3


From d81a090d89d87837d3e18f9c724fe5c89ddf1f64 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Mon, 19 Aug 2019 09:56:17 -0700
Subject: Unify abc_carry_{in,out} into abc_carry and use port dir, as @mithro

---
 techlibs/ice40/cells_sim.v | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

(limited to 'techlibs/ice40')

diff --git a/techlibs/ice40/cells_sim.v b/techlibs/ice40/cells_sim.v
index 5b18fec27..ab04808f4 100644
--- a/techlibs/ice40/cells_sim.v
+++ b/techlibs/ice40/cells_sim.v
@@ -143,11 +143,11 @@ endmodule
 
 (* abc_box_id = 1, lib_whitebox *)
 module \$__ICE40_FULL_ADDER (
-	(* abc_carry_out *) output CO,
+	(* abc_carry *) output CO,
 	output O,
 	input A,
 	input B,
-	(* abc_carry_in *) input CI
+	(* abc_carry *) input CI
 );
 	SB_CARRY carry (
 		.I0(A),
-- 
cgit v1.2.3


From a270af00cc133ac03ec97cf81ed0a7146b7b225e Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Fri, 23 Aug 2019 11:21:44 -0700
Subject: Put abc_* attributes above port

---
 techlibs/ice40/cells_sim.v | 6 ++++--
 1 file changed, 4 insertions(+), 2 deletions(-)

(limited to 'techlibs/ice40')

diff --git a/techlibs/ice40/cells_sim.v b/techlibs/ice40/cells_sim.v
index ab04808f4..c7f3bdad2 100644
--- a/techlibs/ice40/cells_sim.v
+++ b/techlibs/ice40/cells_sim.v
@@ -143,11 +143,13 @@ endmodule
 
 (* abc_box_id = 1, lib_whitebox *)
 module \$__ICE40_FULL_ADDER (
-	(* abc_carry *) output CO,
+	(* abc_carry *)
+	output CO,
 	output O,
 	input A,
 	input B,
-	(* abc_carry *) input CI
+	(* abc_carry *)
+	input CI
 );
 	SB_CARRY carry (
 		.I0(A),
-- 
cgit v1.2.3


From 129df7184a2b85553366f9d56e26ac4eaccc5a52 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Wed, 28 Aug 2019 17:07:07 -0700
Subject: Update to new $__ICE40_CARRY_WRAPPER

---
 techlibs/ice40/cells_sim.v | 19 ++++++++-----------
 1 file changed, 8 insertions(+), 11 deletions(-)

(limited to 'techlibs/ice40')

diff --git a/techlibs/ice40/cells_sim.v b/techlibs/ice40/cells_sim.v
index c7f3bdad2..02726605f 100644
--- a/techlibs/ice40/cells_sim.v
+++ b/techlibs/ice40/cells_sim.v
@@ -142,15 +142,16 @@ module SB_CARRY (output CO, input I0, I1, CI);
 endmodule
 
 (* abc_box_id = 1, lib_whitebox *)
-module \$__ICE40_FULL_ADDER (
+module \$__ICE40_CARRY_WRAPPER (
 	(* abc_carry *)
 	output CO,
 	output O,
-	input A,
-	input B,
+	input A, B,
 	(* abc_carry *)
-	input CI
+	input CI,
+	input I0, I3,
 );
+	parameter LUT = 0;
 	SB_CARRY carry (
 		.I0(A),
 		.I1(B),
@@ -158,16 +159,12 @@ module \$__ICE40_FULL_ADDER (
 		.CO(CO)
 	);
 	SB_LUT4 #(
-		//         I0: 1010 1010 1010 1010
-		//         I1: 1100 1100 1100 1100
-		//         I2: 1111 0000 1111 0000
-		//         I3: 1111 1111 0000 0000
-		.LUT_INIT(16'b 0110_1001_1001_0110)
+		.LUT_INIT(LUT)
 	) adder (
-		.I0(1'b0),
+		.I0(I0),
 		.I1(A),
 		.I2(B),
-		.I3(CI),
+		.I3(I3),
 		.O(O)
 	);
 endmodule
-- 
cgit v1.2.3


From 077e9d4ada7fbc75ab87fe7f390d58e2d53b4472 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Wed, 28 Aug 2019 17:07:24 -0700
Subject: Update box size and timings

---
 techlibs/ice40/abc_hx.box | 8 ++++----
 techlibs/ice40/abc_lp.box | 8 ++++----
 techlibs/ice40/abc_u.box  | 8 ++++----
 3 files changed, 12 insertions(+), 12 deletions(-)

(limited to 'techlibs/ice40')

diff --git a/techlibs/ice40/abc_hx.box b/techlibs/ice40/abc_hx.box
index c0ea742e2..571152129 100644
--- a/techlibs/ice40/abc_hx.box
+++ b/techlibs/ice40/abc_hx.box
@@ -3,11 +3,11 @@
 # NB: Inputs/Outputs must be ordered alphabetically
 #     (with exceptions for carry in/out)
 
-# Inputs: A B CI
+# Inputs: A B I0 I3 CI
 # Outputs: O CO
 #   (NB: carry chain input/output must be last
 #        input/output and have been moved there
 #        overriding the alphabetical ordering)
-$__ICE40_FULL_ADDER 1 1 3 2
-400 379 316
-259 231 126
+$__ICE40_FULL_ADDER 1 1 5 2
+400 379 449 316 316
+259 231 -   -   126
diff --git a/techlibs/ice40/abc_lp.box b/techlibs/ice40/abc_lp.box
index d73b6d649..a9f8699fc 100644
--- a/techlibs/ice40/abc_lp.box
+++ b/techlibs/ice40/abc_lp.box
@@ -3,11 +3,11 @@
 # NB: Inputs/Outputs must be ordered alphabetically
 #     (with exceptions for carry in/out)
 
-# Inputs: A B CI
+# Inputs: A B I0 I3 CI
 # Outputs: O CO
 #   (NB: carry chain input/output must be last
 #        input/output and have been moved there
 #        overriding the alphabetical ordering)
-$__ICE40_FULL_ADDER 1 1 3 2
-589 558 465
-675 609 186 
+$__ICE40_FULL_ADDER 1 1 5 2
+589 558 661 465 465
+675 609 -   -   186
diff --git a/techlibs/ice40/abc_u.box b/techlibs/ice40/abc_u.box
index 42d666051..bc8a8d9cd 100644
--- a/techlibs/ice40/abc_u.box
+++ b/techlibs/ice40/abc_u.box
@@ -3,11 +3,11 @@
 # NB: Inputs/Outputs must be ordered alphabetically
 #     (with exceptions for carry in/out)
 
-# Inputs: A B CI
+# Inputs: A B I0 I3 CI
 # Outputs: O CO
 #   (NB: carry chain input/output must be last
 #        input/output and have been moved there
 #        overriding the alphabetical ordering)
-$__ICE40_FULL_ADDER 1 1 3 2
-1231 1205 874
-675  609  278
+$__ICE40_FULL_ADDER 1 1 5 2
+1231 1205 1285 874 874
+675  609  -    -   278
-- 
cgit v1.2.3


From 2aedee1f0e0f6a6214241f51f5c12d4b67c3ef6f Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Wed, 28 Aug 2019 17:07:36 -0700
Subject: Remove $__ICE40_FULL_ADDER handling from ice40_opt; cannot reason
 with

CARRY_WRAPPER in the same way since I0 and I3 could be used
---
 techlibs/ice40/ice40_opt.cc | 45 ---------------------------------------------
 1 file changed, 45 deletions(-)

(limited to 'techlibs/ice40')

diff --git a/techlibs/ice40/ice40_opt.cc b/techlibs/ice40/ice40_opt.cc
index d5106b805..f528607d6 100644
--- a/techlibs/ice40/ice40_opt.cc
+++ b/techlibs/ice40/ice40_opt.cc
@@ -83,51 +83,6 @@ static void run_ice40_opts(Module *module)
 			}
 			continue;
 		}
-
-		if (cell->type == "$__ICE40_FULL_ADDER")
-		{
-			SigSpec non_const_inputs, replacement_output;
-			int count_zeros = 0, count_ones = 0;
-
-			SigBit inbit[3] = {
-				cell->getPort("\\A"),
-				cell->getPort("\\B"),
-				cell->getPort("\\CI")
-			};
-			for (int i = 0; i < 3; i++)
-				if (inbit[i].wire == nullptr) {
-					if (inbit[i] == State::S1)
-						count_ones++;
-					else
-						count_zeros++;
-				} else
-					non_const_inputs.append(inbit[i]);
-
-			if (count_zeros >= 2)
-				replacement_output = State::S0;
-			else if (count_ones >= 2)
-				replacement_output = State::S1;
-			else if (GetSize(non_const_inputs) == 1)
-				replacement_output = non_const_inputs;
-
-			if (GetSize(replacement_output)) {
-				optimized_co.insert(sigmap(cell->getPort("\\CO")[0]));
-				module->connect(cell->getPort("\\CO")[0], replacement_output);
-				module->design->scratchpad_set_bool("opt.did_something", true);
-				log("Optimized $__ICE40_FULL_ADDER cell back to logic (without SB_CARRY) %s.%s: CO=%s\n",
-						log_id(module), log_id(cell), log_signal(replacement_output));
-				cell->type = "$lut";
-				cell->setPort("\\A", { State::S0, inbit[0], inbit[1], inbit[2] });
-				cell->setPort("\\Y", cell->getPort("\\O"));
-				cell->unsetPort("\\B");
-				cell->unsetPort("\\CI");
-				cell->unsetPort("\\CO");
-				cell->unsetPort("\\O");
-				cell->setParam("\\LUT", RTLIL::Const::from_string("0110100110010110"));
-				cell->setParam("\\WIDTH", 4);
-			}
-			continue;
-		}
 	}
 
 	for (auto cell : sb_lut_cells)
-- 
cgit v1.2.3


From e4f89e01b5710eb9e2e6675a1df13a5a2637b206 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Wed, 28 Aug 2019 17:21:12 -0700
Subject: Specify ice40 family to cells_sim.v using define

---
 techlibs/ice40/synth_ice40.cc | 9 ++++++++-
 1 file changed, 8 insertions(+), 1 deletion(-)

(limited to 'techlibs/ice40')

diff --git a/techlibs/ice40/synth_ice40.cc b/techlibs/ice40/synth_ice40.cc
index c6de81bd9..2f77c03db 100644
--- a/techlibs/ice40/synth_ice40.cc
+++ b/techlibs/ice40/synth_ice40.cc
@@ -238,7 +238,14 @@ struct SynthIce40Pass : public ScriptPass
 	{
 		if (check_label("begin"))
 		{
-			run("read_verilog -icells -lib +/ice40/cells_sim.v");
+			std::string define;
+			if (device_opt == "lp")
+				define = "-D ICE40_LX";
+			else if (device_opt == "u")
+				define = "-D ICE40_U";
+			else
+				define = "-D ICE40_HX";
+			run("read_verilog -icells " + define + " -lib +/ice40/cells_sim.v");
 			run(stringf("hierarchy -check %s", help_mode ? "-top <top>" : top_opt.c_str()));
 			run("proc");
 		}
-- 
cgit v1.2.3


From 2421cb3fed1a990219227ed3cf0632eb221e9698 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Wed, 28 Aug 2019 17:21:37 -0700
Subject: Add arrival times for HX devices

---
 techlibs/ice40/cells_sim.v | 135 ++++++++++++++++++++++++++++++++++++++-------
 1 file changed, 114 insertions(+), 21 deletions(-)

(limited to 'techlibs/ice40')

diff --git a/techlibs/ice40/cells_sim.v b/techlibs/ice40/cells_sim.v
index 02726605f..261d99c9b 100644
--- a/techlibs/ice40/cells_sim.v
+++ b/techlibs/ice40/cells_sim.v
@@ -2,6 +2,10 @@
 `define SB_DFF_REG reg Q = 0
 // `define SB_DFF_REG reg Q
 
+`define ABC_ARRIVAL_HX(TIME) `ifdef ICE40_HX (* abc_arrival=TIME *) `endif
+`define ABC_ARRIVAL_LX(TIME) `ifdef ICE40_LX (* abc_arrival=TIME *) `endif
+`define ABC_ARRIVAL_U(TIME)  `ifdef ICE40_U (* abc_arrival=TIME *) `endif
+
 // SiliconBlue IO Cells
 
 module SB_IO (
@@ -169,20 +173,34 @@ module \$__ICE40_CARRY_WRAPPER (
 	);
 endmodule
 
+// Max delay from: https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L90
+
 // Positive Edge SiliconBlue FF Cells
 
-module SB_DFF (output `SB_DFF_REG, input C, D);
+module SB_DFF (
+	`ABC_ARRIVAL_HX(540)
+	output `SB_DFF_REG,
+	input C, D
+);
 	always @(posedge C)
 		Q <= D;
 endmodule
 
-module SB_DFFE (output `SB_DFF_REG, input C, E, D);
+module SB_DFFE (
+	`ABC_ARRIVAL_HX(540)
+	output `SB_DFF_REG,
+	input C, E, D
+);
 	always @(posedge C)
 		if (E)
 			Q <= D;
 endmodule
 
-module SB_DFFSR (output `SB_DFF_REG, input C, R, D);
+module SB_DFFSR (
+	`ABC_ARRIVAL_HX(540)
+	output `SB_DFF_REG,
+	input C, R, D
+);
 	always @(posedge C)
 		if (R)
 			Q <= 0;
@@ -190,7 +208,11 @@ module SB_DFFSR (output `SB_DFF_REG, input C, R, D);
 			Q <= D;
 endmodule
 
-module SB_DFFR (output `SB_DFF_REG, input C, R, D);
+module SB_DFFR (
+	`ABC_ARRIVAL_HX(540)
+	output `SB_DFF_REG,
+	input C, R, D
+);
 	always @(posedge C, posedge R)
 		if (R)
 			Q <= 0;
@@ -198,7 +220,11 @@ module SB_DFFR (output `SB_DFF_REG, input C, R, D);
 			Q <= D;
 endmodule
 
-module SB_DFFSS (output `SB_DFF_REG, input C, S, D);
+module SB_DFFSS (
+	`ABC_ARRIVAL_HX(540)
+	output `SB_DFF_REG,
+	input C, S, D
+);
 	always @(posedge C)
 		if (S)
 			Q <= 1;
@@ -206,7 +232,11 @@ module SB_DFFSS (output `SB_DFF_REG, input C, S, D);
 			Q <= D;
 endmodule
 
-module SB_DFFS (output `SB_DFF_REG, input C, S, D);
+module SB_DFFS (
+	`ABC_ARRIVAL_HX(540)
+	output `SB_DFF_REG,
+	input C, S, D
+);
 	always @(posedge C, posedge S)
 		if (S)
 			Q <= 1;
@@ -214,7 +244,11 @@ module SB_DFFS (output `SB_DFF_REG, input C, S, D);
 			Q <= D;
 endmodule
 
-module SB_DFFESR (output `SB_DFF_REG, input C, E, R, D);
+module SB_DFFESR (
+	`ABC_ARRIVAL_HX(540)
+	output `SB_DFF_REG,
+	input C, E, R, D
+);
 	always @(posedge C)
 		if (E) begin
 			if (R)
@@ -224,7 +258,11 @@ module SB_DFFESR (output `SB_DFF_REG, input C, E, R, D);
 		end
 endmodule
 
-module SB_DFFER (output `SB_DFF_REG, input C, E, R, D);
+module SB_DFFER (
+	`ABC_ARRIVAL_HX(540)
+	output `SB_DFF_REG,
+	input C, E, R, D
+);
 	always @(posedge C, posedge R)
 		if (R)
 			Q <= 0;
@@ -232,7 +270,11 @@ module SB_DFFER (output `SB_DFF_REG, input C, E, R, D);
 			Q <= D;
 endmodule
 
-module SB_DFFESS (output `SB_DFF_REG, input C, E, S, D);
+module SB_DFFESS (
+	`ABC_ARRIVAL_HX(540)
+	output `SB_DFF_REG,
+	input C, E, S, D
+);
 	always @(posedge C)
 		if (E) begin
 			if (S)
@@ -242,7 +284,11 @@ module SB_DFFESS (output `SB_DFF_REG, input C, E, S, D);
 		end
 endmodule
 
-module SB_DFFES (output `SB_DFF_REG, input C, E, S, D);
+module SB_DFFES (
+	`ABC_ARRIVAL_HX(540)
+	output `SB_DFF_REG,
+	input C, E, S, D
+);
 	always @(posedge C, posedge S)
 		if (S)
 			Q <= 1;
@@ -252,18 +298,30 @@ endmodule
 
 // Negative Edge SiliconBlue FF Cells
 
-module SB_DFFN (output `SB_DFF_REG, input C, D);
+module SB_DFFN (
+	`ABC_ARRIVAL_HX(540)
+	output `SB_DFF_REG,
+	input C, D
+);
 	always @(negedge C)
 		Q <= D;
 endmodule
 
-module SB_DFFNE (output `SB_DFF_REG, input C, E, D);
+module SB_DFFNE (
+	`ABC_ARRIVAL_HX(540)
+	output `SB_DFF_REG,
+	input C, E, D
+);
 	always @(negedge C)
 		if (E)
 			Q <= D;
 endmodule
 
-module SB_DFFNSR (output `SB_DFF_REG, input C, R, D);
+module SB_DFFNSR (
+	`ABC_ARRIVAL_HX(540)
+	output `SB_DFF_REG,
+	input C, R, D
+);
 	always @(negedge C)
 		if (R)
 			Q <= 0;
@@ -271,7 +329,11 @@ module SB_DFFNSR (output `SB_DFF_REG, input C, R, D);
 			Q <= D;
 endmodule
 
-module SB_DFFNR (output `SB_DFF_REG, input C, R, D);
+module SB_DFFNR (
+	`ABC_ARRIVAL_HX(540)
+	output `SB_DFF_REG,
+	input C, R, D
+);
 	always @(negedge C, posedge R)
 		if (R)
 			Q <= 0;
@@ -279,7 +341,11 @@ module SB_DFFNR (output `SB_DFF_REG, input C, R, D);
 			Q <= D;
 endmodule
 
-module SB_DFFNSS (output `SB_DFF_REG, input C, S, D);
+module SB_DFFNSS (
+	`ABC_ARRIVAL_HX(540)
+	output `SB_DFF_REG,
+	input C, S, D
+);
 	always @(negedge C)
 		if (S)
 			Q <= 1;
@@ -287,7 +353,11 @@ module SB_DFFNSS (output `SB_DFF_REG, input C, S, D);
 			Q <= D;
 endmodule
 
-module SB_DFFNS (output `SB_DFF_REG, input C, S, D);
+module SB_DFFNS (
+	`ABC_ARRIVAL_HX(540)
+	output `SB_DFF_REG,
+	input C, S, D
+);
 	always @(negedge C, posedge S)
 		if (S)
 			Q <= 1;
@@ -295,7 +365,11 @@ module SB_DFFNS (output `SB_DFF_REG, input C, S, D);
 			Q <= D;
 endmodule
 
-module SB_DFFNESR (output `SB_DFF_REG, input C, E, R, D);
+module SB_DFFNESR (
+	`ABC_ARRIVAL_HX(540)
+	output `SB_DFF_REG,
+	input C, E, R, D
+);
 	always @(negedge C)
 		if (E) begin
 			if (R)
@@ -305,7 +379,11 @@ module SB_DFFNESR (output `SB_DFF_REG, input C, E, R, D);
 		end
 endmodule
 
-module SB_DFFNER (output `SB_DFF_REG, input C, E, R, D);
+module SB_DFFNER (
+	`ABC_ARRIVAL_HX(540)
+	output `SB_DFF_REG,
+	input C, E, R, D
+);
 	always @(negedge C, posedge R)
 		if (R)
 			Q <= 0;
@@ -313,7 +391,11 @@ module SB_DFFNER (output `SB_DFF_REG, input C, E, R, D);
 			Q <= D;
 endmodule
 
-module SB_DFFNESS (output `SB_DFF_REG, input C, E, S, D);
+module SB_DFFNESS (
+	`ABC_ARRIVAL_HX(540)
+	output `SB_DFF_REG,
+	input C, E, S, D
+);
 	always @(negedge C)
 		if (E) begin
 			if (S)
@@ -323,7 +405,11 @@ module SB_DFFNESS (output `SB_DFF_REG, input C, E, S, D);
 		end
 endmodule
 
-module SB_DFFNES (output `SB_DFF_REG, input C, E, S, D);
+module SB_DFFNES (
+	`ABC_ARRIVAL_HX(540)
+	output `SB_DFF_REG,
+	input C, E, S, D
+);
 	always @(negedge C, posedge S)
 		if (S)
 			Q <= 1;
@@ -334,6 +420,7 @@ endmodule
 // SiliconBlue RAM Cells
 
 module SB_RAM40_4K (
+	`ABC_ARRIVAL_HX(2146) // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L401
 	output [15:0] RDATA,
 	input         RCLK, RCLKE, RE,
 	input  [10:0] RADDR,
@@ -502,6 +589,7 @@ module SB_RAM40_4K (
 endmodule
 
 module SB_RAM40_4KNR (
+	`ABC_ARRIVAL_HX(2146) // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L401
 	output [15:0] RDATA,
 	input         RCLKN, RCLKE, RE,
 	input  [10:0] RADDR,
@@ -567,6 +655,7 @@ module SB_RAM40_4KNR (
 endmodule
 
 module SB_RAM40_4KNW (
+	`ABC_ARRIVAL_HX(2146) // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L401
 	output [15:0] RDATA,
 	input         RCLK, RCLKE, RE,
 	input  [10:0] RADDR,
@@ -632,6 +721,7 @@ module SB_RAM40_4KNW (
 endmodule
 
 module SB_RAM40_4KNRNW (
+	`ABC_ARRIVAL_HX(2146) // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L401
 	output [15:0] RDATA,
 	input         RCLKN, RCLKE, RE,
 	input  [10:0] RADDR,
@@ -700,7 +790,10 @@ endmodule
 
 module ICESTORM_LC (
 	input I0, I1, I2, I3, CIN, CLK, CEN, SR,
-	output LO, O, COUT
+	output LO,
+	`ABC_ARRIVAL_HX(540)
+	output O,
+	output COUT
 );
 	parameter [15:0] LUT_INIT = 0;
 
-- 
cgit v1.2.3


From e569f138704a28654cc52c917bba4decffa29f54 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Wed, 28 Aug 2019 17:22:44 -0700
Subject: Revert "Remove $__ICE40_FULL_ADDER handling from ice40_opt; cannot
 reason with"

This reverts commit 2aedee1f0e0f6a6214241f51f5c12d4b67c3ef6f.
---
 techlibs/ice40/ice40_opt.cc | 45 +++++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 45 insertions(+)

(limited to 'techlibs/ice40')

diff --git a/techlibs/ice40/ice40_opt.cc b/techlibs/ice40/ice40_opt.cc
index f528607d6..d5106b805 100644
--- a/techlibs/ice40/ice40_opt.cc
+++ b/techlibs/ice40/ice40_opt.cc
@@ -83,6 +83,51 @@ static void run_ice40_opts(Module *module)
 			}
 			continue;
 		}
+
+		if (cell->type == "$__ICE40_FULL_ADDER")
+		{
+			SigSpec non_const_inputs, replacement_output;
+			int count_zeros = 0, count_ones = 0;
+
+			SigBit inbit[3] = {
+				cell->getPort("\\A"),
+				cell->getPort("\\B"),
+				cell->getPort("\\CI")
+			};
+			for (int i = 0; i < 3; i++)
+				if (inbit[i].wire == nullptr) {
+					if (inbit[i] == State::S1)
+						count_ones++;
+					else
+						count_zeros++;
+				} else
+					non_const_inputs.append(inbit[i]);
+
+			if (count_zeros >= 2)
+				replacement_output = State::S0;
+			else if (count_ones >= 2)
+				replacement_output = State::S1;
+			else if (GetSize(non_const_inputs) == 1)
+				replacement_output = non_const_inputs;
+
+			if (GetSize(replacement_output)) {
+				optimized_co.insert(sigmap(cell->getPort("\\CO")[0]));
+				module->connect(cell->getPort("\\CO")[0], replacement_output);
+				module->design->scratchpad_set_bool("opt.did_something", true);
+				log("Optimized $__ICE40_FULL_ADDER cell back to logic (without SB_CARRY) %s.%s: CO=%s\n",
+						log_id(module), log_id(cell), log_signal(replacement_output));
+				cell->type = "$lut";
+				cell->setPort("\\A", { State::S0, inbit[0], inbit[1], inbit[2] });
+				cell->setPort("\\Y", cell->getPort("\\O"));
+				cell->unsetPort("\\B");
+				cell->unsetPort("\\CI");
+				cell->unsetPort("\\CO");
+				cell->unsetPort("\\O");
+				cell->setParam("\\LUT", RTLIL::Const::from_string("0110100110010110"));
+				cell->setParam("\\WIDTH", 4);
+			}
+			continue;
+		}
 	}
 
 	for (auto cell : sb_lut_cells)
-- 
cgit v1.2.3


From f5b4bc847c02d6c3e06c086a1375840ccac936cd Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Wed, 28 Aug 2019 17:25:05 -0700
Subject: Adapt to $__ICE40_CARRY_WRAPPER

---
 techlibs/ice40/ice40_opt.cc | 8 +++++---
 1 file changed, 5 insertions(+), 3 deletions(-)

(limited to 'techlibs/ice40')

diff --git a/techlibs/ice40/ice40_opt.cc b/techlibs/ice40/ice40_opt.cc
index d5106b805..58f106f7c 100644
--- a/techlibs/ice40/ice40_opt.cc
+++ b/techlibs/ice40/ice40_opt.cc
@@ -84,7 +84,7 @@ static void run_ice40_opts(Module *module)
 			continue;
 		}
 
-		if (cell->type == "$__ICE40_FULL_ADDER")
+		if (cell->type == "$__ICE40_CARRY_WRAPPER")
 		{
 			SigSpec non_const_inputs, replacement_output;
 			int count_zeros = 0, count_ones = 0;
@@ -114,13 +114,15 @@ static void run_ice40_opts(Module *module)
 				optimized_co.insert(sigmap(cell->getPort("\\CO")[0]));
 				module->connect(cell->getPort("\\CO")[0], replacement_output);
 				module->design->scratchpad_set_bool("opt.did_something", true);
-				log("Optimized $__ICE40_FULL_ADDER cell back to logic (without SB_CARRY) %s.%s: CO=%s\n",
+				log("Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) %s.%s: CO=%s\n",
 						log_id(module), log_id(cell), log_signal(replacement_output));
 				cell->type = "$lut";
-				cell->setPort("\\A", { State::S0, inbit[0], inbit[1], inbit[2] });
+				cell->setPort("\\A", { cell->getPort("\\I0"), inbit[0], inbit[1], cell->getPort("\\I3") });
 				cell->setPort("\\Y", cell->getPort("\\O"));
 				cell->unsetPort("\\B");
 				cell->unsetPort("\\CI");
+				cell->unsetPort("\\I0");
+				cell->unsetPort("\\I3");
 				cell->unsetPort("\\CO");
 				cell->unsetPort("\\O");
 				cell->setParam("\\LUT", RTLIL::Const::from_string("0110100110010110"));
-- 
cgit v1.2.3


From d46d38e4d5e1502ea5cb6075161c87bd837af9eb Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Wed, 28 Aug 2019 17:25:54 -0700
Subject: Trailing comma

---
 techlibs/ice40/cells_sim.v | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'techlibs/ice40')

diff --git a/techlibs/ice40/cells_sim.v b/techlibs/ice40/cells_sim.v
index 02726605f..2a7487f6b 100644
--- a/techlibs/ice40/cells_sim.v
+++ b/techlibs/ice40/cells_sim.v
@@ -149,7 +149,7 @@ module \$__ICE40_CARRY_WRAPPER (
 	input A, B,
 	(* abc_carry *)
 	input CI,
-	input I0, I3,
+	input I0, I3
 );
 	parameter LUT = 0;
 	SB_CARRY carry (
-- 
cgit v1.2.3


From c0b99ed0e8c8c6adf76d70fa71c9753957162e04 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Wed, 28 Aug 2019 18:45:09 -0700
Subject: Do not overwrite LUT param

---
 techlibs/ice40/ice40_opt.cc | 1 -
 1 file changed, 1 deletion(-)

(limited to 'techlibs/ice40')

diff --git a/techlibs/ice40/ice40_opt.cc b/techlibs/ice40/ice40_opt.cc
index 58f106f7c..ea56d3f4d 100644
--- a/techlibs/ice40/ice40_opt.cc
+++ b/techlibs/ice40/ice40_opt.cc
@@ -125,7 +125,6 @@ static void run_ice40_opts(Module *module)
 				cell->unsetPort("\\I3");
 				cell->unsetPort("\\CO");
 				cell->unsetPort("\\O");
-				cell->setParam("\\LUT", RTLIL::Const::from_string("0110100110010110"));
 				cell->setParam("\\WIDTH", 4);
 			}
 			continue;
-- 
cgit v1.2.3


From a4f641f2303bc6f04751a15ec49cf2658ea8eb63 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Wed, 28 Aug 2019 18:45:09 -0700
Subject: Do not overwrite LUT param

---
 techlibs/ice40/ice40_opt.cc | 1 -
 1 file changed, 1 deletion(-)

(limited to 'techlibs/ice40')

diff --git a/techlibs/ice40/ice40_opt.cc b/techlibs/ice40/ice40_opt.cc
index 58f106f7c..ea56d3f4d 100644
--- a/techlibs/ice40/ice40_opt.cc
+++ b/techlibs/ice40/ice40_opt.cc
@@ -125,7 +125,6 @@ static void run_ice40_opts(Module *module)
 				cell->unsetPort("\\I3");
 				cell->unsetPort("\\CO");
 				cell->unsetPort("\\O");
-				cell->setParam("\\LUT", RTLIL::Const::from_string("0110100110010110"));
 				cell->setParam("\\WIDTH", 4);
 			}
 			continue;
-- 
cgit v1.2.3


From e3709e5ee6b28c1156b4768373e244c32c7c5aba Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Wed, 28 Aug 2019 18:51:14 -0700
Subject: LX -> LP

---
 techlibs/ice40/cells_sim.v | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'techlibs/ice40')

diff --git a/techlibs/ice40/cells_sim.v b/techlibs/ice40/cells_sim.v
index 34134d02a..fe80c998d 100644
--- a/techlibs/ice40/cells_sim.v
+++ b/techlibs/ice40/cells_sim.v
@@ -3,7 +3,7 @@
 // `define SB_DFF_REG reg Q
 
 `define ABC_ARRIVAL_HX(TIME) `ifdef ICE40_HX (* abc_arrival=TIME *) `endif
-`define ABC_ARRIVAL_LX(TIME) `ifdef ICE40_LX (* abc_arrival=TIME *) `endif
+`define ABC_ARRIVAL_LP(TIME) `ifdef ICE40_LP (* abc_arrival=TIME *) `endif
 `define ABC_ARRIVAL_U(TIME)  `ifdef ICE40_U (* abc_arrival=TIME *) `endif
 
 // SiliconBlue IO Cells
-- 
cgit v1.2.3


From 927f1e3754987ab794566a521c7a1149d4fbf6a7 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Wed, 28 Aug 2019 18:56:25 -0700
Subject: Add LP timings

---
 techlibs/ice40/cells_sim.v | 26 ++++++++++++++++++++++++++
 1 file changed, 26 insertions(+)

(limited to 'techlibs/ice40')

diff --git a/techlibs/ice40/cells_sim.v b/techlibs/ice40/cells_sim.v
index fe80c998d..b86ec3ea5 100644
--- a/techlibs/ice40/cells_sim.v
+++ b/techlibs/ice40/cells_sim.v
@@ -174,11 +174,13 @@ module \$__ICE40_CARRY_WRAPPER (
 endmodule
 
 // Max delay from: https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L90
+//                 https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L90
 
 // Positive Edge SiliconBlue FF Cells
 
 module SB_DFF (
 	`ABC_ARRIVAL_HX(540)
+	`ABC_ARRIVAL_LP(795)
 	output `SB_DFF_REG,
 	input C, D
 );
@@ -188,6 +190,7 @@ endmodule
 
 module SB_DFFE (
 	`ABC_ARRIVAL_HX(540)
+	`ABC_ARRIVAL_LP(795)
 	output `SB_DFF_REG,
 	input C, E, D
 );
@@ -198,6 +201,7 @@ endmodule
 
 module SB_DFFSR (
 	`ABC_ARRIVAL_HX(540)
+	`ABC_ARRIVAL_LP(795)
 	output `SB_DFF_REG,
 	input C, R, D
 );
@@ -210,6 +214,7 @@ endmodule
 
 module SB_DFFR (
 	`ABC_ARRIVAL_HX(540)
+	`ABC_ARRIVAL_LP(795)
 	output `SB_DFF_REG,
 	input C, R, D
 );
@@ -222,6 +227,7 @@ endmodule
 
 module SB_DFFSS (
 	`ABC_ARRIVAL_HX(540)
+	`ABC_ARRIVAL_LP(795)
 	output `SB_DFF_REG,
 	input C, S, D
 );
@@ -234,6 +240,7 @@ endmodule
 
 module SB_DFFS (
 	`ABC_ARRIVAL_HX(540)
+	`ABC_ARRIVAL_LP(795)
 	output `SB_DFF_REG,
 	input C, S, D
 );
@@ -246,6 +253,7 @@ endmodule
 
 module SB_DFFESR (
 	`ABC_ARRIVAL_HX(540)
+	`ABC_ARRIVAL_LP(795)
 	output `SB_DFF_REG,
 	input C, E, R, D
 );
@@ -260,6 +268,7 @@ endmodule
 
 module SB_DFFER (
 	`ABC_ARRIVAL_HX(540)
+	`ABC_ARRIVAL_LP(795)
 	output `SB_DFF_REG,
 	input C, E, R, D
 );
@@ -272,6 +281,7 @@ endmodule
 
 module SB_DFFESS (
 	`ABC_ARRIVAL_HX(540)
+	`ABC_ARRIVAL_LP(795)
 	output `SB_DFF_REG,
 	input C, E, S, D
 );
@@ -286,6 +296,7 @@ endmodule
 
 module SB_DFFES (
 	`ABC_ARRIVAL_HX(540)
+	`ABC_ARRIVAL_LP(795)
 	output `SB_DFF_REG,
 	input C, E, S, D
 );
@@ -300,6 +311,7 @@ endmodule
 
 module SB_DFFN (
 	`ABC_ARRIVAL_HX(540)
+	`ABC_ARRIVAL_LP(795)
 	output `SB_DFF_REG,
 	input C, D
 );
@@ -309,6 +321,7 @@ endmodule
 
 module SB_DFFNE (
 	`ABC_ARRIVAL_HX(540)
+	`ABC_ARRIVAL_LP(795)
 	output `SB_DFF_REG,
 	input C, E, D
 );
@@ -319,6 +332,7 @@ endmodule
 
 module SB_DFFNSR (
 	`ABC_ARRIVAL_HX(540)
+	`ABC_ARRIVAL_LP(795)
 	output `SB_DFF_REG,
 	input C, R, D
 );
@@ -331,6 +345,7 @@ endmodule
 
 module SB_DFFNR (
 	`ABC_ARRIVAL_HX(540)
+	`ABC_ARRIVAL_LP(795)
 	output `SB_DFF_REG,
 	input C, R, D
 );
@@ -343,6 +358,7 @@ endmodule
 
 module SB_DFFNSS (
 	`ABC_ARRIVAL_HX(540)
+	`ABC_ARRIVAL_LP(795)
 	output `SB_DFF_REG,
 	input C, S, D
 );
@@ -355,6 +371,7 @@ endmodule
 
 module SB_DFFNS (
 	`ABC_ARRIVAL_HX(540)
+	`ABC_ARRIVAL_LP(795)
 	output `SB_DFF_REG,
 	input C, S, D
 );
@@ -367,6 +384,7 @@ endmodule
 
 module SB_DFFNESR (
 	`ABC_ARRIVAL_HX(540)
+	`ABC_ARRIVAL_LP(795)
 	output `SB_DFF_REG,
 	input C, E, R, D
 );
@@ -381,6 +399,7 @@ endmodule
 
 module SB_DFFNER (
 	`ABC_ARRIVAL_HX(540)
+	`ABC_ARRIVAL_LP(795)
 	output `SB_DFF_REG,
 	input C, E, R, D
 );
@@ -393,6 +412,7 @@ endmodule
 
 module SB_DFFNESS (
 	`ABC_ARRIVAL_HX(540)
+	`ABC_ARRIVAL_LP(795)
 	output `SB_DFF_REG,
 	input C, E, S, D
 );
@@ -407,6 +427,7 @@ endmodule
 
 module SB_DFFNES (
 	`ABC_ARRIVAL_HX(540)
+	`ABC_ARRIVAL_LP(795)
 	output `SB_DFF_REG,
 	input C, E, S, D
 );
@@ -421,6 +442,7 @@ endmodule
 
 module SB_RAM40_4K (
 	`ABC_ARRIVAL_HX(2146) // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L401
+	`ABC_ARRIVAL_LP(3163) // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L401
 	output [15:0] RDATA,
 	input         RCLK, RCLKE, RE,
 	input  [10:0] RADDR,
@@ -590,6 +612,7 @@ endmodule
 
 module SB_RAM40_4KNR (
 	`ABC_ARRIVAL_HX(2146) // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L401
+	`ABC_ARRIVAL_LP(3163) // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L401
 	output [15:0] RDATA,
 	input         RCLKN, RCLKE, RE,
 	input  [10:0] RADDR,
@@ -656,6 +679,7 @@ endmodule
 
 module SB_RAM40_4KNW (
 	`ABC_ARRIVAL_HX(2146) // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L401
+	`ABC_ARRIVAL_LP(3163) // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L401
 	output [15:0] RDATA,
 	input         RCLK, RCLKE, RE,
 	input  [10:0] RADDR,
@@ -722,6 +746,7 @@ endmodule
 
 module SB_RAM40_4KNRNW (
 	`ABC_ARRIVAL_HX(2146) // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L401
+	`ABC_ARRIVAL_LP(3163) // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L401
 	output [15:0] RDATA,
 	input         RCLKN, RCLKE, RE,
 	input  [10:0] RADDR,
@@ -792,6 +817,7 @@ module ICESTORM_LC (
 	input I0, I1, I2, I3, CIN, CLK, CEN, SR,
 	output LO,
 	`ABC_ARRIVAL_HX(540)
+	`ABC_ARRIVAL_LP(795)
 	output O,
 	output COUT
 );
-- 
cgit v1.2.3


From 0f4e9f6bc5a5a564b2ddccb0fbebdfa5735aeefd Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Wed, 28 Aug 2019 18:57:34 -0700
Subject: Round not floor

---
 techlibs/ice40/cells_sim.v | 42 +++++++++++++++++++++---------------------
 1 file changed, 21 insertions(+), 21 deletions(-)

(limited to 'techlibs/ice40')

diff --git a/techlibs/ice40/cells_sim.v b/techlibs/ice40/cells_sim.v
index b86ec3ea5..f5fe800f7 100644
--- a/techlibs/ice40/cells_sim.v
+++ b/techlibs/ice40/cells_sim.v
@@ -180,7 +180,7 @@ endmodule
 
 module SB_DFF (
 	`ABC_ARRIVAL_HX(540)
-	`ABC_ARRIVAL_LP(795)
+	`ABC_ARRIVAL_LP(796)
 	output `SB_DFF_REG,
 	input C, D
 );
@@ -190,7 +190,7 @@ endmodule
 
 module SB_DFFE (
 	`ABC_ARRIVAL_HX(540)
-	`ABC_ARRIVAL_LP(795)
+	`ABC_ARRIVAL_LP(796)
 	output `SB_DFF_REG,
 	input C, E, D
 );
@@ -201,7 +201,7 @@ endmodule
 
 module SB_DFFSR (
 	`ABC_ARRIVAL_HX(540)
-	`ABC_ARRIVAL_LP(795)
+	`ABC_ARRIVAL_LP(796)
 	output `SB_DFF_REG,
 	input C, R, D
 );
@@ -214,7 +214,7 @@ endmodule
 
 module SB_DFFR (
 	`ABC_ARRIVAL_HX(540)
-	`ABC_ARRIVAL_LP(795)
+	`ABC_ARRIVAL_LP(796)
 	output `SB_DFF_REG,
 	input C, R, D
 );
@@ -227,7 +227,7 @@ endmodule
 
 module SB_DFFSS (
 	`ABC_ARRIVAL_HX(540)
-	`ABC_ARRIVAL_LP(795)
+	`ABC_ARRIVAL_LP(796)
 	output `SB_DFF_REG,
 	input C, S, D
 );
@@ -240,7 +240,7 @@ endmodule
 
 module SB_DFFS (
 	`ABC_ARRIVAL_HX(540)
-	`ABC_ARRIVAL_LP(795)
+	`ABC_ARRIVAL_LP(796)
 	output `SB_DFF_REG,
 	input C, S, D
 );
@@ -253,7 +253,7 @@ endmodule
 
 module SB_DFFESR (
 	`ABC_ARRIVAL_HX(540)
-	`ABC_ARRIVAL_LP(795)
+	`ABC_ARRIVAL_LP(796)
 	output `SB_DFF_REG,
 	input C, E, R, D
 );
@@ -268,7 +268,7 @@ endmodule
 
 module SB_DFFER (
 	`ABC_ARRIVAL_HX(540)
-	`ABC_ARRIVAL_LP(795)
+	`ABC_ARRIVAL_LP(796)
 	output `SB_DFF_REG,
 	input C, E, R, D
 );
@@ -281,7 +281,7 @@ endmodule
 
 module SB_DFFESS (
 	`ABC_ARRIVAL_HX(540)
-	`ABC_ARRIVAL_LP(795)
+	`ABC_ARRIVAL_LP(796)
 	output `SB_DFF_REG,
 	input C, E, S, D
 );
@@ -296,7 +296,7 @@ endmodule
 
 module SB_DFFES (
 	`ABC_ARRIVAL_HX(540)
-	`ABC_ARRIVAL_LP(795)
+	`ABC_ARRIVAL_LP(796)
 	output `SB_DFF_REG,
 	input C, E, S, D
 );
@@ -311,7 +311,7 @@ endmodule
 
 module SB_DFFN (
 	`ABC_ARRIVAL_HX(540)
-	`ABC_ARRIVAL_LP(795)
+	`ABC_ARRIVAL_LP(796)
 	output `SB_DFF_REG,
 	input C, D
 );
@@ -321,7 +321,7 @@ endmodule
 
 module SB_DFFNE (
 	`ABC_ARRIVAL_HX(540)
-	`ABC_ARRIVAL_LP(795)
+	`ABC_ARRIVAL_LP(796)
 	output `SB_DFF_REG,
 	input C, E, D
 );
@@ -332,7 +332,7 @@ endmodule
 
 module SB_DFFNSR (
 	`ABC_ARRIVAL_HX(540)
-	`ABC_ARRIVAL_LP(795)
+	`ABC_ARRIVAL_LP(796)
 	output `SB_DFF_REG,
 	input C, R, D
 );
@@ -345,7 +345,7 @@ endmodule
 
 module SB_DFFNR (
 	`ABC_ARRIVAL_HX(540)
-	`ABC_ARRIVAL_LP(795)
+	`ABC_ARRIVAL_LP(796)
 	output `SB_DFF_REG,
 	input C, R, D
 );
@@ -358,7 +358,7 @@ endmodule
 
 module SB_DFFNSS (
 	`ABC_ARRIVAL_HX(540)
-	`ABC_ARRIVAL_LP(795)
+	`ABC_ARRIVAL_LP(796)
 	output `SB_DFF_REG,
 	input C, S, D
 );
@@ -371,7 +371,7 @@ endmodule
 
 module SB_DFFNS (
 	`ABC_ARRIVAL_HX(540)
-	`ABC_ARRIVAL_LP(795)
+	`ABC_ARRIVAL_LP(796)
 	output `SB_DFF_REG,
 	input C, S, D
 );
@@ -384,7 +384,7 @@ endmodule
 
 module SB_DFFNESR (
 	`ABC_ARRIVAL_HX(540)
-	`ABC_ARRIVAL_LP(795)
+	`ABC_ARRIVAL_LP(796)
 	output `SB_DFF_REG,
 	input C, E, R, D
 );
@@ -399,7 +399,7 @@ endmodule
 
 module SB_DFFNER (
 	`ABC_ARRIVAL_HX(540)
-	`ABC_ARRIVAL_LP(795)
+	`ABC_ARRIVAL_LP(796)
 	output `SB_DFF_REG,
 	input C, E, R, D
 );
@@ -412,7 +412,7 @@ endmodule
 
 module SB_DFFNESS (
 	`ABC_ARRIVAL_HX(540)
-	`ABC_ARRIVAL_LP(795)
+	`ABC_ARRIVAL_LP(796)
 	output `SB_DFF_REG,
 	input C, E, S, D
 );
@@ -427,7 +427,7 @@ endmodule
 
 module SB_DFFNES (
 	`ABC_ARRIVAL_HX(540)
-	`ABC_ARRIVAL_LP(795)
+	`ABC_ARRIVAL_LP(796)
 	output `SB_DFF_REG,
 	input C, E, S, D
 );
@@ -817,7 +817,7 @@ module ICESTORM_LC (
 	input I0, I1, I2, I3, CIN, CLK, CEN, SR,
 	output LO,
 	`ABC_ARRIVAL_HX(540)
-	`ABC_ARRIVAL_LP(795)
+	`ABC_ARRIVAL_LP(796)
 	output O,
 	output COUT
 );
-- 
cgit v1.2.3


From 4bda902f1b9dccb5603c2beebd71392cbfe34eb9 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Wed, 28 Aug 2019 19:02:54 -0700
Subject: LX -> LP

---
 techlibs/ice40/synth_ice40.cc | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'techlibs/ice40')

diff --git a/techlibs/ice40/synth_ice40.cc b/techlibs/ice40/synth_ice40.cc
index 2f77c03db..a3890268a 100644
--- a/techlibs/ice40/synth_ice40.cc
+++ b/techlibs/ice40/synth_ice40.cc
@@ -240,7 +240,7 @@ struct SynthIce40Pass : public ScriptPass
 		{
 			std::string define;
 			if (device_opt == "lp")
-				define = "-D ICE40_LX";
+				define = "-D ICE40_LP";
 			else if (device_opt == "u")
 				define = "-D ICE40_U";
 			else
-- 
cgit v1.2.3


From efa4ee5c0e6201f357d7c02a7deeb1ba1c23c368 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Wed, 28 Aug 2019 19:03:29 -0700
Subject: Add arrival times for U

---
 techlibs/ice40/cells_sim.v | 26 ++++++++++++++++++++++++++
 1 file changed, 26 insertions(+)

(limited to 'techlibs/ice40')

diff --git a/techlibs/ice40/cells_sim.v b/techlibs/ice40/cells_sim.v
index f5fe800f7..116188acb 100644
--- a/techlibs/ice40/cells_sim.v
+++ b/techlibs/ice40/cells_sim.v
@@ -175,12 +175,14 @@ endmodule
 
 // Max delay from: https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L90
 //                 https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L90
+//                 https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L102
 
 // Positive Edge SiliconBlue FF Cells
 
 module SB_DFF (
 	`ABC_ARRIVAL_HX(540)
 	`ABC_ARRIVAL_LP(796)
+	`ABC_ARRIVAL_U(1391)
 	output `SB_DFF_REG,
 	input C, D
 );
@@ -191,6 +193,7 @@ endmodule
 module SB_DFFE (
 	`ABC_ARRIVAL_HX(540)
 	`ABC_ARRIVAL_LP(796)
+	`ABC_ARRIVAL_U(1391)
 	output `SB_DFF_REG,
 	input C, E, D
 );
@@ -202,6 +205,7 @@ endmodule
 module SB_DFFSR (
 	`ABC_ARRIVAL_HX(540)
 	`ABC_ARRIVAL_LP(796)
+	`ABC_ARRIVAL_U(1391)
 	output `SB_DFF_REG,
 	input C, R, D
 );
@@ -215,6 +219,7 @@ endmodule
 module SB_DFFR (
 	`ABC_ARRIVAL_HX(540)
 	`ABC_ARRIVAL_LP(796)
+	`ABC_ARRIVAL_U(1391)
 	output `SB_DFF_REG,
 	input C, R, D
 );
@@ -228,6 +233,7 @@ endmodule
 module SB_DFFSS (
 	`ABC_ARRIVAL_HX(540)
 	`ABC_ARRIVAL_LP(796)
+	`ABC_ARRIVAL_U(1391)
 	output `SB_DFF_REG,
 	input C, S, D
 );
@@ -241,6 +247,7 @@ endmodule
 module SB_DFFS (
 	`ABC_ARRIVAL_HX(540)
 	`ABC_ARRIVAL_LP(796)
+	`ABC_ARRIVAL_U(1391)
 	output `SB_DFF_REG,
 	input C, S, D
 );
@@ -254,6 +261,7 @@ endmodule
 module SB_DFFESR (
 	`ABC_ARRIVAL_HX(540)
 	`ABC_ARRIVAL_LP(796)
+	`ABC_ARRIVAL_U(1391)
 	output `SB_DFF_REG,
 	input C, E, R, D
 );
@@ -269,6 +277,7 @@ endmodule
 module SB_DFFER (
 	`ABC_ARRIVAL_HX(540)
 	`ABC_ARRIVAL_LP(796)
+	`ABC_ARRIVAL_U(1391)
 	output `SB_DFF_REG,
 	input C, E, R, D
 );
@@ -282,6 +291,7 @@ endmodule
 module SB_DFFESS (
 	`ABC_ARRIVAL_HX(540)
 	`ABC_ARRIVAL_LP(796)
+	`ABC_ARRIVAL_U(1391)
 	output `SB_DFF_REG,
 	input C, E, S, D
 );
@@ -297,6 +307,7 @@ endmodule
 module SB_DFFES (
 	`ABC_ARRIVAL_HX(540)
 	`ABC_ARRIVAL_LP(796)
+	`ABC_ARRIVAL_U(1391)
 	output `SB_DFF_REG,
 	input C, E, S, D
 );
@@ -312,6 +323,7 @@ endmodule
 module SB_DFFN (
 	`ABC_ARRIVAL_HX(540)
 	`ABC_ARRIVAL_LP(796)
+	`ABC_ARRIVAL_U(1391)
 	output `SB_DFF_REG,
 	input C, D
 );
@@ -322,6 +334,7 @@ endmodule
 module SB_DFFNE (
 	`ABC_ARRIVAL_HX(540)
 	`ABC_ARRIVAL_LP(796)
+	`ABC_ARRIVAL_U(1391)
 	output `SB_DFF_REG,
 	input C, E, D
 );
@@ -333,6 +346,7 @@ endmodule
 module SB_DFFNSR (
 	`ABC_ARRIVAL_HX(540)
 	`ABC_ARRIVAL_LP(796)
+	`ABC_ARRIVAL_U(1391)
 	output `SB_DFF_REG,
 	input C, R, D
 );
@@ -346,6 +360,7 @@ endmodule
 module SB_DFFNR (
 	`ABC_ARRIVAL_HX(540)
 	`ABC_ARRIVAL_LP(796)
+	`ABC_ARRIVAL_U(1391)
 	output `SB_DFF_REG,
 	input C, R, D
 );
@@ -359,6 +374,7 @@ endmodule
 module SB_DFFNSS (
 	`ABC_ARRIVAL_HX(540)
 	`ABC_ARRIVAL_LP(796)
+	`ABC_ARRIVAL_U(1391)
 	output `SB_DFF_REG,
 	input C, S, D
 );
@@ -372,6 +388,7 @@ endmodule
 module SB_DFFNS (
 	`ABC_ARRIVAL_HX(540)
 	`ABC_ARRIVAL_LP(796)
+	`ABC_ARRIVAL_U(1391)
 	output `SB_DFF_REG,
 	input C, S, D
 );
@@ -385,6 +402,7 @@ endmodule
 module SB_DFFNESR (
 	`ABC_ARRIVAL_HX(540)
 	`ABC_ARRIVAL_LP(796)
+	`ABC_ARRIVAL_U(1391)
 	output `SB_DFF_REG,
 	input C, E, R, D
 );
@@ -400,6 +418,7 @@ endmodule
 module SB_DFFNER (
 	`ABC_ARRIVAL_HX(540)
 	`ABC_ARRIVAL_LP(796)
+	`ABC_ARRIVAL_U(1391)
 	output `SB_DFF_REG,
 	input C, E, R, D
 );
@@ -413,6 +432,7 @@ endmodule
 module SB_DFFNESS (
 	`ABC_ARRIVAL_HX(540)
 	`ABC_ARRIVAL_LP(796)
+	`ABC_ARRIVAL_U(1391)
 	output `SB_DFF_REG,
 	input C, E, S, D
 );
@@ -428,6 +448,7 @@ endmodule
 module SB_DFFNES (
 	`ABC_ARRIVAL_HX(540)
 	`ABC_ARRIVAL_LP(796)
+	`ABC_ARRIVAL_U(1391)
 	output `SB_DFF_REG,
 	input C, E, S, D
 );
@@ -443,6 +464,7 @@ endmodule
 module SB_RAM40_4K (
 	`ABC_ARRIVAL_HX(2146) // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L401
 	`ABC_ARRIVAL_LP(3163) // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L401
+	`ABC_ARRIVAL_U(1179)  // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L13026
 	output [15:0] RDATA,
 	input         RCLK, RCLKE, RE,
 	input  [10:0] RADDR,
@@ -613,6 +635,7 @@ endmodule
 module SB_RAM40_4KNR (
 	`ABC_ARRIVAL_HX(2146) // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L401
 	`ABC_ARRIVAL_LP(3163) // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L401
+	`ABC_ARRIVAL_U(1179)  // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L13026
 	output [15:0] RDATA,
 	input         RCLKN, RCLKE, RE,
 	input  [10:0] RADDR,
@@ -680,6 +703,7 @@ endmodule
 module SB_RAM40_4KNW (
 	`ABC_ARRIVAL_HX(2146) // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L401
 	`ABC_ARRIVAL_LP(3163) // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L401
+	`ABC_ARRIVAL_U(1179)  // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L13026
 	output [15:0] RDATA,
 	input         RCLK, RCLKE, RE,
 	input  [10:0] RADDR,
@@ -747,6 +771,7 @@ endmodule
 module SB_RAM40_4KNRNW (
 	`ABC_ARRIVAL_HX(2146) // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L401
 	`ABC_ARRIVAL_LP(3163) // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L401
+	`ABC_ARRIVAL_U(1179)  // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L13026
 	output [15:0] RDATA,
 	input         RCLKN, RCLKE, RE,
 	input  [10:0] RADDR,
@@ -818,6 +843,7 @@ module ICESTORM_LC (
 	output LO,
 	`ABC_ARRIVAL_HX(540)
 	`ABC_ARRIVAL_LP(796)
+	`ABC_ARRIVAL_U(1391)
 	output O,
 	output COUT
 );
-- 
cgit v1.2.3


From 309684af16c763f7874beb605d0834c64975d004 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Wed, 28 Aug 2019 19:07:28 -0700
Subject: Add arrival for SB_MAC16.O

---
 techlibs/ice40/cells_sim.v | 1 +
 1 file changed, 1 insertion(+)

(limited to 'techlibs/ice40')

diff --git a/techlibs/ice40/cells_sim.v b/techlibs/ice40/cells_sim.v
index 116188acb..f4cc342eb 100644
--- a/techlibs/ice40/cells_sim.v
+++ b/techlibs/ice40/cells_sim.v
@@ -1445,6 +1445,7 @@ module SB_MAC16 (
 	input ADDSUBTOP, ADDSUBBOT,
 	input OHOLDTOP, OHOLDBOT,
 	input CI, ACCUMCI, SIGNEXTIN,
+	`ABC_ARRIVAL_U(1984)  // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L587
 	output [31:0] O,
 	output CO, ACCUMCO, SIGNEXTOUT
 );
-- 
cgit v1.2.3


From e8e38308689a760b69bd2910a36701b19f64656d Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Wed, 28 Aug 2019 19:09:29 -0700
Subject: Comment out SB_MAC16 arrival time for now, need to handle all its
 modes

---
 techlibs/ice40/cells_sim.v | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'techlibs/ice40')

diff --git a/techlibs/ice40/cells_sim.v b/techlibs/ice40/cells_sim.v
index f4cc342eb..8e5e0358e 100644
--- a/techlibs/ice40/cells_sim.v
+++ b/techlibs/ice40/cells_sim.v
@@ -1445,7 +1445,7 @@ module SB_MAC16 (
 	input ADDSUBTOP, ADDSUBBOT,
 	input OHOLDTOP, OHOLDBOT,
 	input CI, ACCUMCI, SIGNEXTIN,
-	`ABC_ARRIVAL_U(1984)  // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L587
+	//`ABC_ARRIVAL_U(1984)  // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L13026
 	output [31:0] O,
 	output CO, ACCUMCO, SIGNEXTOUT
 );
-- 
cgit v1.2.3


From 25b1670a8425198abfcef4602a3d1ddcc0ca5d40 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Thu, 29 Aug 2019 07:03:32 -0700
Subject: Rename boxes too

---
 techlibs/ice40/abc_hx.box | 2 +-
 techlibs/ice40/abc_lp.box | 2 +-
 techlibs/ice40/abc_u.box  | 2 +-
 3 files changed, 3 insertions(+), 3 deletions(-)

(limited to 'techlibs/ice40')

diff --git a/techlibs/ice40/abc_hx.box b/techlibs/ice40/abc_hx.box
index 571152129..3ea70bc91 100644
--- a/techlibs/ice40/abc_hx.box
+++ b/techlibs/ice40/abc_hx.box
@@ -8,6 +8,6 @@
 #   (NB: carry chain input/output must be last
 #        input/output and have been moved there
 #        overriding the alphabetical ordering)
-$__ICE40_FULL_ADDER 1 1 5 2
+$__ICE40_CARRY_WRAPPER 1 1 5 2
 400 379 449 316 316
 259 231 -   -   126
diff --git a/techlibs/ice40/abc_lp.box b/techlibs/ice40/abc_lp.box
index a9f8699fc..473e92fe9 100644
--- a/techlibs/ice40/abc_lp.box
+++ b/techlibs/ice40/abc_lp.box
@@ -8,6 +8,6 @@
 #   (NB: carry chain input/output must be last
 #        input/output and have been moved there
 #        overriding the alphabetical ordering)
-$__ICE40_FULL_ADDER 1 1 5 2
+$__ICE40_CARRY_WRAPPER 1 1 5 2
 589 558 661 465 465
 675 609 -   -   186
diff --git a/techlibs/ice40/abc_u.box b/techlibs/ice40/abc_u.box
index bc8a8d9cd..f00e247b8 100644
--- a/techlibs/ice40/abc_u.box
+++ b/techlibs/ice40/abc_u.box
@@ -8,6 +8,6 @@
 #   (NB: carry chain input/output must be last
 #        input/output and have been moved there
 #        overriding the alphabetical ordering)
-$__ICE40_FULL_ADDER 1 1 5 2
+$__ICE40_CARRY_WRAPPER 1 1 5 2
 1231 1205 1285 874 874
 675  609  -    -   278
-- 
cgit v1.2.3