From 3b405d985e789ecf0082f724d2d62d3752e4b60c Mon Sep 17 00:00:00 2001 From: "N. Engelhardt" Date: Thu, 17 Oct 2019 21:33:54 +0200 Subject: Call memory_dff before DSP mapping to reserve registers (fixes #1447) --- techlibs/ice40/synth_ice40.cc | 1 + 1 file changed, 1 insertion(+) (limited to 'techlibs/ice40') diff --git a/techlibs/ice40/synth_ice40.cc b/techlibs/ice40/synth_ice40.cc index b66c6bf57..c942126e1 100644 --- a/techlibs/ice40/synth_ice40.cc +++ b/techlibs/ice40/synth_ice40.cc @@ -273,6 +273,7 @@ struct SynthIce40Pass : public ScriptPass run("opt_expr"); run("opt_clean"); if (help_mode || dsp) { + run("memory_dff"); run("techmap -map +/mul2dsp.v -map +/ice40/dsp_map.v -D DSP_A_MAXWIDTH=16 -D DSP_B_MAXWIDTH=16 " "-D DSP_A_MINWIDTH=2 -D DSP_B_MINWIDTH=2 -D DSP_Y_MINWIDTH=11 " "-D DSP_NAME=$__MUL16X16", "(if -dsp)"); -- cgit v1.2.3 From 82f60ba938749ab20694f9070f1046e393f16f3c Mon Sep 17 00:00:00 2001 From: Sean Cross Date: Sat, 19 Oct 2019 14:04:52 +0800 Subject: Makefile: don't assume python is called `python3` On some architectures, notably on Windows, the official name for the Python binary from python.org is `python`. The build system assumes that python is called `python3`, which breaks under this architecture. There is already infrastructure in place to determine the name of the Python binary when building PYOSYS. Since Python is now always required to build Yosys, enable this check universally which sets the `PYTHON_EXECUTABLE` variable. Then, reuse this variable in other Makefiles as necessary, rather than hardcoding `python3` everywhere. Signed-off-by: Sean Cross --- techlibs/ice40/Makefile.inc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'techlibs/ice40') diff --git a/techlibs/ice40/Makefile.inc b/techlibs/ice40/Makefile.inc index 3c33fcb06..31478e80e 100644 --- a/techlibs/ice40/Makefile.inc +++ b/techlibs/ice40/Makefile.inc @@ -14,7 +14,7 @@ EXTRA_OBJS += techlibs/ice40/brams_init.mk techlibs/ice40/brams_init.mk: techlibs/ice40/brams_init.py $(Q) mkdir -p techlibs/ice40 - $(P) python3 $< + $(P) $(PYTHON_EXECUTABLE) $< $(Q) touch techlibs/ice40/brams_init.mk techlibs/ice40/brams_init1.vh: techlibs/ice40/brams_init.mk -- cgit v1.2.3 From 37dd3ad3fe434243303e11c22831579569324def Mon Sep 17 00:00:00 2001 From: David Shah Date: Sun, 20 Oct 2019 10:24:47 +0100 Subject: ice40: Support for post-pnr timing simulation Signed-off-by: David Shah --- techlibs/ice40/cells_sim.v | 108 ++++++++++++++++++++++++++++++++++++++++----- 1 file changed, 96 insertions(+), 12 deletions(-) (limited to 'techlibs/ice40') diff --git a/techlibs/ice40/cells_sim.v b/techlibs/ice40/cells_sim.v index f9e79a61d..4e008ed5e 100644 --- a/techlibs/ice40/cells_sim.v +++ b/techlibs/ice40/cells_sim.v @@ -1,4 +1,4 @@ - +`timescale 1ps / 1ps `define SB_DFF_REG reg Q = 0 // `define SB_DFF_REG reg Q @@ -81,6 +81,37 @@ module SB_IO ( if (PIN_TYPE[5:4] == 2'b11) assign PACKAGE_PIN = outena_q ? dout : 1'bz; endgenerate `endif +`ifdef TIMING +specify + (INPUT_CLK => D_IN_0) = (0:0:0, 0:0:0); + (INPUT_CLK => D_IN_1) = (0:0:0, 0:0:0); + (PACKAGE_PIN => D_IN_0) = (0:0:0, 0:0:0); + (OUTPUT_CLK => PACKAGE_PIN) = (0:0:0, 0:0:0); + (D_OUT_0 => PACKAGE_PIN) = (0:0:0, 0:0:0); + (OUTPUT_ENABLE => PACKAGE_PIN) = (0:0:0, 0:0:0); + + $setuphold(posedge OUTPUT_CLK, posedge D_OUT_0, 0:0:0, 0:0:0); + $setuphold(posedge OUTPUT_CLK, negedge D_OUT_0, 0:0:0, 0:0:0); + $setuphold(negedge OUTPUT_CLK, posedge D_OUT_1, 0:0:0, 0:0:0); + $setuphold(negedge OUTPUT_CLK, negedge D_OUT_1, 0:0:0, 0:0:0); + $setuphold(negedge OUTPUT_CLK, posedge D_OUT_0, 0:0:0, 0:0:0); + $setuphold(negedge OUTPUT_CLK, negedge D_OUT_0, 0:0:0, 0:0:0); + $setuphold(posedge OUTPUT_CLK, posedge D_OUT_1, 0:0:0, 0:0:0); + $setuphold(posedge OUTPUT_CLK, negedge D_OUT_1, 0:0:0, 0:0:0); + $setuphold(posedge INPUT_CLK, posedge CLOCK_ENABLE, 0:0:0, 0:0:0); + $setuphold(posedge INPUT_CLK, negedge CLOCK_ENABLE, 0:0:0, 0:0:0); + $setuphold(posedge OUTPUT_CLK, posedge CLOCK_ENABLE, 0:0:0, 0:0:0); + $setuphold(posedge OUTPUT_CLK, negedge CLOCK_ENABLE, 0:0:0, 0:0:0); + $setuphold(posedge INPUT_CLK, posedge PACKAGE_PIN, 0:0:0, 0:0:0); + $setuphold(posedge INPUT_CLK, negedge PACKAGE_PIN, 0:0:0, 0:0:0); + $setuphold(negedge INPUT_CLK, posedge PACKAGE_PIN, 0:0:0, 0:0:0); + $setuphold(negedge INPUT_CLK, negedge PACKAGE_PIN, 0:0:0, 0:0:0); + $setuphold(posedge OUTPUT_CLK, posedge OUTPUT_ENABLE, 0:0:0, 0:0:0); + $setuphold(posedge OUTPUT_CLK, negedge OUTPUT_ENABLE, 0:0:0, 0:0:0); + $setuphold(negedge OUTPUT_CLK, posedge OUTPUT_ENABLE, 0:0:0, 0:0:0); + $setuphold(negedge OUTPUT_CLK, negedge OUTPUT_ENABLE, 0:0:0, 0:0:0); +endspecify +`endif endmodule module SB_GB_IO ( @@ -127,6 +158,11 @@ module SB_GB ( output GLOBAL_BUFFER_OUTPUT ); assign GLOBAL_BUFFER_OUTPUT = USER_SIGNAL_TO_GLOBAL_BUFFER; +`ifdef TIMING +specify + (USER_SIGNAL_TO_GLOBAL_BUFFER => GLOBAL_BUFFER_OUTPUT) = (0:0:0, 0:0:0); +endspecify +`endif endmodule // SiliconBlue Logic Cells @@ -830,33 +866,81 @@ module ICESTORM_LC ( parameter [0:0] CIN_CONST = 0; parameter [0:0] CIN_SET = 0; + wire I0_pd = (I0 === 1'bz) ? 1'b0 : I0; + wire I1_pd = (I1 === 1'bz) ? 1'b0 : I1; + wire I2_pd = (I2 === 1'bz) ? 1'b0 : I2; + wire I3_pd = (I3 === 1'bz) ? 1'b0 : I3; + wire SR_pd = (SR === 1'bz) ? 1'b0 : SR; + wire CEN_pu = (CEN === 1'bz) ? 1'b1 : CEN; + wire mux_cin = CIN_CONST ? CIN_SET : CIN; - assign COUT = CARRY_ENABLE ? (I1 && I2) || ((I1 || I2) && mux_cin) : 1'bx; + assign COUT = CARRY_ENABLE ? (I1_pd && I2_pd) || ((I1_pd || I2_pd) && mux_cin) : 1'bx; - wire [7:0] lut_s3 = I3 ? LUT_INIT[15:8] : LUT_INIT[7:0]; - wire [3:0] lut_s2 = I2 ? lut_s3[ 7:4] : lut_s3[3:0]; - wire [1:0] lut_s1 = I1 ? lut_s2[ 3:2] : lut_s2[1:0]; - wire lut_o = I0 ? lut_s1[ 1] : lut_s1[ 0]; + wire [7:0] lut_s3 = I3_pd ? LUT_INIT[15:8] : LUT_INIT[7:0]; + wire [3:0] lut_s2 = I2_pd ? lut_s3[ 7:4] : lut_s3[3:0]; + wire [1:0] lut_s1 = I1_pd ? lut_s2[ 3:2] : lut_s2[1:0]; + wire lut_o = I0_pd ? lut_s1[ 1] : lut_s1[ 0]; assign LO = lut_o; wire polarized_clk; assign polarized_clk = CLK ^ NEG_CLK; - reg o_reg; + reg o_reg = 1'b0; always @(posedge polarized_clk) - if (CEN) - o_reg <= SR ? SET_NORESET : lut_o; + if (CEN_pu) + o_reg <= SR_pd ? SET_NORESET : lut_o; - reg o_reg_async; + reg o_reg_async = 1'b0; always @(posedge polarized_clk, posedge SR) - if (SR) + if (SR_pd) o_reg <= SET_NORESET; - else if (CEN) + else if (CEN_pu) o_reg <= lut_o; assign O = DFF_ENABLE ? ASYNC_SR ? o_reg_async : o_reg : lut_o; +`ifdef TIMING +specify + (I0 => O) = (0:0:0, 0:0:0); + (I1 => O) = (0:0:0, 0:0:0); + (I2 => O) = (0:0:0, 0:0:0); + (I3 => O) = (0:0:0, 0:0:0); + (I0 => LO) = (0:0:0, 0:0:0); + (I1 => LO) = (0:0:0, 0:0:0); + (I2 => LO) = (0:0:0, 0:0:0); + (I3 => LO) = (0:0:0, 0:0:0); + (I1 => COUT) = (0:0:0, 0:0:0); + (I2 => COUT) = (0:0:0, 0:0:0); + (CIN => COUT) = (0:0:0, 0:0:0); + (CLK => O) = (0:0:0, 0:0:0); + (SR => O) = (0:0:0, 0:0:0); + $setuphold(posedge CLK, posedge I0, 0:0:0, 0:0:0); + $setuphold(posedge CLK, negedge I0, 0:0:0, 0:0:0); + $setuphold(negedge CLK, posedge I0, 0:0:0, 0:0:0); + $setuphold(negedge CLK, negedge I0, 0:0:0, 0:0:0); + $setuphold(posedge CLK, posedge I1, 0:0:0, 0:0:0); + $setuphold(posedge CLK, negedge I1, 0:0:0, 0:0:0); + $setuphold(negedge CLK, posedge I1, 0:0:0, 0:0:0); + $setuphold(negedge CLK, negedge I1, 0:0:0, 0:0:0); + $setuphold(posedge CLK, posedge I2, 0:0:0, 0:0:0); + $setuphold(posedge CLK, negedge I2, 0:0:0, 0:0:0); + $setuphold(negedge CLK, posedge I2, 0:0:0, 0:0:0); + $setuphold(negedge CLK, negedge I2, 0:0:0, 0:0:0); + $setuphold(posedge CLK, posedge I3, 0:0:0, 0:0:0); + $setuphold(posedge CLK, negedge I3, 0:0:0, 0:0:0); + $setuphold(negedge CLK, posedge I3, 0:0:0, 0:0:0); + $setuphold(negedge CLK, negedge I3, 0:0:0, 0:0:0); + $setuphold(posedge CLK, posedge CEN, 0:0:0, 0:0:0); + $setuphold(posedge CLK, negedge CEN, 0:0:0, 0:0:0); + $setuphold(negedge CLK, posedge CEN, 0:0:0, 0:0:0); + $setuphold(negedge CLK, negedge CEN, 0:0:0, 0:0:0); + $setuphold(posedge CLK, posedge SR, 0:0:0, 0:0:0); + $setuphold(posedge CLK, negedge SR, 0:0:0, 0:0:0); + $setuphold(negedge CLK, posedge SR, 0:0:0, 0:0:0); + $setuphold(negedge CLK, negedge SR, 0:0:0, 0:0:0); +endspecify +`endif endmodule // SiliconBlue PLL Cells -- cgit v1.2.3 From e135ed5d809ae97b0d4d25ff454456aea44af8fc Mon Sep 17 00:00:00 2001 From: David Shah Date: Wed, 23 Oct 2019 18:44:34 +0100 Subject: ice40: Add post-pnr ICESTORM_RAM model and fix FFs Signed-off-by: David Shah --- techlibs/ice40/cells_sim.v | 342 ++++++++++++++++++++++++++++++++++++++++++++- 1 file changed, 340 insertions(+), 2 deletions(-) (limited to 'techlibs/ice40') diff --git a/techlibs/ice40/cells_sim.v b/techlibs/ice40/cells_sim.v index 4e008ed5e..7d1b37fd6 100644 --- a/techlibs/ice40/cells_sim.v +++ b/techlibs/ice40/cells_sim.v @@ -895,9 +895,9 @@ module ICESTORM_LC ( reg o_reg_async = 1'b0; always @(posedge polarized_clk, posedge SR) if (SR_pd) - o_reg <= SET_NORESET; + o_reg_async <= SET_NORESET; else if (CEN_pu) - o_reg <= lut_o; + o_reg_async <= lut_o; assign O = DFF_ENABLE ? ASYNC_SR ? o_reg_async : o_reg : lut_o; `ifdef TIMING @@ -1660,3 +1660,341 @@ module SB_MAC16 ( assign LCI = (BOTADDSUB_CARRYSELECT == 0) ? 1'b0 : (BOTADDSUB_CARRYSELECT == 1) ? 1'b1 : (BOTADDSUB_CARRYSELECT == 2) ? ACCUMCI : CI; assign O = {Oh, Ol}; endmodule + +// Post-place-and-route RAM model +module ICESTORM_RAM( + output RDATA_15, RDATA_14, RDATA_13, RDATA_12, RDATA_11, RDATA_10, RDATA_9, RDATA_8, RDATA_7, RDATA_6, RDATA_5, RDATA_4, RDATA_3, RDATA_2, RDATA_1, RDATA_0, + input RCLK, RCLKE, RE, + input RADDR_10, RADDR_9, RADDR_8, RADDR_7, RADDR_6, RADDR_5, RADDR_4, RADDR_3, RADDR_2, RADDR_1, RADDR_0, + input WCLK, WCLKE, WE, + input WADDR_10, WADDR_9, WADDR_8, WADDR_7, WADDR_6, WADDR_5, WADDR_4, WADDR_3, WADDR_2, WADDR_1, WADDR_0, + input MASK_15, MASK_14, MASK_13, MASK_12, MASK_11, MASK_10, MASK_9, MASK_8, MASK_7, MASK_6, MASK_5, MASK_4, MASK_3, MASK_2, MASK_1, MASK_0, + input WDATA_15, WDATA_14, WDATA_13, WDATA_12, WDATA_11, WDATA_10, WDATA_9, WDATA_8, WDATA_7, WDATA_6, WDATA_5, WDATA_4, WDATA_3, WDATA_2, WDATA_1, WDATA_0 +); + parameter WRITE_MODE = 0; + parameter READ_MODE = 0; + + parameter NEG_CLK_R = 1'b0; + parameter NEG_CLK_W = 1'b0; + + parameter INIT_0 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_1 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_2 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_3 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_4 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_5 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_6 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_7 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_8 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_9 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + + // Pull-down and pull-up functions + function pd; + input x; + begin + pd = (x === 1'bz) ? 1'b0 : x; + end + endfunction + + function pu; + input x; + begin + pu = (x === 1'bz) ? 1'b1 : x; + end + endfunction + + SB_RAM40_4K #( + .WRITE_MODE(WRITE_MODE), + .READ_MODE (READ_MODE ), + .INIT_0 (INIT_0 ), + .INIT_1 (INIT_1 ), + .INIT_2 (INIT_2 ), + .INIT_3 (INIT_3 ), + .INIT_4 (INIT_4 ), + .INIT_5 (INIT_5 ), + .INIT_6 (INIT_6 ), + .INIT_7 (INIT_7 ), + .INIT_8 (INIT_8 ), + .INIT_9 (INIT_9 ), + .INIT_A (INIT_A ), + .INIT_B (INIT_B ), + .INIT_C (INIT_C ), + .INIT_D (INIT_D ), + .INIT_E (INIT_E ), + .INIT_F (INIT_F ) + ) RAM ( + .RDATA({RDATA_15, RDATA_14, RDATA_13, RDATA_12, RDATA_11, RDATA_10, RDATA_9, RDATA_8, RDATA_7, RDATA_6, RDATA_5, RDATA_4, RDATA_3, RDATA_2, RDATA_1, RDATA_0}), + .RCLK (pd(RCLK) ^ NEG_CLK_R), + .RCLKE(pu(RCLKE)), + .RE (pd(RE)), + .RADDR({pd(RADDR_10), pd(RADDR_9), pd(RADDR_8), pd(RADDR_7), pd(RADDR_6), pd(RADDR_5), pd(RADDR_4), pd(RADDR_3), pd(RADDR_2), pd(RADDR_1), pd(RADDR_0)}), + .WCLK (pd(WCLK) ^ NEG_CLK_W), + .WCLKE(pu(WCLKE)), + .WE (pd(WE)), + .WADDR({pd(WADDR_10), pd(WADDR_9), pd(WADDR_8), pd(WADDR_7), pd(WADDR_6), pd(WADDR_5), pd(WADDR_4), pd(WADDR_3), pd(WADDR_2), pd(WADDR_1), pd(WADDR_0)}), + .MASK ({pd(MASK_15), pd(MASK_14), pd(MASK_13), pd(MASK_12), pd(MASK_11), pd(MASK_10), pd(MASK_9), pd(MASK_8), + pd(MASK_7), pd(MASK_6), pd(MASK_5), pd(MASK_4), pd(MASK_3), pd(MASK_2), pd(MASK_1), pd(MASK_0)}), + .WDATA({pd(WDATA_15), pd(WDATA_14), pd(WDATA_13), pd(WDATA_12), pd(WDATA_11), pd(WDATA_10), pd(WDATA_9), pd(WDATA_8), + pd(WDATA_7), pd(WDATA_6), pd(WDATA_5), pd(WDATA_4), pd(WDATA_3), pd(WDATA_2), pd(WDATA_1), pd(WDATA_0)}) + ); + +`ifdef TIMING +specify + (RCLK => RDATA_15) = (0:0:0, 0:0:0); + (RCLK => RDATA_14) = (0:0:0, 0:0:0); + (RCLK => RDATA_13) = (0:0:0, 0:0:0); + (RCLK => RDATA_12) = (0:0:0, 0:0:0); + (RCLK => RDATA_11) = (0:0:0, 0:0:0); + (RCLK => RDATA_10) = (0:0:0, 0:0:0); + (RCLK => RDATA_9) = (0:0:0, 0:0:0); + (RCLK => RDATA_8) = (0:0:0, 0:0:0); + (RCLK => RDATA_7) = (0:0:0, 0:0:0); + (RCLK => RDATA_6) = (0:0:0, 0:0:0); + (RCLK => RDATA_5) = (0:0:0, 0:0:0); + (RCLK => RDATA_4) = (0:0:0, 0:0:0); + (RCLK => RDATA_3) = (0:0:0, 0:0:0); + (RCLK => RDATA_2) = (0:0:0, 0:0:0); + (RCLK => RDATA_1) = (0:0:0, 0:0:0); + (RCLK => RDATA_0) = (0:0:0, 0:0:0); + $setuphold(posedge RCLK, posedge RCLKE, 0:0:0, 0:0:0); + $setuphold(posedge RCLK, negedge RCLKE, 0:0:0, 0:0:0); + $setuphold(negedge RCLK, posedge RCLKE, 0:0:0, 0:0:0); + $setuphold(negedge RCLK, negedge RCLKE, 0:0:0, 0:0:0); + $setuphold(posedge RCLK, posedge RE, 0:0:0, 0:0:0); + $setuphold(posedge RCLK, negedge RE, 0:0:0, 0:0:0); + $setuphold(negedge RCLK, posedge RE, 0:0:0, 0:0:0); + $setuphold(negedge RCLK, negedge RE, 0:0:0, 0:0:0); + $setuphold(posedge RCLK, posedge RADDR_10, 0:0:0, 0:0:0); + $setuphold(posedge RCLK, negedge RADDR_10, 0:0:0, 0:0:0); + $setuphold(negedge RCLK, posedge RADDR_10, 0:0:0, 0:0:0); + $setuphold(negedge RCLK, negedge RADDR_10, 0:0:0, 0:0:0); + $setuphold(posedge RCLK, posedge RADDR_9, 0:0:0, 0:0:0); + $setuphold(posedge RCLK, negedge RADDR_9, 0:0:0, 0:0:0); + $setuphold(negedge RCLK, posedge RADDR_9, 0:0:0, 0:0:0); + $setuphold(negedge RCLK, negedge RADDR_9, 0:0:0, 0:0:0); + $setuphold(posedge RCLK, posedge RADDR_8, 0:0:0, 0:0:0); + $setuphold(posedge RCLK, negedge RADDR_8, 0:0:0, 0:0:0); + $setuphold(negedge RCLK, posedge RADDR_8, 0:0:0, 0:0:0); + $setuphold(negedge RCLK, negedge RADDR_8, 0:0:0, 0:0:0); + $setuphold(posedge RCLK, posedge RADDR_7, 0:0:0, 0:0:0); + $setuphold(posedge RCLK, negedge RADDR_7, 0:0:0, 0:0:0); + $setuphold(negedge RCLK, posedge RADDR_7, 0:0:0, 0:0:0); + $setuphold(negedge RCLK, negedge RADDR_7, 0:0:0, 0:0:0); + $setuphold(posedge RCLK, posedge RADDR_6, 0:0:0, 0:0:0); + $setuphold(posedge RCLK, negedge RADDR_6, 0:0:0, 0:0:0); + $setuphold(negedge RCLK, posedge RADDR_6, 0:0:0, 0:0:0); + $setuphold(negedge RCLK, negedge RADDR_6, 0:0:0, 0:0:0); + $setuphold(posedge RCLK, posedge RADDR_5, 0:0:0, 0:0:0); + $setuphold(posedge RCLK, negedge RADDR_5, 0:0:0, 0:0:0); + $setuphold(negedge RCLK, posedge RADDR_5, 0:0:0, 0:0:0); + $setuphold(negedge RCLK, negedge RADDR_5, 0:0:0, 0:0:0); + $setuphold(posedge RCLK, posedge RADDR_4, 0:0:0, 0:0:0); + $setuphold(posedge RCLK, negedge RADDR_4, 0:0:0, 0:0:0); + $setuphold(negedge RCLK, posedge RADDR_4, 0:0:0, 0:0:0); + $setuphold(negedge RCLK, negedge RADDR_4, 0:0:0, 0:0:0); + $setuphold(posedge RCLK, posedge RADDR_3, 0:0:0, 0:0:0); + $setuphold(posedge RCLK, negedge RADDR_3, 0:0:0, 0:0:0); + $setuphold(negedge RCLK, posedge RADDR_3, 0:0:0, 0:0:0); + $setuphold(negedge RCLK, negedge RADDR_3, 0:0:0, 0:0:0); + $setuphold(posedge RCLK, posedge RADDR_2, 0:0:0, 0:0:0); + $setuphold(posedge RCLK, negedge RADDR_2, 0:0:0, 0:0:0); + $setuphold(negedge RCLK, posedge RADDR_2, 0:0:0, 0:0:0); + $setuphold(negedge RCLK, negedge RADDR_2, 0:0:0, 0:0:0); + $setuphold(posedge RCLK, posedge RADDR_1, 0:0:0, 0:0:0); + $setuphold(posedge RCLK, negedge RADDR_1, 0:0:0, 0:0:0); + $setuphold(negedge RCLK, posedge RADDR_1, 0:0:0, 0:0:0); + $setuphold(negedge RCLK, negedge RADDR_1, 0:0:0, 0:0:0); + $setuphold(posedge RCLK, posedge RADDR_0, 0:0:0, 0:0:0); + $setuphold(posedge RCLK, negedge RADDR_0, 0:0:0, 0:0:0); + $setuphold(negedge RCLK, posedge RADDR_0, 0:0:0, 0:0:0); + $setuphold(negedge RCLK, negedge RADDR_0, 0:0:0, 0:0:0); + $setuphold(posedge WCLK, posedge WCLKE, 0:0:0, 0:0:0); + $setuphold(posedge WCLK, negedge WCLKE, 0:0:0, 0:0:0); + $setuphold(negedge WCLK, posedge WCLKE, 0:0:0, 0:0:0); + $setuphold(negedge WCLK, negedge WCLKE, 0:0:0, 0:0:0); + $setuphold(posedge WCLK, posedge WE, 0:0:0, 0:0:0); + $setuphold(posedge WCLK, negedge WE, 0:0:0, 0:0:0); + $setuphold(negedge WCLK, posedge WE, 0:0:0, 0:0:0); + $setuphold(negedge WCLK, negedge WE, 0:0:0, 0:0:0); + $setuphold(posedge WCLK, posedge WADDR_10, 0:0:0, 0:0:0); + $setuphold(posedge WCLK, negedge WADDR_10, 0:0:0, 0:0:0); + $setuphold(negedge WCLK, posedge WADDR_10, 0:0:0, 0:0:0); + $setuphold(negedge WCLK, negedge WADDR_10, 0:0:0, 0:0:0); + $setuphold(posedge WCLK, posedge WADDR_9, 0:0:0, 0:0:0); + $setuphold(posedge WCLK, negedge WADDR_9, 0:0:0, 0:0:0); + $setuphold(negedge WCLK, posedge WADDR_9, 0:0:0, 0:0:0); + $setuphold(negedge WCLK, negedge WADDR_9, 0:0:0, 0:0:0); + $setuphold(posedge WCLK, posedge WADDR_8, 0:0:0, 0:0:0); + $setuphold(posedge WCLK, negedge WADDR_8, 0:0:0, 0:0:0); + $setuphold(negedge WCLK, posedge WADDR_8, 0:0:0, 0:0:0); + $setuphold(negedge WCLK, negedge WADDR_8, 0:0:0, 0:0:0); + $setuphold(posedge WCLK, posedge WADDR_7, 0:0:0, 0:0:0); + $setuphold(posedge WCLK, negedge WADDR_7, 0:0:0, 0:0:0); + $setuphold(negedge WCLK, posedge WADDR_7, 0:0:0, 0:0:0); + $setuphold(negedge WCLK, negedge WADDR_7, 0:0:0, 0:0:0); + $setuphold(posedge WCLK, posedge WADDR_6, 0:0:0, 0:0:0); + $setuphold(posedge WCLK, negedge WADDR_6, 0:0:0, 0:0:0); + $setuphold(negedge WCLK, posedge WADDR_6, 0:0:0, 0:0:0); + $setuphold(negedge WCLK, negedge WADDR_6, 0:0:0, 0:0:0); + $setuphold(posedge WCLK, posedge WADDR_5, 0:0:0, 0:0:0); + $setuphold(posedge WCLK, negedge WADDR_5, 0:0:0, 0:0:0); + $setuphold(negedge WCLK, posedge WADDR_5, 0:0:0, 0:0:0); + $setuphold(negedge WCLK, negedge WADDR_5, 0:0:0, 0:0:0); + $setuphold(posedge WCLK, posedge WADDR_4, 0:0:0, 0:0:0); + $setuphold(posedge WCLK, negedge WADDR_4, 0:0:0, 0:0:0); + $setuphold(negedge WCLK, posedge WADDR_4, 0:0:0, 0:0:0); + $setuphold(negedge WCLK, negedge WADDR_4, 0:0:0, 0:0:0); + $setuphold(posedge WCLK, posedge WADDR_3, 0:0:0, 0:0:0); + $setuphold(posedge WCLK, negedge WADDR_3, 0:0:0, 0:0:0); + $setuphold(negedge WCLK, posedge WADDR_3, 0:0:0, 0:0:0); + $setuphold(negedge WCLK, negedge WADDR_3, 0:0:0, 0:0:0); + $setuphold(posedge WCLK, posedge WADDR_2, 0:0:0, 0:0:0); + $setuphold(posedge WCLK, negedge WADDR_2, 0:0:0, 0:0:0); + $setuphold(negedge WCLK, posedge WADDR_2, 0:0:0, 0:0:0); + $setuphold(negedge WCLK, negedge WADDR_2, 0:0:0, 0:0:0); + $setuphold(posedge WCLK, posedge WADDR_1, 0:0:0, 0:0:0); + $setuphold(posedge WCLK, negedge WADDR_1, 0:0:0, 0:0:0); + $setuphold(negedge WCLK, posedge WADDR_1, 0:0:0, 0:0:0); + $setuphold(negedge WCLK, negedge WADDR_1, 0:0:0, 0:0:0); + $setuphold(posedge WCLK, posedge WADDR_0, 0:0:0, 0:0:0); + $setuphold(posedge WCLK, negedge WADDR_0, 0:0:0, 0:0:0); + $setuphold(negedge WCLK, posedge WADDR_0, 0:0:0, 0:0:0); + $setuphold(negedge WCLK, negedge WADDR_0, 0:0:0, 0:0:0); + $setuphold(posedge WCLK, posedge MASK_15, 0:0:0, 0:0:0); + $setuphold(posedge WCLK, negedge MASK_15, 0:0:0, 0:0:0); + $setuphold(negedge WCLK, posedge MASK_15, 0:0:0, 0:0:0); + $setuphold(negedge WCLK, negedge MASK_15, 0:0:0, 0:0:0); + $setuphold(posedge WCLK, posedge MASK_14, 0:0:0, 0:0:0); + $setuphold(posedge WCLK, negedge MASK_14, 0:0:0, 0:0:0); + $setuphold(negedge WCLK, posedge MASK_14, 0:0:0, 0:0:0); + $setuphold(negedge WCLK, negedge MASK_14, 0:0:0, 0:0:0); + $setuphold(posedge WCLK, posedge MASK_13, 0:0:0, 0:0:0); + $setuphold(posedge WCLK, negedge MASK_13, 0:0:0, 0:0:0); + $setuphold(negedge WCLK, posedge MASK_13, 0:0:0, 0:0:0); + $setuphold(negedge WCLK, negedge MASK_13, 0:0:0, 0:0:0); + $setuphold(posedge WCLK, posedge MASK_12, 0:0:0, 0:0:0); + $setuphold(posedge WCLK, negedge MASK_12, 0:0:0, 0:0:0); + $setuphold(negedge WCLK, posedge MASK_12, 0:0:0, 0:0:0); + $setuphold(negedge WCLK, negedge MASK_12, 0:0:0, 0:0:0); + $setuphold(posedge WCLK, posedge MASK_11, 0:0:0, 0:0:0); + $setuphold(posedge WCLK, negedge MASK_11, 0:0:0, 0:0:0); + $setuphold(negedge WCLK, posedge MASK_11, 0:0:0, 0:0:0); + $setuphold(negedge WCLK, negedge MASK_11, 0:0:0, 0:0:0); + $setuphold(posedge WCLK, posedge MASK_10, 0:0:0, 0:0:0); + $setuphold(posedge WCLK, negedge MASK_10, 0:0:0, 0:0:0); + $setuphold(negedge WCLK, posedge MASK_10, 0:0:0, 0:0:0); + $setuphold(negedge WCLK, negedge MASK_10, 0:0:0, 0:0:0); + $setuphold(posedge WCLK, posedge MASK_9, 0:0:0, 0:0:0); + $setuphold(posedge WCLK, negedge MASK_9, 0:0:0, 0:0:0); + $setuphold(negedge WCLK, posedge MASK_9, 0:0:0, 0:0:0); + $setuphold(negedge WCLK, negedge MASK_9, 0:0:0, 0:0:0); + $setuphold(posedge WCLK, posedge MASK_8, 0:0:0, 0:0:0); + $setuphold(posedge WCLK, negedge MASK_8, 0:0:0, 0:0:0); + $setuphold(negedge WCLK, posedge MASK_8, 0:0:0, 0:0:0); + $setuphold(negedge WCLK, negedge MASK_8, 0:0:0, 0:0:0); + $setuphold(posedge WCLK, posedge MASK_7, 0:0:0, 0:0:0); + $setuphold(posedge WCLK, negedge MASK_7, 0:0:0, 0:0:0); + $setuphold(negedge WCLK, posedge MASK_7, 0:0:0, 0:0:0); + $setuphold(negedge WCLK, negedge MASK_7, 0:0:0, 0:0:0); + $setuphold(posedge WCLK, posedge MASK_6, 0:0:0, 0:0:0); + $setuphold(posedge WCLK, negedge MASK_6, 0:0:0, 0:0:0); + $setuphold(negedge WCLK, posedge MASK_6, 0:0:0, 0:0:0); + $setuphold(negedge WCLK, negedge MASK_6, 0:0:0, 0:0:0); + $setuphold(posedge WCLK, posedge MASK_5, 0:0:0, 0:0:0); + $setuphold(posedge WCLK, negedge MASK_5, 0:0:0, 0:0:0); + $setuphold(negedge WCLK, posedge MASK_5, 0:0:0, 0:0:0); + $setuphold(negedge WCLK, negedge MASK_5, 0:0:0, 0:0:0); + $setuphold(posedge WCLK, posedge MASK_4, 0:0:0, 0:0:0); + $setuphold(posedge WCLK, negedge MASK_4, 0:0:0, 0:0:0); + $setuphold(negedge WCLK, posedge MASK_4, 0:0:0, 0:0:0); + $setuphold(negedge WCLK, negedge MASK_4, 0:0:0, 0:0:0); + $setuphold(posedge WCLK, posedge MASK_3, 0:0:0, 0:0:0); + $setuphold(posedge WCLK, negedge MASK_3, 0:0:0, 0:0:0); + $setuphold(negedge WCLK, posedge MASK_3, 0:0:0, 0:0:0); + $setuphold(negedge WCLK, negedge MASK_3, 0:0:0, 0:0:0); + $setuphold(posedge WCLK, posedge MASK_2, 0:0:0, 0:0:0); + $setuphold(posedge WCLK, negedge MASK_2, 0:0:0, 0:0:0); + $setuphold(negedge WCLK, posedge MASK_2, 0:0:0, 0:0:0); + $setuphold(negedge WCLK, negedge MASK_2, 0:0:0, 0:0:0); + $setuphold(posedge WCLK, posedge MASK_1, 0:0:0, 0:0:0); + $setuphold(posedge WCLK, negedge MASK_1, 0:0:0, 0:0:0); + $setuphold(negedge WCLK, posedge MASK_1, 0:0:0, 0:0:0); + $setuphold(negedge WCLK, negedge MASK_1, 0:0:0, 0:0:0); + $setuphold(posedge WCLK, posedge MASK_0, 0:0:0, 0:0:0); + $setuphold(posedge WCLK, negedge MASK_0, 0:0:0, 0:0:0); + $setuphold(negedge WCLK, posedge MASK_0, 0:0:0, 0:0:0); + $setuphold(negedge WCLK, negedge MASK_0, 0:0:0, 0:0:0); + $setuphold(posedge WCLK, posedge WDATA_15, 0:0:0, 0:0:0); + $setuphold(posedge WCLK, negedge WDATA_15, 0:0:0, 0:0:0); + $setuphold(negedge WCLK, posedge WDATA_15, 0:0:0, 0:0:0); + $setuphold(negedge WCLK, negedge WDATA_15, 0:0:0, 0:0:0); + $setuphold(posedge WCLK, posedge WDATA_14, 0:0:0, 0:0:0); + $setuphold(posedge WCLK, negedge WDATA_14, 0:0:0, 0:0:0); + $setuphold(negedge WCLK, posedge WDATA_14, 0:0:0, 0:0:0); + $setuphold(negedge WCLK, negedge WDATA_14, 0:0:0, 0:0:0); + $setuphold(posedge WCLK, posedge WDATA_13, 0:0:0, 0:0:0); + $setuphold(posedge WCLK, negedge WDATA_13, 0:0:0, 0:0:0); + $setuphold(negedge WCLK, posedge WDATA_13, 0:0:0, 0:0:0); + $setuphold(negedge WCLK, negedge WDATA_13, 0:0:0, 0:0:0); + $setuphold(posedge WCLK, posedge WDATA_12, 0:0:0, 0:0:0); + $setuphold(posedge WCLK, negedge WDATA_12, 0:0:0, 0:0:0); + $setuphold(negedge WCLK, posedge WDATA_12, 0:0:0, 0:0:0); + $setuphold(negedge WCLK, negedge WDATA_12, 0:0:0, 0:0:0); + $setuphold(posedge WCLK, posedge WDATA_11, 0:0:0, 0:0:0); + $setuphold(posedge WCLK, negedge WDATA_11, 0:0:0, 0:0:0); + $setuphold(negedge WCLK, posedge WDATA_11, 0:0:0, 0:0:0); + $setuphold(negedge WCLK, negedge WDATA_11, 0:0:0, 0:0:0); + $setuphold(posedge WCLK, posedge WDATA_10, 0:0:0, 0:0:0); + $setuphold(posedge WCLK, negedge WDATA_10, 0:0:0, 0:0:0); + $setuphold(negedge WCLK, posedge WDATA_10, 0:0:0, 0:0:0); + $setuphold(negedge WCLK, negedge WDATA_10, 0:0:0, 0:0:0); + $setuphold(posedge WCLK, posedge WDATA_9, 0:0:0, 0:0:0); + $setuphold(posedge WCLK, negedge WDATA_9, 0:0:0, 0:0:0); + $setuphold(negedge WCLK, posedge WDATA_9, 0:0:0, 0:0:0); + $setuphold(negedge WCLK, negedge WDATA_9, 0:0:0, 0:0:0); + $setuphold(posedge WCLK, posedge WDATA_8, 0:0:0, 0:0:0); + $setuphold(posedge WCLK, negedge WDATA_8, 0:0:0, 0:0:0); + $setuphold(negedge WCLK, posedge WDATA_8, 0:0:0, 0:0:0); + $setuphold(negedge WCLK, negedge WDATA_8, 0:0:0, 0:0:0); + $setuphold(posedge WCLK, posedge WDATA_7, 0:0:0, 0:0:0); + $setuphold(posedge WCLK, negedge WDATA_7, 0:0:0, 0:0:0); + $setuphold(negedge WCLK, posedge WDATA_7, 0:0:0, 0:0:0); + $setuphold(negedge WCLK, negedge WDATA_7, 0:0:0, 0:0:0); + $setuphold(posedge WCLK, posedge WDATA_6, 0:0:0, 0:0:0); + $setuphold(posedge WCLK, negedge WDATA_6, 0:0:0, 0:0:0); + $setuphold(negedge WCLK, posedge WDATA_6, 0:0:0, 0:0:0); + $setuphold(negedge WCLK, negedge WDATA_6, 0:0:0, 0:0:0); + $setuphold(posedge WCLK, posedge WDATA_5, 0:0:0, 0:0:0); + $setuphold(posedge WCLK, negedge WDATA_5, 0:0:0, 0:0:0); + $setuphold(negedge WCLK, posedge WDATA_5, 0:0:0, 0:0:0); + $setuphold(negedge WCLK, negedge WDATA_5, 0:0:0, 0:0:0); + $setuphold(posedge WCLK, posedge WDATA_4, 0:0:0, 0:0:0); + $setuphold(posedge WCLK, negedge WDATA_4, 0:0:0, 0:0:0); + $setuphold(negedge WCLK, posedge WDATA_4, 0:0:0, 0:0:0); + $setuphold(negedge WCLK, negedge WDATA_4, 0:0:0, 0:0:0); + $setuphold(posedge WCLK, posedge WDATA_3, 0:0:0, 0:0:0); + $setuphold(posedge WCLK, negedge WDATA_3, 0:0:0, 0:0:0); + $setuphold(negedge WCLK, posedge WDATA_3, 0:0:0, 0:0:0); + $setuphold(negedge WCLK, negedge WDATA_3, 0:0:0, 0:0:0); + $setuphold(posedge WCLK, posedge WDATA_2, 0:0:0, 0:0:0); + $setuphold(posedge WCLK, negedge WDATA_2, 0:0:0, 0:0:0); + $setuphold(negedge WCLK, posedge WDATA_2, 0:0:0, 0:0:0); + $setuphold(negedge WCLK, negedge WDATA_2, 0:0:0, 0:0:0); + $setuphold(posedge WCLK, posedge WDATA_1, 0:0:0, 0:0:0); + $setuphold(posedge WCLK, negedge WDATA_1, 0:0:0, 0:0:0); + $setuphold(negedge WCLK, posedge WDATA_1, 0:0:0, 0:0:0); + $setuphold(negedge WCLK, negedge WDATA_1, 0:0:0, 0:0:0); + $setuphold(posedge WCLK, posedge WDATA_0, 0:0:0, 0:0:0); + $setuphold(posedge WCLK, negedge WDATA_0, 0:0:0, 0:0:0); + $setuphold(negedge WCLK, posedge WDATA_0, 0:0:0, 0:0:0); + $setuphold(negedge WCLK, negedge WDATA_0, 0:0:0, 0:0:0); + +endspecify +`endif +endmodule -- cgit v1.2.3 From 07c854b7afc793a589df06c7fce200260378b379 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Wed, 13 Nov 2019 13:41:16 +0100 Subject: Add "autoname" pass and use it in "synth_ice40" Signed-off-by: Clifford Wolf --- techlibs/ice40/synth_ice40.cc | 1 + 1 file changed, 1 insertion(+) (limited to 'techlibs/ice40') diff --git a/techlibs/ice40/synth_ice40.cc b/techlibs/ice40/synth_ice40.cc index c942126e1..901194b06 100644 --- a/techlibs/ice40/synth_ice40.cc +++ b/techlibs/ice40/synth_ice40.cc @@ -380,6 +380,7 @@ struct SynthIce40Pass : public ScriptPass if (check_label("check")) { + run("autoname"); run("hierarchy -check"); run("stat"); run("check -noinit"); -- cgit v1.2.3