From 62493c91b24c1775f82e64712bf42b175944fe08 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Tue, 19 Feb 2019 13:42:21 +0100 Subject: Add first draft of functional SB_MAC16 model Signed-off-by: Clifford Wolf --- techlibs/ice40/tests/test_dsp_model.gtkw | 87 ++++++++++++++ techlibs/ice40/tests/test_dsp_model.sh | 6 + techlibs/ice40/tests/test_dsp_model.v | 199 +++++++++++++++++++++++++++++++ 3 files changed, 292 insertions(+) create mode 100644 techlibs/ice40/tests/test_dsp_model.gtkw create mode 100644 techlibs/ice40/tests/test_dsp_model.sh create mode 100644 techlibs/ice40/tests/test_dsp_model.v (limited to 'techlibs/ice40/tests') diff --git a/techlibs/ice40/tests/test_dsp_model.gtkw b/techlibs/ice40/tests/test_dsp_model.gtkw new file mode 100644 index 000000000..dafe8916f --- /dev/null +++ b/techlibs/ice40/tests/test_dsp_model.gtkw @@ -0,0 +1,87 @@ +[*] +[*] GTKWave Analyzer v3.3.86 (w)1999-2017 BSI +[*] Tue Feb 19 13:33:31 2019 +[*] +[dumpfile] "/home/clifford/Work/yosys/techlibs/ice40/tests/test_dsp_model.vcd" +[dumpfile_mtime] "Tue Feb 19 13:29:34 2019" +[dumpfile_size] 119605 +[savefile] "/home/clifford/Work/yosys/techlibs/ice40/tests/test_dsp_model.gtkw" +[timestart] 0 +[size] 1850 1362 +[pos] 1816 32 +*-16.399944 42300 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +[sst_width] 223 +[signals_width] 142 +[sst_expanded] 1 +[sst_vpaned_height] 420 +@28 +testbench.CLK +testbench.CE +@200 +- +@28 +testbench.REF_ACCUMCO +testbench.UUT_ACCUMCO +@200 +- +@28 +testbench.REF_CO +testbench.UUT_CO +@200 +- +@22 +testbench.REF_O[31:0] +testbench.UUT_O[31:0] +@200 +- +@28 +testbench.REF_SIGNEXTOUT +testbench.UUT_SIGNEXTOUT +@200 +- +@22 +testbench.A[15:0] +testbench.B[15:0] +testbench.C[15:0] +testbench.D[15:0] +@200 +- +@28 +testbench.AHOLD +testbench.BHOLD +testbench.CHOLD +testbench.DHOLD +@200 +- +@28 +testbench.SIGNEXTIN +testbench.ACCUMCI +testbench.CI +@200 +- +@28 +testbench.ADDSUBTOP +testbench.ADDSUBBOT +@200 +- +@28 +testbench.IRSTTOP +testbench.IRSTBOT +@200 +- +@29 +testbench.OHOLDTOP +@28 +testbench.OHOLDBOT +@200 +- +@28 +testbench.OLOADTOP +testbench.OLOADBOT +@200 +- +@28 +testbench.ORSTTOP +testbench.ORSTBOT +[pattern_trace] 1 +[pattern_trace] 0 diff --git a/techlibs/ice40/tests/test_dsp_model.sh b/techlibs/ice40/tests/test_dsp_model.sh new file mode 100644 index 000000000..ad079b2b6 --- /dev/null +++ b/techlibs/ice40/tests/test_dsp_model.sh @@ -0,0 +1,6 @@ +#!/bin/bash +set -ex +sed 's/SB_MAC16/SB_MAC16_UUT/; /SB_MAC16_UUT/,/endmodule/ p; d;' < ../cells_sim.v > test_dsp_model_uut.v +cat /opt/lscc/iCEcube2.2017.01/verilog/sb_ice_syn.v > test_dsp_model_ref.v +iverilog -s testbench -o test_dsp_model test_dsp_model.v test_dsp_model_uut.v test_dsp_model_ref.v +./test_dsp_model diff --git a/techlibs/ice40/tests/test_dsp_model.v b/techlibs/ice40/tests/test_dsp_model.v new file mode 100644 index 000000000..919bb7917 --- /dev/null +++ b/techlibs/ice40/tests/test_dsp_model.v @@ -0,0 +1,199 @@ +`timescale 1ns / 1ps + +module testbench; + parameter [0:0] NEG_TRIGGER = 0; + parameter [0:0] C_REG = 0; + parameter [0:0] A_REG = 0; + parameter [0:0] B_REG = 0; + parameter [0:0] D_REG = 0; + parameter [0:0] TOP_8x8_MULT_REG = 0; + parameter [0:0] BOT_8x8_MULT_REG = 0; + parameter [0:0] PIPELINE_16x16_MULT_REG1 = 0; + parameter [0:0] PIPELINE_16x16_MULT_REG2 = 0; + parameter [1:0] TOPOUTPUT_SELECT = 0; + parameter [1:0] TOPADDSUB_LOWERINPUT = 2; + parameter [0:0] TOPADDSUB_UPPERINPUT = 1; + parameter [1:0] TOPADDSUB_CARRYSELECT = 2; + parameter [1:0] BOTOUTPUT_SELECT = 0; + parameter [1:0] BOTADDSUB_LOWERINPUT = 2; + parameter [0:0] BOTADDSUB_UPPERINPUT = 1; + parameter [1:0] BOTADDSUB_CARRYSELECT = 2; + parameter [0:0] MODE_8x8 = 0; + parameter [0:0] A_SIGNED = 0; + parameter [0:0] B_SIGNED = 0; + + reg CLK, CE; + reg [15:0] C, A, B, D; + reg AHOLD, BHOLD, CHOLD, DHOLD; + reg IRSTTOP, IRSTBOT; + reg ORSTTOP, ORSTBOT; + reg OLOADTOP, OLOADBOT; + reg ADDSUBTOP, ADDSUBBOT; + reg OHOLDTOP, OHOLDBOT; + reg CI, ACCUMCI, SIGNEXTIN; + + output [31:0] REF_O, UUT_O; + output REF_CO, REF_ACCUMCO, REF_SIGNEXTOUT; + output UUT_CO, UUT_ACCUMCO, UUT_SIGNEXTOUT; + + integer errcount = 0; + + task clkcycle; + begin + #5; + CLK = ~CLK; + #10; + CLK = ~CLK; + #2; + if (REF_O !== UUT_O) begin + $display("ERROR at %1t: REF_O=%b UUT_O=%b", $time, REF_O, UUT_O); + errcount = errcount + 1; + end + if (REF_CO !== UUT_CO) begin + $display("ERROR at %1t: REF_CO=%b UUT_CO=%b", $time, REF_CO, UUT_CO); + errcount = errcount + 1; + end + if (REF_ACCUMCO !== UUT_ACCUMCO) begin + $display("ERROR at %1t: REF_ACCUMCO=%b UUT_ACCUMCO=%b", $time, REF_ACCUMCO, UUT_ACCUMCO); + errcount = errcount + 1; + end + if (REF_SIGNEXTOUT !== UUT_SIGNEXTOUT) begin + $display("ERROR at %1t: REF_SIGNEXTOUT=%b UUT_SIGNEXTOUT=%b", $time, REF_SIGNEXTOUT, UUT_SIGNEXTOUT); + errcount = errcount + 1; + end + #3; + end + endtask + + initial begin + $dumpfile("test_dsp_model.vcd"); + $dumpvars(0, testbench); + + #5; + CLK = NEG_TRIGGER; + CE = 1; + {C, A, B, D} = 0; + {AHOLD, BHOLD, CHOLD, DHOLD} = 0; + {IRSTTOP, IRSTBOT} = 0; + {ORSTTOP, ORSTBOT} = 0; + {OLOADTOP, OLOADBOT} = 0; + {ADDSUBTOP, ADDSUBBOT} = 0; + {OHOLDTOP, OHOLDBOT} = 0; + {CI, ACCUMCI, SIGNEXTIN} = 0; + + // C = 10; + // A = 15; + // B = 22; + // D = 27; + + repeat (10) clkcycle; + + if (errcount == 0) begin + $display("All tests passed."); + end else begin + $display("Caught %1d errors.", errcount); + end + end + + SB_MAC16 #( + .NEG_TRIGGER (NEG_TRIGGER ), + .C_REG (C_REG ), + .A_REG (A_REG ), + .B_REG (B_REG ), + .D_REG (D_REG ), + .TOP_8x8_MULT_REG (TOP_8x8_MULT_REG ), + .BOT_8x8_MULT_REG (BOT_8x8_MULT_REG ), + .PIPELINE_16x16_MULT_REG1 (PIPELINE_16x16_MULT_REG1), + .PIPELINE_16x16_MULT_REG2 (PIPELINE_16x16_MULT_REG2), + .TOPOUTPUT_SELECT (TOPOUTPUT_SELECT ), + .TOPADDSUB_LOWERINPUT (TOPADDSUB_LOWERINPUT ), + .TOPADDSUB_UPPERINPUT (TOPADDSUB_UPPERINPUT ), + .TOPADDSUB_CARRYSELECT (TOPADDSUB_CARRYSELECT ), + .BOTOUTPUT_SELECT (BOTOUTPUT_SELECT ), + .BOTADDSUB_LOWERINPUT (BOTADDSUB_LOWERINPUT ), + .BOTADDSUB_UPPERINPUT (BOTADDSUB_UPPERINPUT ), + .BOTADDSUB_CARRYSELECT (BOTADDSUB_CARRYSELECT ), + .MODE_8x8 (MODE_8x8 ), + .A_SIGNED (A_SIGNED ), + .B_SIGNED (B_SIGNED ) + ) ref ( + .CLK (CLK ), + .CE (CE ), + .C (C ), + .A (A ), + .B (B ), + .D (D ), + .AHOLD (AHOLD ), + .BHOLD (BHOLD ), + .CHOLD (CHOLD ), + .DHOLD (DHOLD ), + .IRSTTOP (IRSTTOP ), + .IRSTBOT (IRSTBOT ), + .ORSTTOP (ORSTTOP ), + .ORSTBOT (ORSTBOT ), + .OLOADTOP (OLOADTOP ), + .OLOADBOT (OLOADBOT ), + .ADDSUBTOP (ADDSUBTOP ), + .ADDSUBBOT (ADDSUBBOT ), + .OHOLDTOP (OHOLDTOP ), + .OHOLDBOT (OHOLDBOT ), + .CI (CI ), + .ACCUMCI (ACCUMCI ), + .SIGNEXTIN (SIGNEXTIN ), + .O (REF_O ), + .CO (REF_CO ), + .ACCUMCO (REF_ACCUMCO ), + .SIGNEXTOUT (REF_SIGNEXTOUT) + ); + + SB_MAC16_UUT #( + .NEG_TRIGGER (NEG_TRIGGER ), + .C_REG (C_REG ), + .A_REG (A_REG ), + .B_REG (B_REG ), + .D_REG (D_REG ), + .TOP_8x8_MULT_REG (TOP_8x8_MULT_REG ), + .BOT_8x8_MULT_REG (BOT_8x8_MULT_REG ), + .PIPELINE_16x16_MULT_REG1 (PIPELINE_16x16_MULT_REG1), + .PIPELINE_16x16_MULT_REG2 (PIPELINE_16x16_MULT_REG2), + .TOPOUTPUT_SELECT (TOPOUTPUT_SELECT ), + .TOPADDSUB_LOWERINPUT (TOPADDSUB_LOWERINPUT ), + .TOPADDSUB_UPPERINPUT (TOPADDSUB_UPPERINPUT ), + .TOPADDSUB_CARRYSELECT (TOPADDSUB_CARRYSELECT ), + .BOTOUTPUT_SELECT (BOTOUTPUT_SELECT ), + .BOTADDSUB_LOWERINPUT (BOTADDSUB_LOWERINPUT ), + .BOTADDSUB_UPPERINPUT (BOTADDSUB_UPPERINPUT ), + .BOTADDSUB_CARRYSELECT (BOTADDSUB_CARRYSELECT ), + .MODE_8x8 (MODE_8x8 ), + .A_SIGNED (A_SIGNED ), + .B_SIGNED (B_SIGNED ) + ) uut ( + .CLK (CLK ), + .CE (CE ), + .C (C ), + .A (A ), + .B (B ), + .D (D ), + .AHOLD (AHOLD ), + .BHOLD (BHOLD ), + .CHOLD (CHOLD ), + .DHOLD (DHOLD ), + .IRSTTOP (IRSTTOP ), + .IRSTBOT (IRSTBOT ), + .ORSTTOP (ORSTTOP ), + .ORSTBOT (ORSTBOT ), + .OLOADTOP (OLOADTOP ), + .OLOADBOT (OLOADBOT ), + .ADDSUBTOP (ADDSUBTOP ), + .ADDSUBBOT (ADDSUBBOT ), + .OHOLDTOP (OHOLDTOP ), + .OHOLDBOT (OHOLDBOT ), + .CI (CI ), + .ACCUMCI (ACCUMCI ), + .SIGNEXTIN (SIGNEXTIN ), + .O (UUT_O ), + .CO (UUT_CO ), + .ACCUMCO (UUT_ACCUMCO ), + .SIGNEXTOUT (UUT_SIGNEXTOUT) + ); +endmodule -- cgit v1.2.3 From 7bf4e4a1855df442191e3d1cc28eeda7e01d051c Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Wed, 20 Feb 2019 12:55:20 +0100 Subject: Improve iCE40 SB_MAC16 model Signed-off-by: Clifford Wolf --- techlibs/ice40/tests/.gitignore | 8 +- techlibs/ice40/tests/test_dsp_model.gtkw | 87 ---------------- techlibs/ice40/tests/test_dsp_model.sh | 9 +- techlibs/ice40/tests/test_dsp_model.v | 169 ++++++++++++++++++++++++++++--- 4 files changed, 169 insertions(+), 104 deletions(-) delete mode 100644 techlibs/ice40/tests/test_dsp_model.gtkw (limited to 'techlibs/ice40/tests') diff --git a/techlibs/ice40/tests/.gitignore b/techlibs/ice40/tests/.gitignore index b58f9ad4a..9795152c2 100644 --- a/techlibs/ice40/tests/.gitignore +++ b/techlibs/ice40/tests/.gitignore @@ -1,2 +1,6 @@ -test_ffs_[01][01][01][01][01]_* -test_bram_[0-9]* +/test_ffs_[01][01][01][01][01]_* +/test_bram_[0-9]* +/test_dsp_model +/test_dsp_model.vcd +/test_dsp_model_ref.v +/test_dsp_model_uut.v diff --git a/techlibs/ice40/tests/test_dsp_model.gtkw b/techlibs/ice40/tests/test_dsp_model.gtkw deleted file mode 100644 index dafe8916f..000000000 --- a/techlibs/ice40/tests/test_dsp_model.gtkw +++ /dev/null @@ -1,87 +0,0 @@ -[*] -[*] GTKWave Analyzer v3.3.86 (w)1999-2017 BSI -[*] Tue Feb 19 13:33:31 2019 -[*] -[dumpfile] "/home/clifford/Work/yosys/techlibs/ice40/tests/test_dsp_model.vcd" -[dumpfile_mtime] "Tue Feb 19 13:29:34 2019" -[dumpfile_size] 119605 -[savefile] "/home/clifford/Work/yosys/techlibs/ice40/tests/test_dsp_model.gtkw" -[timestart] 0 -[size] 1850 1362 -[pos] 1816 32 -*-16.399944 42300 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -[sst_width] 223 -[signals_width] 142 -[sst_expanded] 1 -[sst_vpaned_height] 420 -@28 -testbench.CLK -testbench.CE -@200 -- -@28 -testbench.REF_ACCUMCO -testbench.UUT_ACCUMCO -@200 -- -@28 -testbench.REF_CO -testbench.UUT_CO -@200 -- -@22 -testbench.REF_O[31:0] -testbench.UUT_O[31:0] -@200 -- -@28 -testbench.REF_SIGNEXTOUT -testbench.UUT_SIGNEXTOUT -@200 -- -@22 -testbench.A[15:0] -testbench.B[15:0] -testbench.C[15:0] -testbench.D[15:0] -@200 -- -@28 -testbench.AHOLD -testbench.BHOLD -testbench.CHOLD -testbench.DHOLD -@200 -- -@28 -testbench.SIGNEXTIN -testbench.ACCUMCI -testbench.CI -@200 -- -@28 -testbench.ADDSUBTOP -testbench.ADDSUBBOT -@200 -- -@28 -testbench.IRSTTOP -testbench.IRSTBOT -@200 -- -@29 -testbench.OHOLDTOP -@28 -testbench.OHOLDBOT -@200 -- -@28 -testbench.OLOADTOP -testbench.OLOADBOT -@200 -- -@28 -testbench.ORSTTOP -testbench.ORSTBOT -[pattern_trace] 1 -[pattern_trace] 0 diff --git a/techlibs/ice40/tests/test_dsp_model.sh b/techlibs/ice40/tests/test_dsp_model.sh index ad079b2b6..1bc0cc688 100644 --- a/techlibs/ice40/tests/test_dsp_model.sh +++ b/techlibs/ice40/tests/test_dsp_model.sh @@ -2,5 +2,10 @@ set -ex sed 's/SB_MAC16/SB_MAC16_UUT/; /SB_MAC16_UUT/,/endmodule/ p; d;' < ../cells_sim.v > test_dsp_model_uut.v cat /opt/lscc/iCEcube2.2017.01/verilog/sb_ice_syn.v > test_dsp_model_ref.v -iverilog -s testbench -o test_dsp_model test_dsp_model.v test_dsp_model_uut.v test_dsp_model_ref.v -./test_dsp_model +for tb in testbench \ + testbench_comb_8x8_A testbench_comb_8x8_B testbench_comb_16x16 \ + testbench_seq_16x16_A testbench_seq_16x16_B +do + iverilog -s $tb -o test_dsp_model test_dsp_model.v test_dsp_model_uut.v test_dsp_model_ref.v + vvp -N ./test_dsp_model +done diff --git a/techlibs/ice40/tests/test_dsp_model.v b/techlibs/ice40/tests/test_dsp_model.v index 919bb7917..594bd4ad3 100644 --- a/techlibs/ice40/tests/test_dsp_model.v +++ b/techlibs/ice40/tests/test_dsp_model.v @@ -11,13 +11,13 @@ module testbench; parameter [0:0] PIPELINE_16x16_MULT_REG1 = 0; parameter [0:0] PIPELINE_16x16_MULT_REG2 = 0; parameter [1:0] TOPOUTPUT_SELECT = 0; - parameter [1:0] TOPADDSUB_LOWERINPUT = 2; + parameter [1:0] TOPADDSUB_LOWERINPUT = 0; parameter [0:0] TOPADDSUB_UPPERINPUT = 1; - parameter [1:0] TOPADDSUB_CARRYSELECT = 2; + parameter [1:0] TOPADDSUB_CARRYSELECT = 0; parameter [1:0] BOTOUTPUT_SELECT = 0; - parameter [1:0] BOTADDSUB_LOWERINPUT = 2; + parameter [1:0] BOTADDSUB_LOWERINPUT = 0; parameter [0:0] BOTADDSUB_UPPERINPUT = 1; - parameter [1:0] BOTADDSUB_CARRYSELECT = 2; + parameter [1:0] BOTADDSUB_CARRYSELECT = 0; parameter [0:0] MODE_8x8 = 0; parameter [0:0] A_SIGNED = 0; parameter [0:0] B_SIGNED = 0; @@ -46,7 +46,7 @@ module testbench; CLK = ~CLK; #2; if (REF_O !== UUT_O) begin - $display("ERROR at %1t: REF_O=%b UUT_O=%b", $time, REF_O, UUT_O); + $display("ERROR at %1t: REF_O=%b UUT_O=%b DIFF=%b", $time, REF_O, UUT_O, REF_O ^ UUT_O); errcount = errcount + 1; end if (REF_CO !== UUT_CO) begin @@ -69,29 +69,47 @@ module testbench; $dumpfile("test_dsp_model.vcd"); $dumpvars(0, testbench); - #5; + #2; CLK = NEG_TRIGGER; CE = 1; {C, A, B, D} = 0; {AHOLD, BHOLD, CHOLD, DHOLD} = 0; - {IRSTTOP, IRSTBOT} = 0; - {ORSTTOP, ORSTBOT} = 0; {OLOADTOP, OLOADBOT} = 0; {ADDSUBTOP, ADDSUBBOT} = 0; {OHOLDTOP, OHOLDBOT} = 0; {CI, ACCUMCI, SIGNEXTIN} = 0; - // C = 10; - // A = 15; - // B = 22; - // D = 27; + {IRSTTOP, IRSTBOT} = ~0; + {ORSTTOP, ORSTBOT} = ~0; + + #3; + {IRSTTOP, IRSTBOT} = 0; + {ORSTTOP, ORSTBOT} = 0; + + repeat (300) begin + clkcycle; + + A = $urandom; + B = $urandom; + C = $urandom; + D = $urandom; - repeat (10) clkcycle; + {AHOLD, BHOLD, CHOLD, DHOLD} = $urandom & $urandom & $urandom; + {OLOADTOP, OLOADBOT} = $urandom & $urandom & $urandom; + {ADDSUBTOP, ADDSUBBOT} = $urandom & $urandom & $urandom; + {OHOLDTOP, OHOLDBOT} = $urandom & $urandom & $urandom; + {CI, ACCUMCI, SIGNEXTIN} = $urandom & $urandom & $urandom; + + {IRSTTOP, IRSTBOT} = $urandom & $urandom & $urandom; + {ORSTTOP, ORSTBOT} = $urandom & $urandom & $urandom; + end if (errcount == 0) begin $display("All tests passed."); + $finish; end else begin $display("Caught %1d errors.", errcount); + $stop; end end @@ -197,3 +215,128 @@ module testbench; .SIGNEXTOUT (UUT_SIGNEXTOUT) ); endmodule + +module testbench_comb_8x8_A; + testbench #( + .NEG_TRIGGER (0), + .C_REG (0), + .A_REG (0), + .B_REG (0), + .D_REG (0), + .TOP_8x8_MULT_REG (0), + .BOT_8x8_MULT_REG (0), + .PIPELINE_16x16_MULT_REG1 (0), + .PIPELINE_16x16_MULT_REG2 (0), + .TOPOUTPUT_SELECT (2), // 0=P, 1=Q, 2=8x8, 3=16x16 + .TOPADDSUB_LOWERINPUT (0), // 0=A, 1=8x8, 2=16x16, 3=S-EXT + .TOPADDSUB_UPPERINPUT (0), // 0=Q, 1=C + .TOPADDSUB_CARRYSELECT (0), // 0=0, 1=1, 2=ACI, 3=CI + .BOTOUTPUT_SELECT (2), // 0=R, 1=S, 2=8x8, 3=16x16 + .BOTADDSUB_LOWERINPUT (0), // 0=B, 1=8x8, 2=16x16, 3=S-EXT + .BOTADDSUB_UPPERINPUT (0), // 0=S, 1=D + .BOTADDSUB_CARRYSELECT (0), // 0=0, 1=1, 2=ACI, 3=CI + .MODE_8x8 (0), + .A_SIGNED (0), + .B_SIGNED (0) + ) testbench (); +endmodule + +module testbench_comb_8x8_B; + testbench #( + .NEG_TRIGGER (0), + .C_REG (0), + .A_REG (0), + .B_REG (0), + .D_REG (0), + .TOP_8x8_MULT_REG (0), + .BOT_8x8_MULT_REG (0), + .PIPELINE_16x16_MULT_REG1 (0), + .PIPELINE_16x16_MULT_REG2 (0), + .TOPOUTPUT_SELECT (0), // 0=P, 1=Q, 2=8x8, 3=16x16 + .TOPADDSUB_LOWERINPUT (1), // 0=A, 1=8x8, 2=16x16, 3=S-EXT + .TOPADDSUB_UPPERINPUT (1), // 0=Q, 1=C + .TOPADDSUB_CARRYSELECT (0), // 0=0, 1=1, 2=ACI, 3=CI + .BOTOUTPUT_SELECT (0), // 0=R, 1=S, 2=8x8, 3=16x16 + .BOTADDSUB_LOWERINPUT (1), // 0=B, 1=8x8, 2=16x16, 3=S-EXT + .BOTADDSUB_UPPERINPUT (1), // 0=S, 1=D + .BOTADDSUB_CARRYSELECT (0), // 0=0, 1=1, 2=ACI, 3=CI + .MODE_8x8 (0), + .A_SIGNED (0), + .B_SIGNED (0) + ) testbench (); +endmodule + +module testbench_comb_16x16; + testbench #( + .NEG_TRIGGER (0), + .C_REG (0), + .A_REG (0), + .B_REG (0), + .D_REG (0), + .TOP_8x8_MULT_REG (0), + .BOT_8x8_MULT_REG (0), + .PIPELINE_16x16_MULT_REG1 (0), + .PIPELINE_16x16_MULT_REG2 (0), + .TOPOUTPUT_SELECT (0), // 0=P, 1=Q, 2=8x8, 3=16x16 + .TOPADDSUB_LOWERINPUT (2), // 0=A, 1=8x8, 2=16x16, 3=S-EXT + .TOPADDSUB_UPPERINPUT (1), // 0=Q, 1=C + .TOPADDSUB_CARRYSELECT (2), // 0=0, 1=1, 2=ACI, 3=CI + .BOTOUTPUT_SELECT (0), // 0=R, 1=S, 2=8x8, 3=16x16 + .BOTADDSUB_LOWERINPUT (2), // 0=B, 1=8x8, 2=16x16, 3=S-EXT + .BOTADDSUB_UPPERINPUT (1), // 0=S, 1=D + .BOTADDSUB_CARRYSELECT (2), // 0=0, 1=1, 2=ACI, 3=CI + .MODE_8x8 (0), + .A_SIGNED (0), + .B_SIGNED (0) + ) testbench (); +endmodule + +module testbench_seq_16x16_A; + testbench #( + .NEG_TRIGGER (0), + .C_REG (1), + .A_REG (1), + .B_REG (1), + .D_REG (1), + .TOP_8x8_MULT_REG (1), + .BOT_8x8_MULT_REG (1), + .PIPELINE_16x16_MULT_REG1 (1), + .PIPELINE_16x16_MULT_REG2 (1), + .TOPOUTPUT_SELECT (0), // 0=P, 1=Q, 2=8x8, 3=16x16 + .TOPADDSUB_LOWERINPUT (2), // 0=A, 1=8x8, 2=16x16, 3=S-EXT + .TOPADDSUB_UPPERINPUT (1), // 0=Q, 1=C + .TOPADDSUB_CARRYSELECT (2), // 0=0, 1=1, 2=ACI, 3=CI + .BOTOUTPUT_SELECT (0), // 0=R, 1=S, 2=8x8, 3=16x16 + .BOTADDSUB_LOWERINPUT (2), // 0=B, 1=8x8, 2=16x16, 3=S-EXT + .BOTADDSUB_UPPERINPUT (1), // 0=S, 1=D + .BOTADDSUB_CARRYSELECT (2), // 0=0, 1=1, 2=ACI, 3=CI + .MODE_8x8 (0), + .A_SIGNED (0), + .B_SIGNED (0) + ) testbench (); +endmodule + +module testbench_seq_16x16_B; + testbench #( + .NEG_TRIGGER (0), + .C_REG (1), + .A_REG (1), + .B_REG (1), + .D_REG (1), + .TOP_8x8_MULT_REG (1), + .BOT_8x8_MULT_REG (1), + .PIPELINE_16x16_MULT_REG1 (1), + .PIPELINE_16x16_MULT_REG2 (0), + .TOPOUTPUT_SELECT (1), // 0=P, 1=Q, 2=8x8, 3=16x16 + .TOPADDSUB_LOWERINPUT (2), // 0=A, 1=8x8, 2=16x16, 3=S-EXT + .TOPADDSUB_UPPERINPUT (0), // 0=Q, 1=C + .TOPADDSUB_CARRYSELECT (2), // 0=0, 1=1, 2=ACI, 3=CI + .BOTOUTPUT_SELECT (1), // 0=R, 1=S, 2=8x8, 3=16x16 + .BOTADDSUB_LOWERINPUT (2), // 0=B, 1=8x8, 2=16x16, 3=S-EXT + .BOTADDSUB_UPPERINPUT (0), // 0=S, 1=D + .BOTADDSUB_CARRYSELECT (2), // 0=0, 1=1, 2=ACI, 3=CI + .MODE_8x8 (0), + .A_SIGNED (0), + .B_SIGNED (0) + ) testbench (); +endmodule -- cgit v1.2.3 From 84999a7e680648dff674ce55f634a675852b7dc3 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Wed, 20 Feb 2019 17:18:59 +0100 Subject: Add ice40 test_dsp_map test case generator Signed-off-by: Clifford Wolf --- techlibs/ice40/tests/.gitignore | 4 ++ techlibs/ice40/tests/test_dsp_map.sh | 95 ++++++++++++++++++++++++++++++++++++ 2 files changed, 99 insertions(+) create mode 100644 techlibs/ice40/tests/test_dsp_map.sh (limited to 'techlibs/ice40/tests') diff --git a/techlibs/ice40/tests/.gitignore b/techlibs/ice40/tests/.gitignore index 9795152c2..300ce9aa6 100644 --- a/techlibs/ice40/tests/.gitignore +++ b/techlibs/ice40/tests/.gitignore @@ -4,3 +4,7 @@ /test_dsp_model.vcd /test_dsp_model_ref.v /test_dsp_model_uut.v +/test_dsp_map +/test_dsp_map_tb.v +/test_dsp_map_top.v +/test_dsp_map_syn.v diff --git a/techlibs/ice40/tests/test_dsp_map.sh b/techlibs/ice40/tests/test_dsp_map.sh new file mode 100644 index 000000000..5982e5b34 --- /dev/null +++ b/techlibs/ice40/tests/test_dsp_map.sh @@ -0,0 +1,95 @@ +#!/bin/bash +set -ex + +SZA=$(( 3 + $RANDOM % 13 )) +SZB=$(( 3 + $RANDOM % 13 )) +SZO=$(( 3 + $RANDOM % 29 )) + +C0=clk$(( $RANDOM & 1)) +C1=clk$(( $RANDOM & 1)) +C2=clk$(( $RANDOM & 1)) +C3=clk$(( $RANDOM & 1)) + +E0=$( test $(( $RANDOM & 1 )) -eq 0 && echo posedge || echo negedge ) +E1=$( test $(( $RANDOM & 1 )) -eq 0 && echo posedge || echo negedge ) +E2=$( test $(( $RANDOM & 1 )) -eq 0 && echo posedge || echo negedge ) +E3=$( test $(( $RANDOM & 1 )) -eq 0 && echo posedge || echo negedge ) + +SP=$( test $(( $RANDOM & 1 )) -eq 0 && echo S || echo P ) + +RC=$( test $(( $RANDOM & 1 )) -eq 0 && echo "reset" || echo "!reset" ) +RV="32'h$( echo $RANDOM | md5sum | cut -c1-8 )" + +cat > test_dsp_map_top.v << EOT +module top ( + input clk0, clk1, reset, + input [$SZA:0] A, + input [$SZB:0] B, + output [$SZO:0] O +); + reg [15:0] AA, BB; + reg [31:0] P, S; + + always @($E0 $C0) AA <= A; + always @($E1 $C1) BB <= B; + always @($E2 $C2) P <= AA * BB; + always @($E3 $C3) S <= $RC ? $RV : S + P; + assign O = $SP; +endmodule +EOT + +cat > test_dsp_map_tb.v << EOT +\`timescale 1ns / 1ps +module testbench; + reg clk1, clk0, reset; + reg [$SZA:0] A; + reg [$SZB:0] B; + + wire [$SZO:0] O_top, O_syn; + + top top_inst (.clk0(clk0), .clk1(clk1), .reset(reset), .A(A), .B(B), .O(O_top)); + syn syn_inst (.clk0(clk0), .clk1(clk1), .reset(reset), .A(A), .B(B), .O(O_syn)); + + initial begin + #2; + clk0 = 0; + clk1 = 0; + reset = 1; + A = 0; + B = 0; + + repeat (3) begin + #2; clk0 = ~clk0; + #2; clk0 = ~clk0; + #2; clk1 = ~clk1; + #2; clk1 = ~clk1; + end + + repeat (100) begin + #2; + A = \$urandom; + B = \$urandom; + reset = \$urandom & \$urandom & \$urandom & \$urandom; + if (\$urandom & 1) begin + #2; clk0 = ~clk0; + #2; clk0 = ~clk0; + end else begin + #2; clk1 = ~clk1; + #2; clk1 = ~clk1; + end + #2; + if (O_top !== O_syn) begin + \$display("ERROR: O_top=%b O_syn=%b", O_top, O_syn); + \$stop; + end + \$display("OK O_top=O_syn=%b", O_top); + end + + \$finish; + end +endmodule +EOT + +../../../yosys -p 'read_verilog test_dsp_map_top.v; synth_ice40 -dsp; rename top syn; write_verilog test_dsp_map_syn.v' +iverilog -o test_dsp_map -s testbench test_dsp_map_tb.v test_dsp_map_top.v test_dsp_map_syn.v ../cells_sim.v +vvp -N test_dsp_map -- cgit v1.2.3 From 2fe1c830eb8aea783c75529b42cab04208cea690 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Thu, 21 Feb 2019 13:28:46 +0100 Subject: Bugfix in ice40_dsp Signed-off-by: Clifford Wolf --- techlibs/ice40/tests/.gitignore | 1 + techlibs/ice40/tests/test_dsp_map.sh | 52 ++++++++++++++++++++++-------------- 2 files changed, 33 insertions(+), 20 deletions(-) (limited to 'techlibs/ice40/tests') diff --git a/techlibs/ice40/tests/.gitignore b/techlibs/ice40/tests/.gitignore index 300ce9aa6..120286550 100644 --- a/techlibs/ice40/tests/.gitignore +++ b/techlibs/ice40/tests/.gitignore @@ -5,6 +5,7 @@ /test_dsp_model_ref.v /test_dsp_model_uut.v /test_dsp_map +/test_dsp_map.vcd /test_dsp_map_tb.v /test_dsp_map_top.v /test_dsp_map_syn.v diff --git a/techlibs/ice40/tests/test_dsp_map.sh b/techlibs/ice40/tests/test_dsp_map.sh index 5982e5b34..3f7f134e4 100644 --- a/techlibs/ice40/tests/test_dsp_map.sh +++ b/techlibs/ice40/tests/test_dsp_map.sh @@ -1,26 +1,28 @@ #!/bin/bash set -ex -SZA=$(( 3 + $RANDOM % 13 )) -SZB=$(( 3 + $RANDOM % 13 )) -SZO=$(( 3 + $RANDOM % 29 )) +for iter in {1..100} +do + SZA=$(( 3 + $RANDOM % 13 )) + SZB=$(( 3 + $RANDOM % 13 )) + SZO=$(( 3 + $RANDOM % 29 )) -C0=clk$(( $RANDOM & 1)) -C1=clk$(( $RANDOM & 1)) -C2=clk$(( $RANDOM & 1)) -C3=clk$(( $RANDOM & 1)) + C0=clk$(( $RANDOM & 1)) + C1=clk$(( $RANDOM & 1)) + C2=clk$(( $RANDOM & 1)) + C3=clk$(( $RANDOM & 1)) -E0=$( test $(( $RANDOM & 1 )) -eq 0 && echo posedge || echo negedge ) -E1=$( test $(( $RANDOM & 1 )) -eq 0 && echo posedge || echo negedge ) -E2=$( test $(( $RANDOM & 1 )) -eq 0 && echo posedge || echo negedge ) -E3=$( test $(( $RANDOM & 1 )) -eq 0 && echo posedge || echo negedge ) + E0=$( test $(( $RANDOM & 1 )) -eq 0 && echo posedge || echo negedge ) + E1=$( test $(( $RANDOM & 1 )) -eq 0 && echo posedge || echo negedge ) + E2=$( test $(( $RANDOM & 1 )) -eq 0 && echo posedge || echo negedge ) + E3=$( test $(( $RANDOM & 1 )) -eq 0 && echo posedge || echo negedge ) -SP=$( test $(( $RANDOM & 1 )) -eq 0 && echo S || echo P ) + SP=$( test $(( $RANDOM & 1 )) -eq 0 && echo S || echo P ) -RC=$( test $(( $RANDOM & 1 )) -eq 0 && echo "reset" || echo "!reset" ) -RV="32'h$( echo $RANDOM | md5sum | cut -c1-8 )" + RC=$( test $(( $RANDOM & 1 )) -eq 0 && echo "reset" || echo "!reset" ) + RV="32'h$( echo $RANDOM | md5sum | cut -c1-8 )" -cat > test_dsp_map_top.v << EOT + cat > test_dsp_map_top.v << EOT module top ( input clk0, clk1, reset, input [$SZA:0] A, @@ -38,7 +40,7 @@ module top ( endmodule EOT -cat > test_dsp_map_tb.v << EOT + cat > test_dsp_map_tb.v << EOT \`timescale 1ns / 1ps module testbench; reg clk1, clk0, reset; @@ -51,10 +53,14 @@ module testbench; syn syn_inst (.clk0(clk0), .clk1(clk1), .reset(reset), .A(A), .B(B), .O(O_syn)); initial begin + // \$dumpfile("test_dsp_map.vcd"); + // \$dumpvars(0, testbench); + #2; clk0 = 0; clk1 = 0; reset = 1; + reset = $RC; A = 0; B = 0; @@ -82,14 +88,20 @@ module testbench; \$display("ERROR: O_top=%b O_syn=%b", O_top, O_syn); \$stop; end - \$display("OK O_top=O_syn=%b", O_top); + // \$display("OK O_top=O_syn=%b", O_top); end + \$display("Test passed."); \$finish; end endmodule EOT -../../../yosys -p 'read_verilog test_dsp_map_top.v; synth_ice40 -dsp; rename top syn; write_verilog test_dsp_map_syn.v' -iverilog -o test_dsp_map -s testbench test_dsp_map_tb.v test_dsp_map_top.v test_dsp_map_syn.v ../cells_sim.v -vvp -N test_dsp_map + ../../../yosys -p 'read_verilog test_dsp_map_top.v; synth_ice40 -dsp; rename top syn; write_verilog test_dsp_map_syn.v' + iverilog -o test_dsp_map -s testbench test_dsp_map_tb.v test_dsp_map_top.v test_dsp_map_syn.v ../cells_sim.v + vvp -N test_dsp_map +done + +: "" +: "#### All tests passed. ####" +: "" -- cgit v1.2.3