From 269ff450f55f4354c82db1b98f8eb722317d9250 Mon Sep 17 00:00:00 2001
From: David Shah <dave@ds0.me>
Date: Mon, 8 Jul 2019 15:40:12 +0100
Subject: Add mul2dsp multiplier splitting rule and ECP5 mapping

Signed-off-by: David Shah <dave@ds0.me>
---
 techlibs/ecp5/Makefile.inc  |  1 +
 techlibs/ecp5/dsp_map.v     | 10 ++++++++++
 techlibs/ecp5/synth_ecp5.cc | 33 +++++++++++++++++++++++++++++++--
 3 files changed, 42 insertions(+), 2 deletions(-)
 create mode 100644 techlibs/ecp5/dsp_map.v

(limited to 'techlibs/ecp5')

diff --git a/techlibs/ecp5/Makefile.inc b/techlibs/ecp5/Makefile.inc
index ff39ba4fe..a2f5cadee 100644
--- a/techlibs/ecp5/Makefile.inc
+++ b/techlibs/ecp5/Makefile.inc
@@ -10,6 +10,7 @@ $(eval $(call add_share_file,share/ecp5,techlibs/ecp5/brams_map.v))
 $(eval $(call add_share_file,share/ecp5,techlibs/ecp5/bram.txt))
 $(eval $(call add_share_file,share/ecp5,techlibs/ecp5/arith_map.v))
 $(eval $(call add_share_file,share/ecp5,techlibs/ecp5/latches_map.v))
+$(eval $(call add_share_file,share/ecp5,techlibs/ecp5/dsp_map.v))
 
 $(eval $(call add_share_file,share/ecp5,techlibs/ecp5/abc_5g.box))
 $(eval $(call add_share_file,share/ecp5,techlibs/ecp5/abc_5g.lut))
diff --git a/techlibs/ecp5/dsp_map.v b/techlibs/ecp5/dsp_map.v
new file mode 100644
index 000000000..22e30574c
--- /dev/null
+++ b/techlibs/ecp5/dsp_map.v
@@ -0,0 +1,10 @@
+module \$__MUL18X18 (input [17:0] A, input [17:0] B, output [35:0] OUT);
+	MULT18X18D mult_i(
+		.A0(A[0]), .A1(A[1]), .A2(A[2]), .A3(A[3]), .A4(A[4]), .A5(A[5]), .A6(A[6]), .A7(A[7]), .A8(A[8]), .A9(A[9]), .A10(A[10]), .A11(A[11]), .A12(A[12]), .A13(A[13]), .A14(A[14]), .A15(A[15]), .A16(A[16]), .A17(A[17]),
+		.B0(B[0]), .B1(B[1]), .B2(B[2]), .B3(B[3]), .B4(B[4]), .B5(B[5]), .B6(B[6]), .B7(B[7]), .B8(B[8]), .B9(B[9]), .B10(B[10]), .B11(B[11]), .B12(B[12]), .B13(B[13]), .B14(B[14]), .B15(B[15]), .B16(B[16]), .B17(B[17]),
+		.C17(1'b0), .C16(1'b0), .C15(1'b0), .C14(1'b0), .C13(1'b0), .C12(1'b0), .C11(1'b0), .C10(1'b0), .C9(1'b0), .C8(1'b0), .C7(1'b0), .C6(1'b0), .C5(1'b0), .C4(1'b0), .C3(1'b0), .C2(1'b0), .C1(1'b0), .C0(1'b0),
+		.SIGNEDA(1'b0), .SIGNEDB(1'b0), .SOURCEA(1'b0), .SOURCEB(1'b0),
+
+		.P0(OUT[0]), .P1(OUT[1]), .P2(OUT[2]), .P3(OUT[3]), .P4(OUT[4]), .P5(OUT[5]), .P6(OUT[6]), .P7(OUT[7]), .P8(OUT[8]), .P9(OUT[9]), .P10(OUT[10]), .P11(OUT[11]), .P12(OUT[12]), .P13(OUT[13]), .P14(OUT[14]), .P15(OUT[15]), .P16(OUT[16]), .P17(OUT[17]), .P18(OUT[18]), .P19(OUT[19]), .P20(OUT[20]), .P21(OUT[21]), .P22(OUT[22]), .P23(OUT[23]), .P24(OUT[24]), .P25(OUT[25]), .P26(OUT[26]), .P27(OUT[27]), .P28(OUT[28]), .P29(OUT[29]), .P30(OUT[30]), .P31(OUT[31]), .P32(OUT[32]), .P33(OUT[33]), .P34(OUT[34]), .P35(OUT[35])
+	);
+endmodule
\ No newline at end of file
diff --git a/techlibs/ecp5/synth_ecp5.cc b/techlibs/ecp5/synth_ecp5.cc
index f16a47f01..3b4185930 100644
--- a/techlibs/ecp5/synth_ecp5.cc
+++ b/techlibs/ecp5/synth_ecp5.cc
@@ -89,6 +89,9 @@ struct SynthEcp5Pass : public ScriptPass
 		log("        generate an output netlist (and BLIF file) suitable for VPR\n");
 		log("        (this feature is experimental and incomplete)\n");
 		log("\n");
+		log("    -dsp\n");
+		log("        map multipliers to MULT18X18D (EXPERIMENTAL)\n");
+		log("\n");
 		log("\n");
 		log("The following commands are executed by this synthesis command:\n");
 		help_script();
@@ -96,7 +99,7 @@ struct SynthEcp5Pass : public ScriptPass
 	}
 
 	string top_opt, blif_file, edif_file, json_file;
-	bool noccu2, nodffe, nobram, nodram, nowidelut, flatten, retime, abc2, abc9, vpr;
+	bool noccu2, nodffe, nobram, nodram, nowidelut, flatten, retime, abc2, abc9, dsp, vpr;
 
 	void clear_flags() YS_OVERRIDE
 	{
@@ -114,6 +117,7 @@ struct SynthEcp5Pass : public ScriptPass
 		abc2 = false;
 		vpr = false;
 		abc9 = false;
+		dsp = false;
 	}
 
 	void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
@@ -192,6 +196,10 @@ struct SynthEcp5Pass : public ScriptPass
 				abc9 = true;
 				continue;
 			}
+			if (args[argidx] == "-dsp") {
+				dsp = true;
+				continue;
+			}
 			break;
 		}
 		extra_args(args, argidx, design);
@@ -225,7 +233,28 @@ struct SynthEcp5Pass : public ScriptPass
 
 		if (check_label("coarse"))
 		{
-			run("synth -run coarse");
+			run("opt_expr");
+			run("opt_clean");
+			run("check");
+			run("opt");
+			run("wreduce");
+			run("peepopt");
+			run("opt_clean");
+			run("share");
+			run("techmap -map +/cmp2lut.v -D LUT_WIDTH=4");
+			run("opt_expr");
+			run("opt_clean");
+			if (dsp) {
+				run("techmap -map +/mul2dsp.v -D DSP_A_MAXWIDTH=18 -D DSP_B_MAXWIDTH=18 -D DSP_NAME=$__MUL18X18");
+				run("clean");
+				run("techmap -map +/ecp5/dsp_map.v");
+			}
+			run("alumacc");
+			run("opt");
+			run("fsm");
+			run("opt -fast");
+			run("memory -nomap");
+			run("opt_clean");
 		}
 
 		if (!nobram && check_label("bram", "(skip if -nobram)"))
-- 
cgit v1.2.3


From c865559f9540c29cb9c6302edc8b4a2620c0b49d Mon Sep 17 00:00:00 2001
From: David Shah <dave@ds0.me>
Date: Mon, 8 Jul 2019 19:15:25 +0100
Subject: xc7: Map combinational DSP48E1s

Signed-off-by: David Shah <dave@ds0.me>
---
 techlibs/ecp5/dsp_map.v | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

(limited to 'techlibs/ecp5')

diff --git a/techlibs/ecp5/dsp_map.v b/techlibs/ecp5/dsp_map.v
index 22e30574c..5f7755afb 100644
--- a/techlibs/ecp5/dsp_map.v
+++ b/techlibs/ecp5/dsp_map.v
@@ -1,5 +1,5 @@
 module \$__MUL18X18 (input [17:0] A, input [17:0] B, output [35:0] OUT);
-	MULT18X18D mult_i(
+	MULT18X18D _TECHMAP_REPLACE_ (
 		.A0(A[0]), .A1(A[1]), .A2(A[2]), .A3(A[3]), .A4(A[4]), .A5(A[5]), .A6(A[6]), .A7(A[7]), .A8(A[8]), .A9(A[9]), .A10(A[10]), .A11(A[11]), .A12(A[12]), .A13(A[13]), .A14(A[14]), .A15(A[15]), .A16(A[16]), .A17(A[17]),
 		.B0(B[0]), .B1(B[1]), .B2(B[2]), .B3(B[3]), .B4(B[4]), .B5(B[5]), .B6(B[6]), .B7(B[7]), .B8(B[8]), .B9(B[9]), .B10(B[10]), .B11(B[11]), .B12(B[12]), .B13(B[13]), .B14(B[14]), .B15(B[15]), .B16(B[16]), .B17(B[17]),
 		.C17(1'b0), .C16(1'b0), .C15(1'b0), .C14(1'b0), .C13(1'b0), .C12(1'b0), .C11(1'b0), .C10(1'b0), .C9(1'b0), .C8(1'b0), .C7(1'b0), .C6(1'b0), .C5(1'b0), .C4(1'b0), .C3(1'b0), .C2(1'b0), .C1(1'b0), .C0(1'b0),
@@ -7,4 +7,4 @@ module \$__MUL18X18 (input [17:0] A, input [17:0] B, output [35:0] OUT);
 
 		.P0(OUT[0]), .P1(OUT[1]), .P2(OUT[2]), .P3(OUT[3]), .P4(OUT[4]), .P5(OUT[5]), .P6(OUT[6]), .P7(OUT[7]), .P8(OUT[8]), .P9(OUT[9]), .P10(OUT[10]), .P11(OUT[11]), .P12(OUT[12]), .P13(OUT[13]), .P14(OUT[14]), .P15(OUT[15]), .P16(OUT[16]), .P17(OUT[17]), .P18(OUT[18]), .P19(OUT[19]), .P20(OUT[20]), .P21(OUT[21]), .P22(OUT[22]), .P23(OUT[23]), .P24(OUT[24]), .P25(OUT[25]), .P26(OUT[26]), .P27(OUT[27]), .P28(OUT[28]), .P29(OUT[29]), .P30(OUT[30]), .P31(OUT[31]), .P32(OUT[32]), .P33(OUT[33]), .P34(OUT[34]), .P35(OUT[35])
 	);
-endmodule
\ No newline at end of file
+endmodule
-- 
cgit v1.2.3


From 42f8e68e76a3717cf4ad29c36f0a9a801cde52c1 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Mon, 15 Jul 2019 14:45:47 -0700
Subject: OUT port to Y in generic DSP

---
 techlibs/ecp5/dsp_map.v | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

(limited to 'techlibs/ecp5')

diff --git a/techlibs/ecp5/dsp_map.v b/techlibs/ecp5/dsp_map.v
index 5f7755afb..24e28869e 100644
--- a/techlibs/ecp5/dsp_map.v
+++ b/techlibs/ecp5/dsp_map.v
@@ -1,10 +1,10 @@
-module \$__MUL18X18 (input [17:0] A, input [17:0] B, output [35:0] OUT);
+module \$__MUL18X18 (input [17:0] A, input [17:0] B, output [35:0] Y);
 	MULT18X18D _TECHMAP_REPLACE_ (
 		.A0(A[0]), .A1(A[1]), .A2(A[2]), .A3(A[3]), .A4(A[4]), .A5(A[5]), .A6(A[6]), .A7(A[7]), .A8(A[8]), .A9(A[9]), .A10(A[10]), .A11(A[11]), .A12(A[12]), .A13(A[13]), .A14(A[14]), .A15(A[15]), .A16(A[16]), .A17(A[17]),
 		.B0(B[0]), .B1(B[1]), .B2(B[2]), .B3(B[3]), .B4(B[4]), .B5(B[5]), .B6(B[6]), .B7(B[7]), .B8(B[8]), .B9(B[9]), .B10(B[10]), .B11(B[11]), .B12(B[12]), .B13(B[13]), .B14(B[14]), .B15(B[15]), .B16(B[16]), .B17(B[17]),
 		.C17(1'b0), .C16(1'b0), .C15(1'b0), .C14(1'b0), .C13(1'b0), .C12(1'b0), .C11(1'b0), .C10(1'b0), .C9(1'b0), .C8(1'b0), .C7(1'b0), .C6(1'b0), .C5(1'b0), .C4(1'b0), .C3(1'b0), .C2(1'b0), .C1(1'b0), .C0(1'b0),
 		.SIGNEDA(1'b0), .SIGNEDB(1'b0), .SOURCEA(1'b0), .SOURCEB(1'b0),
 
-		.P0(OUT[0]), .P1(OUT[1]), .P2(OUT[2]), .P3(OUT[3]), .P4(OUT[4]), .P5(OUT[5]), .P6(OUT[6]), .P7(OUT[7]), .P8(OUT[8]), .P9(OUT[9]), .P10(OUT[10]), .P11(OUT[11]), .P12(OUT[12]), .P13(OUT[13]), .P14(OUT[14]), .P15(OUT[15]), .P16(OUT[16]), .P17(OUT[17]), .P18(OUT[18]), .P19(OUT[19]), .P20(OUT[20]), .P21(OUT[21]), .P22(OUT[22]), .P23(OUT[23]), .P24(OUT[24]), .P25(OUT[25]), .P26(OUT[26]), .P27(OUT[27]), .P28(OUT[28]), .P29(OUT[29]), .P30(OUT[30]), .P31(OUT[31]), .P32(OUT[32]), .P33(OUT[33]), .P34(OUT[34]), .P35(OUT[35])
+		.P0(Y[0]), .P1(Y[1]), .P2(Y[2]), .P3(Y[3]), .P4(Y[4]), .P5(Y[5]), .P6(Y[6]), .P7(Y[7]), .P8(Y[8]), .P9(Y[9]), .P10(Y[10]), .P11(Y[11]), .P12(Y[12]), .P13(Y[13]), .P14(Y[14]), .P15(Y[15]), .P16(Y[16]), .P17(Y[17]), .P18(Y[18]), .P19(Y[19]), .P20(Y[20]), .P21(Y[21]), .P22(Y[22]), .P23(Y[23]), .P24(Y[24]), .P25(Y[25]), .P26(Y[26]), .P27(Y[27]), .P28(Y[28]), .P29(Y[29]), .P30(Y[30]), .P31(Y[31]), .P32(Y[32]), .P33(Y[33]), .P34(Y[34]), .P35(Y[35])
 	);
 endmodule
-- 
cgit v1.2.3


From cb84ed23263f8cad8f878a327061ac2c990af812 Mon Sep 17 00:00:00 2001
From: David Shah <dave@ds0.me>
Date: Thu, 8 Aug 2019 15:14:09 +0100
Subject: ecp5: Bring up to date with mul2dsp changes

Signed-off-by: David Shah <dave@ds0.me>
---
 techlibs/ecp5/dsp_map.v     | 9 ++++++++-
 techlibs/ecp5/synth_ecp5.cc | 3 ++-
 2 files changed, 10 insertions(+), 2 deletions(-)

(limited to 'techlibs/ecp5')

diff --git a/techlibs/ecp5/dsp_map.v b/techlibs/ecp5/dsp_map.v
index 24e28869e..cb95ddb1c 100644
--- a/techlibs/ecp5/dsp_map.v
+++ b/techlibs/ecp5/dsp_map.v
@@ -1,9 +1,16 @@
 module \$__MUL18X18 (input [17:0] A, input [17:0] B, output [35:0] Y);
+
+	parameter A_WIDTH = 18;
+	parameter B_WIDTH = 18;
+	parameter Y_WIDTH = 36;
+	parameter A_SIGNED = 0;
+	parameter B_SIGNED = 0;
+
 	MULT18X18D _TECHMAP_REPLACE_ (
 		.A0(A[0]), .A1(A[1]), .A2(A[2]), .A3(A[3]), .A4(A[4]), .A5(A[5]), .A6(A[6]), .A7(A[7]), .A8(A[8]), .A9(A[9]), .A10(A[10]), .A11(A[11]), .A12(A[12]), .A13(A[13]), .A14(A[14]), .A15(A[15]), .A16(A[16]), .A17(A[17]),
 		.B0(B[0]), .B1(B[1]), .B2(B[2]), .B3(B[3]), .B4(B[4]), .B5(B[5]), .B6(B[6]), .B7(B[7]), .B8(B[8]), .B9(B[9]), .B10(B[10]), .B11(B[11]), .B12(B[12]), .B13(B[13]), .B14(B[14]), .B15(B[15]), .B16(B[16]), .B17(B[17]),
 		.C17(1'b0), .C16(1'b0), .C15(1'b0), .C14(1'b0), .C13(1'b0), .C12(1'b0), .C11(1'b0), .C10(1'b0), .C9(1'b0), .C8(1'b0), .C7(1'b0), .C6(1'b0), .C5(1'b0), .C4(1'b0), .C3(1'b0), .C2(1'b0), .C1(1'b0), .C0(1'b0),
-		.SIGNEDA(1'b0), .SIGNEDB(1'b0), .SOURCEA(1'b0), .SOURCEB(1'b0),
+		.SIGNEDA(A_SIGNED), .SIGNEDB(B_SIGNED), .SOURCEA(1'b0), .SOURCEB(1'b0),
 
 		.P0(Y[0]), .P1(Y[1]), .P2(Y[2]), .P3(Y[3]), .P4(Y[4]), .P5(Y[5]), .P6(Y[6]), .P7(Y[7]), .P8(Y[8]), .P9(Y[9]), .P10(Y[10]), .P11(Y[11]), .P12(Y[12]), .P13(Y[13]), .P14(Y[14]), .P15(Y[15]), .P16(Y[16]), .P17(Y[17]), .P18(Y[18]), .P19(Y[19]), .P20(Y[20]), .P21(Y[21]), .P22(Y[22]), .P23(Y[23]), .P24(Y[24]), .P25(Y[25]), .P26(Y[26]), .P27(Y[27]), .P28(Y[28]), .P29(Y[29]), .P30(Y[30]), .P31(Y[31]), .P32(Y[32]), .P33(Y[33]), .P34(Y[34]), .P35(Y[35])
 	);
diff --git a/techlibs/ecp5/synth_ecp5.cc b/techlibs/ecp5/synth_ecp5.cc
index 3129ba929..7be377280 100644
--- a/techlibs/ecp5/synth_ecp5.cc
+++ b/techlibs/ecp5/synth_ecp5.cc
@@ -248,9 +248,10 @@ struct SynthEcp5Pass : public ScriptPass
 			run("opt_expr");
 			run("opt_clean");
 			if (dsp) {
-				run("techmap -map +/mul2dsp.v -D DSP_A_MAXWIDTH=18 -D DSP_B_MAXWIDTH=18 -D DSP_NAME=$__MUL18X18");
+				run("techmap -map +/mul2dsp.v -D DSP_A_MAXWIDTH=18 -D DSP_B_MAXWIDTH=18  -D DSP_A_MINWIDTH=2 -D DSP_B_MINWIDTH=2  -D DSP_NAME=$__MUL18X18");
 				run("clean");
 				run("techmap -map +/ecp5/dsp_map.v");
+				run("chtype -set $mul t:$__soft_mul","(if -dsp)");
 			}
 			run("alumacc");
 			run("opt");
-- 
cgit v1.2.3


From 0492b8b5412683392bc19ad7f15ba6c14e6668f8 Mon Sep 17 00:00:00 2001
From: David Shah <dave@ds0.me>
Date: Thu, 8 Aug 2019 15:18:59 +0100
Subject: ecp5: Replace '-dsp' with inverse logic '-nodsp' to match
 synth_xilinx

Signed-off-by: David Shah <dave@ds0.me>
---
 techlibs/ecp5/synth_ecp5.cc | 22 +++++++++++-----------
 1 file changed, 11 insertions(+), 11 deletions(-)

(limited to 'techlibs/ecp5')

diff --git a/techlibs/ecp5/synth_ecp5.cc b/techlibs/ecp5/synth_ecp5.cc
index 7be377280..1a5359e85 100644
--- a/techlibs/ecp5/synth_ecp5.cc
+++ b/techlibs/ecp5/synth_ecp5.cc
@@ -89,8 +89,8 @@ struct SynthEcp5Pass : public ScriptPass
 		log("        generate an output netlist (and BLIF file) suitable for VPR\n");
 		log("        (this feature is experimental and incomplete)\n");
 		log("\n");
-		log("    -dsp\n");
-		log("        map multipliers to MULT18X18D (EXPERIMENTAL)\n");
+		log("    -nodsp\n");
+		log("        do not map multipliers to MULT18X18D\n");
 		log("\n");
 		log("\n");
 		log("The following commands are executed by this synthesis command:\n");
@@ -99,7 +99,7 @@ struct SynthEcp5Pass : public ScriptPass
 	}
 
 	string top_opt, blif_file, edif_file, json_file;
-	bool noccu2, nodffe, nobram, nolutram, nowidelut, flatten, retime, abc2, abc9, dsp, vpr;
+	bool noccu2, nodffe, nobram, nolutram, nowidelut, flatten, retime, abc2, abc9, nodsp, vpr;
 
 	void clear_flags() YS_OVERRIDE
 	{
@@ -117,7 +117,7 @@ struct SynthEcp5Pass : public ScriptPass
 		abc2 = false;
 		vpr = false;
 		abc9 = false;
-		dsp = false;
+		nodsp = false;
 	}
 
 	void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
@@ -196,8 +196,8 @@ struct SynthEcp5Pass : public ScriptPass
 				abc9 = true;
 				continue;
 			}
-			if (args[argidx] == "-dsp") {
-				dsp = true;
+			if (args[argidx] == "-nodsp") {
+				nodsp = true;
 				continue;
 			}
 			break;
@@ -247,11 +247,11 @@ struct SynthEcp5Pass : public ScriptPass
 			run("techmap -map +/cmp2lut.v -D LUT_WIDTH=4");
 			run("opt_expr");
 			run("opt_clean");
-			if (dsp) {
-				run("techmap -map +/mul2dsp.v -D DSP_A_MAXWIDTH=18 -D DSP_B_MAXWIDTH=18  -D DSP_A_MINWIDTH=2 -D DSP_B_MINWIDTH=2  -D DSP_NAME=$__MUL18X18");
-				run("clean");
-				run("techmap -map +/ecp5/dsp_map.v");
-				run("chtype -set $mul t:$__soft_mul","(if -dsp)");
+			if (!nodsp) {
+				run("techmap -map +/mul2dsp.v -D DSP_A_MAXWIDTH=18 -D DSP_B_MAXWIDTH=18  -D DSP_A_MINWIDTH=2 -D DSP_B_MINWIDTH=2  -D DSP_NAME=$__MUL18X18", "(unless -nodsp)");
+				run("clean", "(unless -nodsp)");
+				run("techmap -map +/ecp5/dsp_map.v", "(unless -nodsp)");
+				run("chtype -set $mul t:$__soft_mul", "(unless -nodsp)");
 			}
 			run("alumacc");
 			run("opt");
-- 
cgit v1.2.3


From 55acf3120fa47bb95be8a6551738f4f9b1c70a21 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Tue, 20 Aug 2019 18:59:03 -0700
Subject: ecp5 to use abc_map.v and _unmap.v

---
 techlibs/ecp5/Makefile.inc  |  3 +++
 techlibs/ecp5/abc_5g.box    | 18 +++++++++---------
 techlibs/ecp5/abc_map.v     | 24 ++++++++++++++++++++++++
 techlibs/ecp5/abc_model.v   | 18 ++++++++++++++++++
 techlibs/ecp5/abc_unmap.v   | 25 +++++++++++++++++++++++++
 techlibs/ecp5/cells_sim.v   |  7 +++----
 techlibs/ecp5/synth_ecp5.cc |  8 +++++++-
 7 files changed, 89 insertions(+), 14 deletions(-)
 create mode 100644 techlibs/ecp5/abc_map.v
 create mode 100644 techlibs/ecp5/abc_model.v
 create mode 100644 techlibs/ecp5/abc_unmap.v

(limited to 'techlibs/ecp5')

diff --git a/techlibs/ecp5/Makefile.inc b/techlibs/ecp5/Makefile.inc
index 73e18112f..cffd5c3a4 100644
--- a/techlibs/ecp5/Makefile.inc
+++ b/techlibs/ecp5/Makefile.inc
@@ -11,6 +11,9 @@ $(eval $(call add_share_file,share/ecp5,techlibs/ecp5/bram.txt))
 $(eval $(call add_share_file,share/ecp5,techlibs/ecp5/arith_map.v))
 $(eval $(call add_share_file,share/ecp5,techlibs/ecp5/latches_map.v))
 
+$(eval $(call add_share_file,share/ecp5,techlibs/ecp5/abc_map.v))
+$(eval $(call add_share_file,share/ecp5,techlibs/ecp5/abc_unmap.v))
+$(eval $(call add_share_file,share/ecp5,techlibs/ecp5/abc_model.v))
 $(eval $(call add_share_file,share/ecp5,techlibs/ecp5/abc_5g.box))
 $(eval $(call add_share_file,share/ecp5,techlibs/ecp5/abc_5g.lut))
 $(eval $(call add_share_file,share/ecp5,techlibs/ecp5/abc_5g_nowide.lut))
diff --git a/techlibs/ecp5/abc_5g.box b/techlibs/ecp5/abc_5g.box
index c757d137d..66ebe196a 100644
--- a/techlibs/ecp5/abc_5g.box
+++ b/techlibs/ecp5/abc_5g.box
@@ -15,16 +15,16 @@ CCU2C   1      1   9      3
 630  379  630  379  526   275  392  141  273
 516  516  516  516  412   412  278  278  43
 
-# Box 2 : TRELLIS_DPR16X4 (16x4 dist ram)
+# Box 2 : TRELLIS_DPR16X4_COMB (16x4 dist ram)
 # Outputs: DO0, DO1, DO2, DO3
-# name            ID  w/b   ins   outs
-TRELLIS_DPR16X4   2     0   14    4
-
-#DI0   DI1   DI2   DI3   RAD0   RAD1   RAD2   RAD3   WAD0    WAD1   WAD2   WAD3  WCK   WRE
--      -     -     -     141    379    275    379    -       -      -      -     -     -
--      -     -     -     141    379    275    379    -       -      -      -     -     -
--      -     -     -     141    379    275    379    -       -      -      -     -     -
--      -     -     -     141    379    275    379    -       -      -      -     -     -
+# name               ID  w/b   ins   outs
+$__ABC_RAM16X2_COMB  2     0   8    4
+
+#A0   A1   A2   A3   RAD0   RAD1   RAD2   RAD3
+0     0    0    0    141    379    275    379
+0     0    0    0    141    379    275    379
+0     0    0    0    141    379    275    379
+0     0    0    0    141    379    275    379
 
 # Box 3 : PFUMX (MUX2)
 # Outputs: Z
diff --git a/techlibs/ecp5/abc_map.v b/techlibs/ecp5/abc_map.v
new file mode 100644
index 000000000..e8187ed18
--- /dev/null
+++ b/techlibs/ecp5/abc_map.v
@@ -0,0 +1,24 @@
+// ---------------------------------------
+
+module TRELLIS_DPR16X4 (
+	input  [3:0] DI,
+	input  [3:0] WAD,
+	input        WRE,
+	input        WCK,
+	input  [3:0] RAD,
+	output [3:0] DO
+);
+	parameter WCKMUX = "WCK";
+	parameter WREMUX = "WRE";
+	parameter [63:0] INITVAL = 64'h0000000000000000;
+    wire [3:0] \$DO ;
+
+    \$__ABC_DPR16X4_SEQ #(
+      .WCKMUX(WCKMUX), .WREMUX(WREMUX), .INITVAL(INITVAL)
+    ) _TECHMAP_REPLACE_ (
+      .DI(DI), .WAD(WAD), .WRE(WRE), .WCK(WCK),
+      .RAD(RAD), .DO(\$DO )
+    );
+
+    \$__ABC_DPR16X4_COMB do (.A(\$DO ), .S(RAD), .Y(DO));
+endmodule
diff --git a/techlibs/ecp5/abc_model.v b/techlibs/ecp5/abc_model.v
new file mode 100644
index 000000000..4eb923cb1
--- /dev/null
+++ b/techlibs/ecp5/abc_model.v
@@ -0,0 +1,18 @@
+// ---------------------------------------
+
+(* abc_box_id=2 *)
+module \$__ABC_DPR16X4_COMB (input [3:0] A, S, output [3:0] Y);
+endmodule
+
+module \$__ABC_DPR16X4_SEQ (
+	input  [3:0] DI,
+	input  [3:0] WAD,
+	input        WRE,
+	input        WCK,
+	input  [3:0] RAD,
+	output [3:0] DO
+);
+	parameter WCKMUX = "WCK";
+	parameter WREMUX = "WRE";
+	parameter [63:0] INITVAL = 64'h0000000000000000;
+endmodule
diff --git a/techlibs/ecp5/abc_unmap.v b/techlibs/ecp5/abc_unmap.v
new file mode 100644
index 000000000..0f918c202
--- /dev/null
+++ b/techlibs/ecp5/abc_unmap.v
@@ -0,0 +1,25 @@
+// ---------------------------------------
+
+module \$__ABC_DPR16X4_COMB (input [3:0] A, S, output [3:0] Y);
+    assign Y = A;
+endmodule
+
+module \$__ABC_DPR16X4_SEQ (
+	input  [3:0] DI,
+	input  [3:0] WAD,
+	input        WRE,
+	input        WCK,
+	input  [3:0] RAD,
+	output [3:0] DO
+);
+	parameter WCKMUX = "WCK";
+	parameter WREMUX = "WRE";
+	parameter [63:0] INITVAL = 64'h0000000000000000;
+
+    TRELLIS_DPR16X4 #(
+      .WCKMUX(WCKMUX), .WREMUX(WREMUX), .INITVAL(INITVAL)
+    ) _TECHMAP_REPLACE_ (
+      .DI(DI), .WAD(WAD), .WRE(WRE), .WCK(WCK),
+      .RAD(RAD), .DO(DO)
+    );
+endmodule
diff --git a/techlibs/ecp5/cells_sim.v b/techlibs/ecp5/cells_sim.v
index 2fcb0369e..f79a27312 100644
--- a/techlibs/ecp5/cells_sim.v
+++ b/techlibs/ecp5/cells_sim.v
@@ -107,11 +107,10 @@ module PFUMX (input ALUT, BLUT, C0, output Z);
 endmodule
 
 // ---------------------------------------
-//(* abc_box_id=2 *)
 module TRELLIS_DPR16X4 (
-	(* abc_scc_break *) input [3:0] DI,
-	(* abc_scc_break *) input [3:0] WAD,
-	(* abc_scc_break *) input       WRE,
+	input  [3:0] DI,
+	input  [3:0] WAD,
+	input        WRE,
 	input        WCK,
 	input  [3:0] RAD,
 	output [3:0] DO
diff --git a/techlibs/ecp5/synth_ecp5.cc b/techlibs/ecp5/synth_ecp5.cc
index 143d1f95c..93e1cd5b5 100644
--- a/techlibs/ecp5/synth_ecp5.cc
+++ b/techlibs/ecp5/synth_ecp5.cc
@@ -278,12 +278,18 @@ struct SynthEcp5Pass : public ScriptPass
 			if (abc2 || help_mode) {
 				run("abc", "      (only if -abc2)");
 			}
-			run("techmap -map +/ecp5/latches_map.v");
+			std::string techmap_args = "-map +/ecp5/latches_map.v";
+			if (abc9)
+				techmap_args += " -map +/ecp5/abc_map.v";
+			run("techmap " + techmap_args);
+
 			if (abc9) {
+				run("read_verilog -icells -lib +/ecp5/abc_model.v");
 				if (nowidelut)
 					run("abc9 -lut +/ecp5/abc_5g_nowide.lut -box +/ecp5/abc_5g.box -W 200");
 				else
 					run("abc9 -lut +/ecp5/abc_5g.lut -box +/ecp5/abc_5g.box -W 200");
+				run("techmap -map +/ecp5/abc_unmap.v");
 			} else {
 				if (nowidelut)
 					run("abc -lut 4 -dress");
-- 
cgit v1.2.3


From d46dc9c5b4362c1e333979cbbac4f3567904fee5 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Tue, 20 Aug 2019 19:18:36 -0700
Subject: ecp5 to use -max_iter 1

---
 techlibs/ecp5/abc_map.v     | 2 +-
 techlibs/ecp5/cells_sim.v   | 2 +-
 techlibs/ecp5/synth_ecp5.cc | 3 +--
 3 files changed, 3 insertions(+), 4 deletions(-)

(limited to 'techlibs/ecp5')

diff --git a/techlibs/ecp5/abc_map.v b/techlibs/ecp5/abc_map.v
index e8187ed18..ffd25f06d 100644
--- a/techlibs/ecp5/abc_map.v
+++ b/techlibs/ecp5/abc_map.v
@@ -13,7 +13,7 @@ module TRELLIS_DPR16X4 (
 	parameter [63:0] INITVAL = 64'h0000000000000000;
     wire [3:0] \$DO ;
 
-    \$__ABC_DPR16X4_SEQ #(
+    TRELLIS_DPR16X4 #(
       .WCKMUX(WCKMUX), .WREMUX(WREMUX), .INITVAL(INITVAL)
     ) _TECHMAP_REPLACE_ (
       .DI(DI), .WAD(WAD), .WRE(WRE), .WCK(WCK),
diff --git a/techlibs/ecp5/cells_sim.v b/techlibs/ecp5/cells_sim.v
index f79a27312..24de0c3c2 100644
--- a/techlibs/ecp5/cells_sim.v
+++ b/techlibs/ecp5/cells_sim.v
@@ -113,7 +113,7 @@ module TRELLIS_DPR16X4 (
 	input        WRE,
 	input        WCK,
 	input  [3:0] RAD,
-	output [3:0] DO
+	/* (* abc_arrival=<TODO> *) */ output [3:0] DO
 );
 	parameter WCKMUX = "WCK";
 	parameter WREMUX = "WRE";
diff --git a/techlibs/ecp5/synth_ecp5.cc b/techlibs/ecp5/synth_ecp5.cc
index 93e1cd5b5..b1d3160ba 100644
--- a/techlibs/ecp5/synth_ecp5.cc
+++ b/techlibs/ecp5/synth_ecp5.cc
@@ -280,11 +280,10 @@ struct SynthEcp5Pass : public ScriptPass
 			}
 			std::string techmap_args = "-map +/ecp5/latches_map.v";
 			if (abc9)
-				techmap_args += " -map +/ecp5/abc_map.v";
+				techmap_args += " -map +/ecp5/abc_map.v -max_iter 1";
 			run("techmap " + techmap_args);
 
 			if (abc9) {
-				run("read_verilog -icells -lib +/ecp5/abc_model.v");
 				if (nowidelut)
 					run("abc9 -lut +/ecp5/abc_5g_nowide.lut -box +/ecp5/abc_5g.box -W 200");
 				else
-- 
cgit v1.2.3


From 6b1b03d9f771addbd54358299faad181b589c9f8 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Tue, 20 Aug 2019 19:20:17 -0700
Subject: ecp5: remove DPR16X4 from abc_unmap.v

---
 techlibs/ecp5/abc_unmap.v | 20 --------------------
 1 file changed, 20 deletions(-)

(limited to 'techlibs/ecp5')

diff --git a/techlibs/ecp5/abc_unmap.v b/techlibs/ecp5/abc_unmap.v
index 0f918c202..d43cdd93f 100644
--- a/techlibs/ecp5/abc_unmap.v
+++ b/techlibs/ecp5/abc_unmap.v
@@ -3,23 +3,3 @@
 module \$__ABC_DPR16X4_COMB (input [3:0] A, S, output [3:0] Y);
     assign Y = A;
 endmodule
-
-module \$__ABC_DPR16X4_SEQ (
-	input  [3:0] DI,
-	input  [3:0] WAD,
-	input        WRE,
-	input        WCK,
-	input  [3:0] RAD,
-	output [3:0] DO
-);
-	parameter WCKMUX = "WCK";
-	parameter WREMUX = "WRE";
-	parameter [63:0] INITVAL = 64'h0000000000000000;
-
-    TRELLIS_DPR16X4 #(
-      .WCKMUX(WCKMUX), .WREMUX(WREMUX), .INITVAL(INITVAL)
-    ) _TECHMAP_REPLACE_ (
-      .DI(DI), .WAD(WAD), .WRE(WRE), .WCK(WCK),
-      .RAD(RAD), .DO(DO)
-    );
-endmodule
-- 
cgit v1.2.3


From 85d39653ac62fa4f1f809fb71b0df82a8bd01dfc Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Fri, 23 Aug 2019 13:20:29 -0700
Subject: Remove unused model

---
 techlibs/ecp5/abc_model.v | 13 -------------
 1 file changed, 13 deletions(-)

(limited to 'techlibs/ecp5')

diff --git a/techlibs/ecp5/abc_model.v b/techlibs/ecp5/abc_model.v
index 4eb923cb1..56a733b75 100644
--- a/techlibs/ecp5/abc_model.v
+++ b/techlibs/ecp5/abc_model.v
@@ -3,16 +3,3 @@
 (* abc_box_id=2 *)
 module \$__ABC_DPR16X4_COMB (input [3:0] A, S, output [3:0] Y);
 endmodule
-
-module \$__ABC_DPR16X4_SEQ (
-	input  [3:0] DI,
-	input  [3:0] WAD,
-	input        WRE,
-	input        WCK,
-	input  [3:0] RAD,
-	output [3:0] DO
-);
-	parameter WCKMUX = "WCK";
-	parameter WREMUX = "WRE";
-	parameter [63:0] INITVAL = 64'h0000000000000000;
-endmodule
-- 
cgit v1.2.3


From 455da572723e4f19ddc1d636b700a5fe1e975fbb Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Fri, 23 Aug 2019 13:21:21 -0700
Subject: Fix spacing

---
 techlibs/ecp5/cells_sim.v | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'techlibs/ecp5')

diff --git a/techlibs/ecp5/cells_sim.v b/techlibs/ecp5/cells_sim.v
index e2bf3c854..01b10f392 100644
--- a/techlibs/ecp5/cells_sim.v
+++ b/techlibs/ecp5/cells_sim.v
@@ -116,7 +116,7 @@ module TRELLIS_DPR16X4 (
 	input        WCK,
 	input  [3:0] RAD,
 	/* (* abc_arrival=<TODO> *) */
-    output [3:0] DO
+	output [3:0] DO
 );
 	parameter WCKMUX = "WCK";
 	parameter WREMUX = "WRE";
-- 
cgit v1.2.3


From 696f854801619644e42f437894847ace96594a6b Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Mon, 2 Sep 2019 12:15:11 -0700
Subject: Rename box

---
 techlibs/ecp5/abc_5g.box | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'techlibs/ecp5')

diff --git a/techlibs/ecp5/abc_5g.box b/techlibs/ecp5/abc_5g.box
index 66ebe196a..a336b4a85 100644
--- a/techlibs/ecp5/abc_5g.box
+++ b/techlibs/ecp5/abc_5g.box
@@ -18,7 +18,7 @@ CCU2C   1      1   9      3
 # Box 2 : TRELLIS_DPR16X4_COMB (16x4 dist ram)
 # Outputs: DO0, DO1, DO2, DO3
 # name               ID  w/b   ins   outs
-$__ABC_RAM16X2_COMB  2     0   8    4
+$__ABC_DPR16X4_COMB  2     0   8    4
 
 #A0   A1   A2   A3   RAD0   RAD1   RAD2   RAD3
 0     0    0    0    141    379    275    379
-- 
cgit v1.2.3


From 84825f937827f3e8fd3702a7ea85b8997ac74534 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Thu, 26 Sep 2019 10:45:14 -0700
Subject: Combine 'flatten' & 'coarse' labels in synth_ecp5 so proc run once

---
 techlibs/ecp5/synth_ecp5.cc | 13 ++++---------
 1 file changed, 4 insertions(+), 9 deletions(-)

(limited to 'techlibs/ecp5')

diff --git a/techlibs/ecp5/synth_ecp5.cc b/techlibs/ecp5/synth_ecp5.cc
index 0a3dcc62c..1f5b1cb6b 100644
--- a/techlibs/ecp5/synth_ecp5.cc
+++ b/techlibs/ecp5/synth_ecp5.cc
@@ -226,16 +226,13 @@ struct SynthEcp5Pass : public ScriptPass
 			run(stringf("hierarchy -check %s", help_mode ? "-top <top>" : top_opt.c_str()));
 		}
 
-		if (flatten && check_label("flatten", "(unless -noflatten)"))
+		if (check_label("coarse"))
 		{
 			run("proc");
-			run("flatten");
+			if (flatten || help_mode)
+				run("flatten");
 			run("tribuf -logic");
 			run("deminout");
-		}
-
-		if (check_label("coarse"))
-		{
 			run("opt_expr");
 			run("opt_clean");
 			run("check");
@@ -248,9 +245,7 @@ struct SynthEcp5Pass : public ScriptPass
 			run("opt_expr");
 			run("opt_clean");
 			if (!nodsp) {
-				run("techmap -map +/mul2dsp.v -D DSP_A_MAXWIDTH=18 -D DSP_B_MAXWIDTH=18  -D DSP_A_MINWIDTH=2 -D DSP_B_MINWIDTH=2  -D DSP_NAME=$__MUL18X18", "(unless -nodsp)");
-				run("clean", "(unless -nodsp)");
-				run("techmap -map +/ecp5/dsp_map.v", "(unless -nodsp)");
+				run("techmap -map +/mul2dsp.v -map +/ecp5/dsp_map.v -D DSP_A_MAXWIDTH=18 -D DSP_B_MAXWIDTH=18  -D DSP_A_MINWIDTH=2 -D DSP_B_MINWIDTH=2  -D DSP_NAME=$__MUL18X18", "(unless -nodsp)");
 				run("chtype -set $mul t:$__soft_mul", "(unless -nodsp)");
 			}
 			run("alumacc");
-- 
cgit v1.2.3