From b1b9e23f949410fe7c337491a5813f2741a5d9a1 Mon Sep 17 00:00:00 2001
From: David Shah <davey1576@gmail.com>
Date: Fri, 13 Jul 2018 13:27:24 +0200
Subject: ecp5: Adding basic cells_sim and mapper for LUTs up to LUT7

Signed-off-by: David Shah <davey1576@gmail.com>
---
 techlibs/ecp5/cells_map.v |  86 +++++++++++
 techlibs/ecp5/cells_sim.v | 387 ++++++++++++++++++++++++++++++++++++++++++++++
 2 files changed, 473 insertions(+)
 create mode 100644 techlibs/ecp5/cells_map.v
 create mode 100644 techlibs/ecp5/cells_sim.v

(limited to 'techlibs/ecp5')

diff --git a/techlibs/ecp5/cells_map.v b/techlibs/ecp5/cells_map.v
new file mode 100644
index 000000000..399697c14
--- /dev/null
+++ b/techlibs/ecp5/cells_map.v
@@ -0,0 +1,86 @@
+`ifndef NO_LUT
+module \$lut (A, Y);
+    parameter WIDTH = 0;
+    parameter LUT = 0;
+
+    input [WIDTH-1:0] A;
+    output Y;
+
+    generate
+        if (WIDTH == 1) begin
+            LUT4 #(.INIT(LUT)) _TECHMAP_REPLACE_ (.Z(Y),
+                .A(A[0]), .B(1'b0), .C(1'b0), .D(1'b0));
+        end else
+        if (WIDTH == 2) begin
+            LUT4 #(.INIT(LUT)) _TECHMAP_REPLACE_ (.Z(Y),
+                .A(A[0]), .B(A[1]), .C(1'b0), .D(1'b0));
+        end else
+        if (WIDTH == 3) begin
+            LUT4 #(.INIT(LUT)) _TECHMAP_REPLACE_ (.Z(Y),
+                .A(A[0]), .B(A[1]), .C(A[2]), .D(1'b0));
+        end else
+        if (WIDTH == 4) begin
+            LUT4 #(.INIT(LUT)) _TECHMAP_REPLACE_ (.Z(Y),
+                .A(A[0]), .B(A[1]), .C(A[2]), .D(A[3]));
+        `ifndef NO_PFUMUX
+        end else
+        if (WIDTH == 5) begin
+            wire f0, f1;
+            LUT4 #(.INIT(LUT[15: 0])) lut0 (.Z(f0),
+                .A(A[0]), .B(A[1]), .C(A[2]), .D(A[3]));
+            LUT4 #(.INIT(LUT[31:16])) lut1 (.Z(f1),
+                .A(A[0]), .B(A[1]), .C(A[2]), .D(A[3]));
+            PFUMX mux5(.ALUT(f1), .BLUT(f0), .SD(A[4]), .Z(Y));
+        end else
+        if (WIDTH == 6) begin
+            wire f0, f1, f2, f3, g0, g1;
+            LUT4 #(.INIT(LUT[15: 0])) lut0 (.Z(f0),
+                .A(A[0]), .B(A[1]), .C(A[2]), .D(A[3]));
+            LUT4 #(.INIT(LUT[31:16])) lut1 (.Z(f1),
+                .A(A[0]), .B(A[1]), .C(A[2]), .D(A[3]));
+
+            LUT4 #(.INIT(LUT[47:32])) lut2 (.Z(f2),
+                .A(A[0]), .B(A[1]), .C(A[2]), .D(A[3]));
+            LUT4 #(.INIT(LUT[63:48])) lut3 (.Z(f3),
+                .A(A[0]), .B(A[1]), .C(A[2]), .D(A[3]));
+
+            PFUMX mux50(.ALUT(f1), .BLUT(f0), .SD(A[4]), .Z(g0));
+            PFUMX mux51(.ALUT(f3), .BLUT(f2), .SD(A[4]), .Z(g1));
+            L6MUX21 mux6 (.D0(g0), .D1(g1), .SD(A[5]), .Z(Y));
+        end else
+        if (WIDTH == 7) begin
+            wire f0, f1, f2, f3, f4, f5, f6, f7, g0, g1, g2, g3, h0, h1;
+            LUT4 #(.INIT(LUT[15: 0])) lut0 (.Z(f0),
+                .A(A[0]), .B(A[1]), .C(A[2]), .D(A[3]));
+            LUT4 #(.INIT(LUT[31:16])) lut1 (.Z(f1),
+                .A(A[0]), .B(A[1]), .C(A[2]), .D(A[3]));
+
+            LUT4 #(.INIT(LUT[47:32])) lut2 (.Z(f2),
+                .A(A[0]), .B(A[1]), .C(A[2]), .D(A[3]));
+            LUT4 #(.INIT(LUT[63:48])) lut3 (.Z(f3),
+                .A(A[0]), .B(A[1]), .C(A[2]), .D(A[3]));
+
+            LUT4 #(.INIT(LUT[79:64])) lut4 (.Z(f4),
+                .A(A[0]), .B(A[1]), .C(A[2]), .D(A[3]));
+            LUT4 #(.INIT(LUT[95:80])) lut5 (.Z(f5),
+                .A(A[0]), .B(A[1]), .C(A[2]), .D(A[3]));
+
+            LUT4 #(.INIT(LUT[111: 96])) lut6 (.Z(f6),
+                .A(A[0]), .B(A[1]), .C(A[2]), .D(A[3]));
+            LUT4 #(.INIT(LUT[127:112])) lut7 (.Z(f7),
+                .A(A[0]), .B(A[1]), .C(A[2]), .D(A[3]));
+
+            PFUMX mux50(.ALUT(f1), .BLUT(f0), .SD(A[4]), .Z(g0));
+            PFUMX mux51(.ALUT(f3), .BLUT(f2), .SD(A[4]), .Z(g1));
+            PFUMX mux52(.ALUT(f5), .BLUT(f4), .SD(A[4]), .Z(g2));
+            PFUMX mux53(.ALUT(f7), .BLUT(f6), .SD(A[4]), .Z(g3));
+            L6MUX21 mux60 (.D0(g0), .D1(g1), .SD(A[5]), .Z(h0));
+            L6MUX21 mux61 (.D0(g2), .D1(g3), .SD(A[5]), .Z(h1));
+            L6MUX21 mux7  (.D0(h0), .D1(h1), .SD(A[6]), .Z(Y));
+        `endif
+        end else begin
+            wire _TECHMAP_FAIL_ = 1;
+        end
+    endgenerate
+endmodule
+`endif
diff --git a/techlibs/ecp5/cells_sim.v b/techlibs/ecp5/cells_sim.v
new file mode 100644
index 000000000..54006218f
--- /dev/null
+++ b/techlibs/ecp5/cells_sim.v
@@ -0,0 +1,387 @@
+// ---------------------------------------
+
+module LUT4(input A, B, C, D, output Z);
+	parameter [15:0] INIT = 16'h0000;
+	assign Z = INIT[{D, C, B, A}];
+endmodule
+
+// ---------------------------------------
+
+module L6MUX21 (input D0, D1, SD, output Z);
+	assign Z = SD ? D1 : D0;
+endmodule
+
+// ---------------------------------------
+
+module CCU2C(input CIN, A0, B0, C0, D0, A1, B1, C1, D1,
+	           output S0, S1, COUT);
+
+	parameter [15:0] INIT0 = 16'h0000;
+	parameter [15:0] INIT1 = 16'h0000;
+	parameter INJECT1_0 = "YES";
+	parameter INJECT1_1 = "YES";
+
+	// First half
+	wire LUT4_0 = INIT0[{D0, C0, B0, A0}];
+	wire LUT2_0 = INIT0[{2'b00, B0, A0}];
+
+	wire gated_cin_0 = (INJECT1_0 == "YES") ? 1'b0 : CIN;
+	assign S0 = LUT4_0 ^ gated_cin_0;
+
+	wire gated_lut2_0 = (INJECT1_0 == "YES") ? 1'b0 : LUT2_0;
+	wire cout_0 = (~LUT4_0 & gated_lut2_0) | (LUT4_0 & CIN);
+
+	// Second half
+	wire LUT4_1 = INIT1[{D1, C1, B1, A1}];
+	wire LUT2_1 = INIT1[{2'b00, B1, A1}];
+
+	wire gated_cin_1 = (INJECT1_1 == "YES") ? 1'b0 : cout_0;
+	assign S1 = LUT4_1 ^ gated_cin_1;
+
+	wire gated_lut2_1 = (INJECT1_1 == "YES") ? 1'b0 : LUT2_1;
+	assign COUT = (~LUT4_1 & gated_lut2_1) | (LUT4_1 & cout_0);
+
+endmodule
+
+// ---------------------------------------
+
+module TRELLIS_RAM16X2 (
+	input DI0, DI1,
+	input WAD0, WAD1, WAD2, WAD3,
+	input WRE, WCK,
+	input RAD0, RAD1, RAD2, RAD3,
+	output DO0, DO1
+);
+  parameter WCKMUX = "WCK";
+	parameter WREMUX = "WRE";
+	parameter INITVAL_0 = 16'h0000;
+	parameter INITVAL_1 = 16'h0000;
+
+	reg [1:0] mem[15:0];
+
+	integer i;
+	initial begin
+		for (i = 0; i < 16; i = i + 1)
+			mem[i] <= {INITVAL_1[i], INITVAL_0[i]};
+	end
+
+	wire muxwck = (WCKMUX == "INV") ? ~WCK : WCK;
+
+	wire muxwre = (WREMUX == "1") ? 1'b1 :
+							  (WREMUX == "0") ? 1'b0 :
+							  (WREMUX == "INV") ? ~WRE :
+							  WRE;
+
+	always @(posedge muxwck)
+		if (muxwre)
+			mem[{WAD3, WAD2, WAD1, WAD0}] <= {DI1, DI0};
+
+	assign {DO1, DO0} = mem[{RAD3, RAD2, RAD1, RAD0}];
+endmodule
+
+// ---------------------------------------
+
+module PFUMX (input ALUT, BLUT, C0, output Z);
+	assign Z = C0 ? ALUT : BLUT;
+endmodule
+
+// ---------------------------------------
+
+module DPR16X4C (
+		input [3:0] DI,
+		input WCK, WRE,
+		input [3:0] RAD,
+		input [3:0] WAD,
+		output [3:0] DO
+);
+	// For legacy Lattice compatibility, INITIVAL is a hex
+	// string rather than a numeric parameter
+	parameter INITVAL = "0x0000000000000000";
+
+	function [63:0] convert_initval;
+		input [143:0] hex_initval;
+		reg done;
+		reg [63:0] temp;
+		reg [7:0] char;
+		integer i;
+		begin
+			done = 1'b0;
+			temp = 0;
+			for (i = 0; i < 16; i = i + 1) begin
+				if (!done) begin
+					char = hex_initval[8*i +: 8];
+					if (char == "x") begin
+						done = 1'b1;
+					end else begin
+						if (char >= "0" && char <= "9")
+							temp[4*i +: 4] = char - "0";
+						else if (char >= "A" && char <= "F")
+							temp[4*i +: 4] = 10 + char - "A";
+						else if (char >= "a" && char <= "f")
+							temp[4*i +: 4] = 10 + char - "a";
+					end
+				end
+			end
+			convert_initval = temp;
+		end
+	endfunction
+
+	localparam conv_initval = convert_initval(INITVAL);
+
+	reg [3:0] ram[0:15];
+	integer i;
+	initial begin
+		for (i = 0; i < 15; i = i + 1) begin
+			ram[i] = conv_initval[4*i +: 4];
+		end
+	end
+
+	always @(posedge WCK)
+		if (WRE)
+			ram[WAD] <= DI;
+
+	assign DO = ram[RAD];
+
+endmodule
+
+// ---------------------------------------
+
+module TRELLIS_FF(input CLK, LSR, CE, DI, output reg Q);
+	parameter GSR = "ENABLED";
+	parameter [127:0] CEMUX = "1";
+	parameter CLKMUX = "CLK";
+	parameter LSRMUX = "LSR";
+	parameter SRMODE = "LSR_OVER_CE";
+	parameter REGSET = "RESET";
+
+	wire muxce = (CEMUX == "1") ? 1'b1 :
+	             (CEMUX == "0") ? 1'b0 :
+							 (CEMUX == "INV") ? ~CE :
+							 CE;
+
+	wire muxlsr = (LSRMUX == "INV") ? ~LSR : LSR;
+	wire muxclk = (CLKMUX == "INV") ? ~CLK : CLK;
+
+	wire srval = (REGSET == "SET") ? 1'b1 : 1'b0;
+
+	initial Q = 1'b0;
+
+	generate
+		if (SRMODE == "ASYNC") begin
+			always @(posedge muxclk, posedge muxlsr)
+				if (muxlsr)
+					Q <= srval;
+				else
+					Q <= DI;
+		end else begin
+			always @(posedge muxclk)
+				if (muxlsr)
+					Q <= srval;
+				else
+					Q <= DI;
+		end
+	endgenerate
+endmodule
+
+// ---------------------------------------
+
+module OBZ(input I, T, output O);
+assign O = T ? 1'bz : I;
+endmodule
+
+// ---------------------------------------
+
+module IB(input I, output O);
+assign O = I;
+endmodule
+
+// ---------------------------------------
+
+module TRELLIS_IO(
+	inout B,
+	input I,
+	input T,
+	output O
+);
+	parameter DIR = "INPUT";
+
+	generate
+		if (DIR == "INPUT") begin
+			assign B = 1'bz;
+			assign O = B;
+		end else if (DIR == "OUTPUT") begin
+			assign B = T ? 1'bz : I;
+			assign O = 1'bx;
+		end else if (DIR == "INOUT") begin
+			assign B = T ? 1'bz : I;
+			assign O = B;
+		end else begin
+			ERROR_UNKNOWN_IO_MODE error();
+		end
+	endgenerate
+
+endmodule
+
+// ---------------------------------------
+
+module OB(input I, output O);
+assign O = I;
+endmodule
+
+// ---------------------------------------
+
+module BB(input I, T, output O, inout B);
+assign B = T ? 1'bz : I;
+assign O = B;
+endmodule
+
+// ---------------------------------------
+
+module INV(input A, output Z);
+	assign Z = !A;
+endmodule
+
+// ---------------------------------------
+
+module TRELLIS_SLICE(
+	input A0, B0, C0, D0,
+	input A1, B1, C1, D1,
+	input M0, M1,
+	input FCI, FXA, FXB,
+
+	input CLK, LSR, CE,
+	input DI0, DI1,
+
+	input WD0, WD1,
+	input WAD0, WAD1, WAD2, WAD3,
+	input WRE, WCK,
+
+	output F0, Q0,
+	output F1, Q1,
+	output FCO, OFX0, OFX1,
+
+	output WDO0, WDO1, WDO2, WDO3,
+	output WADO0, WADO1, WADO2, WADO3
+);
+
+	parameter MODE = "LOGIC";
+	parameter GSR = "ENABLED";
+	parameter SRMODE = "LSR_OVER_CE";
+	parameter [127:0] CEMUX = "1";
+	parameter CLKMUX = "CLK";
+	parameter LSRMUX = "LSR";
+	parameter LUT0_INITVAL = 16'h0000;
+	parameter LUT1_INITVAL = 16'h0000;
+	parameter REG0_SD = "0";
+	parameter REG1_SD = "0";
+	parameter REG0_REGSET = "RESET";
+	parameter REG1_REGSET = "RESET";
+	parameter [127:0] CCU2_INJECT1_0 = "NO";
+	parameter [127:0] CCU2_INJECT1_1 = "NO";
+	parameter WREMUX = "WRE";
+
+	function [15:0] permute_initval;
+		input [15:0] initval;
+		integer i;
+		begin
+			for (i = 0; i < 16; i = i + 1) begin
+				permute_initval[{i[0], i[2], i[1], i[3]}] = initval[i];
+			end
+		end
+	endfunction
+
+	generate
+		if (MODE == "LOGIC") begin
+			// LUTs
+			LUT4 #(
+				.INIT(LUT0_INITVAL)
+			) lut4_0 (
+				.A(A0), .B(B0), .C(C0), .D(D0),
+				.Z(F0)
+			);
+			LUT4 #(
+				.INIT(LUT1_INITVAL)
+			) lut4_1 (
+				.A(A1), .B(B1), .C(C1), .D(D1),
+				.Z(F1)
+			);
+			// LUT expansion muxes
+			PFUMX lut5_mux (.ALUT(F1), .BLUT(F0), .C0(M0), .Z(OFX0));
+			L6MUX21 lutx_mux (.D0(FXA), .D1(FXB), .SD(M1), .Z(OFX1));
+		end else if (MODE == "CCU2") begin
+			CCU2C #(
+				.INIT0(LUT0_INITVAL),
+				.INIT1(LUT1_INITVAL),
+				.INJECT1_0(CCU2_INJECT1_0),
+				.INJECT1_1(CCU2_INJECT1_1)
+		  ) ccu2c_i (
+				.CIN(FCI),
+				.A0(A0), .B0(B0), .C0(C0), .D0(D0),
+				.A1(A1), .B1(B1), .C1(C1), .D1(D1),
+				.S0(F0), .S1(F1),
+				.COUT(FCO)
+			);
+		end else if (MODE == "RAMW") begin
+			assign WDO0 = C1;
+			assign WDO1 = A1;
+			assign WDO2 = D1;
+			assign WDO3 = B1;
+			assign WADO0 = D0;
+			assign WADO1 = B0;
+			assign WADO2 = C0;
+			assign WADO3 = A0;
+		end else if (MODE == "DPRAM") begin
+			TRELLIS_RAM16X2 #(
+				.INITVAL_0(permute_initval(LUT0_INITVAL)),
+				.INITVAL_1(permute_initval(LUT1_INITVAL)),
+				.WREMUX(WREMUX)
+			) ram_i (
+				.DI0(WD0), .DI1(WD1),
+				.WAD0(WAD0), .WAD1(WAD1), .WAD2(WAD2), .WAD3(WAD3),
+				.WRE(WRE), .WCK(WCK),
+				.RAD0(D0), .RAD1(B0), .RAD2(C0), .RAD3(A0),
+				.DO0(F0), .DO1(F1)
+			);
+			// TODO: confirm RAD and INITVAL ordering
+			// DPRAM mode contract?
+			always @(*) begin
+				assert(A0==A1);
+				assert(B0==B1);
+				assert(C0==C1);
+				assert(D0==D1);
+			end
+		end else begin
+			ERROR_UNKNOWN_SLICE_MODE error();
+		end
+	endgenerate
+
+	// FF input selection muxes
+	wire muxdi0 = (REG0_SD == "1") ? DI0 : M0;
+	wire muxdi1 = (REG1_SD == "1") ? DI1 : M1;
+	// Flipflops
+	TRELLIS_FF #(
+		.GSR(GSR),
+		.CEMUX(CEMUX),
+		.CLKMUX(CLKMUX),
+		.LSRMUX(LSRMUX),
+		.SRMODE(SRMODE),
+		.REGSET(REG0_REGSET)
+	) ff_0 (
+		.CLK(CLK), .LSR(LSR), .CE(CE),
+		.DI(muxdi0),
+		.Q(Q0)
+	);
+	TRELLIS_FF #(
+		.GSR(GSR),
+		.CEMUX(CEMUX),
+		.CLKMUX(CLKMUX),
+		.LSRMUX(LSRMUX),
+		.SRMODE(SRMODE),
+		.REGSET(REG1_REGSET)
+	) ff_1 (
+		.CLK(CLK), .LSR(LSR), .CE(CE),
+		.DI(muxdi1),
+		.Q(Q1)
+	);
+endmodule
+
-- 
cgit v1.2.3


From 1def34f2a64603a3186dc50460fe964f1f197a43 Mon Sep 17 00:00:00 2001
From: David Shah <davey1576@gmail.com>
Date: Fri, 13 Jul 2018 14:08:42 +0200
Subject: ecp5: Adding DRAM map

Signed-off-by: David Shah <davey1576@gmail.com>
---
 techlibs/ecp5/cells_sim.v | 37 ++++++++++++++++++++++++++++++++++++-
 techlibs/ecp5/dram.txt    | 12 ++++++++++++
 techlibs/ecp5/drams_map.v | 28 ++++++++++++++++++++++++++++
 3 files changed, 76 insertions(+), 1 deletion(-)
 create mode 100644 techlibs/ecp5/dram.txt
 create mode 100644 techlibs/ecp5/drams_map.v

(limited to 'techlibs/ecp5')

diff --git a/techlibs/ecp5/cells_sim.v b/techlibs/ecp5/cells_sim.v
index 54006218f..06e6133a7 100644
--- a/techlibs/ecp5/cells_sim.v
+++ b/techlibs/ecp5/cells_sim.v
@@ -52,7 +52,7 @@ module TRELLIS_RAM16X2 (
 	input RAD0, RAD1, RAD2, RAD3,
 	output DO0, DO1
 );
-  parameter WCKMUX = "WCK";
+  	parameter WCKMUX = "WCK";
 	parameter WREMUX = "WRE";
 	parameter INITVAL_0 = 16'h0000;
 	parameter INITVAL_1 = 16'h0000;
@@ -87,6 +87,41 @@ endmodule
 
 // ---------------------------------------
 
+module TRELLIS_DPR16X4 (
+	input [3:0] DI,
+	input [3:0] WAD,
+	input WRE, WCK,
+	input [3:0] RAD,
+	output [3:0] DO
+);
+  	parameter WCKMUX = "WCK";
+	parameter WREMUX = "WRE";
+	parameter [63:0] INITVAL = 64'h0000000000000000;
+
+	reg [3:0] mem[15:0];
+
+	integer i;
+	initial begin
+		for (i = 0; i < 16; i = i + 1)
+			mem[i] <= INITVAL[4*i :+ 4];
+	end
+
+	wire muxwck = (WCKMUX == "INV") ? ~WCK : WCK;
+
+	wire muxwre = (WREMUX == "1") ? 1'b1 :
+							  (WREMUX == "0") ? 1'b0 :
+							  (WREMUX == "INV") ? ~WRE :
+							  WRE;
+
+	always @(posedge muxwck)
+		if (muxwre)
+			mem[WAD] <= DI;
+
+	assign DO = mem[RAD];
+endmodule
+
+// ---------------------------------------
+
 module DPR16X4C (
 		input [3:0] DI,
 		input WCK, WRE,
diff --git a/techlibs/ecp5/dram.txt b/techlibs/ecp5/dram.txt
new file mode 100644
index 000000000..a13111f0c
--- /dev/null
+++ b/techlibs/ecp5/dram.txt
@@ -0,0 +1,12 @@
+bram $__TRELLIS_DPR16X4
+  init 1
+  abits 4
+  dbits 4
+  groups 2
+  ports  1 1
+  wrmode 0 1
+  enable 0 1
+  transp 0 0
+  clocks 0 1
+  clkpol 0 2
+endbram
diff --git a/techlibs/ecp5/drams_map.v b/techlibs/ecp5/drams_map.v
new file mode 100644
index 000000000..3b3de831f
--- /dev/null
+++ b/techlibs/ecp5/drams_map.v
@@ -0,0 +1,28 @@
+module \$__TRELLIS_DPR16X4 (CLK1, A1ADDR, A1DATA, B1ADDR, B1DATA, B1EN);
+	parameter [63:0] INIT = 64'bx;
+	parameter CLKPOL2 = 1;
+	input CLK1;
+
+	input [3:0] A1ADDR;
+	output [3:0] A1DATA;
+
+	input [3:0] B1ADDR;
+	input [3:0] B1DATA;
+	input B1EN;
+
+	localparam WCKMUX = CLKPOL2 ? "WCK" : "INV";
+
+	TRELLIS_DPR16X4 #(
+		.INITVAL(INIT),
+		.WCKMUX(WCKMUX),
+		.WREMUX("WRE")
+	) _TECHMAP_REPLACE_ (
+		.RAD(A1ADDR),
+		.DO(A1DATA),
+
+		.WAD(B1ADDR),
+		.DI(B1DATA),
+		.WCK(CLK1),
+		.WRE(B1EN)
+	);
+endmodule
-- 
cgit v1.2.3


From eb8f3f7dc467156ffaec0ed1a471fe5e610709c7 Mon Sep 17 00:00:00 2001
From: David Shah <davey1576@gmail.com>
Date: Fri, 13 Jul 2018 14:32:23 +0200
Subject: ecp5: Adding DFF maps

Signed-off-by: David Shah <davey1576@gmail.com>
---
 techlibs/ecp5/cells_map.v | 29 +++++++++++++++++++++++++++++
 techlibs/ecp5/cells_sim.v |  2 +-
 2 files changed, 30 insertions(+), 1 deletion(-)

(limited to 'techlibs/ecp5')

diff --git a/techlibs/ecp5/cells_map.v b/techlibs/ecp5/cells_map.v
index 399697c14..05874ec09 100644
--- a/techlibs/ecp5/cells_map.v
+++ b/techlibs/ecp5/cells_map.v
@@ -1,3 +1,32 @@
+module  \$_DFF_N_ (input D, C, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("1"), .CLKMUX("INV"), .LSRMUX("LSR"), .REGSET("RESET"))  _TECHMAP_REPLACE_ (.CLK(C), .LSR(1'b0), .DI(D), .Q(Q)); endmodule
+module  \$_DFF_P_ (input D, C, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("1"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("RESET"))  _TECHMAP_REPLACE_ (.CLK(C), .LSR(1'b0), .DI(D), .Q(Q)); endmodule
+
+module  \$_DFFE_NN_ (input D, C, E, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("INV"), .CLKMUX("INV"), .LSRMUX("LSR"), .REGSET("RESET"))  _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(1'b0), .DI(D), .Q(Q)); endmodule
+module  \$_DFFE_PN_ (input D, C, E, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("INV"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("RESET"))  _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(1'b0), .DI(D), .Q(Q)); endmodule
+
+module  \$_DFFE_NP_ (input D, C, E, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("CE"), .CLKMUX("INV"), .LSRMUX("LSR"), .REGSET("RESET"))  _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(1'b0), .DI(D), .Q(Q)); endmodule
+module  \$_DFFE_PP_ (input D, C, E, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("RESET"))  _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(1'b0), .DI(D), .Q(Q)); endmodule
+
+module  \$_DFF_NN0_ (input D, C, R, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("1"), .CLKMUX("INV"), .LSRMUX("INV"), .REGSET("RESET"))  _TECHMAP_REPLACE_ (.CLK(C), .LSR(R), .DI(D), .Q(Q)); endmodule
+module  \$_DFF_NN1_ (input D, C, R, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("1"), .CLKMUX("INV"), .LSRMUX("INV"), .REGSET("SET"))  _TECHMAP_REPLACE_ (.CLK(C), .LSR(R), .DI(D), .Q(Q)); endmodule
+module  \$_DFF_PN0_ (input D, C, R, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("1"), .CLKMUX("CLK"), .LSRMUX("INV"), .REGSET("RESET"))  _TECHMAP_REPLACE_ (.CLK(C), .LSR(R), .DI(D), .Q(Q)); endmodule
+module  \$_DFF_PN1_ (input D, C, R, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("1"), .CLKMUX("CLK"), .LSRMUX("INV"), .REGSET("SET"))  _TECHMAP_REPLACE_ (.CLK(C), .LSR(R), .DI(D), .Q(Q)); endmodule
+
+module  \$_DFF_NP0_ (input D, C, R, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("1"), .CLKMUX("INV"), .LSRMUX("LSR"), .REGSET("RESET"))  _TECHMAP_REPLACE_ (.CLK(C), .LSR(R), .DI(D), .Q(Q)); endmodule
+module  \$_DFF_NP1_ (input D, C, R, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("1"), .CLKMUX("INV"), .LSRMUX("LSR"), .REGSET("SET"))  _TECHMAP_REPLACE_ (.CLK(C), .LSR(R), .DI(D), .Q(Q)); endmodule
+module  \$_DFF_PP0_ (input D, C, R, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("1"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("RESET"))  _TECHMAP_REPLACE_ (.CLK(C), .LSR(R), .DI(D), .Q(Q)); endmodule
+module  \$_DFF_PP1_ (input D, C, R, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("1"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("SET"))  _TECHMAP_REPLACE_ (.CLK(C), .LSR(R), .DI(D), .Q(Q)); endmodule
+
+module  \$__DFFE_NN0 (input D, C, E, R, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("CE"), .CLKMUX("INV"), .LSRMUX("INV"), .REGSET("RESET"))  _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(R), .DI(D), .Q(Q)); endmodule
+module  \$__DFFE_NN1 (input D, C, E, R, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("CE"), .CLKMUX("INV"), .LSRMUX("INV"), .REGSET("SET"))  _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(R), .DI(D), .Q(Q)); endmodule
+module  \$__DFFE_PN0 (input D, C, E, R, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("INV"), .REGSET("RESET"))  _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(R), .DI(D), .Q(Q)); endmodule
+module  \$__DFFE_PN1 (input D, C, E, R, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("INV"), .REGSET("SET"))  _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(R), .DI(D), .Q(Q)); endmodule
+
+module  \$__DFFE_NP0 (input D, C, E, R, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("CE"), .CLKMUX("INV"), .LSRMUX("LSR"), .REGSET("RESET"))  _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(R), .DI(D), .Q(Q)); endmodule
+module  \$__DFFE_NP1 (input D, C, E, R, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("CE"), .CLKMUX("INV"), .LSRMUX("LSR"), .REGSET("SET"))  _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(R), .DI(D), .Q(Q)); endmodule
+module  \$__DFFE_PP0 (input D, C, E, R, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("RESET"))  _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(R), .DI(D), .Q(Q)); endmodule
+module  \$__DFFE_PP1 (input D, C, E, R, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("SET"))  _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(R), .DI(D), .Q(Q)); endmodule
+
 `ifndef NO_LUT
 module \$lut (A, Y);
     parameter WIDTH = 0;
diff --git a/techlibs/ecp5/cells_sim.v b/techlibs/ecp5/cells_sim.v
index 06e6133a7..32aec4e93 100644
--- a/techlibs/ecp5/cells_sim.v
+++ b/techlibs/ecp5/cells_sim.v
@@ -199,7 +199,7 @@ module TRELLIS_FF(input CLK, LSR, CE, DI, output reg Q);
 
 	wire srval = (REGSET == "SET") ? 1'b1 : 1'b0;
 
-	initial Q = 1'b0;
+	initial Q = srval;
 
 	generate
 		if (SRMODE == "ASYNC") begin
-- 
cgit v1.2.3


From c2d7be140a2b40ecb553f87437c6f958786030ad Mon Sep 17 00:00:00 2001
From: David Shah <davey1576@gmail.com>
Date: Fri, 13 Jul 2018 14:52:25 +0200
Subject: ecp5: Adding basic synth_ecp5 based on synth_ice40

Signed-off-by: David Shah <davey1576@gmail.com>
---
 techlibs/ecp5/Makefile.inc  |   7 +
 techlibs/ecp5/cells_map.v   |  14 +-
 techlibs/ecp5/synth_ecp5.cc | 331 ++++++++++++++++++++++++++++++++++++++++++++
 3 files changed, 345 insertions(+), 7 deletions(-)
 create mode 100644 techlibs/ecp5/Makefile.inc
 create mode 100644 techlibs/ecp5/synth_ecp5.cc

(limited to 'techlibs/ecp5')

diff --git a/techlibs/ecp5/Makefile.inc b/techlibs/ecp5/Makefile.inc
new file mode 100644
index 000000000..e0900f8f4
--- /dev/null
+++ b/techlibs/ecp5/Makefile.inc
@@ -0,0 +1,7 @@
+
+OBJS += techlibs/ecp5/synth_ecp5.o
+
+$(eval $(call add_share_file,share/ecp5,techlibs/ecp5/cells_map.v))
+$(eval $(call add_share_file,share/ecp5,techlibs/ecp5/cells_sim.v))
+$(eval $(call add_share_file,share/ecp5,techlibs/ecp5/drams_map.v))
+$(eval $(call add_share_file,share/ecp5,techlibs/ecp5/dram.txt))
diff --git a/techlibs/ecp5/cells_map.v b/techlibs/ecp5/cells_map.v
index 05874ec09..6bce03755 100644
--- a/techlibs/ecp5/cells_map.v
+++ b/techlibs/ecp5/cells_map.v
@@ -59,7 +59,7 @@ module \$lut (A, Y);
                 .A(A[0]), .B(A[1]), .C(A[2]), .D(A[3]));
             LUT4 #(.INIT(LUT[31:16])) lut1 (.Z(f1),
                 .A(A[0]), .B(A[1]), .C(A[2]), .D(A[3]));
-            PFUMX mux5(.ALUT(f1), .BLUT(f0), .SD(A[4]), .Z(Y));
+            PFUMX mux5(.ALUT(f1), .BLUT(f0), .C0(A[4]), .Z(Y));
         end else
         if (WIDTH == 6) begin
             wire f0, f1, f2, f3, g0, g1;
@@ -73,8 +73,8 @@ module \$lut (A, Y);
             LUT4 #(.INIT(LUT[63:48])) lut3 (.Z(f3),
                 .A(A[0]), .B(A[1]), .C(A[2]), .D(A[3]));
 
-            PFUMX mux50(.ALUT(f1), .BLUT(f0), .SD(A[4]), .Z(g0));
-            PFUMX mux51(.ALUT(f3), .BLUT(f2), .SD(A[4]), .Z(g1));
+            PFUMX mux50(.ALUT(f1), .BLUT(f0), .C0(A[4]), .Z(g0));
+            PFUMX mux51(.ALUT(f3), .BLUT(f2), .C0(A[4]), .Z(g1));
             L6MUX21 mux6 (.D0(g0), .D1(g1), .SD(A[5]), .Z(Y));
         end else
         if (WIDTH == 7) begin
@@ -99,10 +99,10 @@ module \$lut (A, Y);
             LUT4 #(.INIT(LUT[127:112])) lut7 (.Z(f7),
                 .A(A[0]), .B(A[1]), .C(A[2]), .D(A[3]));
 
-            PFUMX mux50(.ALUT(f1), .BLUT(f0), .SD(A[4]), .Z(g0));
-            PFUMX mux51(.ALUT(f3), .BLUT(f2), .SD(A[4]), .Z(g1));
-            PFUMX mux52(.ALUT(f5), .BLUT(f4), .SD(A[4]), .Z(g2));
-            PFUMX mux53(.ALUT(f7), .BLUT(f6), .SD(A[4]), .Z(g3));
+            PFUMX mux50(.ALUT(f1), .BLUT(f0), .C0(A[4]), .Z(g0));
+            PFUMX mux51(.ALUT(f3), .BLUT(f2), .C0(A[4]), .Z(g1));
+            PFUMX mux52(.ALUT(f5), .BLUT(f4), .C0(A[4]), .Z(g2));
+            PFUMX mux53(.ALUT(f7), .BLUT(f6), .C0(A[4]), .Z(g3));
             L6MUX21 mux60 (.D0(g0), .D1(g1), .SD(A[5]), .Z(h0));
             L6MUX21 mux61 (.D0(g2), .D1(g3), .SD(A[5]), .Z(h1));
             L6MUX21 mux7  (.D0(h0), .D1(h1), .SD(A[6]), .Z(Y));
diff --git a/techlibs/ecp5/synth_ecp5.cc b/techlibs/ecp5/synth_ecp5.cc
new file mode 100644
index 000000000..219496738
--- /dev/null
+++ b/techlibs/ecp5/synth_ecp5.cc
@@ -0,0 +1,331 @@
+/*
+ *  yosys -- Yosys Open SYnthesis Suite
+ *
+ *  Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
+ *  Copyright (C) 2018 Clifford Wolf <dave@ds0.me>
+ *
+ *  Permission to use, copy, modify, and/or distribute this software for any
+ *  purpose with or without fee is hereby granted, provided that the above
+ *  copyright notice and this permission notice appear in all copies.
+ *
+ *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ */
+
+#include "kernel/register.h"
+#include "kernel/celltypes.h"
+#include "kernel/rtlil.h"
+#include "kernel/log.h"
+
+USING_YOSYS_NAMESPACE
+PRIVATE_NAMESPACE_BEGIN
+
+struct SynthEcp5Pass : public ScriptPass
+{
+	SynthEcp5Pass() : ScriptPass("synth_ecp5", "synthesis for ECP5 FPGAs") { }
+
+	virtual void help() YS_OVERRIDE
+	{
+		//   |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
+		log("\n");
+		log("    synth_ecp5 [options]\n");
+		log("\n");
+		log("This command runs synthesis for ECP5 FPGAs.\n");
+		log("\n");
+		log("    -top <module>\n");
+		log("        use the specified module as top module\n");
+		log("\n");
+		log("    -blif <file>\n");
+		log("        write the design to the specified BLIF file. writing of an output file\n");
+		log("        is omitted if this parameter is not specified.\n");
+		log("\n");
+		log("    -edif <file>\n");
+		log("        write the design to the specified EDIF file. writing of an output file\n");
+		log("        is omitted if this parameter is not specified.\n");
+		log("\n");
+		log("    -json <file>\n");
+		log("        write the design to the specified JSON file. writing of an output file\n");
+		log("        is omitted if this parameter is not specified.\n");
+		log("\n");
+		log("    -run <from_label>:<to_label>\n");
+		log("        only run the commands between the labels (see below). an empty\n");
+		log("        from label is synonymous to 'begin', and empty to label is\n");
+		log("        synonymous to the end of the command list.\n");
+		log("\n");
+		log("    -noflatten\n");
+		log("        do not flatten design before synthesis\n");
+		log("\n");
+		log("    -retime\n");
+		log("        run 'abc' with -dff option\n");
+		log("\n");
+		log("    -noccu2\n");
+		log("        do not use CCU2 cells in output netlist\n");
+		log("\n");
+		log("    -nodffe\n");
+		log("        do not use flipflops with CE in output netlist\n");
+		log("\n");
+		log("    -nobram\n");
+		log("        do not use BRAM cells in output netlist\n");
+		log("\n");
+		log("    -nodram\n");
+		log("        do not use distributed RAM cells in output netlist\n");
+		log("\n");
+		log("    -nomux\n");
+		log("        do not use PFU muxes to implement LUTs larger than LUT4s\n");
+		log("\n");
+		log("    -abc2\n");
+		log("        run two passes of 'abc' for slightly improved logic density\n");
+		log("\n");
+		log("    -vpr\n");
+		log("        generate an output netlist (and BLIF file) suitable for VPR\n");
+		log("        (this feature is experimental and incomplete)\n");
+		log("\n");
+		log("\n");
+		log("The following commands are executed by this synthesis command:\n");
+		help_script();
+		log("\n");
+	}
+
+	string top_opt, blif_file, edif_file, json_file;
+	bool noccu2, nodffe, nobram, nodram, nomux, flatten, retime, abc2, vpr;
+
+	virtual void clear_flags() YS_OVERRIDE
+	{
+		top_opt = "-auto-top";
+		blif_file = "";
+		edif_file = "";
+		json_file = "";
+		noccu2 = false;
+		nodffe = false;
+		nobram = false;
+		nodram = false;
+		nomux = false;
+		flatten = true;
+		retime = false;
+		abc2 = false;
+		vpr = false;
+	}
+
+	virtual void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
+	{
+		string run_from, run_to;
+		clear_flags();
+
+		size_t argidx;
+		for (argidx = 1; argidx < args.size(); argidx++)
+		{
+			if (args[argidx] == "-top" && argidx+1 < args.size()) {
+				top_opt = "-top " + args[++argidx];
+				continue;
+			}
+			if (args[argidx] == "-blif" && argidx+1 < args.size()) {
+				blif_file = args[++argidx];
+				continue;
+			}
+			if (args[argidx] == "-edif" && argidx+1 < args.size()) {
+				edif_file = args[++argidx];
+				continue;
+			}
+			if (args[argidx] == "-json" && argidx+1 < args.size()) {
+				json_file = args[++argidx];
+				continue;
+			}
+			if (args[argidx] == "-run" && argidx+1 < args.size()) {
+				size_t pos = args[argidx+1].find(':');
+				if (pos == std::string::npos)
+					break;
+				run_from = args[++argidx].substr(0, pos);
+				run_to = args[argidx].substr(pos+1);
+				continue;
+			}
+			if (args[argidx] == "-flatten") {
+				flatten = true;
+				continue;
+			}
+			if (args[argidx] == "-noflatten") {
+				flatten = false;
+				continue;
+			}
+			if (args[argidx] == "-retime") {
+				retime = true;
+				continue;
+			}
+			if (args[argidx] == "-noccu2") {
+				noccu2 = true;
+				continue;
+			}
+			if (args[argidx] == "-nodffe") {
+				nodffe = true;
+				continue;
+			}
+			if (args[argidx] == "-nobram") {
+				nobram = true;
+				continue;
+			}
+			if (args[argidx] == "-nodram") {
+				nodram = true;
+				continue;
+			}
+			if (args[argidx] == "-abc2") {
+				abc2 = true;
+				continue;
+			}
+			if (args[argidx] == "-vpr") {
+				vpr = true;
+				continue;
+			}
+			break;
+		}
+		extra_args(args, argidx, design);
+
+		if (!design->full_selection())
+			log_cmd_error("This comannd only operates on fully selected designs!\n");
+
+		log_header(design, "Executing SYNTH_ECP5 pass.\n");
+		log_push();
+
+		run_script(design, run_from, run_to);
+
+		log_pop();
+	}
+
+	virtual void script() YS_OVERRIDE
+	{
+		if (check_label("begin"))
+		{
+			run("read_verilog -lib +/ecp5/cells_sim.v");
+			run(stringf("hierarchy -check %s", help_mode ? "-top <top>" : top_opt.c_str()));
+		}
+
+		if (flatten && check_label("flatten", "(unless -noflatten)"))
+		{
+			run("proc");
+			run("flatten");
+			run("tribuf -logic");
+			run("deminout");
+		}
+
+		if (check_label("coarse"))
+		{
+			run("synth -run coarse");
+		}
+
+		if (!nobram && check_label("bram", "(skip if -nobram)"))
+		{
+			//TODO
+#if 0
+			run("memory_bram -rules +/ecp5/brams.txt");
+			run("techmap -map +/ecp5/brams_map.v");
+#endif
+		}
+
+		if (!nodram && check_label("dram", "(skip if -nodram)"))
+		{
+			run("memory_bram -rules +/ecp5/dram.txt");
+			run("techmap -map +/ecp5/drams_map.v");
+		}
+
+		if (check_label("fine"))
+		{
+			run("opt -fast -mux_undef -undriven -fine");
+			run("memory_map");
+			run("opt -undriven -fine");
+			//TODO
+#if 0
+			if (nocarry)
+				run("techmap");
+			else
+				run("techmap -map +/techmap.v -map +/ecp5/arith_map.v");
+#else
+				run("techmap");
+#endif
+			if (retime || help_mode)
+				run("abc -dff", "(only if -retime)");
+		}
+
+		if (check_label("map_ffs"))
+		{
+			run("dffsr2dff");
+			if (!nodffe)
+				run("dff2dffe -direct-match $_DFF_*");
+			run("techmap -D NO_LUT -map +/ecp5/cells_map.v");
+			run("opt_expr -mux_undef");
+			run("simplemap");
+			// TODO
+#if 0
+			run("ecp5_ffinit");
+			run("ecp5_ffssr");
+#endif
+		}
+
+		if (check_label("map_luts"))
+		{
+			if (abc2 || help_mode) {
+				run("abc", "      (only if -abc2)");
+			}
+			//TODO
+#if 0
+			run("techmap -map +/ecp5/latches_map.v");
+#endif
+			if (nomux)
+				run("abc -lut 4");
+			else
+				run("abc -lut 4:7");
+			run("clean");
+		}
+
+		if (check_label("map_cells"))
+		{
+			if (vpr)
+				run("techmap -D NO_LUT -map +/ecp5/cells_map.v");
+			else
+				run("techmap -map +/ecp5/cells_map.v", "(with -D NO_LUT in vpr mode)");
+
+			run("clean");
+		}
+
+		if (check_label("check"))
+		{
+			run("hierarchy -check");
+			run("stat");
+			run("check -noinit");
+		}
+
+		if (check_label("blif"))
+		{
+			if (!blif_file.empty() || help_mode) {
+				if (vpr || help_mode) {
+					run(stringf("opt_clean -purge"),
+							"                                 (vpr mode)");
+					run(stringf("write_blif -attr -cname -conn -param %s",
+							help_mode ? "<file-name>" : blif_file.c_str()),
+							" (vpr mode)");
+				}
+				if (!vpr)
+					run(stringf("write_blif -gates -attr -param %s",
+							help_mode ? "<file-name>" : blif_file.c_str()),
+							"       (non-vpr mode)");
+			}
+		}
+
+		if (check_label("edif"))
+		{
+			if (!edif_file.empty() || help_mode)
+				run(stringf("write_edif %s", help_mode ? "<file-name>" : edif_file.c_str()));
+		}
+
+		if (check_label("json"))
+		{
+			if (!json_file.empty() || help_mode)
+				run(stringf("write_json %s", help_mode ? "<file-name>" : json_file.c_str()));
+		}
+	}
+} SynthEcp5Pass;
+
+PRIVATE_NAMESPACE_END
-- 
cgit v1.2.3


From 11c916840d127d7e32fd9689f1c86cdc847352e0 Mon Sep 17 00:00:00 2001
From: David Shah <davey1576@gmail.com>
Date: Fri, 13 Jul 2018 15:46:12 +0200
Subject: ecp5: Initial arith_map implementation

Signed-off-by: David Shah <davey1576@gmail.com>
---
 techlibs/ecp5/Makefile.inc  |  1 +
 techlibs/ecp5/arith_map.v   | 78 +++++++++++++++++++++++++++++++++++++++++++++
 techlibs/ecp5/synth_ecp5.cc |  7 +---
 3 files changed, 80 insertions(+), 6 deletions(-)
 create mode 100644 techlibs/ecp5/arith_map.v

(limited to 'techlibs/ecp5')

diff --git a/techlibs/ecp5/Makefile.inc b/techlibs/ecp5/Makefile.inc
index e0900f8f4..9d3247347 100644
--- a/techlibs/ecp5/Makefile.inc
+++ b/techlibs/ecp5/Makefile.inc
@@ -5,3 +5,4 @@ $(eval $(call add_share_file,share/ecp5,techlibs/ecp5/cells_map.v))
 $(eval $(call add_share_file,share/ecp5,techlibs/ecp5/cells_sim.v))
 $(eval $(call add_share_file,share/ecp5,techlibs/ecp5/drams_map.v))
 $(eval $(call add_share_file,share/ecp5,techlibs/ecp5/dram.txt))
+$(eval $(call add_share_file,share/ecp5,techlibs/ecp5/arith_map.v))
diff --git a/techlibs/ecp5/arith_map.v b/techlibs/ecp5/arith_map.v
new file mode 100644
index 000000000..3c2b86deb
--- /dev/null
+++ b/techlibs/ecp5/arith_map.v
@@ -0,0 +1,78 @@
+/*
+ *  yosys -- Yosys Open SYnthesis Suite
+ *
+ *  Copyright (C) 2012  Clifford Wolf <clifford@clifford.at>
+ *  Copyright (C) 2018  David Shah <dave@ds0.me>
+ *
+ *  Permission to use, copy, modify, and/or distribute this software for any
+ *  purpose with or without fee is hereby granted, provided that the above
+ *  copyright notice and this permission notice appear in all copies.
+ *
+ *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ */
+
+(* techmap_celltype = "$alu" *)
+module _80_ecp5_alu (A, B, CI, BI, X, Y, CO);
+	parameter A_SIGNED = 0;
+	parameter B_SIGNED = 0;
+	parameter A_WIDTH = 1;
+	parameter B_WIDTH = 1;
+	parameter Y_WIDTH = 1;
+
+	input [A_WIDTH-1:0] A;
+	input [B_WIDTH-1:0] B;
+	output [Y_WIDTH-1:0] X, Y;
+
+	input CI, BI;
+	output [Y_WIDTH-1:0] CO;
+
+	wire _TECHMAP_FAIL_ = Y_WIDTH <= 2;
+
+	wire [Y_WIDTH-1:0] A_buf, B_buf;
+	\$pos #(.A_SIGNED(A_SIGNED), .A_WIDTH(A_WIDTH), .Y_WIDTH(Y_WIDTH)) A_conv (.A(A), .Y(A_buf));
+	\$pos #(.A_SIGNED(B_SIGNED), .A_WIDTH(B_WIDTH), .Y_WIDTH(Y_WIDTH)) B_conv (.A(B), .Y(B_buf));
+
+	function integer round_up2;
+		input integer N;
+		begin
+			round_up2 = ((N / 2) + 1) * 2;
+		end
+	endfunction
+
+	localparam Y_WIDTH2 = round_up2(Y_WIDTH);
+
+	wire [Y_WIDTH2-1:0] AA = A_buf;
+	wire [Y_WIDTH2-1:0] BB = BI ? ~B_buf : B_buf;
+	wire [Y_WIDTH2-1:0] C = {CO, CI};
+	wire [Y_WIDTH2-1:0] FCO;
+
+	genvar i;
+	generate for (i = 0; i < Y_WIDTH2; i = i + 2) begin:slice
+		CCU2C #(
+			.INIT0(16'b0110011010101010),
+			.INIT1(16'b0110011010101010),
+			.INJECT1_0(1'b0),
+			.INJECT1_1(1'b0)
+	   ) ccu2c_i (
+			.CIN(C[i]),
+			.A0(AA[i]), .B0(BB[i]), .C0(1'b0), .D0(1'b1),
+			.A1(AA[i+1]), .B1(BB[i]), .C1(1'b0), .D1(1'b1),
+			.S0(F0), .S1(F1),
+			.COUT(FCO[i])
+		);
+
+		assign CO[i] = (AA[i] && BB[i]) || (C[i] && (AA[i] || BB[i]));
+		if (i < Y_WIDTH)
+			assign CO[i+1] = FCO[i];
+
+	end endgenerate
+
+	assign X = AA ^ BB;
+endmodule
diff --git a/techlibs/ecp5/synth_ecp5.cc b/techlibs/ecp5/synth_ecp5.cc
index 219496738..86d2027de 100644
--- a/techlibs/ecp5/synth_ecp5.cc
+++ b/techlibs/ecp5/synth_ecp5.cc
@@ -236,15 +236,10 @@ struct SynthEcp5Pass : public ScriptPass
 			run("opt -fast -mux_undef -undriven -fine");
 			run("memory_map");
 			run("opt -undriven -fine");
-			//TODO
-#if 0
-			if (nocarry)
+			if (noccu2)
 				run("techmap");
 			else
 				run("techmap -map +/techmap.v -map +/ecp5/arith_map.v");
-#else
-				run("techmap");
-#endif
 			if (retime || help_mode)
 				run("abc -dff", "(only if -retime)");
 		}
-- 
cgit v1.2.3


From b0fea67cc66ceac64e2cb71874c36cde21aa34df Mon Sep 17 00:00:00 2001
From: David Shah <davey1576@gmail.com>
Date: Fri, 13 Jul 2018 15:49:59 +0200
Subject: ecp5: Fixing arith_map

Signed-off-by: David Shah <davey1576@gmail.com>
---
 techlibs/ecp5/arith_map.v | 9 +++++----
 1 file changed, 5 insertions(+), 4 deletions(-)

(limited to 'techlibs/ecp5')

diff --git a/techlibs/ecp5/arith_map.v b/techlibs/ecp5/arith_map.v
index 3c2b86deb..cf21ee80e 100644
--- a/techlibs/ecp5/arith_map.v
+++ b/techlibs/ecp5/arith_map.v
@@ -51,7 +51,7 @@ module _80_ecp5_alu (A, B, CI, BI, X, Y, CO);
 	wire [Y_WIDTH2-1:0] AA = A_buf;
 	wire [Y_WIDTH2-1:0] BB = BI ? ~B_buf : B_buf;
 	wire [Y_WIDTH2-1:0] C = {CO, CI};
-	wire [Y_WIDTH2-1:0] FCO;
+	wire [Y_WIDTH2-1:0] FCO, Y1;
 
 	genvar i;
 	generate for (i = 0; i < Y_WIDTH2; i = i + 2) begin:slice
@@ -64,14 +64,15 @@ module _80_ecp5_alu (A, B, CI, BI, X, Y, CO);
 			.CIN(C[i]),
 			.A0(AA[i]), .B0(BB[i]), .C0(1'b0), .D0(1'b1),
 			.A1(AA[i+1]), .B1(BB[i]), .C1(1'b0), .D1(1'b1),
-			.S0(F0), .S1(F1),
+			.S0(Y[i]), .S1(Y1[i]),
 			.COUT(FCO[i])
 		);
 
 		assign CO[i] = (AA[i] && BB[i]) || (C[i] && (AA[i] || BB[i]));
-		if (i < Y_WIDTH)
+		if (i < Y_WIDTH) begin
 			assign CO[i+1] = FCO[i];
-
+			assign Y[i+1] = Y1[i];
+		end
 	end endgenerate
 
 	assign X = AA ^ BB;
-- 
cgit v1.2.3


From 4a60bc83ab47b76632b38fcaec4cefffa152f507 Mon Sep 17 00:00:00 2001
From: David Shah <davey1576@gmail.com>
Date: Fri, 13 Jul 2018 16:14:08 +0200
Subject: ecp5: Cells and mappings fixes

Signed-off-by: David Shah <davey1576@gmail.com>
---
 techlibs/ecp5/arith_map.v | 6 +++---
 techlibs/ecp5/cells_sim.v | 4 ++--
 2 files changed, 5 insertions(+), 5 deletions(-)

(limited to 'techlibs/ecp5')

diff --git a/techlibs/ecp5/arith_map.v b/techlibs/ecp5/arith_map.v
index cf21ee80e..05d44b9b4 100644
--- a/techlibs/ecp5/arith_map.v
+++ b/techlibs/ecp5/arith_map.v
@@ -58,12 +58,12 @@ module _80_ecp5_alu (A, B, CI, BI, X, Y, CO);
 		CCU2C #(
 			.INIT0(16'b0110011010101010),
 			.INIT1(16'b0110011010101010),
-			.INJECT1_0(1'b0),
-			.INJECT1_1(1'b0)
+			.INJECT1_0("NO"),
+			.INJECT1_1("NO")
 	   ) ccu2c_i (
 			.CIN(C[i]),
 			.A0(AA[i]), .B0(BB[i]), .C0(1'b0), .D0(1'b1),
-			.A1(AA[i+1]), .B1(BB[i]), .C1(1'b0), .D1(1'b1),
+			.A1(AA[i+1]), .B1(BB[i+1]), .C1(1'b0), .D1(1'b1),
 			.S0(Y[i]), .S1(Y1[i]),
 			.COUT(FCO[i])
 		);
diff --git a/techlibs/ecp5/cells_sim.v b/techlibs/ecp5/cells_sim.v
index 32aec4e93..6c53a78eb 100644
--- a/techlibs/ecp5/cells_sim.v
+++ b/techlibs/ecp5/cells_sim.v
@@ -103,7 +103,7 @@ module TRELLIS_DPR16X4 (
 	integer i;
 	initial begin
 		for (i = 0; i < 16; i = i + 1)
-			mem[i] <= INITVAL[4*i :+ 4];
+			mem[i] <= {INITVAL[i+3], INITVAL[i+2], INITVAL[i+1], INITVAL[i]};
 	end
 
 	wire muxwck = (WCKMUX == "INV") ? ~WCK : WCK;
@@ -197,7 +197,7 @@ module TRELLIS_FF(input CLK, LSR, CE, DI, output reg Q);
 	wire muxlsr = (LSRMUX == "INV") ? ~LSR : LSR;
 	wire muxclk = (CLKMUX == "INV") ? ~CLK : CLK;
 
-	wire srval = (REGSET == "SET") ? 1'b1 : 1'b0;
+	localparam srval = (REGSET == "SET") ? 1'b1 : 1'b0;
 
 	initial Q = srval;
 
-- 
cgit v1.2.3


From 241429abac67de34b073db46550b1c2b4a42d425 Mon Sep 17 00:00:00 2001
From: David Shah <davey1576@gmail.com>
Date: Fri, 13 Jul 2018 16:25:52 +0200
Subject: ecp5: Add DRAM match rule

Signed-off-by: David Shah <davey1576@gmail.com>
---
 techlibs/ecp5/dram.txt | 4 ++++
 1 file changed, 4 insertions(+)

(limited to 'techlibs/ecp5')

diff --git a/techlibs/ecp5/dram.txt b/techlibs/ecp5/dram.txt
index a13111f0c..b3252fa9a 100644
--- a/techlibs/ecp5/dram.txt
+++ b/techlibs/ecp5/dram.txt
@@ -10,3 +10,7 @@ bram $__TRELLIS_DPR16X4
   clocks 0 1
   clkpol 0 2
 endbram
+
+match $__TRELLIS_DPR16X4
+  make_outreg
+endmatch
-- 
cgit v1.2.3


From 459d3679134d4e30d9b4bfbc7007368d229c9e9f Mon Sep 17 00:00:00 2001
From: David Shah <davey1576@gmail.com>
Date: Sat, 14 Jul 2018 15:54:30 +0200
Subject: ecp5: Adding synchronous set/reset support

Signed-off-by: David Shah <davey1576@gmail.com>
---
 techlibs/ecp5/cells_map.v   | 58 ++++++++++++++++++++++++++++++---------------
 techlibs/ecp5/synth_ecp5.cc |  5 ++--
 2 files changed, 42 insertions(+), 21 deletions(-)

(limited to 'techlibs/ecp5')

diff --git a/techlibs/ecp5/cells_map.v b/techlibs/ecp5/cells_map.v
index 6bce03755..48162a4dc 100644
--- a/techlibs/ecp5/cells_map.v
+++ b/techlibs/ecp5/cells_map.v
@@ -7,25 +7,45 @@ module  \$_DFFE_PN_ (input D, C, E, output Q); TRELLIS_FF #(.GSR("DISABLED"), .C
 module  \$_DFFE_NP_ (input D, C, E, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("CE"), .CLKMUX("INV"), .LSRMUX("LSR"), .REGSET("RESET"))  _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(1'b0), .DI(D), .Q(Q)); endmodule
 module  \$_DFFE_PP_ (input D, C, E, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("RESET"))  _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(1'b0), .DI(D), .Q(Q)); endmodule
 
-module  \$_DFF_NN0_ (input D, C, R, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("1"), .CLKMUX("INV"), .LSRMUX("INV"), .REGSET("RESET"))  _TECHMAP_REPLACE_ (.CLK(C), .LSR(R), .DI(D), .Q(Q)); endmodule
-module  \$_DFF_NN1_ (input D, C, R, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("1"), .CLKMUX("INV"), .LSRMUX("INV"), .REGSET("SET"))  _TECHMAP_REPLACE_ (.CLK(C), .LSR(R), .DI(D), .Q(Q)); endmodule
-module  \$_DFF_PN0_ (input D, C, R, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("1"), .CLKMUX("CLK"), .LSRMUX("INV"), .REGSET("RESET"))  _TECHMAP_REPLACE_ (.CLK(C), .LSR(R), .DI(D), .Q(Q)); endmodule
-module  \$_DFF_PN1_ (input D, C, R, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("1"), .CLKMUX("CLK"), .LSRMUX("INV"), .REGSET("SET"))  _TECHMAP_REPLACE_ (.CLK(C), .LSR(R), .DI(D), .Q(Q)); endmodule
-
-module  \$_DFF_NP0_ (input D, C, R, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("1"), .CLKMUX("INV"), .LSRMUX("LSR"), .REGSET("RESET"))  _TECHMAP_REPLACE_ (.CLK(C), .LSR(R), .DI(D), .Q(Q)); endmodule
-module  \$_DFF_NP1_ (input D, C, R, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("1"), .CLKMUX("INV"), .LSRMUX("LSR"), .REGSET("SET"))  _TECHMAP_REPLACE_ (.CLK(C), .LSR(R), .DI(D), .Q(Q)); endmodule
-module  \$_DFF_PP0_ (input D, C, R, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("1"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("RESET"))  _TECHMAP_REPLACE_ (.CLK(C), .LSR(R), .DI(D), .Q(Q)); endmodule
-module  \$_DFF_PP1_ (input D, C, R, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("1"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("SET"))  _TECHMAP_REPLACE_ (.CLK(C), .LSR(R), .DI(D), .Q(Q)); endmodule
-
-module  \$__DFFE_NN0 (input D, C, E, R, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("CE"), .CLKMUX("INV"), .LSRMUX("INV"), .REGSET("RESET"))  _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(R), .DI(D), .Q(Q)); endmodule
-module  \$__DFFE_NN1 (input D, C, E, R, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("CE"), .CLKMUX("INV"), .LSRMUX("INV"), .REGSET("SET"))  _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(R), .DI(D), .Q(Q)); endmodule
-module  \$__DFFE_PN0 (input D, C, E, R, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("INV"), .REGSET("RESET"))  _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(R), .DI(D), .Q(Q)); endmodule
-module  \$__DFFE_PN1 (input D, C, E, R, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("INV"), .REGSET("SET"))  _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(R), .DI(D), .Q(Q)); endmodule
-
-module  \$__DFFE_NP0 (input D, C, E, R, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("CE"), .CLKMUX("INV"), .LSRMUX("LSR"), .REGSET("RESET"))  _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(R), .DI(D), .Q(Q)); endmodule
-module  \$__DFFE_NP1 (input D, C, E, R, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("CE"), .CLKMUX("INV"), .LSRMUX("LSR"), .REGSET("SET"))  _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(R), .DI(D), .Q(Q)); endmodule
-module  \$__DFFE_PP0 (input D, C, E, R, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("RESET"))  _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(R), .DI(D), .Q(Q)); endmodule
-module  \$__DFFE_PP1 (input D, C, E, R, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("SET"))  _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(R), .DI(D), .Q(Q)); endmodule
+module  \$_DFF_NN0_ (input D, C, R, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("1"), .CLKMUX("INV"), .LSRMUX("INV"), .REGSET("RESET"), .SRMODE("ASYNC"))  _TECHMAP_REPLACE_ (.CLK(C), .LSR(R), .DI(D), .Q(Q)); endmodule
+module  \$_DFF_NN1_ (input D, C, R, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("1"), .CLKMUX("INV"), .LSRMUX("INV"), .REGSET("SET"), .SRMODE("ASYNC"))  _TECHMAP_REPLACE_ (.CLK(C), .LSR(R), .DI(D), .Q(Q)); endmodule
+module  \$_DFF_PN0_ (input D, C, R, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("1"), .CLKMUX("CLK"), .LSRMUX("INV"), .REGSET("RESET"), .SRMODE("ASYNC"))  _TECHMAP_REPLACE_ (.CLK(C), .LSR(R), .DI(D), .Q(Q)); endmodule
+module  \$_DFF_PN1_ (input D, C, R, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("1"), .CLKMUX("CLK"), .LSRMUX("INV"), .REGSET("SET"), .SRMODE("ASYNC"))  _TECHMAP_REPLACE_ (.CLK(C), .LSR(R), .DI(D), .Q(Q)); endmodule
+
+module  \$_DFF_NP0_ (input D, C, R, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("1"), .CLKMUX("INV"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("ASYNC"))  _TECHMAP_REPLACE_ (.CLK(C), .LSR(R), .DI(D), .Q(Q)); endmodule
+module  \$_DFF_NP1_ (input D, C, R, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("1"), .CLKMUX("INV"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("ASYNC"))  _TECHMAP_REPLACE_ (.CLK(C), .LSR(R), .DI(D), .Q(Q)); endmodule
+module  \$_DFF_PP0_ (input D, C, R, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("1"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("ASYNC"))  _TECHMAP_REPLACE_ (.CLK(C), .LSR(R), .DI(D), .Q(Q)); endmodule
+module  \$_DFF_PP1_ (input D, C, R, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("1"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("ASYNC"))  _TECHMAP_REPLACE_ (.CLK(C), .LSR(R), .DI(D), .Q(Q)); endmodule
+
+module  \$__DFFS_NN0_ (input D, C, R, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("1"), .CLKMUX("INV"), .LSRMUX("INV"), .REGSET("RESET"), .SRMODE("LSR_OVER_CE"))  _TECHMAP_REPLACE_ (.CLK(C), .LSR(R), .DI(D), .Q(Q)); endmodule
+module  \$__DFFS_NN1_ (input D, C, R, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("1"), .CLKMUX("INV"), .LSRMUX("INV"), .REGSET("SET"), .SRMODE("LSR_OVER_CE"))  _TECHMAP_REPLACE_ (.CLK(C), .LSR(R), .DI(D), .Q(Q)); endmodule
+module  \$__DFFS_PN0_ (input D, C, R, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("1"), .CLKMUX("CLK"), .LSRMUX("INV"), .REGSET("RESET"), .SRMODE("LSR_OVER_CE"))  _TECHMAP_REPLACE_ (.CLK(C), .LSR(R), .DI(D), .Q(Q)); endmodule
+module  \$__DFFS_PN1_ (input D, C, R, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("1"), .CLKMUX("CLK"), .LSRMUX("INV"), .REGSET("SET"), .SRMODE("LSR_OVER_CE"))  _TECHMAP_REPLACE_ (.CLK(C), .LSR(R), .DI(D), .Q(Q)); endmodule
+
+module  \$__DFFS_NP0_ (input D, C, R, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("1"), .CLKMUX("INV"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("LSR_OVER_CE"))  _TECHMAP_REPLACE_ (.CLK(C), .LSR(R), .DI(D), .Q(Q)); endmodule
+module  \$__DFFS_NP1_ (input D, C, R, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("1"), .CLKMUX("INV"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("LSR_OVER_CE"))  _TECHMAP_REPLACE_ (.CLK(C), .LSR(R), .DI(D), .Q(Q)); endmodule
+module  \$__DFFS_PP0_ (input D, C, R, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("1"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("LSR_OVER_CE"))  _TECHMAP_REPLACE_ (.CLK(C), .LSR(R), .DI(D), .Q(Q)); endmodule
+module  \$__DFFS_PP1_ (input D, C, R, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("1"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("LSR_OVER_CE"))  _TECHMAP_REPLACE_ (.CLK(C), .LSR(R), .DI(D), .Q(Q)); endmodule
+
+module  \$__DFFE_NN0 (input D, C, E, R, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("CE"), .CLKMUX("INV"), .LSRMUX("INV"), .REGSET("RESET"), .SRMODE("ASYNC"))  _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(R), .DI(D), .Q(Q)); endmodule
+module  \$__DFFE_NN1 (input D, C, E, R, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("CE"), .CLKMUX("INV"), .LSRMUX("INV"), .REGSET("SET"), .SRMODE("ASYNC"))  _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(R), .DI(D), .Q(Q)); endmodule
+module  \$__DFFE_PN0 (input D, C, E, R, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("INV"), .REGSET("RESET"), .SRMODE("ASYNC"))  _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(R), .DI(D), .Q(Q)); endmodule
+module  \$__DFFE_PN1 (input D, C, E, R, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("INV"), .REGSET("SET"), .SRMODE("ASYNC"))  _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(R), .DI(D), .Q(Q)); endmodule
+
+module  \$__DFFE_NP0 (input D, C, E, R, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("CE"), .CLKMUX("INV"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("ASYNC"))  _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(R), .DI(D), .Q(Q)); endmodule
+module  \$__DFFE_NP1 (input D, C, E, R, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("CE"), .CLKMUX("INV"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("ASYNC"))  _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(R), .DI(D), .Q(Q)); endmodule
+module  \$__DFFE_PP0 (input D, C, E, R, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("ASYNC"))  _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(R), .DI(D), .Q(Q)); endmodule
+module  \$__DFFE_PP1 (input D, C, E, R, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("ASYNC"))  _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(R), .DI(D), .Q(Q)); endmodule
+
+module  \$__DFFSE_NN0 (input D, C, E, R, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("CE"), .CLKMUX("INV"), .LSRMUX("INV"), .REGSET("RESET"), .SRMODE("LSR_OVER_CE"))  _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(R), .DI(D), .Q(Q)); endmodule
+module  \$__DFFSE_NN1 (input D, C, E, R, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("CE"), .CLKMUX("INV"), .LSRMUX("INV"), .REGSET("SET"), .SRMODE("LSR_OVER_CE"))  _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(R), .DI(D), .Q(Q)); endmodule
+module  \$__DFFSE_PN0 (input D, C, E, R, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("INV"), .REGSET("RESET"), .SRMODE("LSR_OVER_CE"))  _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(R), .DI(D), .Q(Q)); endmodule
+module  \$__DFFSE_PN1 (input D, C, E, R, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("INV"), .REGSET("SET"), .SRMODE("LSR_OVER_CE"))  _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(R), .DI(D), .Q(Q)); endmodule
+
+module  \$__DFFSE_NP0 (input D, C, E, R, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("CE"), .CLKMUX("INV"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("LSR_OVER_CE"))  _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(R), .DI(D), .Q(Q)); endmodule
+module  \$__DFFSE_NP1 (input D, C, E, R, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("CE"), .CLKMUX("INV"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("LSR_OVER_CE"))  _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(R), .DI(D), .Q(Q)); endmodule
+module  \$__DFFSE_PP0 (input D, C, E, R, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("LSR_OVER_CE"))  _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(R), .DI(D), .Q(Q)); endmodule
+module  \$__DFFSE_PP1 (input D, C, E, R, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("LSR_OVER_CE"))  _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(R), .DI(D), .Q(Q)); endmodule
 
 `ifndef NO_LUT
 module \$lut (A, Y);
diff --git a/techlibs/ecp5/synth_ecp5.cc b/techlibs/ecp5/synth_ecp5.cc
index 86d2027de..b54bf4204 100644
--- a/techlibs/ecp5/synth_ecp5.cc
+++ b/techlibs/ecp5/synth_ecp5.cc
@@ -247,15 +247,16 @@ struct SynthEcp5Pass : public ScriptPass
 		if (check_label("map_ffs"))
 		{
 			run("dffsr2dff");
+			run("dff2dffs");
+			run("opt_clean");
 			if (!nodffe)
-				run("dff2dffe -direct-match $_DFF_*");
+				run("dff2dffe -direct-match $_DFF_* -direct-match $__DFFS_*");
 			run("techmap -D NO_LUT -map +/ecp5/cells_map.v");
 			run("opt_expr -mux_undef");
 			run("simplemap");
 			// TODO
 #if 0
 			run("ecp5_ffinit");
-			run("ecp5_ffssr");
 #endif
 		}
 
-- 
cgit v1.2.3


From b2c62ff8efb9650ac3eefab4e7756b7ba303962e Mon Sep 17 00:00:00 2001
From: David Shah <davey1576@gmail.com>
Date: Mon, 16 Jul 2018 14:33:13 +0200
Subject: ecp5: ECP5 synthesis fixes

Signed-off-by: David Shah <davey1576@gmail.com>
---
 techlibs/ecp5/arith_map.v   |  4 ++--
 techlibs/ecp5/cells_sim.v   | 39 ++++++++++++++++++++++++++-------------
 techlibs/ecp5/synth_ecp5.cc |  4 ++++
 3 files changed, 32 insertions(+), 15 deletions(-)

(limited to 'techlibs/ecp5')

diff --git a/techlibs/ecp5/arith_map.v b/techlibs/ecp5/arith_map.v
index 05d44b9b4..1094c5f8a 100644
--- a/techlibs/ecp5/arith_map.v
+++ b/techlibs/ecp5/arith_map.v
@@ -42,7 +42,7 @@ module _80_ecp5_alu (A, B, CI, BI, X, Y, CO);
 	function integer round_up2;
 		input integer N;
 		begin
-			round_up2 = ((N / 2) + 1) * 2;
+			round_up2 = ((N + 1) / 2) * 2;
 		end
 	endfunction
 
@@ -69,7 +69,7 @@ module _80_ecp5_alu (A, B, CI, BI, X, Y, CO);
 		);
 
 		assign CO[i] = (AA[i] && BB[i]) || (C[i] && (AA[i] || BB[i]));
-		if (i < Y_WIDTH) begin
+		if (i+1 < Y_WIDTH) begin
 			assign CO[i+1] = FCO[i];
 			assign Y[i+1] = Y1[i];
 		end
diff --git a/techlibs/ecp5/cells_sim.v b/techlibs/ecp5/cells_sim.v
index 6c53a78eb..1755da24b 100644
--- a/techlibs/ecp5/cells_sim.v
+++ b/techlibs/ecp5/cells_sim.v
@@ -67,10 +67,15 @@ module TRELLIS_RAM16X2 (
 
 	wire muxwck = (WCKMUX == "INV") ? ~WCK : WCK;
 
-	wire muxwre = (WREMUX == "1") ? 1'b1 :
-							  (WREMUX == "0") ? 1'b0 :
-							  (WREMUX == "INV") ? ~WRE :
-							  WRE;
+	reg muxwre;
+	always @(*)
+		case (WREMUX)
+			"1": muxwre = 1'b1;
+			"0": muxwre = 1'b0;
+			"INV": muxwre = ~WRE;
+			default: muxwre = WRE;
+		endcase
+
 
 	always @(posedge muxwck)
 		if (muxwre)
@@ -108,10 +113,14 @@ module TRELLIS_DPR16X4 (
 
 	wire muxwck = (WCKMUX == "INV") ? ~WCK : WCK;
 
-	wire muxwre = (WREMUX == "1") ? 1'b1 :
-							  (WREMUX == "0") ? 1'b0 :
-							  (WREMUX == "INV") ? ~WRE :
-							  WRE;
+	reg muxwre;
+	always @(*)
+		case (WREMUX)
+			"1": muxwre = 1'b1;
+			"0": muxwre = 1'b0;
+			"INV": muxwre = ~WRE;
+			default: muxwre = WRE;
+		endcase
 
 	always @(posedge muxwck)
 		if (muxwre)
@@ -167,7 +176,7 @@ module DPR16X4C (
 	integer i;
 	initial begin
 		for (i = 0; i < 15; i = i + 1) begin
-			ram[i] = conv_initval[4*i +: 4];
+			ram[i] <= conv_initval[4*i +: 4];
 		end
 	end
 
@@ -189,10 +198,14 @@ module TRELLIS_FF(input CLK, LSR, CE, DI, output reg Q);
 	parameter SRMODE = "LSR_OVER_CE";
 	parameter REGSET = "RESET";
 
-	wire muxce = (CEMUX == "1") ? 1'b1 :
-	             (CEMUX == "0") ? 1'b0 :
-							 (CEMUX == "INV") ? ~CE :
-							 CE;
+	reg muxce;
+	always @(*)
+		case (CEMUX)
+			"1": muxce = 1'b1;
+			"0": muxce = 1'b0;
+			"INV": muxce = ~CE;
+			default: muxce = CE;
+		endcase
 
 	wire muxlsr = (LSRMUX == "INV") ? ~LSR : LSR;
 	wire muxclk = (CLKMUX == "INV") ? ~CLK : CLK;
diff --git a/techlibs/ecp5/synth_ecp5.cc b/techlibs/ecp5/synth_ecp5.cc
index b54bf4204..76051d1a2 100644
--- a/techlibs/ecp5/synth_ecp5.cc
+++ b/techlibs/ecp5/synth_ecp5.cc
@@ -172,6 +172,10 @@ struct SynthEcp5Pass : public ScriptPass
 				nodram = true;
 				continue;
 			}
+			if (args[argidx] == "-nomux") {
+				nomux = true;
+				continue;
+			}
 			if (args[argidx] == "-abc2") {
 				abc2 = true;
 				continue;
-- 
cgit v1.2.3


From e9ef077266652b4a76773287199a0b7f18b94a3d Mon Sep 17 00:00:00 2001
From: David Shah <davey1576@gmail.com>
Date: Mon, 16 Jul 2018 15:20:34 +0200
Subject: ecp5: Fixing 'X' issues with LUT simulation models

Signed-off-by: David Shah <davey1576@gmail.com>
---
 techlibs/ecp5/cells_sim.v | 25 +++++++++++++++++++------
 1 file changed, 19 insertions(+), 6 deletions(-)

(limited to 'techlibs/ecp5')

diff --git a/techlibs/ecp5/cells_sim.v b/techlibs/ecp5/cells_sim.v
index 1755da24b..cf1446a52 100644
--- a/techlibs/ecp5/cells_sim.v
+++ b/techlibs/ecp5/cells_sim.v
@@ -1,8 +1,11 @@
 // ---------------------------------------
 
 module LUT4(input A, B, C, D, output Z);
-	parameter [15:0] INIT = 16'h0000;
-	assign Z = INIT[{D, C, B, A}];
+    parameter [15:0] INIT = 16'h0000;
+    wire [7:0] s3 = D ?     INIT[15:8] :     INIT[7:0];
+    wire [3:0] s2 = C ?       s3[ 7:4] :       s3[3:0];
+    wire [1:0] s1 = B ?       s2[ 3:2] :       s2[1:0];
+    assign Z =      A ?          s1[1] :         s1[0];
 endmodule
 
 // ---------------------------------------
@@ -22,8 +25,9 @@ module CCU2C(input CIN, A0, B0, C0, D0, A1, B1, C1, D1,
 	parameter INJECT1_1 = "YES";
 
 	// First half
-	wire LUT4_0 = INIT0[{D0, C0, B0, A0}];
-	wire LUT2_0 = INIT0[{2'b00, B0, A0}];
+	wire LUT4_0, LUT2_0;
+	LUT4 #(.INIT(INIT0)) lut4_0(.A(A0), .B(B0), .C(C0), .D(D0), .Z(LUT4_0));
+	LUT2 #(.INIT(INIT0[3:0])) lut2_0(.A(A0), .B(B0), .Z(LUT2_0));
 
 	wire gated_cin_0 = (INJECT1_0 == "YES") ? 1'b0 : CIN;
 	assign S0 = LUT4_0 ^ gated_cin_0;
@@ -32,8 +36,9 @@ module CCU2C(input CIN, A0, B0, C0, D0, A1, B1, C1, D1,
 	wire cout_0 = (~LUT4_0 & gated_lut2_0) | (LUT4_0 & CIN);
 
 	// Second half
-	wire LUT4_1 = INIT1[{D1, C1, B1, A1}];
-	wire LUT2_1 = INIT1[{2'b00, B1, A1}];
+	wire LUT4_1, LUT2_1;
+	LUT4 #(.INIT(INIT1)) lut4_1(.A(A1), .B(B1), .C(C1), .D(D1), .Z(LUT4_1));
+	LUT2 #(.INIT(INIT1[3:0])) lut2_1(.A(A1), .B(B1), .Z(LUT2_1));
 
 	wire gated_cin_1 = (INJECT1_1 == "YES") ? 1'b0 : cout_0;
 	assign S1 = LUT4_1 ^ gated_cin_1;
@@ -190,6 +195,14 @@ endmodule
 
 // ---------------------------------------
 
+module LUT2(input A, B, output Z);
+    parameter [3:0] INIT = 4'h0;
+    wire [1:0] s1 = B ?     INIT[ 3:2] :     INIT[1:0];
+    assign Z =      A ?          s1[1] :         s1[0];
+endmodule
+
+// ---------------------------------------
+
 module TRELLIS_FF(input CLK, LSR, CE, DI, output reg Q);
 	parameter GSR = "ENABLED";
 	parameter [127:0] CEMUX = "1";
-- 
cgit v1.2.3


From 3a3558acce25807d6ce75280cc3f43aeb52974df Mon Sep 17 00:00:00 2001
From: David Shah <davey1576@gmail.com>
Date: Mon, 16 Jul 2018 15:56:12 +0200
Subject: ecp5: Fixing miscellaneous sim model issues

Signed-off-by: David Shah <davey1576@gmail.com>
---
 techlibs/ecp5/cells_sim.v | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

(limited to 'techlibs/ecp5')

diff --git a/techlibs/ecp5/cells_sim.v b/techlibs/ecp5/cells_sim.v
index cf1446a52..1700694e8 100644
--- a/techlibs/ecp5/cells_sim.v
+++ b/techlibs/ecp5/cells_sim.v
@@ -232,13 +232,13 @@ module TRELLIS_FF(input CLK, LSR, CE, DI, output reg Q);
 			always @(posedge muxclk, posedge muxlsr)
 				if (muxlsr)
 					Q <= srval;
-				else
+				else if (muxce)
 					Q <= DI;
 		end else begin
 			always @(posedge muxclk)
 				if (muxlsr)
 					Q <= srval;
-				else
+				else if (muxce)
 					Q <= DI;
 		end
 	endgenerate
-- 
cgit v1.2.3


From 3aa4484a3cd9a2e82fddd499cde575eaf8c565cc Mon Sep 17 00:00:00 2001
From: Henner Zeller <h.zeller@acm.org>
Date: Fri, 20 Jul 2018 23:41:18 -0700
Subject: Consistent use of 'override' for virtual methods in derived classes.

o Not all derived methods were marked 'override', but it is a great
  feature of C++11 that we should make use of.
o While at it: touched header files got a -*- c++ -*- for emacs to
  provide support for that language.
o use YS_OVERRIDE for all override keywords (though we should probably
  use the plain keyword going forward now that C++11 is established)
---
 techlibs/ecp5/synth_ecp5.cc | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

(limited to 'techlibs/ecp5')

diff --git a/techlibs/ecp5/synth_ecp5.cc b/techlibs/ecp5/synth_ecp5.cc
index 76051d1a2..a13dd8d41 100644
--- a/techlibs/ecp5/synth_ecp5.cc
+++ b/techlibs/ecp5/synth_ecp5.cc
@@ -30,7 +30,7 @@ struct SynthEcp5Pass : public ScriptPass
 {
 	SynthEcp5Pass() : ScriptPass("synth_ecp5", "synthesis for ECP5 FPGAs") { }
 
-	virtual void help() YS_OVERRIDE
+	void help() YS_OVERRIDE
 	{
 		//   |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
 		log("\n");
@@ -95,7 +95,7 @@ struct SynthEcp5Pass : public ScriptPass
 	string top_opt, blif_file, edif_file, json_file;
 	bool noccu2, nodffe, nobram, nodram, nomux, flatten, retime, abc2, vpr;
 
-	virtual void clear_flags() YS_OVERRIDE
+	void clear_flags() YS_OVERRIDE
 	{
 		top_opt = "-auto-top";
 		blif_file = "";
@@ -112,7 +112,7 @@ struct SynthEcp5Pass : public ScriptPass
 		vpr = false;
 	}
 
-	virtual void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
+	void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
 	{
 		string run_from, run_to;
 		clear_flags();
@@ -199,7 +199,7 @@ struct SynthEcp5Pass : public ScriptPass
 		log_pop();
 	}
 
-	virtual void script() YS_OVERRIDE
+	void script() YS_OVERRIDE
 	{
 		if (check_label("begin"))
 		{
-- 
cgit v1.2.3


From fcd39e1398b950aa19c5fec157770bd7c3fa2227 Mon Sep 17 00:00:00 2001
From: David Shah <davey1576@gmail.com>
Date: Mon, 1 Oct 2018 18:34:41 +0100
Subject: ecp5: Don't map ROMs to DRAM

Signed-off-by: David Shah <davey1576@gmail.com>
---
 techlibs/ecp5/dram.txt | 1 +
 1 file changed, 1 insertion(+)

(limited to 'techlibs/ecp5')

diff --git a/techlibs/ecp5/dram.txt b/techlibs/ecp5/dram.txt
index b3252fa9a..b94357429 100644
--- a/techlibs/ecp5/dram.txt
+++ b/techlibs/ecp5/dram.txt
@@ -13,4 +13,5 @@ endbram
 
 match $__TRELLIS_DPR16X4
   make_outreg
+  min wports 1
 endmatch
-- 
cgit v1.2.3


From 31e22c8b96eea5e833d32dea7d72dfe1556bf7e0 Mon Sep 17 00:00:00 2001
From: David Shah <dave@ds0.me>
Date: Fri, 5 Oct 2018 11:35:59 +0100
Subject: ecp5: Add blackbox for DP16KD

Signed-off-by: David Shah <dave@ds0.me>
---
 techlibs/ecp5/cells_sim.v | 93 +++++++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 93 insertions(+)

(limited to 'techlibs/ecp5')

diff --git a/techlibs/ecp5/cells_sim.v b/techlibs/ecp5/cells_sim.v
index 1700694e8..c89fde1b1 100644
--- a/techlibs/ecp5/cells_sim.v
+++ b/techlibs/ecp5/cells_sim.v
@@ -446,3 +446,96 @@ module TRELLIS_SLICE(
 	);
 endmodule
 
+(* blackbox *)
+module DP16KD(
+  input DIA17, DIA16, DIA15, DIA14, DIA13, DIA12, DIA11, DIA10, DIA9, DIA8, DIA7, DIA6, DIA5, DIA4, DIA3, DIA2, DIA1, DIA0,
+  input ADA13, ADA12, ADA11, ADA10, ADA9, ADA8, ADA7, ADA6, ADA5, ADA4, ADA3, ADA2, ADA1, ADA0,
+  input CEA, OCEA, CLKA, WEA, RSTA,
+  input CSA2, CSA1, CSA0,
+  output DOA17, DOA16, DOA15, DOA14, DOA13, DOA12, DOA11, DOA10, DOA9, DOA8, DOA7, DOA6, DOA5, DOA4, DOA3, DOA2, DOA1, DOA0,
+
+  input DIB17, DIB16, DIB15, DIB14, DIB13, DIB12, DIB11, DIB10, DIB9, DIB8, DIB7, DIB6, DIB5, DIB4, DIB3, DIB2, DIB1, DIB0,
+  input ADB13, ADB12, ADB11, ADB10, ADB9, ADB8, ADB7, ADB6, ADB5, ADB4, ADB3, ADB2, ADB1, ADB0,
+  input CEB, OCEB, CLKB, WEB, RSTB,
+  input CSB2, CSB1, CSB0,
+  output DOB17, DOB16, DOB15, DOB14, DOB13, DOB12, DOB11, DOB10, DOB9, DOB8, DOB7, DOB6, DOB5, DOB4, DOB3, DOB2, DOB1, DOB0
+);
+  parameter DATA_WIDTH_A = 18;
+  parameter DATA_WIDTH_B = 18;
+
+  parameter REGMODE_A = "NOREG";
+  parameter REGMODE_B = "NOREG";
+
+  parameter RESETMODE = "SYNC";
+  parameter ASYNC_RESET_RELEASE = "SYNC";
+
+  parameter CSDECODE_A = "0b000";
+  parameter CSDECODE_B = "0b000";
+
+  parameter GSR = "ENABLED";
+
+  parameter INITVAL_00 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
+  parameter INITVAL_01 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
+  parameter INITVAL_02 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
+  parameter INITVAL_03 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
+  parameter INITVAL_04 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
+  parameter INITVAL_05 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
+  parameter INITVAL_06 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
+  parameter INITVAL_07 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
+  parameter INITVAL_08 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
+  parameter INITVAL_09 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
+  parameter INITVAL_0A = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
+  parameter INITVAL_0B = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
+  parameter INITVAL_0C = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
+  parameter INITVAL_0D = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
+  parameter INITVAL_0E = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
+  parameter INITVAL_0F = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
+  parameter INITVAL_10 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
+  parameter INITVAL_11 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
+  parameter INITVAL_12 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
+  parameter INITVAL_13 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
+  parameter INITVAL_14 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
+  parameter INITVAL_15 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
+  parameter INITVAL_16 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
+  parameter INITVAL_17 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
+  parameter INITVAL_18 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
+  parameter INITVAL_19 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
+  parameter INITVAL_1A = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
+  parameter INITVAL_1B = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
+  parameter INITVAL_1C = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
+  parameter INITVAL_1D = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
+  parameter INITVAL_1E = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
+  parameter INITVAL_1F = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
+  parameter INITVAL_20 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
+  parameter INITVAL_21 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
+  parameter INITVAL_22 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
+  parameter INITVAL_23 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
+  parameter INITVAL_24 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
+  parameter INITVAL_25 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
+  parameter INITVAL_26 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
+  parameter INITVAL_27 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
+  parameter INITVAL_28 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
+  parameter INITVAL_29 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
+  parameter INITVAL_2A = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
+  parameter INITVAL_2B = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
+  parameter INITVAL_2C = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
+  parameter INITVAL_2D = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
+  parameter INITVAL_2E = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
+  parameter INITVAL_2F = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
+  parameter INITVAL_30 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
+  parameter INITVAL_31 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
+  parameter INITVAL_32 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
+  parameter INITVAL_33 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
+  parameter INITVAL_34 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
+  parameter INITVAL_35 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
+  parameter INITVAL_36 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
+  parameter INITVAL_37 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
+  parameter INITVAL_38 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
+  parameter INITVAL_39 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
+  parameter INITVAL_3A = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
+  parameter INITVAL_3B = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
+  parameter INITVAL_3C = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
+  parameter INITVAL_3D = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
+  parameter INITVAL_3E = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
+  parameter INITVAL_3F = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
+endmodule
-- 
cgit v1.2.3


From 346cbbdbdc0dbe291bfa96b8b1e6300c911c6e89 Mon Sep 17 00:00:00 2001
From: David Shah <dave@ds0.me>
Date: Tue, 9 Oct 2018 14:19:04 +0100
Subject: ecp5: Adding BRAM initialisation and config

Signed-off-by: David Shah <dave@ds0.me>
---
 techlibs/ecp5/.gitignore    |  3 +++
 techlibs/ecp5/Makefile.inc  | 15 +++++++++++++++
 techlibs/ecp5/bram.txt      | 29 +++++++++++++++++++++++++++++
 techlibs/ecp5/brams_init.py | 22 ++++++++++++++++++++++
 techlibs/ecp5/cells_sim.v   |  4 ++++
 5 files changed, 73 insertions(+)
 create mode 100644 techlibs/ecp5/.gitignore
 create mode 100644 techlibs/ecp5/bram.txt
 create mode 100755 techlibs/ecp5/brams_init.py

(limited to 'techlibs/ecp5')

diff --git a/techlibs/ecp5/.gitignore b/techlibs/ecp5/.gitignore
new file mode 100644
index 000000000..84d260810
--- /dev/null
+++ b/techlibs/ecp5/.gitignore
@@ -0,0 +1,3 @@
+bram_init_1_2_4.vh
+bram_init_9_18_36.vh
+brams_init.mk
diff --git a/techlibs/ecp5/Makefile.inc b/techlibs/ecp5/Makefile.inc
index 9d3247347..95d40fccf 100644
--- a/techlibs/ecp5/Makefile.inc
+++ b/techlibs/ecp5/Makefile.inc
@@ -5,4 +5,19 @@ $(eval $(call add_share_file,share/ecp5,techlibs/ecp5/cells_map.v))
 $(eval $(call add_share_file,share/ecp5,techlibs/ecp5/cells_sim.v))
 $(eval $(call add_share_file,share/ecp5,techlibs/ecp5/drams_map.v))
 $(eval $(call add_share_file,share/ecp5,techlibs/ecp5/dram.txt))
+$(eval $(call add_share_file,share/ecp5,techlibs/ecp5/bram.txt))
 $(eval $(call add_share_file,share/ecp5,techlibs/ecp5/arith_map.v))
+
+EXTRA_OBJS += techlibs/ecp5/brams_init.mk
+.SECONDARY: techlibs/ecp5/brams_init.mk
+
+techlibs/ecp5/brams_init.mk: techlibs/ecp5/brams_init.py
+	$(Q) mkdir -p techlibs/ecp5
+	$(P) python3 $<
+	$(Q) touch $@
+
+techlibs/ecp5/bram_init_1_2_4.vh: techlibs/ecp5/brams_init.mk
+techlibs/ecp5/bram_init_9_18_36.vh: techlibs/ecp5/brams_init.mk
+
+$(eval $(call add_share_file,share/ecp5,techlibs/ecp5/bram_init_1_2_4.vh))
+$(eval $(call add_share_file,share/ecp5,techlibs/ecp5/bram_init_9_18_36.vh))
diff --git a/techlibs/ecp5/bram.txt b/techlibs/ecp5/bram.txt
new file mode 100644
index 000000000..9d22e4afe
--- /dev/null
+++ b/techlibs/ecp5/bram.txt
@@ -0,0 +1,29 @@
+bram $__ECP5_DP16KD
+  init 1
+
+  abits 10 @a10d18
+  dbits 18 @a10d18
+  abits 11 @a11d9
+  dbits 9  @a11d9
+  abits 12 @a12d4
+  dbits 4  @a12d4
+  abits 13 @a13d2
+  dbits 2  @a13d2
+  abits 14 @a14d1
+  dbits 1  @a14d1
+
+  groups 2
+  ports 1 1
+  wrmode 1 0
+  enable 2 1 @a10d18
+  enable 1 1 @a11d9 @a12d4 @a13d2 @a14d1
+  transp 0 2
+  clocks 1 2
+  clkpol 2 2
+endbram
+
+match $__ECP5_DP16KD
+  min bits 2048
+  min efficiency 5
+  shuffle_enable B
+endmatch
diff --git a/techlibs/ecp5/brams_init.py b/techlibs/ecp5/brams_init.py
new file mode 100755
index 000000000..6f650b2a9
--- /dev/null
+++ b/techlibs/ecp5/brams_init.py
@@ -0,0 +1,22 @@
+#!/usr/bin/env python3
+with open("techlibs/ecp5/bram_init_1_2_4.vh", "w") as f:
+    for i in range(0, 0x40):
+        init_snippets = []
+        for j in range(32):
+            init_snippets.append("INIT[%4d*8 +: 8]" % (32 * i + j))
+            init_snippets.append("3'b000" if (j % 2 == 1) else "1'b0")
+        init_snippets = list(reversed(init_snippets))
+        for k in range(8, 64, 8):
+            init_snippets[k] = "\n          " + init_snippets[k]
+        print(".INIT_%02X({%s})," % (i, ", ".join(init_snippets)), file=f)
+
+with open("techlibs/ecp5/bram_init_9_18_36.vh", "w") as f:
+    for i in range(0, 0x40):
+        init_snippets = []
+        for j in range(16):
+            init_snippets.append("INIT[%3d*18 +: 18]" % (16 * i + j))
+            init_snippets.append("2'b00")
+        init_snippets = list(reversed(init_snippets))
+        for k in range(8, 32, 8):
+            init_snippets[k] = "\n          " + init_snippets[k]
+        print(".INIT_%02X({%s})," % (i, ", ".join(init_snippets)), file=f)
diff --git a/techlibs/ecp5/cells_sim.v b/techlibs/ecp5/cells_sim.v
index c89fde1b1..3e7e83aac 100644
--- a/techlibs/ecp5/cells_sim.v
+++ b/techlibs/ecp5/cells_sim.v
@@ -472,6 +472,10 @@ module DP16KD(
   parameter CSDECODE_A = "0b000";
   parameter CSDECODE_B = "0b000";
 
+  parameter WRITEMODE_A = "NORMAL";
+  parameter WRITEMODE_B = "NORMAL";
+
+
   parameter GSR = "ENABLED";
 
   parameter INITVAL_00 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
-- 
cgit v1.2.3


From 2ef1af8b58c845f4ca070a0469fe42212bcb5eee Mon Sep 17 00:00:00 2001
From: David Shah <dave@ds0.me>
Date: Wed, 10 Oct 2018 16:11:00 +0100
Subject: ecp5: Script for BRAM IO connections

Signed-off-by: David Shah <dave@ds0.me>
---
 techlibs/ecp5/.gitignore       |   5 ++
 techlibs/ecp5/bram_map.v       |   0
 techlibs/ecp5/brams_connect.py |  46 +++++++++++++++
 techlibs/ecp5/cells_sim.v      | 128 ++++++++++++++++++++---------------------
 4 files changed, 115 insertions(+), 64 deletions(-)
 create mode 100644 techlibs/ecp5/bram_map.v
 create mode 100755 techlibs/ecp5/brams_connect.py

(limited to 'techlibs/ecp5')

diff --git a/techlibs/ecp5/.gitignore b/techlibs/ecp5/.gitignore
index 84d260810..3f66045f8 100644
--- a/techlibs/ecp5/.gitignore
+++ b/techlibs/ecp5/.gitignore
@@ -1,3 +1,8 @@
 bram_init_1_2_4.vh
 bram_init_9_18_36.vh
 brams_init.mk
+bram_conn_1.vh
+bram_conn_2.vh
+bram_conn_4.vh
+bram_conn_9.vh
+bram_conn_18.vh
diff --git a/techlibs/ecp5/bram_map.v b/techlibs/ecp5/bram_map.v
new file mode 100644
index 000000000..e69de29bb
diff --git a/techlibs/ecp5/brams_connect.py b/techlibs/ecp5/brams_connect.py
new file mode 100755
index 000000000..f86dcfcf0
--- /dev/null
+++ b/techlibs/ecp5/brams_connect.py
@@ -0,0 +1,46 @@
+#!/usr/bin/env python3
+
+def write_bus_ports(f, ada_bits, adb_bits, dia_bits, dob_bits):
+    ada_conn = [".ADA%d(%s)" % (i, ada_bits[i]) for i in range(len(ada_bits))]
+    adb_conn = [".ADB%d(%s)" % (i, adb_bits[i]) for i in range(len(adb_bits))]
+    dia_conn = [".DIA%d(%s)" % (i, dia_bits[i]) for i in range(len(dia_bits))]
+    dob_conn = [".DOB%d(%s)" % (i, dob_bits[i]) for i in range(len(dob_bits))]
+    print("    %s," % ", ".join(ada_conn), file=f)
+    print("    %s," % ", ".join(adb_conn), file=f)
+    print("    %s," % ", ".join(dia_conn), file=f)
+    print("    %s," % ", ".join(dob_conn), file=f)
+
+with open("techlibs/ecp5/bram_conn_1.vh", "w") as f:
+    ada_bits = ["A1ADDR[%d]" % i for i in range(14)]
+    adb_bits = ["B1ADDR[%d]" % i for i in range(14)]
+    dia_bits = ["A1DATA[0]"] + ["1'b0" for i in range(17)]
+    dob_bits = ["B1DATA[0]"]
+    write_bus_ports(f, ada_bits, adb_bits, dia_bits, dob_bits)
+
+with open("techlibs/ecp5/bram_conn_2.vh", "w") as f:
+    ada_bits = ["1'b0"] + ["A1ADDR[%d]" % i for i in range(13)]
+    adb_bits = ["1'b0"] + ["B1ADDR[%d]" % i for i in range(13)]
+    dia_bits = ["A1DATA[%d]" % i for i in range(2)] + ["1'b0" for i in range(16)]
+    dob_bits = ["B1DATA[%d]" % i for i in range(2)]
+    write_bus_ports(f, ada_bits, adb_bits, dia_bits, dob_bits)
+
+with open("techlibs/ecp5/bram_conn_4.vh", "w") as f:
+    ada_bits = ["1'b0", "1'b0"] + ["A1ADDR[%d]" % i for i in range(12)]
+    adb_bits = ["1'b0", "1'b0"] + ["B1ADDR[%d]" % i for i in range(12)]
+    dia_bits = ["A1DATA[%d]" % i for i in range(4)] + ["1'b0" for i in range(14)]
+    dob_bits = ["B1DATA[%d]" % i for i in range(4)]
+    write_bus_ports(f, ada_bits, adb_bits, dia_bits, dob_bits)
+
+with open("techlibs/ecp5/bram_conn_9.vh", "w") as f:
+    ada_bits = ["1'b0", "1'b0", "1'b0"] + ["A1ADDR[%d]" % i for i in range(11)]
+    adb_bits = ["1'b0", "1'b0", "1'b0"] + ["B1ADDR[%d]" % i for i in range(11)]
+    dia_bits = ["A1DATA[%d]" % i for i in range(9)] + ["1'b0" for i in range(9)]
+    dob_bits = ["B1DATA[%d]" % i for i in range(9)]
+    write_bus_ports(f, ada_bits, adb_bits, dia_bits, dob_bits)
+
+with open("techlibs/ecp5/bram_conn_18.vh", "w") as f:
+    ada_bits = ["A1EN[0]", "A1EN[1]", "1'b0", "1'b0"] + ["A1ADDR[%d]" % i for i in range(10)]
+    adb_bits = ["1'b0", "1'b0", "1'b0", "1'b0"] + ["B1ADDR[%d]" % i for i in range(10)]
+    dia_bits = ["A1DATA[%d]" % i for i in range(18)]
+    dob_bits = ["B1DATA[%d]" % i for i in range(18)]
+    write_bus_ports(f, ada_bits, adb_bits, dia_bits, dob_bits)
diff --git a/techlibs/ecp5/cells_sim.v b/techlibs/ecp5/cells_sim.v
index 3e7e83aac..4732381ca 100644
--- a/techlibs/ecp5/cells_sim.v
+++ b/techlibs/ecp5/cells_sim.v
@@ -478,68 +478,68 @@ module DP16KD(
 
   parameter GSR = "ENABLED";
 
-  parameter INITVAL_00 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
-  parameter INITVAL_01 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
-  parameter INITVAL_02 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
-  parameter INITVAL_03 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
-  parameter INITVAL_04 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
-  parameter INITVAL_05 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
-  parameter INITVAL_06 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
-  parameter INITVAL_07 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
-  parameter INITVAL_08 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
-  parameter INITVAL_09 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
-  parameter INITVAL_0A = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
-  parameter INITVAL_0B = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
-  parameter INITVAL_0C = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
-  parameter INITVAL_0D = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
-  parameter INITVAL_0E = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
-  parameter INITVAL_0F = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
-  parameter INITVAL_10 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
-  parameter INITVAL_11 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
-  parameter INITVAL_12 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
-  parameter INITVAL_13 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
-  parameter INITVAL_14 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
-  parameter INITVAL_15 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
-  parameter INITVAL_16 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
-  parameter INITVAL_17 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
-  parameter INITVAL_18 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
-  parameter INITVAL_19 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
-  parameter INITVAL_1A = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
-  parameter INITVAL_1B = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
-  parameter INITVAL_1C = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
-  parameter INITVAL_1D = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
-  parameter INITVAL_1E = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
-  parameter INITVAL_1F = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
-  parameter INITVAL_20 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
-  parameter INITVAL_21 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
-  parameter INITVAL_22 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
-  parameter INITVAL_23 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
-  parameter INITVAL_24 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
-  parameter INITVAL_25 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
-  parameter INITVAL_26 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
-  parameter INITVAL_27 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
-  parameter INITVAL_28 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
-  parameter INITVAL_29 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
-  parameter INITVAL_2A = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
-  parameter INITVAL_2B = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
-  parameter INITVAL_2C = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
-  parameter INITVAL_2D = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
-  parameter INITVAL_2E = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
-  parameter INITVAL_2F = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
-  parameter INITVAL_30 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
-  parameter INITVAL_31 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
-  parameter INITVAL_32 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
-  parameter INITVAL_33 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
-  parameter INITVAL_34 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
-  parameter INITVAL_35 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
-  parameter INITVAL_36 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
-  parameter INITVAL_37 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
-  parameter INITVAL_38 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
-  parameter INITVAL_39 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
-  parameter INITVAL_3A = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
-  parameter INITVAL_3B = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
-  parameter INITVAL_3C = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
-  parameter INITVAL_3D = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
-  parameter INITVAL_3E = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
-  parameter INITVAL_3F = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
+  parameter INITVAL_00 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+  parameter INITVAL_01 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+  parameter INITVAL_02 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+  parameter INITVAL_03 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+  parameter INITVAL_04 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+  parameter INITVAL_05 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+  parameter INITVAL_06 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+  parameter INITVAL_07 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+  parameter INITVAL_08 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+  parameter INITVAL_09 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+  parameter INITVAL_0A = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+  parameter INITVAL_0B = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+  parameter INITVAL_0C = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+  parameter INITVAL_0D = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+  parameter INITVAL_0E = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+  parameter INITVAL_0F = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+  parameter INITVAL_10 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+  parameter INITVAL_11 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+  parameter INITVAL_12 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+  parameter INITVAL_13 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+  parameter INITVAL_14 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+  parameter INITVAL_15 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+  parameter INITVAL_16 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+  parameter INITVAL_17 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+  parameter INITVAL_18 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+  parameter INITVAL_19 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+  parameter INITVAL_1A = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+  parameter INITVAL_1B = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+  parameter INITVAL_1C = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+  parameter INITVAL_1D = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+  parameter INITVAL_1E = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+  parameter INITVAL_1F = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+  parameter INITVAL_20 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+  parameter INITVAL_21 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+  parameter INITVAL_22 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+  parameter INITVAL_23 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+  parameter INITVAL_24 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+  parameter INITVAL_25 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+  parameter INITVAL_26 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+  parameter INITVAL_27 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+  parameter INITVAL_28 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+  parameter INITVAL_29 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+  parameter INITVAL_2A = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+  parameter INITVAL_2B = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+  parameter INITVAL_2C = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+  parameter INITVAL_2D = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+  parameter INITVAL_2E = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+  parameter INITVAL_2F = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+  parameter INITVAL_30 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+  parameter INITVAL_31 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+  parameter INITVAL_32 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+  parameter INITVAL_33 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+  parameter INITVAL_34 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+  parameter INITVAL_35 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+  parameter INITVAL_36 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+  parameter INITVAL_37 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+  parameter INITVAL_38 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+  parameter INITVAL_39 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+  parameter INITVAL_3A = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+  parameter INITVAL_3B = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+  parameter INITVAL_3C = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+  parameter INITVAL_3D = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+  parameter INITVAL_3E = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+  parameter INITVAL_3F = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
 endmodule
-- 
cgit v1.2.3


From 983fb7ff88ab5f398073e2aa1d5e44eb03d01ee3 Mon Sep 17 00:00:00 2001
From: David Shah <dave@ds0.me>
Date: Wed, 10 Oct 2018 16:35:19 +0100
Subject: ecp5: First BRAM type maps successfully

Signed-off-by: David Shah <dave@ds0.me>
---
 techlibs/ecp5/.gitignore    |  1 +
 techlibs/ecp5/Makefile.inc  | 23 ++++++++++++++++++++--
 techlibs/ecp5/bram.txt      |  4 ++--
 techlibs/ecp5/bram_map.v    |  0
 techlibs/ecp5/brams_init.py |  4 ++--
 techlibs/ecp5/brams_map.v   | 47 +++++++++++++++++++++++++++++++++++++++++++++
 techlibs/ecp5/cells_sim.v   |  2 ++
 techlibs/ecp5/synth_ecp5.cc |  5 +----
 8 files changed, 76 insertions(+), 10 deletions(-)
 delete mode 100644 techlibs/ecp5/bram_map.v
 create mode 100644 techlibs/ecp5/brams_map.v

(limited to 'techlibs/ecp5')

diff --git a/techlibs/ecp5/.gitignore b/techlibs/ecp5/.gitignore
index 3f66045f8..54c329735 100644
--- a/techlibs/ecp5/.gitignore
+++ b/techlibs/ecp5/.gitignore
@@ -6,3 +6,4 @@ bram_conn_2.vh
 bram_conn_4.vh
 bram_conn_9.vh
 bram_conn_18.vh
+brams_connect.mk
diff --git a/techlibs/ecp5/Makefile.inc b/techlibs/ecp5/Makefile.inc
index 95d40fccf..f45859392 100644
--- a/techlibs/ecp5/Makefile.inc
+++ b/techlibs/ecp5/Makefile.inc
@@ -5,19 +5,38 @@ $(eval $(call add_share_file,share/ecp5,techlibs/ecp5/cells_map.v))
 $(eval $(call add_share_file,share/ecp5,techlibs/ecp5/cells_sim.v))
 $(eval $(call add_share_file,share/ecp5,techlibs/ecp5/drams_map.v))
 $(eval $(call add_share_file,share/ecp5,techlibs/ecp5/dram.txt))
+$(eval $(call add_share_file,share/ecp5,techlibs/ecp5/brams_map.v))
 $(eval $(call add_share_file,share/ecp5,techlibs/ecp5/bram.txt))
 $(eval $(call add_share_file,share/ecp5,techlibs/ecp5/arith_map.v))
 
-EXTRA_OBJS += techlibs/ecp5/brams_init.mk
-.SECONDARY: techlibs/ecp5/brams_init.mk
+EXTRA_OBJS += techlibs/ecp5/brams_init.mk techlibs/ecp5/brams_connect.mk
+.SECONDARY: techlibs/ecp5/brams_init.mk techlibs/ecp5/brams_connect.mk
 
 techlibs/ecp5/brams_init.mk: techlibs/ecp5/brams_init.py
 	$(Q) mkdir -p techlibs/ecp5
 	$(P) python3 $<
 	$(Q) touch $@
 
+techlibs/ecp5/brams_connect.mk: techlibs/ecp5/brams_connect.py
+	$(Q) mkdir -p techlibs/ecp5
+	$(P) python3 $<
+	$(Q) touch $@
+
+
 techlibs/ecp5/bram_init_1_2_4.vh: techlibs/ecp5/brams_init.mk
 techlibs/ecp5/bram_init_9_18_36.vh: techlibs/ecp5/brams_init.mk
 
+techlibs/ecp5/bram_conn_1.vh: techlibs/ecp5/brams_connect.mk
+techlibs/ecp5/bram_conn_2.vh: techlibs/ecp5/brams_connect.mk
+techlibs/ecp5/bram_conn_4.vh: techlibs/ecp5/brams_connect.mk
+techlibs/ecp5/bram_conn_9.vh: techlibs/ecp5/brams_connect.mk
+techlibs/ecp5/bram_conn_18.vh: techlibs/ecp5/brams_connect.mk
+
 $(eval $(call add_share_file,share/ecp5,techlibs/ecp5/bram_init_1_2_4.vh))
 $(eval $(call add_share_file,share/ecp5,techlibs/ecp5/bram_init_9_18_36.vh))
+
+$(eval $(call add_share_file,share/ecp5,techlibs/ecp5/bram_conn_1.vh))
+$(eval $(call add_share_file,share/ecp5,techlibs/ecp5/bram_conn_2.vh))
+$(eval $(call add_share_file,share/ecp5,techlibs/ecp5/bram_conn_4.vh))
+$(eval $(call add_share_file,share/ecp5,techlibs/ecp5/bram_conn_9.vh))
+$(eval $(call add_share_file,share/ecp5,techlibs/ecp5/bram_conn_18.vh))
diff --git a/techlibs/ecp5/bram.txt b/techlibs/ecp5/bram.txt
index 9d22e4afe..f223a42b8 100644
--- a/techlibs/ecp5/bram.txt
+++ b/techlibs/ecp5/bram.txt
@@ -18,8 +18,8 @@ bram $__ECP5_DP16KD
   enable 2 1 @a10d18
   enable 1 1 @a11d9 @a12d4 @a13d2 @a14d1
   transp 0 2
-  clocks 1 2
-  clkpol 2 2
+  clocks 2 3
+  clkpol 2 3
 endbram
 
 match $__ECP5_DP16KD
diff --git a/techlibs/ecp5/bram_map.v b/techlibs/ecp5/bram_map.v
deleted file mode 100644
index e69de29bb..000000000
diff --git a/techlibs/ecp5/brams_init.py b/techlibs/ecp5/brams_init.py
index 6f650b2a9..96a47bdcd 100755
--- a/techlibs/ecp5/brams_init.py
+++ b/techlibs/ecp5/brams_init.py
@@ -8,7 +8,7 @@ with open("techlibs/ecp5/bram_init_1_2_4.vh", "w") as f:
         init_snippets = list(reversed(init_snippets))
         for k in range(8, 64, 8):
             init_snippets[k] = "\n          " + init_snippets[k]
-        print(".INIT_%02X({%s})," % (i, ", ".join(init_snippets)), file=f)
+        print(".INITVAL_%02X({%s})," % (i, ", ".join(init_snippets)), file=f)
 
 with open("techlibs/ecp5/bram_init_9_18_36.vh", "w") as f:
     for i in range(0, 0x40):
@@ -19,4 +19,4 @@ with open("techlibs/ecp5/bram_init_9_18_36.vh", "w") as f:
         init_snippets = list(reversed(init_snippets))
         for k in range(8, 32, 8):
             init_snippets[k] = "\n          " + init_snippets[k]
-        print(".INIT_%02X({%s})," % (i, ", ".join(init_snippets)), file=f)
+        print(".INITVAL_%02X({%s})," % (i, ", ".join(init_snippets)), file=f)
diff --git a/techlibs/ecp5/brams_map.v b/techlibs/ecp5/brams_map.v
new file mode 100644
index 000000000..894f5c46f
--- /dev/null
+++ b/techlibs/ecp5/brams_map.v
@@ -0,0 +1,47 @@
+module \$__ECP5_DP16KD (CLK2, CLK3, A1ADDR, A1DATA, A1EN, B1ADDR, B1DATA, B1EN);
+	parameter CFG_ABITS = 10;
+	parameter CFG_DBITS = 18;
+	parameter CFG_ENABLE_A = 2;
+
+	parameter CLKPOL2 = 1;
+	parameter CLKPOL3 = 1;
+	parameter [18431:0] INIT = 18432'bx;
+	parameter TRANSP2 = 0;
+
+	input CLK2;
+	input CLK3;
+
+	input [CFG_ABITS-1:0] A1ADDR;
+	input [CFG_DBITS-1:0] A1DATA;
+	input [CFG_ENABLE_A-1:0] A1EN;
+
+	input [CFG_ABITS-1:0] B1ADDR;
+	output [CFG_DBITS-1:0] B1DATA;
+	input B1EN;
+
+	localparam CLKAMUX = CLKPOL2 ? "CLKA" : "INV";
+	localparam CLKBMUX = CLKPOL3 ? "CLKB" : "INV";
+
+	localparam WRITEMODE_A = TRANSP2 ? "WRITETHROUGH" : "NORMAL";
+
+
+	generate if (CFG_DBITS == 1) begin
+		DP16KD #(
+			`include "bram_init_1_2_4.vh"
+			.DATA_WIDTH_A(1),
+			.DATA_WIDTH_B(1),
+			.CLKAMUX(CLKAMUX),
+			.CLKBMUX(CLKBMUX),
+			.WRITEMODE_A(WRITEMODE_A),
+			.GSR("DISABLED")
+		) _TECHMAP_REPLACE_ (
+			`include "bram_conn_1.vh"
+			.CLKA(CLK2), .CLKB(CLK3),
+			.WEA(1'b1), .CEA(|A1EN), .OCEA(1'b1),
+			.WEB(1'b0), .CEB(B1EN), .OCEB(1'b1),
+			.RSTA(1'b0), .RSTB(1'b0)
+		);
+	end else begin
+		wire TECHMAP_FAIL = 1'b1;
+	end endgenerate
+endmodule
diff --git a/techlibs/ecp5/cells_sim.v b/techlibs/ecp5/cells_sim.v
index 4732381ca..e43632c64 100644
--- a/techlibs/ecp5/cells_sim.v
+++ b/techlibs/ecp5/cells_sim.v
@@ -475,6 +475,8 @@ module DP16KD(
   parameter WRITEMODE_A = "NORMAL";
   parameter WRITEMODE_B = "NORMAL";
 
+  parameter CLKAMUX = "CLKA";
+  parameter CLKBMUX = "CLKB";
 
   parameter GSR = "ENABLED";
 
diff --git a/techlibs/ecp5/synth_ecp5.cc b/techlibs/ecp5/synth_ecp5.cc
index a13dd8d41..ab56a9444 100644
--- a/techlibs/ecp5/synth_ecp5.cc
+++ b/techlibs/ecp5/synth_ecp5.cc
@@ -222,11 +222,8 @@ struct SynthEcp5Pass : public ScriptPass
 
 		if (!nobram && check_label("bram", "(skip if -nobram)"))
 		{
-			//TODO
-#if 0
-			run("memory_bram -rules +/ecp5/brams.txt");
+			run("memory_bram -rules +/ecp5/bram.txt");
 			run("techmap -map +/ecp5/brams_map.v");
-#endif
 		}
 
 		if (!nodram && check_label("dram", "(skip if -nodram)"))
-- 
cgit v1.2.3


From bdfead8c648db77b9350f941d6578a48bdaa2203 Mon Sep 17 00:00:00 2001
From: David Shah <dave@ds0.me>
Date: Wed, 10 Oct 2018 17:18:17 +0100
Subject: ecp5: Adding BRAM maps for all size options

Signed-off-by: David Shah <dave@ds0.me>
---
 techlibs/ecp5/brams_map.v | 65 ++++++++++++++++++++++++++++++++++++++++++++++-
 1 file changed, 64 insertions(+), 1 deletion(-)

(limited to 'techlibs/ecp5')

diff --git a/techlibs/ecp5/brams_map.v b/techlibs/ecp5/brams_map.v
index 894f5c46f..61dee7054 100644
--- a/techlibs/ecp5/brams_map.v
+++ b/techlibs/ecp5/brams_map.v
@@ -24,7 +24,6 @@ module \$__ECP5_DP16KD (CLK2, CLK3, A1ADDR, A1DATA, A1EN, B1ADDR, B1DATA, B1EN);
 
 	localparam WRITEMODE_A = TRANSP2 ? "WRITETHROUGH" : "NORMAL";
 
-
 	generate if (CFG_DBITS == 1) begin
 		DP16KD #(
 			`include "bram_init_1_2_4.vh"
@@ -41,6 +40,70 @@ module \$__ECP5_DP16KD (CLK2, CLK3, A1ADDR, A1DATA, A1EN, B1ADDR, B1DATA, B1EN);
 			.WEB(1'b0), .CEB(B1EN), .OCEB(1'b1),
 			.RSTA(1'b0), .RSTB(1'b0)
 		);
+	end else if (CFG_DBITS == 2) begin
+		DP16KD #(
+			`include "bram_init_1_2_4.vh"
+			.DATA_WIDTH_A(2),
+			.DATA_WIDTH_B(2),
+			.CLKAMUX(CLKAMUX),
+			.CLKBMUX(CLKBMUX),
+			.WRITEMODE_A(WRITEMODE_A),
+			.GSR("DISABLED")
+		) _TECHMAP_REPLACE_ (
+			`include "bram_conn_2.vh"
+			.CLKA(CLK2), .CLKB(CLK3),
+			.WEA(1'b1), .CEA(|A1EN), .OCEA(1'b1),
+			.WEB(1'b0), .CEB(B1EN), .OCEB(1'b1),
+			.RSTA(1'b0), .RSTB(1'b0)
+		);
+	end else if (CFG_DBITS <= 4) begin
+		DP16KD #(
+			`include "bram_init_1_2_4.vh"
+			.DATA_WIDTH_A(4),
+			.DATA_WIDTH_B(4),
+			.CLKAMUX(CLKAMUX),
+			.CLKBMUX(CLKBMUX),
+			.WRITEMODE_A(WRITEMODE_A),
+			.GSR("DISABLED")
+		) _TECHMAP_REPLACE_ (
+			`include "bram_conn_4.vh"
+			.CLKA(CLK2), .CLKB(CLK3),
+			.WEA(1'b1), .CEA(|A1EN), .OCEA(1'b1),
+			.WEB(1'b0), .CEB(B1EN), .OCEB(1'b1),
+			.RSTA(1'b0), .RSTB(1'b0)
+		);
+	end else if (CFG_DBITS <= 9) begin
+		DP16KD #(
+			`include "bram_init_9_18_36.vh"
+			.DATA_WIDTH_A(9),
+			.DATA_WIDTH_B(9),
+			.CLKAMUX(CLKAMUX),
+			.CLKBMUX(CLKBMUX),
+			.WRITEMODE_A(WRITEMODE_A),
+			.GSR("DISABLED")
+		) _TECHMAP_REPLACE_ (
+			`include "bram_conn_9.vh"
+			.CLKA(CLK2), .CLKB(CLK3),
+			.WEA(1'b1), .CEA(|A1EN), .OCEA(1'b1),
+			.WEB(1'b0), .CEB(B1EN), .OCEB(1'b1),
+			.RSTA(1'b0), .RSTB(1'b0)
+		);
+	end else if (CFG_DBITS <= 18) begin
+		DP16KD #(
+			`include "bram_init_9_18_36.vh"
+			.DATA_WIDTH_A(18),
+			.DATA_WIDTH_B(18),
+			.CLKAMUX(CLKAMUX),
+			.CLKBMUX(CLKBMUX),
+			.WRITEMODE_A(WRITEMODE_A),
+			.GSR("DISABLED")
+		) _TECHMAP_REPLACE_ (
+			`include "bram_conn_18.vh"
+			.CLKA(CLK2), .CLKB(CLK3),
+			.WEA(1'b1), .CEA(|A1EN), .OCEA(1'b1),
+			.WEB(1'b0), .CEB(B1EN), .OCEB(1'b1),
+			.RSTA(1'b0), .RSTB(1'b0)
+		);
 	end else begin
 		wire TECHMAP_FAIL = 1'b1;
 	end endgenerate
-- 
cgit v1.2.3


From 812538a036f380b613d1cd3fe2f182e376150d16 Mon Sep 17 00:00:00 2001
From: David Shah <dave@ds0.me>
Date: Fri, 12 Oct 2018 14:22:21 +0100
Subject: BRAM improvements

Signed-off-by: David Shah <dave@ds0.me>
---
 techlibs/ecp5/brams_map.v | 27 ++++++++++++++++-----------
 1 file changed, 16 insertions(+), 11 deletions(-)

(limited to 'techlibs/ecp5')

diff --git a/techlibs/ecp5/brams_map.v b/techlibs/ecp5/brams_map.v
index 61dee7054..7f40f8458 100644
--- a/techlibs/ecp5/brams_map.v
+++ b/techlibs/ecp5/brams_map.v
@@ -22,7 +22,7 @@ module \$__ECP5_DP16KD (CLK2, CLK3, A1ADDR, A1DATA, A1EN, B1ADDR, B1DATA, B1EN);
 	localparam CLKAMUX = CLKPOL2 ? "CLKA" : "INV";
 	localparam CLKBMUX = CLKPOL3 ? "CLKB" : "INV";
 
-	localparam WRITEMODE_A = TRANSP2 ? "WRITETHROUGH" : "NORMAL";
+	localparam WRITEMODE_A = TRANSP2 ? "WRITETHROUGH" : "READBEFOREWRITE";
 
 	generate if (CFG_DBITS == 1) begin
 		DP16KD #(
@@ -32,12 +32,13 @@ module \$__ECP5_DP16KD (CLK2, CLK3, A1ADDR, A1DATA, A1EN, B1ADDR, B1DATA, B1EN);
 			.CLKAMUX(CLKAMUX),
 			.CLKBMUX(CLKBMUX),
 			.WRITEMODE_A(WRITEMODE_A),
+			.WRITEMODE_B("READBEFOREWRITE"),
 			.GSR("DISABLED")
 		) _TECHMAP_REPLACE_ (
 			`include "bram_conn_1.vh"
 			.CLKA(CLK2), .CLKB(CLK3),
-			.WEA(1'b1), .CEA(|A1EN), .OCEA(1'b1),
-			.WEB(1'b0), .CEB(B1EN), .OCEB(1'b1),
+			.WEA(|A1EN), .CEA(1'b1), .OCEA(1'b1),
+			.WEB(1'b0), .CEB(1'b1), .OCEB(B1EN),
 			.RSTA(1'b0), .RSTB(1'b0)
 		);
 	end else if (CFG_DBITS == 2) begin
@@ -48,12 +49,13 @@ module \$__ECP5_DP16KD (CLK2, CLK3, A1ADDR, A1DATA, A1EN, B1ADDR, B1DATA, B1EN);
 			.CLKAMUX(CLKAMUX),
 			.CLKBMUX(CLKBMUX),
 			.WRITEMODE_A(WRITEMODE_A),
+			.WRITEMODE_B("READBEFOREWRITE"),
 			.GSR("DISABLED")
 		) _TECHMAP_REPLACE_ (
 			`include "bram_conn_2.vh"
 			.CLKA(CLK2), .CLKB(CLK3),
-			.WEA(1'b1), .CEA(|A1EN), .OCEA(1'b1),
-			.WEB(1'b0), .CEB(B1EN), .OCEB(1'b1),
+			.WEA(|A1EN), .CEA(1'b1), .OCEA(1'b1),
+			.WEB(1'b0), .CEB(1'b1), .OCEB(B1EN),
 			.RSTA(1'b0), .RSTB(1'b0)
 		);
 	end else if (CFG_DBITS <= 4) begin
@@ -64,12 +66,13 @@ module \$__ECP5_DP16KD (CLK2, CLK3, A1ADDR, A1DATA, A1EN, B1ADDR, B1DATA, B1EN);
 			.CLKAMUX(CLKAMUX),
 			.CLKBMUX(CLKBMUX),
 			.WRITEMODE_A(WRITEMODE_A),
+			.WRITEMODE_B("READBEFOREWRITE"),
 			.GSR("DISABLED")
 		) _TECHMAP_REPLACE_ (
 			`include "bram_conn_4.vh"
 			.CLKA(CLK2), .CLKB(CLK3),
-			.WEA(1'b1), .CEA(|A1EN), .OCEA(1'b1),
-			.WEB(1'b0), .CEB(B1EN), .OCEB(1'b1),
+			.WEA(|A1EN), .CEA(1'b1), .OCEA(1'b1),
+			.WEB(1'b0), .CEB(1'b1), .OCEB(B1EN),
 			.RSTA(1'b0), .RSTB(1'b0)
 		);
 	end else if (CFG_DBITS <= 9) begin
@@ -80,12 +83,13 @@ module \$__ECP5_DP16KD (CLK2, CLK3, A1ADDR, A1DATA, A1EN, B1ADDR, B1DATA, B1EN);
 			.CLKAMUX(CLKAMUX),
 			.CLKBMUX(CLKBMUX),
 			.WRITEMODE_A(WRITEMODE_A),
+			.WRITEMODE_B("READBEFOREWRITE"),
 			.GSR("DISABLED")
 		) _TECHMAP_REPLACE_ (
 			`include "bram_conn_9.vh"
 			.CLKA(CLK2), .CLKB(CLK3),
-			.WEA(1'b1), .CEA(|A1EN), .OCEA(1'b1),
-			.WEB(1'b0), .CEB(B1EN), .OCEB(1'b1),
+			.WEA(|A1EN), .CEA(1'b1), .OCEA(1'b1),
+			.WEB(1'b0), .CEB(1'b1), .OCEB(B1EN),
 			.RSTA(1'b0), .RSTB(1'b0)
 		);
 	end else if (CFG_DBITS <= 18) begin
@@ -96,12 +100,13 @@ module \$__ECP5_DP16KD (CLK2, CLK3, A1ADDR, A1DATA, A1EN, B1ADDR, B1DATA, B1EN);
 			.CLKAMUX(CLKAMUX),
 			.CLKBMUX(CLKBMUX),
 			.WRITEMODE_A(WRITEMODE_A),
+			.WRITEMODE_B("READBEFOREWRITE"),
 			.GSR("DISABLED")
 		) _TECHMAP_REPLACE_ (
 			`include "bram_conn_18.vh"
 			.CLKA(CLK2), .CLKB(CLK3),
-			.WEA(1'b1), .CEA(|A1EN), .OCEA(1'b1),
-			.WEB(1'b0), .CEB(B1EN), .OCEB(1'b1),
+			.WEA(|A1EN), .CEA(1'b1), .OCEA(1'b1),
+			.WEB(1'b0), .CEB(1'b1), .OCEB(B1EN),
 			.RSTA(1'b0), .RSTB(1'b0)
 		);
 	end else begin
-- 
cgit v1.2.3


From df4bfa0ad69c1c4ba75222616d02dae3d1abe5de Mon Sep 17 00:00:00 2001
From: David Shah <dave@ds0.me>
Date: Tue, 16 Oct 2018 12:48:39 +0100
Subject: ecp5: Disable LSR inversion

Signed-off-by: David Shah <dave@ds0.me>
---
 techlibs/ecp5/brams_map.v | 10 +++++-----
 techlibs/ecp5/cells_map.v | 32 ++++++++++++++++----------------
 2 files changed, 21 insertions(+), 21 deletions(-)

(limited to 'techlibs/ecp5')

diff --git a/techlibs/ecp5/brams_map.v b/techlibs/ecp5/brams_map.v
index 7f40f8458..b2c136863 100644
--- a/techlibs/ecp5/brams_map.v
+++ b/techlibs/ecp5/brams_map.v
@@ -38,7 +38,7 @@ module \$__ECP5_DP16KD (CLK2, CLK3, A1ADDR, A1DATA, A1EN, B1ADDR, B1DATA, B1EN);
 			`include "bram_conn_1.vh"
 			.CLKA(CLK2), .CLKB(CLK3),
 			.WEA(|A1EN), .CEA(1'b1), .OCEA(1'b1),
-			.WEB(1'b0), .CEB(1'b1), .OCEB(B1EN),
+			.WEB(1'b0), .CEB(B1EN), .OCEB(1'b1),
 			.RSTA(1'b0), .RSTB(1'b0)
 		);
 	end else if (CFG_DBITS == 2) begin
@@ -55,7 +55,7 @@ module \$__ECP5_DP16KD (CLK2, CLK3, A1ADDR, A1DATA, A1EN, B1ADDR, B1DATA, B1EN);
 			`include "bram_conn_2.vh"
 			.CLKA(CLK2), .CLKB(CLK3),
 			.WEA(|A1EN), .CEA(1'b1), .OCEA(1'b1),
-			.WEB(1'b0), .CEB(1'b1), .OCEB(B1EN),
+			.WEB(1'b0), .CEB(B1EN), .OCEB(1'b1),
 			.RSTA(1'b0), .RSTB(1'b0)
 		);
 	end else if (CFG_DBITS <= 4) begin
@@ -72,7 +72,7 @@ module \$__ECP5_DP16KD (CLK2, CLK3, A1ADDR, A1DATA, A1EN, B1ADDR, B1DATA, B1EN);
 			`include "bram_conn_4.vh"
 			.CLKA(CLK2), .CLKB(CLK3),
 			.WEA(|A1EN), .CEA(1'b1), .OCEA(1'b1),
-			.WEB(1'b0), .CEB(1'b1), .OCEB(B1EN),
+			.WEB(1'b0), .CEB(B1EN), .OCEB(1'b1),
 			.RSTA(1'b0), .RSTB(1'b0)
 		);
 	end else if (CFG_DBITS <= 9) begin
@@ -89,7 +89,7 @@ module \$__ECP5_DP16KD (CLK2, CLK3, A1ADDR, A1DATA, A1EN, B1ADDR, B1DATA, B1EN);
 			`include "bram_conn_9.vh"
 			.CLKA(CLK2), .CLKB(CLK3),
 			.WEA(|A1EN), .CEA(1'b1), .OCEA(1'b1),
-			.WEB(1'b0), .CEB(1'b1), .OCEB(B1EN),
+			.WEB(1'b0), .CEB(B1EN), .OCEB(1'b1),
 			.RSTA(1'b0), .RSTB(1'b0)
 		);
 	end else if (CFG_DBITS <= 18) begin
@@ -106,7 +106,7 @@ module \$__ECP5_DP16KD (CLK2, CLK3, A1ADDR, A1DATA, A1EN, B1ADDR, B1DATA, B1EN);
 			`include "bram_conn_18.vh"
 			.CLKA(CLK2), .CLKB(CLK3),
 			.WEA(|A1EN), .CEA(1'b1), .OCEA(1'b1),
-			.WEB(1'b0), .CEB(1'b1), .OCEB(B1EN),
+			.WEB(1'b0), .CEB(B1EN), .OCEB(1'b1),
 			.RSTA(1'b0), .RSTB(1'b0)
 		);
 	end else begin
diff --git a/techlibs/ecp5/cells_map.v b/techlibs/ecp5/cells_map.v
index 48162a4dc..23182bdeb 100644
--- a/techlibs/ecp5/cells_map.v
+++ b/techlibs/ecp5/cells_map.v
@@ -7,40 +7,40 @@ module  \$_DFFE_PN_ (input D, C, E, output Q); TRELLIS_FF #(.GSR("DISABLED"), .C
 module  \$_DFFE_NP_ (input D, C, E, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("CE"), .CLKMUX("INV"), .LSRMUX("LSR"), .REGSET("RESET"))  _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(1'b0), .DI(D), .Q(Q)); endmodule
 module  \$_DFFE_PP_ (input D, C, E, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("RESET"))  _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(1'b0), .DI(D), .Q(Q)); endmodule
 
-module  \$_DFF_NN0_ (input D, C, R, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("1"), .CLKMUX("INV"), .LSRMUX("INV"), .REGSET("RESET"), .SRMODE("ASYNC"))  _TECHMAP_REPLACE_ (.CLK(C), .LSR(R), .DI(D), .Q(Q)); endmodule
-module  \$_DFF_NN1_ (input D, C, R, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("1"), .CLKMUX("INV"), .LSRMUX("INV"), .REGSET("SET"), .SRMODE("ASYNC"))  _TECHMAP_REPLACE_ (.CLK(C), .LSR(R), .DI(D), .Q(Q)); endmodule
-module  \$_DFF_PN0_ (input D, C, R, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("1"), .CLKMUX("CLK"), .LSRMUX("INV"), .REGSET("RESET"), .SRMODE("ASYNC"))  _TECHMAP_REPLACE_ (.CLK(C), .LSR(R), .DI(D), .Q(Q)); endmodule
-module  \$_DFF_PN1_ (input D, C, R, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("1"), .CLKMUX("CLK"), .LSRMUX("INV"), .REGSET("SET"), .SRMODE("ASYNC"))  _TECHMAP_REPLACE_ (.CLK(C), .LSR(R), .DI(D), .Q(Q)); endmodule
+module  \$_DFF_NN0_ (input D, C, R, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("1"), .CLKMUX("INV"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("ASYNC"))  _TECHMAP_REPLACE_ (.CLK(C), .LSR(!R), .DI(D), .Q(Q)); endmodule
+module  \$_DFF_NN1_ (input D, C, R, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("1"), .CLKMUX("INV"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("ASYNC"))  _TECHMAP_REPLACE_ (.CLK(C), .LSR(!R), .DI(D), .Q(Q)); endmodule
+module  \$_DFF_PN0_ (input D, C, R, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("1"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("ASYNC"))  _TECHMAP_REPLACE_ (.CLK(C), .LSR(!R), .DI(D), .Q(Q)); endmodule
+module  \$_DFF_PN1_ (input D, C, R, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("1"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("ASYNC"))  _TECHMAP_REPLACE_ (.CLK(C), .LSR(!R), .DI(D), .Q(Q)); endmodule
 
 module  \$_DFF_NP0_ (input D, C, R, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("1"), .CLKMUX("INV"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("ASYNC"))  _TECHMAP_REPLACE_ (.CLK(C), .LSR(R), .DI(D), .Q(Q)); endmodule
 module  \$_DFF_NP1_ (input D, C, R, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("1"), .CLKMUX("INV"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("ASYNC"))  _TECHMAP_REPLACE_ (.CLK(C), .LSR(R), .DI(D), .Q(Q)); endmodule
 module  \$_DFF_PP0_ (input D, C, R, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("1"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("ASYNC"))  _TECHMAP_REPLACE_ (.CLK(C), .LSR(R), .DI(D), .Q(Q)); endmodule
 module  \$_DFF_PP1_ (input D, C, R, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("1"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("ASYNC"))  _TECHMAP_REPLACE_ (.CLK(C), .LSR(R), .DI(D), .Q(Q)); endmodule
 
-module  \$__DFFS_NN0_ (input D, C, R, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("1"), .CLKMUX("INV"), .LSRMUX("INV"), .REGSET("RESET"), .SRMODE("LSR_OVER_CE"))  _TECHMAP_REPLACE_ (.CLK(C), .LSR(R), .DI(D), .Q(Q)); endmodule
-module  \$__DFFS_NN1_ (input D, C, R, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("1"), .CLKMUX("INV"), .LSRMUX("INV"), .REGSET("SET"), .SRMODE("LSR_OVER_CE"))  _TECHMAP_REPLACE_ (.CLK(C), .LSR(R), .DI(D), .Q(Q)); endmodule
-module  \$__DFFS_PN0_ (input D, C, R, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("1"), .CLKMUX("CLK"), .LSRMUX("INV"), .REGSET("RESET"), .SRMODE("LSR_OVER_CE"))  _TECHMAP_REPLACE_ (.CLK(C), .LSR(R), .DI(D), .Q(Q)); endmodule
-module  \$__DFFS_PN1_ (input D, C, R, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("1"), .CLKMUX("CLK"), .LSRMUX("INV"), .REGSET("SET"), .SRMODE("LSR_OVER_CE"))  _TECHMAP_REPLACE_ (.CLK(C), .LSR(R), .DI(D), .Q(Q)); endmodule
+module  \$__DFFS_NN0_ (input D, C, R, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("1"), .CLKMUX("INV"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("LSR_OVER_CE"))  _TECHMAP_REPLACE_ (.CLK(C), .LSR(!R), .DI(D), .Q(Q)); endmodule
+module  \$__DFFS_NN1_ (input D, C, R, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("1"), .CLKMUX("INV"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("LSR_OVER_CE"))  _TECHMAP_REPLACE_ (.CLK(C), .LSR(!R), .DI(D), .Q(Q)); endmodule
+module  \$__DFFS_PN0_ (input D, C, R, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("1"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("LSR_OVER_CE"))  _TECHMAP_REPLACE_ (.CLK(C), .LSR(!R), .DI(D), .Q(Q)); endmodule
+module  \$__DFFS_PN1_ (input D, C, R, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("1"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("LSR_OVER_CE"))  _TECHMAP_REPLACE_ (.CLK(C), .LSR(!R), .DI(D), .Q(Q)); endmodule
 
 module  \$__DFFS_NP0_ (input D, C, R, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("1"), .CLKMUX("INV"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("LSR_OVER_CE"))  _TECHMAP_REPLACE_ (.CLK(C), .LSR(R), .DI(D), .Q(Q)); endmodule
 module  \$__DFFS_NP1_ (input D, C, R, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("1"), .CLKMUX("INV"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("LSR_OVER_CE"))  _TECHMAP_REPLACE_ (.CLK(C), .LSR(R), .DI(D), .Q(Q)); endmodule
 module  \$__DFFS_PP0_ (input D, C, R, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("1"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("LSR_OVER_CE"))  _TECHMAP_REPLACE_ (.CLK(C), .LSR(R), .DI(D), .Q(Q)); endmodule
 module  \$__DFFS_PP1_ (input D, C, R, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("1"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("LSR_OVER_CE"))  _TECHMAP_REPLACE_ (.CLK(C), .LSR(R), .DI(D), .Q(Q)); endmodule
 
-module  \$__DFFE_NN0 (input D, C, E, R, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("CE"), .CLKMUX("INV"), .LSRMUX("INV"), .REGSET("RESET"), .SRMODE("ASYNC"))  _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(R), .DI(D), .Q(Q)); endmodule
-module  \$__DFFE_NN1 (input D, C, E, R, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("CE"), .CLKMUX("INV"), .LSRMUX("INV"), .REGSET("SET"), .SRMODE("ASYNC"))  _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(R), .DI(D), .Q(Q)); endmodule
-module  \$__DFFE_PN0 (input D, C, E, R, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("INV"), .REGSET("RESET"), .SRMODE("ASYNC"))  _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(R), .DI(D), .Q(Q)); endmodule
-module  \$__DFFE_PN1 (input D, C, E, R, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("INV"), .REGSET("SET"), .SRMODE("ASYNC"))  _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(R), .DI(D), .Q(Q)); endmodule
+module  \$__DFFE_NN0 (input D, C, E, R, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("CE"), .CLKMUX("INV"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("ASYNC"))  _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(!R), .DI(D), .Q(Q)); endmodule
+module  \$__DFFE_NN1 (input D, C, E, R, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("CE"), .CLKMUX("INV"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("ASYNC"))  _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(!R), .DI(D), .Q(Q)); endmodule
+module  \$__DFFE_PN0 (input D, C, E, R, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("ASYNC"))  _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(!R), .DI(D), .Q(Q)); endmodule
+module  \$__DFFE_PN1 (input D, C, E, R, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("ASYNC"))  _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(!R), .DI(D), .Q(Q)); endmodule
 
 module  \$__DFFE_NP0 (input D, C, E, R, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("CE"), .CLKMUX("INV"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("ASYNC"))  _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(R), .DI(D), .Q(Q)); endmodule
 module  \$__DFFE_NP1 (input D, C, E, R, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("CE"), .CLKMUX("INV"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("ASYNC"))  _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(R), .DI(D), .Q(Q)); endmodule
 module  \$__DFFE_PP0 (input D, C, E, R, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("ASYNC"))  _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(R), .DI(D), .Q(Q)); endmodule
 module  \$__DFFE_PP1 (input D, C, E, R, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("ASYNC"))  _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(R), .DI(D), .Q(Q)); endmodule
 
-module  \$__DFFSE_NN0 (input D, C, E, R, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("CE"), .CLKMUX("INV"), .LSRMUX("INV"), .REGSET("RESET"), .SRMODE("LSR_OVER_CE"))  _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(R), .DI(D), .Q(Q)); endmodule
-module  \$__DFFSE_NN1 (input D, C, E, R, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("CE"), .CLKMUX("INV"), .LSRMUX("INV"), .REGSET("SET"), .SRMODE("LSR_OVER_CE"))  _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(R), .DI(D), .Q(Q)); endmodule
-module  \$__DFFSE_PN0 (input D, C, E, R, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("INV"), .REGSET("RESET"), .SRMODE("LSR_OVER_CE"))  _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(R), .DI(D), .Q(Q)); endmodule
-module  \$__DFFSE_PN1 (input D, C, E, R, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("INV"), .REGSET("SET"), .SRMODE("LSR_OVER_CE"))  _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(R), .DI(D), .Q(Q)); endmodule
+module  \$__DFFSE_NN0 (input D, C, E, R, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("CE"), .CLKMUX("INV"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("LSR_OVER_CE"))  _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(!R), .DI(D), .Q(Q)); endmodule
+module  \$__DFFSE_NN1 (input D, C, E, R, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("CE"), .CLKMUX("INV"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("LSR_OVER_CE"))  _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(!R), .DI(D), .Q(Q)); endmodule
+module  \$__DFFSE_PN0 (input D, C, E, R, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("LSR_OVER_CE"))  _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(!R), .DI(D), .Q(Q)); endmodule
+module  \$__DFFSE_PN1 (input D, C, E, R, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("LSR_OVER_CE"))  _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(!R), .DI(D), .Q(Q)); endmodule
 
 module  \$__DFFSE_NP0 (input D, C, E, R, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("CE"), .CLKMUX("INV"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("LSR_OVER_CE"))  _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(R), .DI(D), .Q(Q)); endmodule
 module  \$__DFFSE_NP1 (input D, C, E, R, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("CE"), .CLKMUX("INV"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("LSR_OVER_CE"))  _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(R), .DI(D), .Q(Q)); endmodule
-- 
cgit v1.2.3


From 677b8ed3ca70dad1dec288c274e64ebb0ef4011b Mon Sep 17 00:00:00 2001
From: David Shah <dave@ds0.me>
Date: Thu, 18 Oct 2018 19:39:48 +0100
Subject: ecp5: Add latch inference

Signed-off-by: David Shah <dave@ds0.me>
---
 techlibs/ecp5/Makefile.inc  |  1 +
 techlibs/ecp5/latches_map.v | 11 +++++++++++
 techlibs/ecp5/synth_ecp5.cc |  3 ---
 3 files changed, 12 insertions(+), 3 deletions(-)
 create mode 100644 techlibs/ecp5/latches_map.v

(limited to 'techlibs/ecp5')

diff --git a/techlibs/ecp5/Makefile.inc b/techlibs/ecp5/Makefile.inc
index f45859392..9b6f061bd 100644
--- a/techlibs/ecp5/Makefile.inc
+++ b/techlibs/ecp5/Makefile.inc
@@ -8,6 +8,7 @@ $(eval $(call add_share_file,share/ecp5,techlibs/ecp5/dram.txt))
 $(eval $(call add_share_file,share/ecp5,techlibs/ecp5/brams_map.v))
 $(eval $(call add_share_file,share/ecp5,techlibs/ecp5/bram.txt))
 $(eval $(call add_share_file,share/ecp5,techlibs/ecp5/arith_map.v))
+$(eval $(call add_share_file,share/ecp5,techlibs/ecp5/latches_map.v))
 
 EXTRA_OBJS += techlibs/ecp5/brams_init.mk techlibs/ecp5/brams_connect.mk
 .SECONDARY: techlibs/ecp5/brams_init.mk techlibs/ecp5/brams_connect.mk
diff --git a/techlibs/ecp5/latches_map.v b/techlibs/ecp5/latches_map.v
new file mode 100644
index 000000000..c28f88cf7
--- /dev/null
+++ b/techlibs/ecp5/latches_map.v
@@ -0,0 +1,11 @@
+module \$_DLATCH_N_ (E, D, Q);
+  wire [1023:0] _TECHMAP_DO_ = "simplemap; opt";
+  input E, D;
+  output Q = !E ? D : Q;
+endmodule
+
+module \$_DLATCH_P_ (E, D, Q);
+  wire [1023:0] _TECHMAP_DO_ = "simplemap; opt";
+  input E, D;
+  output Q = E ? D : Q;
+endmodule
diff --git a/techlibs/ecp5/synth_ecp5.cc b/techlibs/ecp5/synth_ecp5.cc
index ab56a9444..cb6a4c3d8 100644
--- a/techlibs/ecp5/synth_ecp5.cc
+++ b/techlibs/ecp5/synth_ecp5.cc
@@ -266,10 +266,7 @@ struct SynthEcp5Pass : public ScriptPass
 			if (abc2 || help_mode) {
 				run("abc", "      (only if -abc2)");
 			}
-			//TODO
-#if 0
 			run("techmap -map +/ecp5/latches_map.v");
-#endif
 			if (nomux)
 				run("abc -lut 4");
 			else
-- 
cgit v1.2.3


From d29b517fef05973dda3c556a95fbfb478d6e7e50 Mon Sep 17 00:00:00 2001
From: David Shah <dave@ds0.me>
Date: Thu, 18 Oct 2018 19:40:02 +0100
Subject: ecp5: Sim model fixes

Signed-off-by: David Shah <dave@ds0.me>
---
 techlibs/ecp5/cells_sim.v | 8 +++++---
 1 file changed, 5 insertions(+), 3 deletions(-)

(limited to 'techlibs/ecp5')

diff --git a/techlibs/ecp5/cells_sim.v b/techlibs/ecp5/cells_sim.v
index e43632c64..6e4b0a5ac 100644
--- a/techlibs/ecp5/cells_sim.v
+++ b/techlibs/ecp5/cells_sim.v
@@ -265,16 +265,18 @@ module TRELLIS_IO(
 	output O
 );
 	parameter DIR = "INPUT";
+	reg T_pd;
+	always @(*) if (T === 1'bz) T_pd <= 1'b0; else T_pd <= T;
 
 	generate
 		if (DIR == "INPUT") begin
 			assign B = 1'bz;
 			assign O = B;
 		end else if (DIR == "OUTPUT") begin
-			assign B = T ? 1'bz : I;
+			assign B = T_pd ? 1'bz : I;
 			assign O = 1'bx;
-		end else if (DIR == "INOUT") begin
-			assign B = T ? 1'bz : I;
+		end else if (DIR == "BIDIR") begin
+			assign B = T_pd ? 1'bz : I;
 			assign O = B;
 		end else begin
 			ERROR_UNKNOWN_IO_MODE error();
-- 
cgit v1.2.3


From 101f5234ff17c0395672a93da6ee10294212ad90 Mon Sep 17 00:00:00 2001
From: David Shah <davey1576@gmail.com>
Date: Sun, 21 Oct 2018 19:27:02 +0100
Subject: ecp5: Add DSP blackboxes

Signed-off-by: David Shah <davey1576@gmail.com>
---
 techlibs/ecp5/Makefile.inc  |   1 +
 techlibs/ecp5/cells_bb.v    | 116 ++++++++++++++++++++++++++++++++++++++++++++
 techlibs/ecp5/synth_ecp5.cc |   2 +-
 3 files changed, 118 insertions(+), 1 deletion(-)
 create mode 100644 techlibs/ecp5/cells_bb.v

(limited to 'techlibs/ecp5')

diff --git a/techlibs/ecp5/Makefile.inc b/techlibs/ecp5/Makefile.inc
index 9b6f061bd..b23d5c70e 100644
--- a/techlibs/ecp5/Makefile.inc
+++ b/techlibs/ecp5/Makefile.inc
@@ -3,6 +3,7 @@ OBJS += techlibs/ecp5/synth_ecp5.o
 
 $(eval $(call add_share_file,share/ecp5,techlibs/ecp5/cells_map.v))
 $(eval $(call add_share_file,share/ecp5,techlibs/ecp5/cells_sim.v))
+$(eval $(call add_share_file,share/ecp5,techlibs/ecp5/cells_bb.v))
 $(eval $(call add_share_file,share/ecp5,techlibs/ecp5/drams_map.v))
 $(eval $(call add_share_file,share/ecp5,techlibs/ecp5/dram.txt))
 $(eval $(call add_share_file,share/ecp5,techlibs/ecp5/brams_map.v))
diff --git a/techlibs/ecp5/cells_bb.v b/techlibs/ecp5/cells_bb.v
new file mode 100644
index 000000000..7ef02ef6a
--- /dev/null
+++ b/techlibs/ecp5/cells_bb.v
@@ -0,0 +1,116 @@
+// ECP5 Blackbox cells
+// FIXME: Create sim models
+
+(* blackbox *)
+module MULT18X18D(
+	input A0, A1, A2, A3, A4, A5, A6, A7, A8, A9, A10, A11, A12, A13, A14, A15, A16, A17,
+	input B0, B1, B2, B3, B4, B5, B6, B7, B8, B9, B10, B11, B12, B13, B14, B15, B16, B17,
+	input C0, C1, C2, C3, C4, C5, C6, C7, C8, C9, C10, C11, C12, C13, C14, C15, C16, C17,
+	input SIGNEDA, SIGNEDB, SOURCEA, SOURCEB,
+	input CLK0, CLK1, CLK2, CLK3,
+	input CE0, CE1, CE2, CE3,
+	input RST0, RST1, RST2, RST3,
+	input SRIA0, SRIA1, SRIA2, SRIA3, SRIA4, SRIA5, SRIA6, SRIA7, SRIA8, SRIA9, SRIA10, SRIA11, SRIA12, SRIA13, SRIA14, SRIA15, SRIA16, SRIA17,
+	input SRIB0, SRIB1, SRIB2, SRIB3, SRIB4, SRIB5, SRIB6, SRIB7, SRIB8, SRIB9, SRIB10, SRIB11, SRIB12, SRIB13, SRIB14, SRIB15, SRIB16, SRIB17,
+	output SROA0, SROA1, SROA2, SROA3, SROA4, SROA5, SROA6, SROA7, SROA8, SROA9, SROA10, SROA11, SROA12, SROA13, SROA14, SROA15, SROA16, SROA17,
+	output SROB0, SROB1, SROB2, SROB3, SROB4, SROB5, SROB6, SROB7, SROB8, SROB9, SROB10, SROB11, SROB12, SROB13, SROB14, SROB15, SROB16, SROB17,
+	output ROA0, ROA1, ROA2, ROA3, ROA4, ROA5, ROA6, ROA7, ROA8, ROA9, ROA10, ROA11, ROA12, ROA13, ROA14, ROA15, ROA16, ROA17,
+	output ROB0, ROB1, ROB2, ROB3, ROB4, ROB5, ROB6, ROB7, ROB8, ROB9, ROB10, ROB11, ROB12, ROB13, ROB14, ROB15, ROB16, ROB17,
+	output ROC0, ROC1, ROC2, ROC3, ROC4, ROC5, ROC6, ROC7, ROC8, ROC9, ROC10, ROC11, ROC12, ROC13, ROC14, ROC15, ROC16, ROC17,
+	output P0, P1, P2, P3, P4, P5, P6, P7, P8, P9, P10, P11, P12, P13, P14, P15, P16, P17, P18, P19, P20, P21, P22, P23, P24, P25, P26, P27, P28, P29, P30, P31, P32, P33, P34, P35,
+	output SIGNEDP
+);
+	parameter REG_INPUTA_CLK = "NONE";
+	parameter REG_INPUTA_CE = "CE0";
+	parameter REG_INPUTA_RST = "RST0";
+	parameter REG_INPUTB_CLK = "NONE";
+	parameter REG_INPUTB_CE = "CE0";
+	parameter REG_INPUTB_RST = "RST0";
+	parameter REG_INPUTC_CLK = "NONE";
+	parameter REG_INPUTC_CE = "CE0";
+	parameter REG_INPUTC_RST = "RST0";
+	parameter REG_PIPELINE_CLK = "NONE";
+	parameter REG_PIPELINE_CE = "CE0";
+	parameter REG_PIPELINE_RST = "RST0";
+	parameter REG_OUTPUT_CLK = "NONE";
+	parameter REG_OUTPUT_CE = "CE0";
+	parameter REG_OUTPUT_RST = "RST0";
+	parameter [127:0] CLK0_DIV = "ENABLED";
+	parameter [127:0] CLK1_DIV = "ENABLED";
+	parameter [127:0] CLK2_DIV = "ENABLED";
+	parameter [127:0] CLK3_DIV = "ENABLED";
+	parameter HIGHSPEED_CLK = "NONE";
+	parameter [127:0] GSR = "ENABLED";
+	parameter CAS_MATCH_REG = "FALSE";
+	parameter [127:0] SOURCEB_MODE = "B_SHIFT";
+	parameter [127:0] MULT_BYPASS = "DISABLED";
+	parameter [127:0] RESETMODE = "SYNC";
+endmodule
+
+(* blackbox *)
+module ALU54B(
+	input CLK0, CLK1, CLK2, CLK3,
+	input CE0, CE1, CE2, CE3,
+	input RST0, RST1, RST2, RST3,
+	input SIGNEDIA, SIGNEDIB, SIGNEDCIN,
+	input A0, A1, A2, A3, A4, A5, A6, A7, A8, A9, A10, A11, A12, A13, A14, A15, A16, A17, A18, A19, A20, A21, A22, A23, A24, A25, A26, A27, A28, A29, A30, A31, A32, A33, A34, A35,
+	input B0, B1, B2, B3, B4, B5, B6, B7, B8, B9, B10, B11, B12, B13, B14, B15, B16, B17, B18, B19, B20, B21, B22, B23, B24, B25, B26, B27, B28, B29, B30, B31, B32, B33, B34, B35,
+	input C0, C1, C2, C3, C4, C5, C6, C7, C8, C9, C10, C11, C12, C13, C14, C15, C16, C17, C18, C19, C20, C21, C22, C23, C24, C25, C26, C27, C28, C29, C30, C31, C32, C33, C34, C35, C36, C37, C38, C39, C40, C41, C42, C43, C44, C45, C46, C47, C48, C49, C50, C51, C52, C53,
+	input CFB0, CFB1, CFB2, CFB3, CFB4, CFB5, CFB6, CFB7, CFB8, CFB9, CFB10, CFB11, CFB12, CFB13, CFB14, CFB15, CFB16, CFB17, CFB18, CFB19, CFB20, CFB21, CFB22, CFB23, CFB24, CFB25, CFB26, CFB27, CFB28, CFB29, CFB30, CFB31, CFB32, CFB33, CFB34, CFB35, CFB36, CFB37, CFB38, CFB39, CFB40, CFB41, CFB42, CFB43, CFB44, CFB45, CFB46, CFB47, CFB48, CFB49, CFB50, CFB51, CFB52, CFB53,
+	input MA0, MA1, MA2, MA3, MA4, MA5, MA6, MA7, MA8, MA9, MA10, MA11, MA12, MA13, MA14, MA15, MA16, MA17, MA18, MA19, MA20, MA21, MA22, MA23, MA24, MA25, MA26, MA27, MA28, MA29, MA30, MA31, MA32, MA33, MA34, MA35,
+	input MB0, MB1, MB2, MB3, MB4, MB5, MB6, MB7, MB8, MB9, MB10, MB11, MB12, MB13, MB14, MB15, MB16, MB17, MB18, MB19, MB20, MB21, MB22, MB23, MB24, MB25, MB26, MB27, MB28, MB29, MB30, MB31, MB32, MB33, MB34, MB35,
+	input CIN0, CIN1, CIN2, CIN3, CIN4, CIN5, CIN6, CIN7, CIN8, CIN9, CIN10, CIN11, CIN12, CIN13, CIN14, CIN15, CIN16, CIN17, CIN18, CIN19, CIN20, CIN21, CIN22, CIN23, CIN24, CIN25, CIN26, CIN27, CIN28, CIN29, CIN30, CIN31, CIN32, CIN33, CIN34, CIN35, CIN36, CIN37, CIN38, CIN39, CIN40, CIN41, CIN42, CIN43, CIN44, CIN45, CIN46, CIN47, CIN48, CIN49, CIN50, CIN51, CIN52, CIN53,
+	input OP0, OP1, OP2, OP3, OP4, OP5, OP6, OP7, OP8, OP9, OP10,
+	output R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, R13, R14, R15, R16, R17, R18, R19, R20, R21, R22, R23, R24, R25, R26, R27, R28, R29, R30, R31, R32, R33, R34, R35, R36, R37, R38, R39, R40, R41, R42, R43, R44, R45, R46, R47, R48, R49, R50, R51, R52, R53,
+	output CO0, CO1, CO2, CO3, CO4, CO5, CO6, CO7, CO8, CO9, CO10, CO11, CO12, CO13, CO14, CO15, CO16, CO17, CO18, CO19, CO20, CO21, CO22, CO23, CO24, CO25, CO26, CO27, CO28, CO29, CO30, CO31, CO32, CO33, CO34, CO35, CO36, CO37, CO38, CO39, CO40, CO41, CO42, CO43, CO44, CO45, CO46, CO47, CO48, CO49, CO50, CO51, CO52, CO53,
+	output EQZ, EQZM, EQOM, EQPAT, EQPATB,
+	output OVER, UNDER, OVERUNDER,
+	output SIGNEDR
+);
+	parameter REG_INPUTC0_CLK = "NONE";
+	parameter REG_INPUTC0_CE = "CE0";
+	parameter REG_INPUTC0_RST = "RST0";
+	parameter REG_INPUTC1_CLK = "NONE";
+	parameter REG_INPUTC1_CE = "CE0";
+	parameter REG_INPUTC1_RST = "RST0";
+	parameter REG_OPCODEOP0_0_CLK = "NONE";
+	parameter REG_OPCODEOP0_0_CE = "CE0";
+	parameter REG_OPCODEOP0_0_RST = "RST0";
+	parameter REG_OPCODEOP1_0_CLK = "NONE";
+	parameter REG_OPCODEOP0_1_CLK = "NONE";
+	parameter REG_OPCODEOP0_1_CE = "CE0";
+	parameter REG_OPCODEOP0_1_RST = "RST0";
+	parameter REG_OPCODEIN_0_CLK = "NONE";
+	parameter REG_OPCODEIN_0_CE = "CE0";
+	parameter REG_OPCODEIN_0_RST = "RST0";
+	parameter REG_OPCODEIN_1_CLK = "NONE";
+	parameter REG_OPCODEIN_1_CE = "CE0";
+	parameter REG_OPCODEIN_1_RST = "RST0";
+	parameter REG_OUTPUT0_CLK = "NONE";
+	parameter REG_OUTPUT0_CE = "CE0";
+	parameter REG_OUTPUT0_RST = "RST0";
+	parameter REG_OUTPUT1_CLK = "NONE";
+	parameter REG_OUTPUT1_CE = "CE0";
+	parameter REG_OUTPUT1_RST = "RST0";
+	parameter REG_FLAG_CLK = "NONE";
+	parameter REG_FLAG_CE = "CE0";
+	parameter REG_FLAG_RST = "RST0";
+	parameter [127:0] MCPAT_SOURCE = "STATIC";
+	parameter [127:0] MASKPAT_SOURCE = "STATIC";
+	parameter MASK01 = "0x00000000000000";
+	parameter REG_INPUTCFB_CLK = "NONE";
+	parameter REG_INPUTCFB_CE = "CE0";
+	parameter REG_INPUTCFB_RST = "RST0";
+	parameter [127:0] CLK0_DIV = "ENABLED";
+	parameter [127:0] CLK1_DIV = "ENABLED";
+	parameter [127:0] CLK2_DIV = "ENABLED";
+	parameter [127:0] CLK3_DIV = "ENABLED";
+	parameter MCPAT = "0x00000000000000";
+	parameter MASKPAT = "0x00000000000000";
+	parameter RNDPAT = "0x00000000000000";
+	parameter [127:0] GSR = "ENABLED";
+	parameter [127:0] RESETMODE = "SYNC";
+	parameter MULT9_MODE = "DISABLED";
+	parameter FORCE_ZERO_BARREL_SHIFT = "DISABLED";
+	parameter LEGACY = "DISABLED";
+endmodule
diff --git a/techlibs/ecp5/synth_ecp5.cc b/techlibs/ecp5/synth_ecp5.cc
index cb6a4c3d8..825e131c4 100644
--- a/techlibs/ecp5/synth_ecp5.cc
+++ b/techlibs/ecp5/synth_ecp5.cc
@@ -203,7 +203,7 @@ struct SynthEcp5Pass : public ScriptPass
 	{
 		if (check_label("begin"))
 		{
-			run("read_verilog -lib +/ecp5/cells_sim.v");
+			run("read_verilog -lib +/ecp5/cells_sim.v +/ecp5/cells_bb.v");
 			run(stringf("hierarchy -check %s", help_mode ? "-top <top>" : top_opt.c_str()));
 		}
 
-- 
cgit v1.2.3


From b65932edc4a00860cafc04f962f2a08dd782b075 Mon Sep 17 00:00:00 2001
From: David Shah <davey1576@gmail.com>
Date: Mon, 22 Oct 2018 16:20:38 +0100
Subject: ecp5: Remove DSP parameters that don't work

Signed-off-by: David Shah <davey1576@gmail.com>
---
 techlibs/ecp5/cells_bb.v | 21 ---------------------
 1 file changed, 21 deletions(-)

(limited to 'techlibs/ecp5')

diff --git a/techlibs/ecp5/cells_bb.v b/techlibs/ecp5/cells_bb.v
index 7ef02ef6a..8644abecd 100644
--- a/techlibs/ecp5/cells_bb.v
+++ b/techlibs/ecp5/cells_bb.v
@@ -27,23 +27,16 @@ module MULT18X18D(
 	parameter REG_INPUTB_CE = "CE0";
 	parameter REG_INPUTB_RST = "RST0";
 	parameter REG_INPUTC_CLK = "NONE";
-	parameter REG_INPUTC_CE = "CE0";
-	parameter REG_INPUTC_RST = "RST0";
 	parameter REG_PIPELINE_CLK = "NONE";
 	parameter REG_PIPELINE_CE = "CE0";
 	parameter REG_PIPELINE_RST = "RST0";
 	parameter REG_OUTPUT_CLK = "NONE";
-	parameter REG_OUTPUT_CE = "CE0";
-	parameter REG_OUTPUT_RST = "RST0";
 	parameter [127:0] CLK0_DIV = "ENABLED";
 	parameter [127:0] CLK1_DIV = "ENABLED";
 	parameter [127:0] CLK2_DIV = "ENABLED";
 	parameter [127:0] CLK3_DIV = "ENABLED";
-	parameter HIGHSPEED_CLK = "NONE";
 	parameter [127:0] GSR = "ENABLED";
-	parameter CAS_MATCH_REG = "FALSE";
 	parameter [127:0] SOURCEB_MODE = "B_SHIFT";
-	parameter [127:0] MULT_BYPASS = "DISABLED";
 	parameter [127:0] RESETMODE = "SYNC";
 endmodule
 
@@ -68,11 +61,7 @@ module ALU54B(
 	output SIGNEDR
 );
 	parameter REG_INPUTC0_CLK = "NONE";
-	parameter REG_INPUTC0_CE = "CE0";
-	parameter REG_INPUTC0_RST = "RST0";
 	parameter REG_INPUTC1_CLK = "NONE";
-	parameter REG_INPUTC1_CE = "CE0";
-	parameter REG_INPUTC1_RST = "RST0";
 	parameter REG_OPCODEOP0_0_CLK = "NONE";
 	parameter REG_OPCODEOP0_0_CE = "CE0";
 	parameter REG_OPCODEOP0_0_RST = "RST0";
@@ -87,20 +76,11 @@ module ALU54B(
 	parameter REG_OPCODEIN_1_CE = "CE0";
 	parameter REG_OPCODEIN_1_RST = "RST0";
 	parameter REG_OUTPUT0_CLK = "NONE";
-	parameter REG_OUTPUT0_CE = "CE0";
-	parameter REG_OUTPUT0_RST = "RST0";
 	parameter REG_OUTPUT1_CLK = "NONE";
-	parameter REG_OUTPUT1_CE = "CE0";
-	parameter REG_OUTPUT1_RST = "RST0";
 	parameter REG_FLAG_CLK = "NONE";
-	parameter REG_FLAG_CE = "CE0";
-	parameter REG_FLAG_RST = "RST0";
 	parameter [127:0] MCPAT_SOURCE = "STATIC";
 	parameter [127:0] MASKPAT_SOURCE = "STATIC";
 	parameter MASK01 = "0x00000000000000";
-	parameter REG_INPUTCFB_CLK = "NONE";
-	parameter REG_INPUTCFB_CE = "CE0";
-	parameter REG_INPUTCFB_RST = "RST0";
 	parameter [127:0] CLK0_DIV = "ENABLED";
 	parameter [127:0] CLK1_DIV = "ENABLED";
 	parameter [127:0] CLK2_DIV = "ENABLED";
@@ -110,7 +90,6 @@ module ALU54B(
 	parameter RNDPAT = "0x00000000000000";
 	parameter [127:0] GSR = "ENABLED";
 	parameter [127:0] RESETMODE = "SYNC";
-	parameter MULT9_MODE = "DISABLED";
 	parameter FORCE_ZERO_BARREL_SHIFT = "DISABLED";
 	parameter LEGACY = "DISABLED";
 endmodule
-- 
cgit v1.2.3


From 1f51332808b5dce76d74a64bd84e4e51c65f6998 Mon Sep 17 00:00:00 2001
From: David Shah <dave@ds0.me>
Date: Wed, 7 Nov 2018 14:56:38 +0000
Subject: ecp5: Adding some blackbox cells

Signed-off-by: David Shah <dave@ds0.me>
---
 techlibs/ecp5/cells_bb.v  | 390 ++++++++++++++++++++++++++++++++++++++++++++++
 techlibs/ecp5/cells_sim.v |   2 +-
 2 files changed, 391 insertions(+), 1 deletion(-)

(limited to 'techlibs/ecp5')

diff --git a/techlibs/ecp5/cells_bb.v b/techlibs/ecp5/cells_bb.v
index 8644abecd..401b976d8 100644
--- a/techlibs/ecp5/cells_bb.v
+++ b/techlibs/ecp5/cells_bb.v
@@ -93,3 +93,393 @@ module ALU54B(
 	parameter FORCE_ZERO_BARREL_SHIFT = "DISABLED";
 	parameter LEGACY = "DISABLED";
 endmodule
+
+(* blackbox *)
+module EHXPLLL (
+	input CLKI, CLKFB,
+	input PHASESEL1, PHASESEL0, PHASEDIR, PHASESTEP, PHASELOADREG,
+	input STDBY, PLLWAKESYNC,
+	input RST, ENCLKOP, ENCLKOS, ENCLKOS2, ENCLKOS3,
+	output CLKOP, CLKOS, CLKOS2, CLKOS3,
+	output LOCK, INTLOCK,
+	output REFCLK, CLKINTFB
+);
+	parameter CLKI_DIV = 1;
+	parameter CLKFB_DIV = 1;
+	parameter CLKOP_DIV = 8;
+	parameter CLKOS_DIV = 8;
+	parameter CLKOS2_DIV = 8;
+	parameter CLKOS3_DIV = 8;
+	parameter CLKOP_ENABLE = "ENABLED";
+	parameter CLKOS_ENABLE = "DISABLED";
+	parameter CLKOS2_ENABLE = "DISABLED";
+	parameter CLKOS3_ENABLE = "DISABLED";
+	parameter CLKOP_CPHASE = 0;
+	parameter CLKOS_CPHASE = 0;
+	parameter CLKOS2_CPHASE = 0;
+	parameter CLKOS3_CPHASE = 0;
+	parameter CLKOP_FPHASE = 0;
+	parameter CLKOS_FPHASE = 0;
+	parameter CLKOS2_FPHASE = 0;
+	parameter CLKOS3_FPHASE = 0;
+	parameter FEEDBK_PATH = "CLKOP";
+	parameter CLKOP_TRIM_POL = "RISING";
+	parameter CLKOP_TRIM_DELAY = 0;
+	parameter CLKOS_TRIM_POL = "RISING";
+	parameter CLKOS_TRIM_DELAY = 0;
+	parameter OUTDIVIDER_MUXA = "DIVA";
+	parameter OUTDIVIDER_MUXB = "DIVB";
+	parameter OUTDIVIDER_MUXC = "DIVC";
+	parameter OUTDIVIDER_MUXD = "DIVD";
+	parameter PLL_LOCK_MODE = 0;
+	parameter PLL_LOCK_DELAY = 200;
+	parameter STDBY_ENABLE = "DISABLED";
+	parameter REFIN_RESET = "DISABLED";
+	parameter SYNC_ENABLE = "DISABLED";
+	parameter INT_LOCK_STICKY = "ENABLED";
+	parameter DPHASE_SOURCE = "DISABLED";
+	parameter PLLRST_ENA = "DISABLED";
+	parameter INTFB_WAKE = "DISABLED";
+endmodule
+
+(* blackbox *)
+module DTR(
+	input STARTPULSE,
+	output DTROUT7, DTROUT6, DTROUT5, DTROUT4, DTROUT3, DTROUT2, DTROUT1, DTROUT0
+);
+endmodule
+
+(* blackbox *)
+module OSCG(
+	output OSC
+);
+parameter DIV = 128;
+endmodule
+
+(* blackbox *)
+module IDDRX1F(
+	input D, SCLK, RST,
+	output Q0, Q1
+);
+	parameter GSR = "ENABLED";
+endmodule
+
+(* blackbox *)
+module ODDRX1F(
+	input SCLK, RST, D0, D1,
+	output Q
+);
+	parameter GSR = "ENABLED";
+endmodule
+
+(* blackbox *)
+module CLKDIVF(
+	input CLKI, RST, ALIGNWD,
+	output CDIVX
+);
+	parameter GSR = "DISABLED";
+	parameter DIV = "2.0";
+endmodule
+
+(* blackbox *)
+module DCCA(
+	input CLKI, CE,
+	output CLKO
+);
+endmodule
+
+(* blackbox *) (* keep *)
+module DCUA(
+	input CH0_HDINP, CH1_HDINP, CH0_HDINN, CH1_HDINN,
+	input D_TXBIT_CLKP_FROM_ND, D_TXBIT_CLKN_FROM_ND, D_SYNC_ND, D_TXPLL_LOL_FROM_ND,
+	input CH0_RX_REFCLK, CH1_RX_REFCLK, CH0_FF_RXI_CLK, CH1_FF_RXI_CLK, CH0_FF_TXI_CLK, CH1_FF_TXI_CLK, CH0_FF_EBRD_CLK, CH1_FF_EBRD_CLK,
+	input CH0_FF_TX_D_0, CH1_FF_TX_D_0, CH0_FF_TX_D_1, CH1_FF_TX_D_1, CH0_FF_TX_D_2, CH1_FF_TX_D_2, CH0_FF_TX_D_3, CH1_FF_TX_D_3,
+	input CH0_FF_TX_D_4, CH1_FF_TX_D_4, CH0_FF_TX_D_5, CH1_FF_TX_D_5, CH0_FF_TX_D_6, CH1_FF_TX_D_6, CH0_FF_TX_D_7, CH1_FF_TX_D_7,
+	input CH0_FF_TX_D_8, CH1_FF_TX_D_8, CH0_FF_TX_D_9, CH1_FF_TX_D_9, CH0_FF_TX_D_10, CH1_FF_TX_D_10, CH0_FF_TX_D_11, CH1_FF_TX_D_11,
+	input CH0_FF_TX_D_12, CH1_FF_TX_D_12, CH0_FF_TX_D_13, CH1_FF_TX_D_13, CH0_FF_TX_D_14, CH1_FF_TX_D_14, CH0_FF_TX_D_15, CH1_FF_TX_D_15,
+	input CH0_FF_TX_D_16, CH1_FF_TX_D_16, CH0_FF_TX_D_17, CH1_FF_TX_D_17, CH0_FF_TX_D_18, CH1_FF_TX_D_18, CH0_FF_TX_D_19, CH1_FF_TX_D_19,
+	input CH0_FF_TX_D_20, CH1_FF_TX_D_20, CH0_FF_TX_D_21, CH1_FF_TX_D_21, CH0_FF_TX_D_22, CH1_FF_TX_D_22, CH0_FF_TX_D_23, CH1_FF_TX_D_23,
+	input CH0_FFC_EI_EN, CH1_FFC_EI_EN, CH0_FFC_PCIE_DET_EN, CH1_FFC_PCIE_DET_EN, CH0_FFC_PCIE_CT, CH1_FFC_PCIE_CT, CH0_FFC_SB_INV_RX, CH1_FFC_SB_INV_RX,
+	input CH0_FFC_ENABLE_CGALIGN, CH1_FFC_ENABLE_CGALIGN, CH0_FFC_SIGNAL_DETECT, CH1_FFC_SIGNAL_DETECT, CH0_FFC_FB_LOOPBACK, CH1_FFC_FB_LOOPBACK, CH0_FFC_SB_PFIFO_LP, CH1_FFC_SB_PFIFO_LP,
+	input CH0_FFC_PFIFO_CLR, CH1_FFC_PFIFO_CLR, CH0_FFC_RATE_MODE_RX, CH1_FFC_RATE_MODE_RX, CH0_FFC_RATE_MODE_TX, CH1_FFC_RATE_MODE_TX, CH0_FFC_DIV11_MODE_RX, CH1_FFC_DIV11_MODE_RX, CH0_FFC_RX_GEAR_MODE, CH1_FFC_RX_GEAR_MODE, CH0_FFC_TX_GEAR_MODE, CH1_FFC_TX_GEAR_MODE,
+	input CH0_FFC_DIV11_MODE_TX, CH1_FFC_DIV11_MODE_TX, CH0_FFC_LDR_CORE2TX_EN, CH1_FFC_LDR_CORE2TX_EN, CH0_FFC_LANE_TX_RST, CH1_FFC_LANE_TX_RST, CH0_FFC_LANE_RX_RST, CH1_FFC_LANE_RX_RST,
+	input CH0_FFC_RRST, CH1_FFC_RRST, CH0_FFC_TXPWDNB, CH1_FFC_TXPWDNB, CH0_FFC_RXPWDNB, CH1_FFC_RXPWDNB, CH0_LDR_CORE2TX, CH1_LDR_CORE2TX,
+	input D_SCIWDATA0, D_SCIWDATA1, D_SCIWDATA2, D_SCIWDATA3, D_SCIWDATA4, D_SCIWDATA5, D_SCIWDATA6, D_SCIWDATA7,
+	input D_SCIADDR0, D_SCIADDR1, D_SCIADDR2, D_SCIADDR3, D_SCIADDR4, D_SCIADDR5, D_SCIENAUX, D_SCISELAUX,
+	input CH0_SCIEN, CH1_SCIEN, CH0_SCISEL, CH1_SCISEL, D_SCIRD, D_SCIWSTN, D_CYAWSTN, D_FFC_SYNC_TOGGLE,
+	input D_FFC_DUAL_RST, D_FFC_MACRO_RST, D_FFC_MACROPDB, D_FFC_TRST, CH0_FFC_CDR_EN_BITSLIP, CH1_FFC_CDR_EN_BITSLIP, D_SCAN_ENABLE, D_SCAN_IN_0,
+	input D_SCAN_IN_1, D_SCAN_IN_2, D_SCAN_IN_3, D_SCAN_IN_4, D_SCAN_IN_5, D_SCAN_IN_6, D_SCAN_IN_7, D_SCAN_MODE,
+	input D_SCAN_RESET, D_CIN0, D_CIN1, D_CIN2, D_CIN3, D_CIN4, D_CIN5, D_CIN6,D_CIN7, D_CIN8, D_CIN9, D_CIN10, D_CIN11,
+	output CH0_HDOUTP, CH1_HDOUTP, CH0_HDOUTN, CH1_HDOUTN, D_TXBIT_CLKP_TO_ND, D_TXBIT_CLKN_TO_ND, D_SYNC_PULSE2ND, D_TXPLL_LOL_TO_ND,
+	output CH0_FF_RX_F_CLK, CH1_FF_RX_F_CLK, CH0_FF_RX_H_CLK, CH1_FF_RX_H_CLK, CH0_FF_TX_F_CLK, CH1_FF_TX_F_CLK, CH0_FF_TX_H_CLK, CH1_FF_TX_H_CLK,
+	output CH0_FF_RX_PCLK, CH1_FF_RX_PCLK, CH0_FF_TX_PCLK, CH1_FF_TX_PCLK, CH0_FF_RX_D_0, CH1_FF_RX_D_0, CH0_FF_RX_D_1, CH1_FF_RX_D_1,
+	output CH0_FF_RX_D_2, CH1_FF_RX_D_2, CH0_FF_RX_D_3, CH1_FF_RX_D_3, CH0_FF_RX_D_4, CH1_FF_RX_D_4, CH0_FF_RX_D_5, CH1_FF_RX_D_5,
+	output CH0_FF_RX_D_6, CH1_FF_RX_D_6, CH0_FF_RX_D_7, CH1_FF_RX_D_7, CH0_FF_RX_D_8, CH1_FF_RX_D_8, CH0_FF_RX_D_9, CH1_FF_RX_D_9,
+	output CH0_FF_RX_D_10, CH1_FF_RX_D_10, CH0_FF_RX_D_11, CH1_FF_RX_D_11, CH0_FF_RX_D_12, CH1_FF_RX_D_12, CH0_FF_RX_D_13, CH1_FF_RX_D_13,
+	output CH0_FF_RX_D_14, CH1_FF_RX_D_14, CH0_FF_RX_D_15, CH1_FF_RX_D_15, CH0_FF_RX_D_16, CH1_FF_RX_D_16, CH0_FF_RX_D_17, CH1_FF_RX_D_17,
+	output CH0_FF_RX_D_18, CH1_FF_RX_D_18, CH0_FF_RX_D_19, CH1_FF_RX_D_19, CH0_FF_RX_D_20, CH1_FF_RX_D_20, CH0_FF_RX_D_21, CH1_FF_RX_D_21,
+	output CH0_FF_RX_D_22, CH1_FF_RX_D_22, CH0_FF_RX_D_23, CH1_FF_RX_D_23, CH0_FFS_PCIE_DONE, CH1_FFS_PCIE_DONE, CH0_FFS_PCIE_CON, CH1_FFS_PCIE_CON,
+	output CH0_FFS_RLOS, CH1_FFS_RLOS, CH0_FFS_LS_SYNC_STATUS, CH1_FFS_LS_SYNC_STATUS, CH0_FFS_CC_UNDERRUN, CH1_FFS_CC_UNDERRUN, CH0_FFS_CC_OVERRUN, CH1_FFS_CC_OVERRUN,
+	output CH0_FFS_RXFBFIFO_ERROR, CH1_FFS_RXFBFIFO_ERROR, CH0_FFS_TXFBFIFO_ERROR, CH1_FFS_TXFBFIFO_ERROR, CH0_FFS_RLOL, CH1_FFS_RLOL, CH0_FFS_SKP_ADDED, CH1_FFS_SKP_ADDED,
+	output CH0_FFS_SKP_DELETED, CH1_FFS_SKP_DELETED, CH0_LDR_RX2CORE, CH1_LDR_RX2CORE, D_SCIRDATA0, D_SCIRDATA1, D_SCIRDATA2, D_SCIRDATA3,
+	output D_SCIRDATA4, D_SCIRDATA5, D_SCIRDATA6, D_SCIRDATA7, D_SCIINT, D_SCAN_OUT_0, D_SCAN_OUT_1, D_SCAN_OUT_2, D_SCAN_OUT_3, D_SCAN_OUT_4, D_SCAN_OUT_5, D_SCAN_OUT_6, D_SCAN_OUT_7,
+	output D_COUT0, D_COUT1, D_COUT2, D_COUT3, D_COUT4, D_COUT5, D_COUT6, D_COUT7, D_COUT8, D_COUT9, D_COUT10, D_COUT11, D_COUT12, D_COUT13, D_COUT14, D_COUT15, D_COUT16, D_COUT17, D_COUT18, D_COUT19,
+
+	input  D_REFCLKI,
+	output D_FFS_PLOL
+);
+	parameter CH0_AUTO_CALIB_EN = "0b0";
+	parameter CH0_AUTO_FACQ_EN = "0b0";
+	parameter CH0_BAND_THRESHOLD = "0b000000";
+	parameter CH0_CALIB_CK_MODE = "0b0";
+	parameter CH0_CC_MATCH_1 = "0b0000000000";
+	parameter CH0_CC_MATCH_2 = "0b0000000000";
+	parameter CH0_CC_MATCH_3 = "0b0000000000";
+	parameter CH0_CC_MATCH_4 = "0b0000000000";
+	parameter CH0_CDR_CNT4SEL = "0b00";
+	parameter CH0_CDR_CNT8SEL = "0b00";
+	parameter CH0_CTC_BYPASS = "0b0";
+	parameter CH0_DCOATDCFG = "0b00";
+	parameter CH0_DCOATDDLY = "0b00";
+	parameter CH0_DCOBYPSATD = "0b0";
+	parameter CH0_DCOCALDIV = "0b000";
+	parameter CH0_DCOCTLGI = "0b000";
+	parameter CH0_DCODISBDAVOID = "0b0";
+	parameter CH0_DCOFLTDAC = "0b00";
+	parameter CH0_DCOFTNRG = "0b000";
+	parameter CH0_DCOIOSTUNE = "0b000";
+	parameter CH0_DCOITUNE = "0b00";
+	parameter CH0_DCOITUNE4LSB = "0b000";
+	parameter CH0_DCOIUPDNX2 = "0b0";
+	parameter CH0_DCONUOFLSB = "0b000";
+	parameter CH0_DCOSCALEI = "0b00";
+	parameter CH0_DCOSTARTVAL = "0b000";
+	parameter CH0_DCOSTEP = "0b00";
+	parameter CH0_DEC_BYPASS = "0b0";
+	parameter CH0_ENABLE_CG_ALIGN = "0b0";
+	parameter CH0_ENC_BYPASS = "0b0";
+	parameter CH0_FF_RX_F_CLK_DIS = "0b0";
+	parameter CH0_FF_RX_H_CLK_EN = "0b0";
+	parameter CH0_FF_TX_F_CLK_DIS = "0b0";
+	parameter CH0_FF_TX_H_CLK_EN = "0b0";
+	parameter CH0_GE_AN_ENABLE = "0b0";
+	parameter CH0_INVERT_RX = "0b0";
+	parameter CH0_INVERT_TX = "0b0";
+	parameter CH0_LDR_CORE2TX_SEL = "0b0";
+	parameter CH0_LDR_RX2CORE_SEL = "0b0";
+	parameter CH0_LEQ_OFFSET_SEL = "0b0";
+	parameter CH0_LEQ_OFFSET_TRIM = "0b000";
+	parameter CH0_LSM_DISABLE = "0b0";
+	parameter CH0_MATCH_2_ENABLE = "0b0";
+	parameter CH0_MATCH_4_ENABLE = "0b0";
+	parameter CH0_MIN_IPG_CNT = "0b00";
+	parameter CH0_PCIE_EI_EN = "0b0";
+	parameter CH0_PCIE_MODE = "0b0";
+	parameter CH0_PCS_DET_TIME_SEL = "0b00";
+	parameter CH0_PDEN_SEL = "0b0";
+	parameter CH0_PRBS_ENABLE = "0b0";
+	parameter CH0_PRBS_LOCK = "0b0";
+	parameter CH0_PRBS_SELECTION = "0b0";
+	parameter CH0_RATE_MODE_RX = "0b0";
+	parameter CH0_RATE_MODE_TX = "0b0";
+	parameter CH0_RCV_DCC_EN = "0b0";
+	parameter CH0_REG_BAND_OFFSET = "0b0000";
+	parameter CH0_REG_BAND_SEL = "0b000000";
+	parameter CH0_REG_IDAC_EN = "0b0";
+	parameter CH0_REG_IDAC_SEL = "0b0000000000";
+	parameter CH0_REQ_EN = "0b0";
+	parameter CH0_REQ_LVL_SET = "0b00";
+	parameter CH0_RIO_MODE = "0b0";
+	parameter CH0_RLOS_SEL = "0b0";
+	parameter CH0_RPWDNB = "0b0";
+	parameter CH0_RTERM_RX = "0b00000";
+	parameter CH0_RTERM_TX = "0b00000";
+	parameter CH0_RXIN_CM = "0b00";
+	parameter CH0_RXTERM_CM = "0b00";
+	parameter CH0_RX_DCO_CK_DIV = "0b000";
+	parameter CH0_RX_DIV11_SEL = "0b0";
+	parameter CH0_RX_GEAR_BYPASS = "0b0";
+	parameter CH0_RX_GEAR_MODE = "0b0";
+	parameter CH0_RX_LOS_CEQ = "0b00";
+	parameter CH0_RX_LOS_EN = "0b0";
+	parameter CH0_RX_LOS_HYST_EN = "0b0";
+	parameter CH0_RX_LOS_LVL = "0b000";
+	parameter CH0_RX_RATE_SEL = "0b0000";
+	parameter CH0_RX_SB_BYPASS = "0b0";
+	parameter CH0_SB_BYPASS = "0b0";
+	parameter CH0_SEL_SD_RX_CLK = "0b0";
+	parameter CH0_TDRV_DAT_SEL = "0b00";
+	parameter CH0_TDRV_POST_EN = "0b0";
+	parameter CH0_TDRV_PRE_EN = "0b0";
+	parameter CH0_TDRV_SLICE0_CUR = "0b000";
+	parameter CH0_TDRV_SLICE0_SEL = "0b00";
+	parameter CH0_TDRV_SLICE1_CUR = "0b000";
+	parameter CH0_TDRV_SLICE1_SEL = "0b00";
+	parameter CH0_TDRV_SLICE2_CUR = "0b00";
+	parameter CH0_TDRV_SLICE2_SEL = "0b00";
+	parameter CH0_TDRV_SLICE3_CUR = "0b00";
+	parameter CH0_TDRV_SLICE3_SEL = "0b00";
+	parameter CH0_TDRV_SLICE4_CUR = "0b00";
+	parameter CH0_TDRV_SLICE4_SEL = "0b00";
+	parameter CH0_TDRV_SLICE5_CUR = "0b00";
+	parameter CH0_TDRV_SLICE5_SEL = "0b00";
+	parameter CH0_TPWDNB = "0b0";
+	parameter CH0_TX_CM_SEL = "0b00";
+	parameter CH0_TX_DIV11_SEL = "0b0";
+	parameter CH0_TX_GEAR_BYPASS = "0b0";
+	parameter CH0_TX_GEAR_MODE = "0b0";
+	parameter CH0_TX_POST_SIGN = "0b0";
+	parameter CH0_TX_PRE_SIGN = "0b0";
+	parameter CH0_UC_MODE = "0b0";
+	parameter CH0_UDF_COMMA_A = "0b0000000000";
+	parameter CH0_UDF_COMMA_B = "0b0000000000";
+	parameter CH0_UDF_COMMA_MASK = "0b0000000000";
+	parameter CH0_WA_BYPASS = "0b0";
+	parameter CH0_WA_MODE = "0b0";
+	parameter CH1_AUTO_CALIB_EN = "0b0";
+	parameter CH1_AUTO_FACQ_EN = "0b0";
+	parameter CH1_BAND_THRESHOLD = "0b000000";
+	parameter CH1_CALIB_CK_MODE = "0b0";
+	parameter CH1_CC_MATCH_1 = "0b0000000000";
+	parameter CH1_CC_MATCH_2 = "0b0000000000";
+	parameter CH1_CC_MATCH_3 = "0b0000000000";
+	parameter CH1_CC_MATCH_4 = "0b0000000000";
+	parameter CH1_CDR_CNT4SEL = "0b00";
+	parameter CH1_CDR_CNT8SEL = "0b00";
+	parameter CH1_CTC_BYPASS = "0b0";
+	parameter CH1_DCOATDCFG = "0b00";
+	parameter CH1_DCOATDDLY = "0b00";
+	parameter CH1_DCOBYPSATD = "0b0";
+	parameter CH1_DCOCALDIV = "0b000";
+	parameter CH1_DCOCTLGI = "0b000";
+	parameter CH1_DCODISBDAVOID = "0b0";
+	parameter CH1_DCOFLTDAC = "0b00";
+	parameter CH1_DCOFTNRG = "0b000";
+	parameter CH1_DCOIOSTUNE = "0b000";
+	parameter CH1_DCOITUNE = "0b00";
+	parameter CH1_DCOITUNE4LSB = "0b000";
+	parameter CH1_DCOIUPDNX2 = "0b0";
+	parameter CH1_DCONUOFLSB = "0b000";
+	parameter CH1_DCOSCALEI = "0b00";
+	parameter CH1_DCOSTARTVAL = "0b000";
+	parameter CH1_DCOSTEP = "0b00";
+	parameter CH1_DEC_BYPASS = "0b0";
+	parameter CH1_ENABLE_CG_ALIGN = "0b0";
+	parameter CH1_ENC_BYPASS = "0b0";
+	parameter CH1_FF_RX_F_CLK_DIS = "0b0";
+	parameter CH1_FF_RX_H_CLK_EN = "0b0";
+	parameter CH1_FF_TX_F_CLK_DIS = "0b0";
+	parameter CH1_FF_TX_H_CLK_EN = "0b0";
+	parameter CH1_GE_AN_ENABLE = "0b0";
+	parameter CH1_INVERT_RX = "0b0";
+	parameter CH1_INVERT_TX = "0b0";
+	parameter CH1_LDR_CORE2TX_SEL = "0b0";
+	parameter CH1_LDR_RX2CORE_SEL = "0b0";
+	parameter CH1_LEQ_OFFSET_SEL = "0b0";
+	parameter CH1_LEQ_OFFSET_TRIM = "0b000";
+	parameter CH1_LSM_DISABLE = "0b0";
+	parameter CH1_MATCH_2_ENABLE = "0b0";
+	parameter CH1_MATCH_4_ENABLE = "0b0";
+	parameter CH1_MIN_IPG_CNT = "0b00";
+	parameter CH1_PCIE_EI_EN = "0b0";
+	parameter CH1_PCIE_MODE = "0b0";
+	parameter CH1_PCS_DET_TIME_SEL = "0b00";
+	parameter CH1_PDEN_SEL = "0b0";
+	parameter CH1_PRBS_ENABLE = "0b0";
+	parameter CH1_PRBS_LOCK = "0b0";
+	parameter CH1_PRBS_SELECTION = "0b0";
+	parameter CH1_RATE_MODE_RX = "0b0";
+	parameter CH1_RATE_MODE_TX = "0b0";
+	parameter CH1_RCV_DCC_EN = "0b0";
+	parameter CH1_REG_BAND_OFFSET = "0b0000";
+	parameter CH1_REG_BAND_SEL = "0b000000";
+	parameter CH1_REG_IDAC_EN = "0b0";
+	parameter CH1_REG_IDAC_SEL = "0b0000000000";
+	parameter CH1_REQ_EN = "0b0";
+	parameter CH1_REQ_LVL_SET = "0b00";
+	parameter CH1_RIO_MODE = "0b0";
+	parameter CH1_RLOS_SEL = "0b0";
+	parameter CH1_RPWDNB = "0b0";
+	parameter CH1_RTERM_RX = "0b00000";
+	parameter CH1_RTERM_TX = "0b00000";
+	parameter CH1_RXIN_CM = "0b00";
+	parameter CH1_RXTERM_CM = "0b00";
+	parameter CH1_RX_DCO_CK_DIV = "0b000";
+	parameter CH1_RX_DIV11_SEL = "0b0";
+	parameter CH1_RX_GEAR_BYPASS = "0b0";
+	parameter CH1_RX_GEAR_MODE = "0b0";
+	parameter CH1_RX_LOS_CEQ = "0b00";
+	parameter CH1_RX_LOS_EN = "0b0";
+	parameter CH1_RX_LOS_HYST_EN = "0b0";
+	parameter CH1_RX_LOS_LVL = "0b000";
+	parameter CH1_RX_RATE_SEL = "0b0000";
+	parameter CH1_RX_SB_BYPASS = "0b0";
+	parameter CH1_SB_BYPASS = "0b0";
+	parameter CH1_SEL_SD_RX_CLK = "0b0";
+	parameter CH1_TDRV_DAT_SEL = "0b00";
+	parameter CH1_TDRV_POST_EN = "0b0";
+	parameter CH1_TDRV_PRE_EN = "0b0";
+	parameter CH1_TDRV_SLICE0_CUR = "0b000";
+	parameter CH1_TDRV_SLICE0_SEL = "0b00";
+	parameter CH1_TDRV_SLICE1_CUR = "0b000";
+	parameter CH1_TDRV_SLICE1_SEL = "0b00";
+	parameter CH1_TDRV_SLICE2_CUR = "0b00";
+	parameter CH1_TDRV_SLICE2_SEL = "0b00";
+	parameter CH1_TDRV_SLICE3_CUR = "0b00";
+	parameter CH1_TDRV_SLICE3_SEL = "0b00";
+	parameter CH1_TDRV_SLICE4_CUR = "0b00";
+	parameter CH1_TDRV_SLICE4_SEL = "0b00";
+	parameter CH1_TDRV_SLICE5_CUR = "0b00";
+	parameter CH1_TDRV_SLICE5_SEL = "0b00";
+	parameter CH1_TPWDNB = "0b0";
+	parameter CH1_TX_CM_SEL = "0b00";
+	parameter CH1_TX_DIV11_SEL = "0b0";
+	parameter CH1_TX_GEAR_BYPASS = "0b0";
+	parameter CH1_TX_GEAR_MODE = "0b0";
+	parameter CH1_TX_POST_SIGN = "0b0";
+	parameter CH1_TX_PRE_SIGN = "0b0";
+	parameter CH1_UC_MODE = "0b0";
+	parameter CH1_UDF_COMMA_A = "0b0000000000";
+	parameter CH1_UDF_COMMA_B = "0b0000000000";
+	parameter CH1_UDF_COMMA_MASK = "0b0000000000";
+	parameter CH1_WA_BYPASS = "0b0";
+	parameter CH1_WA_MODE = "0b0";
+	parameter D_BITCLK_FROM_ND_EN = "0b0";
+	parameter D_BITCLK_LOCAL_EN = "0b0";
+	parameter D_BITCLK_ND_EN = "0b0";
+	parameter D_BUS8BIT_SEL = "0b0";
+	parameter D_CDR_LOL_SET = "0b00";
+	parameter D_CMUSETBIASI = "0b00";
+	parameter D_CMUSETI4CPP = "0b0000";
+	parameter D_CMUSETI4CPZ = "0b0000";
+	parameter D_CMUSETI4VCO = "0b00";
+	parameter D_CMUSETICP4P = "0b00";
+	parameter D_CMUSETICP4Z = "0b000";
+	parameter D_CMUSETINITVCT = "0b00";
+	parameter D_CMUSETISCL4VCO = "0b000";
+	parameter D_CMUSETP1GM = "0b000";
+	parameter D_CMUSETP2AGM = "0b000";
+	parameter D_CMUSETZGM = "0b000";
+	parameter D_DCO_CALIB_TIME_SEL = "0b00";
+	parameter D_HIGH_MARK = "0b0000";
+	parameter D_IB_PWDNB = "0b0";
+	parameter D_ISETLOS = "0b00000000";
+	parameter D_LOW_MARK = "0b0000";
+	parameter D_MACROPDB = "0b0";
+	parameter D_PD_ISET = "0b00";
+	parameter D_PLL_LOL_SET = "0b00";
+	parameter D_REFCK_MODE = "0b000";
+	parameter D_REQ_ISET = "0b000";
+	parameter D_RG_EN = "0b0";
+	parameter D_RG_SET = "0b00";
+	parameter D_SETICONST_AUX = "0b00";
+	parameter D_SETICONST_CH = "0b00";
+	parameter D_SETIRPOLY_AUX = "0b00";
+	parameter D_SETIRPOLY_CH = "0b00";
+	parameter D_SETPLLRC = "0b000000";
+	parameter D_SYNC_LOCAL_EN = "0b0";
+	parameter D_SYNC_ND_EN = "0b0";
+	parameter D_TXPLL_PWDNB = "0b0";
+	parameter D_TX_VCO_CK_DIV = "0b000";
+	parameter D_XGE_MODE = "0b0";
+endmodule
diff --git a/techlibs/ecp5/cells_sim.v b/techlibs/ecp5/cells_sim.v
index 6e4b0a5ac..507ab1beb 100644
--- a/techlibs/ecp5/cells_sim.v
+++ b/techlibs/ecp5/cells_sim.v
@@ -257,7 +257,7 @@ assign O = I;
 endmodule
 
 // ---------------------------------------
-
+(* keep *)
 module TRELLIS_IO(
 	inout B,
 	input I,
-- 
cgit v1.2.3


From 960c8794fa0da7c0ea8b6bf39bf309425fab17b3 Mon Sep 17 00:00:00 2001
From: David Shah <dave@ds0.me>
Date: Fri, 9 Nov 2018 15:18:30 +0000
Subject: ecp5: Add blackboxes for ancillary DCU cells

Signed-off-by: David Shah <dave@ds0.me>
---
 techlibs/ecp5/cells_bb.v | 18 ++++++++++++++++++
 1 file changed, 18 insertions(+)

(limited to 'techlibs/ecp5')

diff --git a/techlibs/ecp5/cells_bb.v b/techlibs/ecp5/cells_bb.v
index 401b976d8..2585c14a9 100644
--- a/techlibs/ecp5/cells_bb.v
+++ b/techlibs/ecp5/cells_bb.v
@@ -483,3 +483,21 @@ module DCUA(
 	parameter D_TX_VCO_CK_DIV = "0b000";
 	parameter D_XGE_MODE = "0b0";
 endmodule
+
+(* blackbox *)
+module EXTREFB (
+	input  REFCLKP, REFCLKN,
+	output REFCLKO
+);
+	parameter REFCK_PWDNB = "0b0";
+	parameter REFCK_RTERM = "0b0";
+	parameter REFCK_DCBIAS_EN = "0b0";
+endmodule
+
+(* blackbox *)
+module PCSCLKDIV (
+	input CLKI, RST, SEL2, SEL1, SEL0,
+	output CDIV1, CDIVX
+);
+	parameter GSR = "DISABLED";
+endmodule
-- 
cgit v1.2.3


From fae3e645a25550be1879b9320a82f1abc54a668e Mon Sep 17 00:00:00 2001
From: David Shah <dave@ds0.me>
Date: Fri, 9 Nov 2018 18:25:42 +0000
Subject: ecp5: Add 'fake' DCU parameters

Signed-off-by: David Shah <dave@ds0.me>
---
 techlibs/ecp5/cells_bb.v | 11 +++++++++++
 1 file changed, 11 insertions(+)

(limited to 'techlibs/ecp5')

diff --git a/techlibs/ecp5/cells_bb.v b/techlibs/ecp5/cells_bb.v
index 2585c14a9..057f9d737 100644
--- a/techlibs/ecp5/cells_bb.v
+++ b/techlibs/ecp5/cells_bb.v
@@ -482,6 +482,17 @@ module DCUA(
 	parameter D_TXPLL_PWDNB = "0b0";
 	parameter D_TX_VCO_CK_DIV = "0b000";
 	parameter D_XGE_MODE = "0b0";
+
+// These parameters don't do anything but are
+// needed for compatability with Diamond
+	parameter D_TX_MAX_RATE = "2.5";
+	parameter D_RX_MAX_RATE = "2.5";
+	parameter CH0_TXAMPLITUDE = "0d1300";
+	parameter CH1_TXAMPLITUDE = "0d1300";
+	parameter CH0_PROTOCOL = "8B10B";
+	parameter CH1_PROTOCOL = "8B10B";
+	parameter CH0_CDR_MAX_RATE = "2.5";
+	parameter CH1_CDR_MAX_RATE = "2.5";
 endmodule
 
 (* blackbox *)
-- 
cgit v1.2.3


From ebe9351f82279f83ef16a24faac9853d40b3ece1 Mon Sep 17 00:00:00 2001
From: Larry Doolittle <ldoolitt@recycle.lbl.gov>
Date: Fri, 28 Dec 2018 08:21:53 -0800
Subject: Fix 7 instances of add_share_file to add_gen_share_file

in techlibs/ecp5/Makefile.inc to permit out-of-tree builds
---
 techlibs/ecp5/Makefile.inc | 16 ++++++++--------
 1 file changed, 8 insertions(+), 8 deletions(-)

(limited to 'techlibs/ecp5')

diff --git a/techlibs/ecp5/Makefile.inc b/techlibs/ecp5/Makefile.inc
index b23d5c70e..8df02be5f 100644
--- a/techlibs/ecp5/Makefile.inc
+++ b/techlibs/ecp5/Makefile.inc
@@ -34,11 +34,11 @@ techlibs/ecp5/bram_conn_4.vh: techlibs/ecp5/brams_connect.mk
 techlibs/ecp5/bram_conn_9.vh: techlibs/ecp5/brams_connect.mk
 techlibs/ecp5/bram_conn_18.vh: techlibs/ecp5/brams_connect.mk
 
-$(eval $(call add_share_file,share/ecp5,techlibs/ecp5/bram_init_1_2_4.vh))
-$(eval $(call add_share_file,share/ecp5,techlibs/ecp5/bram_init_9_18_36.vh))
-
-$(eval $(call add_share_file,share/ecp5,techlibs/ecp5/bram_conn_1.vh))
-$(eval $(call add_share_file,share/ecp5,techlibs/ecp5/bram_conn_2.vh))
-$(eval $(call add_share_file,share/ecp5,techlibs/ecp5/bram_conn_4.vh))
-$(eval $(call add_share_file,share/ecp5,techlibs/ecp5/bram_conn_9.vh))
-$(eval $(call add_share_file,share/ecp5,techlibs/ecp5/bram_conn_18.vh))
+$(eval $(call add_gen_share_file,share/ecp5,techlibs/ecp5/bram_init_1_2_4.vh))
+$(eval $(call add_gen_share_file,share/ecp5,techlibs/ecp5/bram_init_9_18_36.vh))
+
+$(eval $(call add_gen_share_file,share/ecp5,techlibs/ecp5/bram_conn_1.vh))
+$(eval $(call add_gen_share_file,share/ecp5,techlibs/ecp5/bram_conn_2.vh))
+$(eval $(call add_gen_share_file,share/ecp5,techlibs/ecp5/bram_conn_4.vh))
+$(eval $(call add_gen_share_file,share/ecp5,techlibs/ecp5/bram_conn_9.vh))
+$(eval $(call add_gen_share_file,share/ecp5,techlibs/ecp5/bram_conn_18.vh))
-- 
cgit v1.2.3


From efa278e232d20ea080743801bd91d55ec62955cf Mon Sep 17 00:00:00 2001
From: whitequark <whitequark@whitequark.org>
Date: Fri, 7 Dec 2018 19:14:07 +0000
Subject: Fix typographical and grammatical errors and inconsistencies.

The initial list of hits was generated with the codespell command
below, and each hit was evaluated and fixed manually while taking
context into consideration.

    DIRS="kernel/ frontends/ backends/ passes/ techlibs/"
    DIRS="${DIRS} libs/ezsat/ libs/subcircuit"
    codespell $DIRS -S *.o -L upto,iff,thru,synopsys,uint

More hits were found by looking through comments and strings manually.
---
 techlibs/ecp5/cells_bb.v    | 2 +-
 techlibs/ecp5/synth_ecp5.cc | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

(limited to 'techlibs/ecp5')

diff --git a/techlibs/ecp5/cells_bb.v b/techlibs/ecp5/cells_bb.v
index 057f9d737..425d62d24 100644
--- a/techlibs/ecp5/cells_bb.v
+++ b/techlibs/ecp5/cells_bb.v
@@ -484,7 +484,7 @@ module DCUA(
 	parameter D_XGE_MODE = "0b0";
 
 // These parameters don't do anything but are
-// needed for compatability with Diamond
+// needed for compatibility with Diamond
 	parameter D_TX_MAX_RATE = "2.5";
 	parameter D_RX_MAX_RATE = "2.5";
 	parameter CH0_TXAMPLITUDE = "0d1300";
diff --git a/techlibs/ecp5/synth_ecp5.cc b/techlibs/ecp5/synth_ecp5.cc
index 825e131c4..2e9176a84 100644
--- a/techlibs/ecp5/synth_ecp5.cc
+++ b/techlibs/ecp5/synth_ecp5.cc
@@ -189,7 +189,7 @@ struct SynthEcp5Pass : public ScriptPass
 		extra_args(args, argidx, design);
 
 		if (!design->full_selection())
-			log_cmd_error("This comannd only operates on fully selected designs!\n");
+			log_cmd_error("This command only operates on fully selected designs!\n");
 
 		log_header(design, "Executing SYNTH_ECP5 pass.\n");
 		log_push();
-- 
cgit v1.2.3


From 01ea72f53a9707d741a1178d0ac4c4f69d6b65db Mon Sep 17 00:00:00 2001
From: David Shah <dave@ds0.me>
Date: Mon, 21 Jan 2019 12:33:47 +0000
Subject: ecp5: Increase threshold for ALU mapping

Signed-off-by: David Shah <dave@ds0.me>
---
 techlibs/ecp5/arith_map.v | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'techlibs/ecp5')

diff --git a/techlibs/ecp5/arith_map.v b/techlibs/ecp5/arith_map.v
index 1094c5f8a..eb7947601 100644
--- a/techlibs/ecp5/arith_map.v
+++ b/techlibs/ecp5/arith_map.v
@@ -33,7 +33,7 @@ module _80_ecp5_alu (A, B, CI, BI, X, Y, CO);
 	input CI, BI;
 	output [Y_WIDTH-1:0] CO;
 
-	wire _TECHMAP_FAIL_ = Y_WIDTH <= 2;
+	wire _TECHMAP_FAIL_ = Y_WIDTH <= 4;
 
 	wire [Y_WIDTH-1:0] A_buf, B_buf;
 	\$pos #(.A_SIGNED(A_SIGNED), .A_WIDTH(A_WIDTH), .Y_WIDTH(Y_WIDTH)) A_conv (.A(A), .Y(A_buf));
-- 
cgit v1.2.3


From d8003e87d1c5962e660ce84150239444b7fb037d Mon Sep 17 00:00:00 2001
From: David Shah <dave@ds0.me>
Date: Mon, 21 Jan 2019 12:34:34 +0000
Subject: ecp5: More blackboxes

Signed-off-by: David Shah <dave@ds0.me>
---
 techlibs/ecp5/cells_bb.v | 17 +++++++++++++++++
 1 file changed, 17 insertions(+)

(limited to 'techlibs/ecp5')

diff --git a/techlibs/ecp5/cells_bb.v b/techlibs/ecp5/cells_bb.v
index 425d62d24..32fb5c1ef 100644
--- a/techlibs/ecp5/cells_bb.v
+++ b/techlibs/ecp5/cells_bb.v
@@ -156,6 +156,23 @@ module OSCG(
 parameter DIV = 128;
 endmodule
 
+(* blackbox *) (* keep *)
+module USRMCLK(
+	input USRMCLKI, USRMCLKTS,
+	output USRMCLKO
+);
+endmodule
+
+(* blackbox *) (* keep *)
+module JTAGG(
+	input TCK, TMS, TDI, JTDO2, JTDO1,
+	output TDO, JTDI, JTCK, JRTI2, JRTI1,
+	output JSHIFT, JUPDATE, JRSTN, JCE2, JCE1
+);
+parameter ER1 = "ENABLED";
+parameter ER2 = "ENABLED";
+endmodule
+
 (* blackbox *)
 module IDDRX1F(
 	input D, SCLK, RST,
-- 
cgit v1.2.3


From ee8c9e854f0b5f6500d030d4c700b29f042fb57f Mon Sep 17 00:00:00 2001
From: David Shah <dave@ds0.me>
Date: Mon, 21 Jan 2019 12:35:22 +0000
Subject: ecp5: Add LSRMODE to flipflops for PRLD support

Signed-off-by: David Shah <dave@ds0.me>
---
 techlibs/ecp5/cells_sim.v | 23 ++++++++++++++++-------
 1 file changed, 16 insertions(+), 7 deletions(-)

(limited to 'techlibs/ecp5')

diff --git a/techlibs/ecp5/cells_sim.v b/techlibs/ecp5/cells_sim.v
index 507ab1beb..ca5d020f3 100644
--- a/techlibs/ecp5/cells_sim.v
+++ b/techlibs/ecp5/cells_sim.v
@@ -203,13 +203,14 @@ endmodule
 
 // ---------------------------------------
 
-module TRELLIS_FF(input CLK, LSR, CE, DI, output reg Q);
+module TRELLIS_FF(input CLK, LSR, CE, DI, M, output reg Q);
 	parameter GSR = "ENABLED";
 	parameter [127:0] CEMUX = "1";
 	parameter CLKMUX = "CLK";
 	parameter LSRMUX = "LSR";
 	parameter SRMODE = "LSR_OVER_CE";
 	parameter REGSET = "RESET";
+	parameter [127:0] LSRMODE = "LSR";
 
 	reg muxce;
 	always @(*)
@@ -222,8 +223,12 @@ module TRELLIS_FF(input CLK, LSR, CE, DI, output reg Q);
 
 	wire muxlsr = (LSRMUX == "INV") ? ~LSR : LSR;
 	wire muxclk = (CLKMUX == "INV") ? ~CLK : CLK;
-
-	localparam srval = (REGSET == "SET") ? 1'b1 : 1'b0;
+	generate
+		if (LSRMODE == "PRLD")
+			wire srval = M;
+		else
+			localparam srval = (REGSET == "SET") ? 1'b1 : 1'b0;
+	endgenerate
 
 	initial Q = srval;
 
@@ -339,6 +344,8 @@ module TRELLIS_SLICE(
 	parameter REG1_SD = "0";
 	parameter REG0_REGSET = "RESET";
 	parameter REG1_REGSET = "RESET";
+	parameter REG0_LSRMODE = "LSR";
+	parameter REG1_LSRMODE = "LSR";
 	parameter [127:0] CCU2_INJECT1_0 = "NO";
 	parameter [127:0] CCU2_INJECT1_1 = "NO";
 	parameter WREMUX = "WRE";
@@ -428,10 +435,11 @@ module TRELLIS_SLICE(
 		.CLKMUX(CLKMUX),
 		.LSRMUX(LSRMUX),
 		.SRMODE(SRMODE),
-		.REGSET(REG0_REGSET)
+		.REGSET(REG0_REGSET),
+		.LSRMODE(REG0_LSRMODE)
 	) ff_0 (
 		.CLK(CLK), .LSR(LSR), .CE(CE),
-		.DI(muxdi0),
+		.DI(muxdi0), .M(M0),
 		.Q(Q0)
 	);
 	TRELLIS_FF #(
@@ -440,10 +448,11 @@ module TRELLIS_SLICE(
 		.CLKMUX(CLKMUX),
 		.LSRMUX(LSRMUX),
 		.SRMODE(SRMODE),
-		.REGSET(REG1_REGSET)
+		.REGSET(REG1_REGSET),
+		.LSRMODE(REG1_LSRMODE)
 	) ff_1 (
 		.CLK(CLK), .LSR(LSR), .CE(CE),
-		.DI(muxdi1),
+		.DI(muxdi1), .M(M1),
 		.Q(Q1)
 	);
 endmodule
-- 
cgit v1.2.3


From 549b8e74b2cef41a23e609bdb65c5b04b3141a61 Mon Sep 17 00:00:00 2001
From: David Shah <dave@ds0.me>
Date: Fri, 30 Nov 2018 19:29:03 +0000
Subject: ecp5: Support for flipflop initialisation

Signed-off-by: David Shah <dave@ds0.me>
---
 techlibs/ecp5/Makefile.inc   |   2 +-
 techlibs/ecp5/ecp5_ffinit.cc | 198 +++++++++++++++++++++++++++++++++++++++++++
 techlibs/ecp5/synth_ecp5.cc  |   3 -
 3 files changed, 199 insertions(+), 4 deletions(-)
 create mode 100644 techlibs/ecp5/ecp5_ffinit.cc

(limited to 'techlibs/ecp5')

diff --git a/techlibs/ecp5/Makefile.inc b/techlibs/ecp5/Makefile.inc
index 8df02be5f..4db087e87 100644
--- a/techlibs/ecp5/Makefile.inc
+++ b/techlibs/ecp5/Makefile.inc
@@ -1,5 +1,5 @@
 
-OBJS += techlibs/ecp5/synth_ecp5.o
+OBJS += techlibs/ecp5/synth_ecp5.o techlibs/ecp5/ecp5_ffinit.o
 
 $(eval $(call add_share_file,share/ecp5,techlibs/ecp5/cells_map.v))
 $(eval $(call add_share_file,share/ecp5,techlibs/ecp5/cells_sim.v))
diff --git a/techlibs/ecp5/ecp5_ffinit.cc b/techlibs/ecp5/ecp5_ffinit.cc
new file mode 100644
index 000000000..02945fff4
--- /dev/null
+++ b/techlibs/ecp5/ecp5_ffinit.cc
@@ -0,0 +1,198 @@
+/*
+ *  yosys -- Yosys Open SYnthesis Suite
+ *
+ *  Copyright (C) 2012  Clifford Wolf <clifford@clifford.at>
+ *  Copyright (C) 2018-19  David Shah <david@symbioticeda.com>
+ *
+ *  Permission to use, copy, modify, and/or distribute this software for any
+ *  purpose with or without fee is hereby granted, provided that the above
+ *  copyright notice and this permission notice appear in all copies.
+ *
+ *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ */
+
+#include "kernel/yosys.h"
+#include "kernel/sigtools.h"
+
+USING_YOSYS_NAMESPACE
+PRIVATE_NAMESPACE_BEGIN
+
+struct Ecp5FfinitPass : public Pass {
+	Ecp5FfinitPass() : Pass("ecp5_ffinit", "ECP5: handle FF init values") { }
+	void help() YS_OVERRIDE
+	{
+		//   |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
+		log("\n");
+		log("    ecp5_ffinit [options] [selection]\n");
+		log("\n");
+		log("Remove init values for FF output signals when equal to reset value.\n");
+		log("If reset is not used, set the reset value to the init value, otherwise\n");
+		log("unmap out the reset (if not an async reset).\n");
+	}
+	void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
+	{
+		log_header(design, "Executing ECP5_FFINIT pass (implement FF init values).\n");
+
+		size_t argidx;
+		for (argidx = 1; argidx < args.size(); argidx++)
+		{
+			// if (args[argidx] == "-singleton") {
+			// 	singleton_mode = true;
+			// 	continue;
+			// }
+			break;
+		}
+		extra_args(args, argidx, design);
+
+		for (auto module : design->selected_modules())
+		{
+			log("Handling FF init values in %s.\n", log_id(module));
+
+			SigMap sigmap(module);
+			pool<Wire*> init_wires;
+			dict<SigBit, State> initbits;
+			dict<SigBit, SigBit> initbit_to_wire;
+			pool<SigBit> handled_initbits;
+
+			for (auto wire : module->selected_wires())
+			{
+				if (wire->attributes.count("\\init") == 0)
+					continue;
+
+				SigSpec wirebits = sigmap(wire);
+				Const initval = wire->attributes.at("\\init");
+				init_wires.insert(wire);
+
+				for (int i = 0; i < GetSize(wirebits) && i < GetSize(initval); i++)
+				{
+					SigBit bit = wirebits[i];
+					State val = initval[i];
+
+					if (val != State::S0 && val != State::S1)
+						continue;
+
+					if (initbits.count(bit)) {
+						if (initbits.at(bit) != val)
+							log_error("Conflicting init values for signal %s (%s = %s, %s = %s).\n",
+									log_signal(bit), log_signal(SigBit(wire, i)), log_signal(val),
+									log_signal(initbit_to_wire[bit]), log_signal(initbits.at(bit)));
+						continue;
+					}
+
+					initbits[bit] = val;
+					initbit_to_wire[bit] = SigBit(wire, i);
+				}
+			}
+			for (auto cell : module->selected_cells())
+			{
+				if (cell->type != "\\TRELLIS_FF")
+					continue;
+				SigSpec sig_d = cell->getPort("\\DI");
+				SigSpec sig_q = cell->getPort("\\Q");
+				SigSpec sig_lsr = cell->getPort("\\LSR");
+
+				if (GetSize(sig_d) < 1 || GetSize(sig_q) < 1)
+					continue;
+
+				SigBit bit_d = sigmap(sig_d[0]);
+				SigBit bit_q = sigmap(sig_q[0]);
+
+				std::string regset = "RESET";
+				if (cell->hasParam("\\REGSET"))
+					regset = cell->getParam("\\REGSET").decode_string();
+				State resetState;
+				if (regset == "SET")
+					resetState = State::S1;
+				else if (regset == "RESET")
+					resetState = State::S0;
+				else
+					log_error("FF cell %s has illegal REGSET value %s.\n",
+						log_id(cell), regset.c_str());
+
+				if (!initbits.count(bit_q))
+					continue;
+
+				State val = initbits.at(bit_q);
+
+				log("FF init value for cell %s (%s): %s = %c\n", log_id(cell), log_id(cell->type),
+						log_signal(bit_q), val != State::S0 ? '1' : '0');
+				// Initval is the same as the reset state. Matches hardware, nowt more to do
+				if (val == resetState) {
+					handled_initbits.insert(bit_q);
+					continue;
+				}
+
+				if (GetSize(sig_lsr) >= 1 && sig_lsr[0] != State::S0) {
+					std::string srmode = "LSR_OVER_CE";
+					if (cell->hasParam("\\SRMODE"))
+						srmode = cell->getParam("\\SRMODE").decode_string();
+					if (srmode == "ASYNC") {
+						log("Async reset value %c for FF cell %s inconsistent with init value %c.\n",
+							resetState != State::S0 ? '1' : '0', log_id(cell), val != State::S0 ? '1' : '0');
+					} else {
+						SigBit bit_lsr = sigmap(sig_lsr[0]);
+						Wire *new_bit_d = module->addWire(NEW_ID);
+						if (resetState == State::S0) {
+							module->addAndnotGate(NEW_ID, bit_d, bit_lsr, new_bit_d);
+						} else {
+							module->addOrGate(NEW_ID, bit_d, bit_lsr, new_bit_d);
+						}
+
+						cell->setPort("\\DI", new_bit_d);
+						cell->setPort("\\LSR", State::S0);
+
+						if(cell->hasPort("\\CE")) {
+							std::string cemux = "CE";
+							if (cell->hasParam("\\CEMUX"))
+								cemux = cell->getParam("\\CEMUX").decode_string();
+							SigSpec sig_ce = cell->getPort("\\CE");
+							if (GetSize(sig_ce) >= 1) {
+								SigBit bit_ce = sigmap(sig_ce[0]);
+								Wire *new_bit_ce = module->addWire(NEW_ID);
+								if (cemux == "INV")
+									module->addAndnotGate(NEW_ID, bit_ce, bit_lsr, new_bit_ce);
+								else
+									module->addOrGate(NEW_ID, bit_ce, bit_lsr, new_bit_ce);
+								cell->setPort("\\CE", new_bit_ce);
+							}
+						}
+						cell->setParam("\\REGSET", val != State::S0 ? Const("SET") : Const("RESET"));
+						handled_initbits.insert(bit_q);
+					}
+				} else {
+					cell->setParam("\\REGSET", val != State::S0 ? Const("SET") : Const("RESET"));
+					handled_initbits.insert(bit_q);
+				}
+			}
+
+			for (auto wire : init_wires)
+			{
+				if (wire->attributes.count("\\init") == 0)
+					continue;
+
+				SigSpec wirebits = sigmap(wire);
+				Const &initval = wire->attributes.at("\\init");
+				bool remove_attribute = true;
+
+				for (int i = 0; i < GetSize(wirebits) && i < GetSize(initval); i++) {
+					if (handled_initbits.count(wirebits[i]))
+						initval[i] = State::Sx;
+					else if (initval[i] != State::Sx)
+						remove_attribute = false;
+				}
+
+				if (remove_attribute)
+					wire->attributes.erase("\\init");
+			}
+		}
+	}
+} Ecp5FfinitPass;
+
+PRIVATE_NAMESPACE_END
diff --git a/techlibs/ecp5/synth_ecp5.cc b/techlibs/ecp5/synth_ecp5.cc
index 2e9176a84..835f10d8c 100644
--- a/techlibs/ecp5/synth_ecp5.cc
+++ b/techlibs/ecp5/synth_ecp5.cc
@@ -255,10 +255,7 @@ struct SynthEcp5Pass : public ScriptPass
 			run("techmap -D NO_LUT -map +/ecp5/cells_map.v");
 			run("opt_expr -mux_undef");
 			run("simplemap");
-			// TODO
-#if 0
 			run("ecp5_ffinit");
-#endif
 		}
 
 		if (check_label("map_luts"))
-- 
cgit v1.2.3


From 95789c61360d3842265409bd948115f471e005b4 Mon Sep 17 00:00:00 2001
From: David Shah <davey1576@gmail.com>
Date: Wed, 6 Feb 2019 22:20:39 +0100
Subject: ecp5: Use abc -dress

Signed-off-by: David Shah <davey1576@gmail.com>
---
 techlibs/ecp5/synth_ecp5.cc | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

(limited to 'techlibs/ecp5')

diff --git a/techlibs/ecp5/synth_ecp5.cc b/techlibs/ecp5/synth_ecp5.cc
index 2e9176a84..bda03d251 100644
--- a/techlibs/ecp5/synth_ecp5.cc
+++ b/techlibs/ecp5/synth_ecp5.cc
@@ -268,9 +268,9 @@ struct SynthEcp5Pass : public ScriptPass
 			}
 			run("techmap -map +/ecp5/latches_map.v");
 			if (nomux)
-				run("abc -lut 4");
+				run("abc -lut 4 -dress");
 			else
-				run("abc -lut 4:7");
+				run("abc -lut 4:7 -dress");
 			run("clean");
 		}
 
-- 
cgit v1.2.3


From 7913baedd8c776243cbcf5ce73549943d1fe83a2 Mon Sep 17 00:00:00 2001
From: David Shah <dave@ds0.me>
Date: Tue, 12 Feb 2019 12:04:41 +0000
Subject: ecp5: Full set of IO-related blackboxes

Signed-off-by: David Shah <dave@ds0.me>
---
 techlibs/ecp5/cells_bb.v | 102 +++++++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 102 insertions(+)

(limited to 'techlibs/ecp5')

diff --git a/techlibs/ecp5/cells_bb.v b/techlibs/ecp5/cells_bb.v
index 32fb5c1ef..5b8d6bb4a 100644
--- a/techlibs/ecp5/cells_bb.v
+++ b/techlibs/ecp5/cells_bb.v
@@ -181,6 +181,31 @@ module IDDRX1F(
 	parameter GSR = "ENABLED";
 endmodule
 
+(* blackbox *)
+module IDDRX2F(
+	input D, SCLK, ECLK, RST,
+	output Q0, Q1, Q2, Q3
+);
+	parameter GSR = "ENABLED";
+endmodule
+
+(* blackbox *)
+module IDDR71B(
+	input D, SCLK, ECLK, RST, ALIGNWD,
+	output Q0, Q1, Q2, Q3, Q4, Q5, Q6
+);
+	parameter GSR = "ENABLED";
+endmodule
+
+(* blackbox *)
+module IDDRX2DQA(
+	input D, DQSR90, ECLK, SCLK, RST,
+	input RDPNTR2, RDPNTR1, RDPNTR0, WRPNTR2, WRPNTR1, WRPNTR0,
+	output Q0, Q1, Q2, Q3, QWL
+);
+	parameter GSR = "ENABLED";
+endmodule
+
 (* blackbox *)
 module ODDRX1F(
 	input SCLK, RST, D0, D1,
@@ -189,6 +214,83 @@ module ODDRX1F(
 	parameter GSR = "ENABLED";
 endmodule
 
+(* blackbox *)
+module ODDRX2F(
+	input SCLK, ECLK, RST, D0, D1, D2, D3,
+	output Q
+);
+	parameter GSR = "ENABLED";
+endmodule
+
+(* blackbox *)
+module ODDR71B(
+	input SCLK, ECLK, RST, D0, D1, D2, D3, D4, D5, D6,
+	output Q
+);
+	parameter GSR = "ENABLED";
+endmodule
+
+(* blackbox *)
+module OSHX2A(
+	input D0, D1, RST, ECLK, SCLK,
+	output Q
+);
+	parameter GSR = "ENABLED";
+endmodule
+
+(* blackbox *)
+module ODDRX2DQA(
+	input D0, D1, D2, D3, RST, ECLK, SCLK, DQSW270,
+	output Q
+);
+	parameter GSR = "ENABLED";
+endmodule
+
+(* blackbox *)
+module ODDRX2DQSB(
+	input D0, D1, D2, D3, RST, ECLK, SCLK, DQSW,
+	output Q
+);
+	parameter GSR = "ENABLED";
+endmodule
+
+(* blackbox *)
+module TSHX2DQA(
+	input T0, T1, SCLK, ECLK, DQSW270, RST,
+	output Q
+);
+	parameter GSR = "ENABLED";
+	parameter REGSET = "SET";
+endmodule
+
+(* blackbox *)
+module TSHX2DQSA(
+	input T0, T1, SCLK, ECLK, DQSW, RST,
+	output Q
+);
+	parameter GSR = "ENABLED";
+	parameter REGSET = "SET";
+endmodule
+
+
+(* blackbox *)
+module DQSBUFM(
+	input DQSI, READ1, READ0, READCLKSEL2, READCLKSEL1, READCLKSEL0, DDRDEL,
+	input ECLK, SCLK,
+	input DYNDELAY7, DYNDELAY6, DYNDELAY5, DYNDELAY4,
+	input DYNDELAY3, DYNDELAY2, DYNDELAY1, DYNDELAY0, 
+	input RST, RDLOADN, RDMOVE, RDDIRECTION, WRLOADN, WRMOVE, WRDIRECTION, PAUSE,
+	output DQSR90, DQSW, DQSW270,
+	output RDPNTR2, RDPNTR1, RDPNTR0, WRPNTR2, WRPNTR1, WRPNTR0,
+	output DATAVALID, BURSTDET, RDCFLAG, WRCFLAG
+);
+	parameter DQS_LI_DEL_ADJ = "FACTORYONLY";
+	parameter DQS_LI_DEL_VAL = 0;
+	parameter DQS_LO_DEL_ADJ = "FACTORYONLY";
+	parameter DQS_LO_DEL_VAL = 0;
+	parameter GSR = "ENABLED";
+endmodule
+
 (* blackbox *)
 module CLKDIVF(
 	input CLKI, RST, ALIGNWD,
-- 
cgit v1.2.3


From e0bc190879d1c722c267ae9370a16ce202345b76 Mon Sep 17 00:00:00 2001
From: David Shah <dave@ds0.me>
Date: Wed, 13 Feb 2019 11:23:25 +0000
Subject: ecp5: Add ECLKSYNCB blackbox

Signed-off-by: David Shah <dave@ds0.me>
---
 techlibs/ecp5/cells_bb.v | 8 +++++++-
 1 file changed, 7 insertions(+), 1 deletion(-)

(limited to 'techlibs/ecp5')

diff --git a/techlibs/ecp5/cells_bb.v b/techlibs/ecp5/cells_bb.v
index 5b8d6bb4a..1de623fcd 100644
--- a/techlibs/ecp5/cells_bb.v
+++ b/techlibs/ecp5/cells_bb.v
@@ -272,7 +272,6 @@ module TSHX2DQSA(
 	parameter REGSET = "SET";
 endmodule
 
-
 (* blackbox *)
 module DQSBUFM(
 	input DQSI, READ1, READ0, READCLKSEL2, READCLKSEL1, READCLKSEL0, DDRDEL,
@@ -300,6 +299,13 @@ module CLKDIVF(
 	parameter DIV = "2.0";
 endmodule
 
+(* blackbox *)
+module ECLKSYNCB(
+	input ECLKI, STOP,
+	output ECLKO
+);
+endmodule
+
 (* blackbox *)
 module DCCA(
 	input CLKI, CE,
-- 
cgit v1.2.3


From c36f15b489c1d47e94901e9286c4f1c2afb815c4 Mon Sep 17 00:00:00 2001
From: David Shah <davey1576@gmail.com>
Date: Tue, 19 Feb 2019 14:10:43 +0000
Subject: ecp5: Add DELAYF/DELAYG blackboxes

Signed-off-by: David Shah <davey1576@gmail.com>
---
 techlibs/ecp5/cells_bb.v | 18 ++++++++++++++++++
 1 file changed, 18 insertions(+)

(limited to 'techlibs/ecp5')

diff --git a/techlibs/ecp5/cells_bb.v b/techlibs/ecp5/cells_bb.v
index 1de623fcd..bac17260f 100644
--- a/techlibs/ecp5/cells_bb.v
+++ b/techlibs/ecp5/cells_bb.v
@@ -173,6 +173,24 @@ parameter ER1 = "ENABLED";
 parameter ER2 = "ENABLED";
 endmodule
 
+(* blackbox *)
+module DELAYF(
+	input A, LOADN, MOVE, DIRECTION,
+	output Z, CFLAG
+);
+	parameter DEL_MODE = "USER_DEFINED";
+	parameter DEL_VALUE = 0;
+endmodule
+
+(* blackbox *)
+module DELAYG(
+	input A,
+	output Z
+);
+	parameter DEL_MODE = "USER_DEFINED";
+	parameter DEL_VALUE = 0;
+endmodule
+
 (* blackbox *)
 module IDDRX1F(
 	input D, SCLK, RST,
-- 
cgit v1.2.3


From bb56cb738d6586059855cc3deefad12119673157 Mon Sep 17 00:00:00 2001
From: David Shah <davey1576@gmail.com>
Date: Tue, 19 Feb 2019 19:34:37 +0000
Subject: ecp5: Add DDRDLLA

Signed-off-by: David Shah <davey1576@gmail.com>
---
 techlibs/ecp5/cells_bb.v | 9 +++++++++
 1 file changed, 9 insertions(+)

(limited to 'techlibs/ecp5')

diff --git a/techlibs/ecp5/cells_bb.v b/techlibs/ecp5/cells_bb.v
index bac17260f..223e19b9e 100644
--- a/techlibs/ecp5/cells_bb.v
+++ b/techlibs/ecp5/cells_bb.v
@@ -308,6 +308,15 @@ module DQSBUFM(
 	parameter GSR = "ENABLED";
 endmodule
 
+(* blackbox *)
+module DDRDLLA(
+	input CLK, RST, UDDCNTLN, FREEZE,
+	output LOCK, DDRDEL, DCNTL7, DCNTL6, DCNTL5, DCNTL4, DCNTL3, DCNTL2, DCNTL1, DCNTL0
+);
+	parameter FORCE_MAX_DELAY = "NO";
+	parameter GSR = "ENABLED";
+endmodule
+
 (* blackbox *)
 module CLKDIVF(
 	input CLKI, RST, ALIGNWD,
-- 
cgit v1.2.3


From fa2f595cfa240b86edb26e859449c1c54eaf49ef Mon Sep 17 00:00:00 2001
From: David Shah <davey1576@gmail.com>
Date: Tue, 19 Feb 2019 19:35:10 +0000
Subject: ecp5: Compatibility with Migen AsyncResetSynchronizer

Signed-off-by: David Shah <davey1576@gmail.com>
---
 techlibs/ecp5/cells_map.v |  3 +++
 techlibs/ecp5/cells_sim.v | 17 +++++++++++++++++
 2 files changed, 20 insertions(+)

(limited to 'techlibs/ecp5')

diff --git a/techlibs/ecp5/cells_map.v b/techlibs/ecp5/cells_map.v
index 23182bdeb..6ab4b69f2 100644
--- a/techlibs/ecp5/cells_map.v
+++ b/techlibs/ecp5/cells_map.v
@@ -47,6 +47,9 @@ module  \$__DFFSE_NP1 (input D, C, E, R, output Q); TRELLIS_FF #(.GSR("DISABLED"
 module  \$__DFFSE_PP0 (input D, C, E, R, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("LSR_OVER_CE"))  _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(R), .DI(D), .Q(Q)); endmodule
 module  \$__DFFSE_PP1 (input D, C, E, R, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("LSR_OVER_CE"))  _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(R), .DI(D), .Q(Q)); endmodule
 
+// For Diamond compatibility, FIXME: add all Diamond flipflop mappings
+module FD1S3BX(input PD, D, CK, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("1"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("ASYNC"))  _TECHMAP_REPLACE_ (.CLK(CK), .LSR(PD), .DI(D), .Q(Q)); endmodule
+
 `ifndef NO_LUT
 module \$lut (A, Y);
     parameter WIDTH = 0;
diff --git a/techlibs/ecp5/cells_sim.v b/techlibs/ecp5/cells_sim.v
index ca5d020f3..d2d8b5793 100644
--- a/techlibs/ecp5/cells_sim.v
+++ b/techlibs/ecp5/cells_sim.v
@@ -556,3 +556,20 @@ module DP16KD(
   parameter INITVAL_3E = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
   parameter INITVAL_3F = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
 endmodule
+
+// For Diamond compatibility, FIXME: add all Diamond flipflop mappings
+module FD1S3BX(input PD, D, CK, output Q);
+	TRELLIS_FF #(
+		.GSR("DISABLED"),
+		.CEMUX("1"),
+		.CLKMUX("CLK"),
+		.LSRMUX("LSR"),
+		.REGSET("SET"),
+		.SRMODE("ASYNC")
+	) tff_i (
+		.CLK(CK),
+		.LSR(PD),
+		.DI(D),
+		.Q(Q)
+	);
+endmodule
-- 
cgit v1.2.3


From 61fc411c5d7237e420ee6eb9f6eb093e70d1007d Mon Sep 17 00:00:00 2001
From: Larry Doolittle <ldoolitt@recycle.lbl.gov>
Date: Sun, 24 Feb 2019 22:08:52 -0800
Subject: Clean up some whitepsace outliers

---
 techlibs/ecp5/cells_sim.v | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

(limited to 'techlibs/ecp5')

diff --git a/techlibs/ecp5/cells_sim.v b/techlibs/ecp5/cells_sim.v
index 507ab1beb..f27540bd7 100644
--- a/techlibs/ecp5/cells_sim.v
+++ b/techlibs/ecp5/cells_sim.v
@@ -57,7 +57,7 @@ module TRELLIS_RAM16X2 (
 	input RAD0, RAD1, RAD2, RAD3,
 	output DO0, DO1
 );
-  	parameter WCKMUX = "WCK";
+	parameter WCKMUX = "WCK";
 	parameter WREMUX = "WRE";
 	parameter INITVAL_0 = 16'h0000;
 	parameter INITVAL_1 = 16'h0000;
@@ -104,7 +104,7 @@ module TRELLIS_DPR16X4 (
 	input [3:0] RAD,
 	output [3:0] DO
 );
-  	parameter WCKMUX = "WCK";
+	parameter WCKMUX = "WCK";
 	parameter WREMUX = "WRE";
 	parameter [63:0] INITVAL = 64'h0000000000000000;
 
-- 
cgit v1.2.3


From ca2b3feed82f923f06d0cf57787818f0f6793157 Mon Sep 17 00:00:00 2001
From: Miodrag Milanovic <mmicko@gmail.com>
Date: Fri, 1 Mar 2019 19:25:23 +0100
Subject: Fix ECP5 cells_sim for iverilog

---
 techlibs/ecp5/cells_sim.v | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

(limited to 'techlibs/ecp5')

diff --git a/techlibs/ecp5/cells_sim.v b/techlibs/ecp5/cells_sim.v
index 8320ee70a..1e4002ee0 100644
--- a/techlibs/ecp5/cells_sim.v
+++ b/techlibs/ecp5/cells_sim.v
@@ -223,11 +223,12 @@ module TRELLIS_FF(input CLK, LSR, CE, DI, M, output reg Q);
 
 	wire muxlsr = (LSRMUX == "INV") ? ~LSR : LSR;
 	wire muxclk = (CLKMUX == "INV") ? ~CLK : CLK;
+	wire srval;
 	generate
 		if (LSRMODE == "PRLD")
-			wire srval = M;
+			assign srval = M;
 		else
-			localparam srval = (REGSET == "SET") ? 1'b1 : 1'b0;
+			assign srval = (REGSET == "SET") ? 1'b1 : 1'b0;
 	endgenerate
 
 	initial Q = srval;
-- 
cgit v1.2.3


From 777864d02ea3382c822a764e928e06b6142da6ec Mon Sep 17 00:00:00 2001
From: David Shah <dave@ds0.me>
Date: Mon, 4 Mar 2019 11:18:53 +0000
Subject: ecp5: Demote conflicting FF init values to a warning

Signed-off-by: David Shah <dave@ds0.me>
---
 techlibs/ecp5/ecp5_ffinit.cc | 9 +++++++--
 1 file changed, 7 insertions(+), 2 deletions(-)

(limited to 'techlibs/ecp5')

diff --git a/techlibs/ecp5/ecp5_ffinit.cc b/techlibs/ecp5/ecp5_ffinit.cc
index 02945fff4..dbd16cac9 100644
--- a/techlibs/ecp5/ecp5_ffinit.cc
+++ b/techlibs/ecp5/ecp5_ffinit.cc
@@ -79,10 +79,12 @@ struct Ecp5FfinitPass : public Pass {
 						continue;
 
 					if (initbits.count(bit)) {
-						if (initbits.at(bit) != val)
-							log_error("Conflicting init values for signal %s (%s = %s, %s = %s).\n",
+						if (initbits.at(bit) != val) {
+							log_warning("Conflicting init values for signal %s (%s = %s, %s = %s).\n",
 									log_signal(bit), log_signal(SigBit(wire, i)), log_signal(val),
 									log_signal(initbit_to_wire[bit]), log_signal(initbits.at(bit)));
+							initbits.at(bit) = State::Sx;
+						}
 						continue;
 					}
 
@@ -121,6 +123,9 @@ struct Ecp5FfinitPass : public Pass {
 
 				State val = initbits.at(bit_q);
 
+				if (val == State::Sx)
+					continue;
+
 				log("FF init value for cell %s (%s): %s = %c\n", log_id(cell), log_id(cell->type),
 						log_signal(bit_q), val != State::S0 ? '1' : '0');
 				// Initval is the same as the reset state. Matches hardware, nowt more to do
-- 
cgit v1.2.3


From 9d117eba9d65cf978716f1c7d41e86466ca03fc6 Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Tue, 30 Apr 2019 14:46:12 +0200
Subject: Add handling of init attributes in "opt_expr -undriven"

Signed-off-by: Clifford Wolf <clifford@clifford.at>
---
 techlibs/ecp5/synth_ecp5.cc | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'techlibs/ecp5')

diff --git a/techlibs/ecp5/synth_ecp5.cc b/techlibs/ecp5/synth_ecp5.cc
index 4b889d672..c6e12248e 100644
--- a/techlibs/ecp5/synth_ecp5.cc
+++ b/techlibs/ecp5/synth_ecp5.cc
@@ -253,7 +253,7 @@ struct SynthEcp5Pass : public ScriptPass
 			if (!nodffe)
 				run("dff2dffe -direct-match $_DFF_* -direct-match $__DFFS_*");
 			run("techmap -D NO_LUT -map +/ecp5/cells_map.v");
-			run("opt_expr -mux_undef");
+			run("opt_expr -undriven -mux_undef");
 			run("simplemap");
 			run("ecp5_ffinit");
 		}
-- 
cgit v1.2.3


From f3a26730b610e1d80ca408e6913311bdfc82914c Mon Sep 17 00:00:00 2001
From: whitequark <whitequark@whitequark.org>
Date: Thu, 6 Jun 2019 10:03:03 +0000
Subject: ECP5: implement all Diamond I/O buffer primitives.

---
 techlibs/ecp5/cells_map.v | 15 +++++++++++++++
 1 file changed, 15 insertions(+)

(limited to 'techlibs/ecp5')

diff --git a/techlibs/ecp5/cells_map.v b/techlibs/ecp5/cells_map.v
index 6ab4b69f2..f6c71a03d 100644
--- a/techlibs/ecp5/cells_map.v
+++ b/techlibs/ecp5/cells_map.v
@@ -47,6 +47,21 @@ module  \$__DFFSE_NP1 (input D, C, E, R, output Q); TRELLIS_FF #(.GSR("DISABLED"
 module  \$__DFFSE_PP0 (input D, C, E, R, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("LSR_OVER_CE"))  _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(R), .DI(D), .Q(Q)); endmodule
 module  \$__DFFSE_PP1 (input D, C, E, R, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("LSR_OVER_CE"))  _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(R), .DI(D), .Q(Q)); endmodule
 
+// Diamond I/O buffers
+module IB   (input I, output O); (* PULLMODE="NONE" *) TRELLIS_IO #(.DIR("INPUT")) _TECHMAP_REPLACE_ (.B(I), .O(O)); endmodule
+module IBPU (input I, output O); (* PULLMODE="UP"   *) TRELLIS_IO #(.DIR("INPUT"))   _TECHMAP_REPLACE_ (.B(I), .O(O)); endmodule
+module IBPD (input I, output O); (* PULLMODE="DOWN" *) TRELLIS_IO #(.DIR("INPUT")) _TECHMAP_REPLACE_ (.B(I), .O(O)); endmodule
+module OB   (input I, output O); (* PULLMODE="NONE" *) TRELLIS_IO #(.DIR("OUTPUT")) _TECHMAP_REPLACE_ (.B(O), .I(I)); endmodule
+module OBZ  (input I, T, output O); (* PULLMODE="NONE" *) TRELLIS_IO #(.DIR("OUTPUT")) _TECHMAP_REPLACE_ (.B(O), .I(I), .T(T)); endmodule
+module OBZPU(input I, T, output O); (* PULLMODE="UP"   *) TRELLIS_IO #(.DIR("OUTPUT"))   _TECHMAP_REPLACE_ (.B(O), .I(I), .T(T)); endmodule
+module OBZPD(input I, T, output O); (* PULLMODE="DOWN" *) TRELLIS_IO #(.DIR("OUTPUT")) _TECHMAP_REPLACE_ (.B(O), .I(I), .T(T)); endmodule
+module OBCO (input I, output OT, OC); OLVDS _TECHMAP_REPLACE_ (.A(I), .Z(OT), .ZN(OC)); endmodule
+module BB   (input I, T, output O, inout B); (* PULLMODE="NONE" *) TRELLIS_IO #(.DIR("BIDIR")) _TECHMAP_REPLACE_ (.B(B), .I(I), .O(O), .T(T)); endmodule
+module BBPU (input I, T, output O, inout B); (* PULLMODE="UP"   *) TRELLIS_IO #(.DIR("BIDIR"))   _TECHMAP_REPLACE_ (.B(B), .I(I), .O(O), .T(T)); endmodule
+module BBPD (input I, T, output O, inout B); (* PULLMODE="DOWN" *) TRELLIS_IO #(.DIR("BIDIR")) _TECHMAP_REPLACE_ (.B(B), .I(I), .O(O), .T(T)); endmodule
+module ILVDS(input A, AN, output Z); TRELLIS_IO #(.DIR("INPUT"))  _TECHMAP_REPLACE_ (.B(A), .O(Z)); endmodule
+module OLVDS(input A, output Z, ZN); TRELLIS_IO #(.DIR("OUTPUT")) _TECHMAP_REPLACE_ (.B(Z), .I(A)); endmodule
+
 // For Diamond compatibility, FIXME: add all Diamond flipflop mappings
 module FD1S3BX(input PD, D, CK, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("1"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("ASYNC"))  _TECHMAP_REPLACE_ (.CLK(CK), .LSR(PD), .DI(D), .Q(Q)); endmodule
 
-- 
cgit v1.2.3


From 95665730540c0fd7c76690f28d0fd6b5f13f2223 Mon Sep 17 00:00:00 2001
From: David Shah <dave@ds0.me>
Date: Fri, 14 Jun 2019 12:02:12 +0100
Subject: ecp5: Add abc9 option

Signed-off-by: David Shah <dave@ds0.me>
---
 techlibs/ecp5/Makefile.inc  |   3 +
 techlibs/ecp5/abc_5g.box    |  36 ++++++++++++
 techlibs/ecp5/abc_5g.lut    |  25 +++++++++
 techlibs/ecp5/cells_map.v   | 133 ++++++++++++++++++++++++++------------------
 techlibs/ecp5/cells_sim.v   |  32 +++++++----
 techlibs/ecp5/synth_ecp5.cc |  25 +++++++--
 6 files changed, 184 insertions(+), 70 deletions(-)
 create mode 100644 techlibs/ecp5/abc_5g.box
 create mode 100644 techlibs/ecp5/abc_5g.lut

(limited to 'techlibs/ecp5')

diff --git a/techlibs/ecp5/Makefile.inc b/techlibs/ecp5/Makefile.inc
index 4db087e87..eee3b418f 100644
--- a/techlibs/ecp5/Makefile.inc
+++ b/techlibs/ecp5/Makefile.inc
@@ -11,6 +11,9 @@ $(eval $(call add_share_file,share/ecp5,techlibs/ecp5/bram.txt))
 $(eval $(call add_share_file,share/ecp5,techlibs/ecp5/arith_map.v))
 $(eval $(call add_share_file,share/ecp5,techlibs/ecp5/latches_map.v))
 
+$(eval $(call add_share_file,share/ecp5,techlibs/ecp5/abc_5g.box))
+$(eval $(call add_share_file,share/ecp5,techlibs/ecp5/abc_5g.lut))
+
 EXTRA_OBJS += techlibs/ecp5/brams_init.mk techlibs/ecp5/brams_connect.mk
 .SECONDARY: techlibs/ecp5/brams_init.mk techlibs/ecp5/brams_connect.mk
 
diff --git a/techlibs/ecp5/abc_5g.box b/techlibs/ecp5/abc_5g.box
new file mode 100644
index 000000000..72af6d9cb
--- /dev/null
+++ b/techlibs/ecp5/abc_5g.box
@@ -0,0 +1,36 @@
+# Box 1 : CCU2C (2xCARRY + 2xLUT4)
+# Outputs: S0, S1, COUT
+# name  ID   w/b   ins    outs
+CCU2C   1      1   9      3
+
+#A0   A1   B0   B1   C0    C1  D0   D1   CIN
+379  -    379  -    275   -    141  -    257
+630  379  630  379  526   275  392  141  273
+516  516  516  516  412   412  278  278  43
+
+# Box 2 : TRELLIS_DPR16X4 (16x4 dist ram)
+# Outputs: DO0, DO1, DO2, DO3, DO4
+# name            ID  w/b   ins   outs
+TRELLIS_DPR16X4   2     0   14    4
+
+#DI0   DI1   DI2   DI3   RAD0   RAD1   RAD2   RAD3   WAD0    WAD1   WAD2   WAD3  WCK   WRE
+-      -     -     -     141    379    275    379    -       -      -      -     -     -
+-      -     -     -     141    379    275    379    -       -      -      -     -     -
+-      -     -     -     141    379    275    379    -       -      -      -     -     -
+-      -     -     -     141    379    275    379    -       -      -      -     -     -
+
+# Box 3 : PFUMX (MUX2)
+# Outputs: Z
+# name  ID   w/b   ins    outs
+PFUMX   3    1     3      1
+
+#ALUT  BLUT  C0
+98     98    151
+
+# Box 4 : L6MUX21 (MUX2)
+# Outputs: Z
+# name   ID   w/b   ins    outs
+L6MUX21  4    1     3      1
+
+#D0    D1    SD
+140    141   148
diff --git a/techlibs/ecp5/abc_5g.lut b/techlibs/ecp5/abc_5g.lut
new file mode 100644
index 000000000..e8aa9b35d
--- /dev/null
+++ b/techlibs/ecp5/abc_5g.lut
@@ -0,0 +1,25 @@
+# ECP5-5G LUT library for ABC
+# Note that ECP5 architecture assigns difference
+# in LUT input delay to interconnect, so this is
+# considered too
+
+
+# Simple LUTs
+#  area  D    C    B    A
+1  1     141
+2  1     141  275
+3  1     141  275  379
+4  1     141  275  379  379
+
+# LUT5 = 2x LUT4 + PFUMX
+#  area  M0   D    C    B    A
+5  2     151  239  373  477  477
+
+# LUT6 = 2x LUT5 + MUX2
+#  area  M1   M0   D    C    B    A
+6  4     148  292  380  514  618  618
+
+# LUT7 = 2x LUT6 + MUX2
+#  area  M2   M1   M0   D    C    B    A
+7  8     148  289  433  521  655  759  759
+
diff --git a/techlibs/ecp5/cells_map.v b/techlibs/ecp5/cells_map.v
index f6c71a03d..53a89e8a3 100644
--- a/techlibs/ecp5/cells_map.v
+++ b/techlibs/ecp5/cells_map.v
@@ -70,80 +70,107 @@ module \$lut (A, Y);
     parameter WIDTH = 0;
     parameter LUT = 0;
 
+
+    // Need to swap input ordering, and fix init accordingly,
+    // to match ABC's expectation of LUT inputs in non-decreasing
+    // delay order
+    localparam P_WIDTH = WIDTH < 4 ? 4 : WIDTH;
+    function [P_WIDTH-1:0] permute_index;
+        input [P_WIDTH-1:0] i;
+        integer j;
+        begin
+            permute_index = 0;
+            for (j = 0; j < P_WIDTH; j = j + 1)
+                permute_index[P_WIDTH-1 - j] = i[j];
+        end
+    endfunction
+
+    function [2**P_WIDTH-1:0] permute_init;
+        input [2**P_WIDTH-1:0] orig;
+        integer i;
+        begin
+            permute_init = 0;
+            for (i = 0; i < 2**P_WIDTH; i = i + 1)
+                permute_init[i] = orig[permute_index(i)];
+        end
+    endfunction
+
+    parameter [2**P_WIDTH-1:0] P_LUT = permute_init(LUT);
+
     input [WIDTH-1:0] A;
     output Y;
 
     generate
         if (WIDTH == 1) begin
-            LUT4 #(.INIT(LUT)) _TECHMAP_REPLACE_ (.Z(Y),
-                .A(A[0]), .B(1'b0), .C(1'b0), .D(1'b0));
+            LUT4 #(.INIT(P_LUT)) _TECHMAP_REPLACE_ (.Z(Y),
+                .A(1'b0), .B(1'b0), .C(1'b0), .D(A[0]));
         end else
         if (WIDTH == 2) begin
-            LUT4 #(.INIT(LUT)) _TECHMAP_REPLACE_ (.Z(Y),
-                .A(A[0]), .B(A[1]), .C(1'b0), .D(1'b0));
+            LUT4 #(.INIT(P_LUT)) _TECHMAP_REPLACE_ (.Z(Y),
+                .A(1'b0), .B(1'b0), .C(A[1]), .D(A[0]));
         end else
         if (WIDTH == 3) begin
-            LUT4 #(.INIT(LUT)) _TECHMAP_REPLACE_ (.Z(Y),
-                .A(A[0]), .B(A[1]), .C(A[2]), .D(1'b0));
+            LUT4 #(.INIT(P_LUT)) _TECHMAP_REPLACE_ (.Z(Y),
+                .A(1'b0), .B(A[2]), .C(A[1]), .D(A[0]));
         end else
         if (WIDTH == 4) begin
-            LUT4 #(.INIT(LUT)) _TECHMAP_REPLACE_ (.Z(Y),
-                .A(A[0]), .B(A[1]), .C(A[2]), .D(A[3]));
+            LUT4 #(.INIT(P_LUT)) _TECHMAP_REPLACE_ (.Z(Y),
+                .A(A[3]), .B(A[2]), .C(A[1]), .D(A[0]));
         `ifndef NO_PFUMUX
         end else
         if (WIDTH == 5) begin
             wire f0, f1;
-            LUT4 #(.INIT(LUT[15: 0])) lut0 (.Z(f0),
-                .A(A[0]), .B(A[1]), .C(A[2]), .D(A[3]));
-            LUT4 #(.INIT(LUT[31:16])) lut1 (.Z(f1),
-                .A(A[0]), .B(A[1]), .C(A[2]), .D(A[3]));
-            PFUMX mux5(.ALUT(f1), .BLUT(f0), .C0(A[4]), .Z(Y));
+            LUT4 #(.INIT(P_LUT[15: 0])) lut0 (.Z(f0),
+                .A(A[4]), .B(A[3]), .C(A[2]), .D(A[1]));
+            LUT4 #(.INIT(P_LUT[31:16])) lut1 (.Z(f1),
+                .A(A[4]), .B(A[3]), .C(A[2]), .D(A[1]));
+            PFUMX mux5(.ALUT(f1), .BLUT(f0), .C0(A[0]), .Z(Y));
         end else
         if (WIDTH == 6) begin
             wire f0, f1, f2, f3, g0, g1;
-            LUT4 #(.INIT(LUT[15: 0])) lut0 (.Z(f0),
-                .A(A[0]), .B(A[1]), .C(A[2]), .D(A[3]));
-            LUT4 #(.INIT(LUT[31:16])) lut1 (.Z(f1),
-                .A(A[0]), .B(A[1]), .C(A[2]), .D(A[3]));
-
-            LUT4 #(.INIT(LUT[47:32])) lut2 (.Z(f2),
-                .A(A[0]), .B(A[1]), .C(A[2]), .D(A[3]));
-            LUT4 #(.INIT(LUT[63:48])) lut3 (.Z(f3),
-                .A(A[0]), .B(A[1]), .C(A[2]), .D(A[3]));
-
-            PFUMX mux50(.ALUT(f1), .BLUT(f0), .C0(A[4]), .Z(g0));
-            PFUMX mux51(.ALUT(f3), .BLUT(f2), .C0(A[4]), .Z(g1));
-            L6MUX21 mux6 (.D0(g0), .D1(g1), .SD(A[5]), .Z(Y));
+            LUT4 #(.INIT(P_LUT[15: 0])) lut0 (.Z(f0),
+                .A(A[5]), .B(A[4]), .C(A[3]), .D(A[2]));
+            LUT4 #(.INIT(P_LUT[31:16])) lut1 (.Z(f1),
+                .A(A[5]), .B(A[4]), .C(A[3]), .D(A[2]));
+
+            LUT4 #(.INIT(P_LUT[47:32])) lut2 (.Z(f2),
+                .A(A[5]), .B(A[4]), .C(A[3]), .D(A[2]));
+            LUT4 #(.INIT(P_LUT[63:48])) lut3 (.Z(f3),
+                .A(A[5]), .B(A[4]), .C(A[3]), .D(A[2]));
+
+            PFUMX mux50(.ALUT(f1), .BLUT(f0), .C0(A[1]), .Z(g0));
+            PFUMX mux51(.ALUT(f3), .BLUT(f2), .C0(A[1]), .Z(g1));
+            L6MUX21 mux6 (.D0(g0), .D1(g1), .SD(A[0]), .Z(Y));
         end else
         if (WIDTH == 7) begin
             wire f0, f1, f2, f3, f4, f5, f6, f7, g0, g1, g2, g3, h0, h1;
-            LUT4 #(.INIT(LUT[15: 0])) lut0 (.Z(f0),
-                .A(A[0]), .B(A[1]), .C(A[2]), .D(A[3]));
-            LUT4 #(.INIT(LUT[31:16])) lut1 (.Z(f1),
-                .A(A[0]), .B(A[1]), .C(A[2]), .D(A[3]));
-
-            LUT4 #(.INIT(LUT[47:32])) lut2 (.Z(f2),
-                .A(A[0]), .B(A[1]), .C(A[2]), .D(A[3]));
-            LUT4 #(.INIT(LUT[63:48])) lut3 (.Z(f3),
-                .A(A[0]), .B(A[1]), .C(A[2]), .D(A[3]));
-
-            LUT4 #(.INIT(LUT[79:64])) lut4 (.Z(f4),
-                .A(A[0]), .B(A[1]), .C(A[2]), .D(A[3]));
-            LUT4 #(.INIT(LUT[95:80])) lut5 (.Z(f5),
-                .A(A[0]), .B(A[1]), .C(A[2]), .D(A[3]));
-
-            LUT4 #(.INIT(LUT[111: 96])) lut6 (.Z(f6),
-                .A(A[0]), .B(A[1]), .C(A[2]), .D(A[3]));
-            LUT4 #(.INIT(LUT[127:112])) lut7 (.Z(f7),
-                .A(A[0]), .B(A[1]), .C(A[2]), .D(A[3]));
-
-            PFUMX mux50(.ALUT(f1), .BLUT(f0), .C0(A[4]), .Z(g0));
-            PFUMX mux51(.ALUT(f3), .BLUT(f2), .C0(A[4]), .Z(g1));
-            PFUMX mux52(.ALUT(f5), .BLUT(f4), .C0(A[4]), .Z(g2));
-            PFUMX mux53(.ALUT(f7), .BLUT(f6), .C0(A[4]), .Z(g3));
-            L6MUX21 mux60 (.D0(g0), .D1(g1), .SD(A[5]), .Z(h0));
-            L6MUX21 mux61 (.D0(g2), .D1(g3), .SD(A[5]), .Z(h1));
-            L6MUX21 mux7  (.D0(h0), .D1(h1), .SD(A[6]), .Z(Y));
+            LUT4 #(.INIT(P_LUT[15: 0])) lut0 (.Z(f0),
+                .A(A[6]), .B(A[5]), .C(A[4]), .D(A[3]));
+            LUT4 #(.INIT(P_LUT[31:16])) lut1 (.Z(f1),
+                .A(A[6]), .B(A[5]), .C(A[4]), .D(A[3]));
+
+            LUT4 #(.INIT(P_LUT[47:32])) lut2 (.Z(f2),
+                .A(A[6]), .B(A[5]), .C(A[4]), .D(A[3]));
+            LUT4 #(.INIT(P_LUT[63:48])) lut3 (.Z(f3),
+                .A(A[6]), .B(A[5]), .C(A[4]), .D(A[3]));
+
+            LUT4 #(.INIT(P_LUT[79:64])) lut4 (.Z(f4),
+                .A(A[6]), .B(A[5]), .C(A[4]), .D(A[3]));
+            LUT4 #(.INIT(P_LUT[95:80])) lut5 (.Z(f5),
+                .A(A[6]), .B(A[5]), .C(A[4]), .D(A[3]));
+
+            LUT4 #(.INIT(P_LUT[111: 96])) lut6 (.Z(f6),
+                .A(A[6]), .B(A[5]), .C(A[4]), .D(A[3]));
+            LUT4 #(.INIT(P_LUT[127:112])) lut7 (.Z(f7),
+                .A(A[6]), .B(A[5]), .C(A[4]), .D(A[3]));
+
+            PFUMX mux50(.ALUT(f1), .BLUT(f0), .C0(A[2]), .Z(g0));
+            PFUMX mux51(.ALUT(f3), .BLUT(f2), .C0(A[2]), .Z(g1));
+            PFUMX mux52(.ALUT(f5), .BLUT(f4), .C0(A[2]), .Z(g2));
+            PFUMX mux53(.ALUT(f7), .BLUT(f6), .C0(A[2]), .Z(g3));
+            L6MUX21 mux60 (.D0(g0), .D1(g1), .SD(A[1]), .Z(h0));
+            L6MUX21 mux61 (.D0(g2), .D1(g3), .SD(A[1]), .Z(h1));
+            L6MUX21 mux7  (.D0(h0), .D1(h1), .SD(A[0]), .Z(Y));
         `endif
         end else begin
             wire _TECHMAP_FAIL_ = 1;
diff --git a/techlibs/ecp5/cells_sim.v b/techlibs/ecp5/cells_sim.v
index 1e4002ee0..430aadbd7 100644
--- a/techlibs/ecp5/cells_sim.v
+++ b/techlibs/ecp5/cells_sim.v
@@ -9,15 +9,17 @@ module LUT4(input A, B, C, D, output Z);
 endmodule
 
 // ---------------------------------------
-
+(* abc_box_id=4, lib_whitebox *)
 module L6MUX21 (input D0, D1, SD, output Z);
 	assign Z = SD ? D1 : D0;
 endmodule
 
 // ---------------------------------------
-
-module CCU2C(input CIN, A0, B0, C0, D0, A1, B1, C1, D1,
-	           output S0, S1, COUT);
+(* abc_box_id=1, abc_carry, lib_whitebox *)
+module CCU2C((* abc_carry_in *) input CIN,
+			   input A0, B0, C0, D0, A1, B1, C1, D1,
+	           output S0, S1,
+	         (* abc_carry_out *) output COUT);
 
 	parameter [15:0] INIT0 = 16'h0000;
 	parameter [15:0] INIT1 = 16'h0000;
@@ -26,9 +28,13 @@ module CCU2C(input CIN, A0, B0, C0, D0, A1, B1, C1, D1,
 
 	// First half
 	wire LUT4_0, LUT2_0;
+`ifdef _ABC
+	assign LUT4_0 = INIT0[{D0, C0, B0, A0}];
+	assign LUT2_0 = INIT0[{2'b00, B0, A0}];
+`else
 	LUT4 #(.INIT(INIT0)) lut4_0(.A(A0), .B(B0), .C(C0), .D(D0), .Z(LUT4_0));
 	LUT2 #(.INIT(INIT0[3:0])) lut2_0(.A(A0), .B(B0), .Z(LUT2_0));
-
+`endif
 	wire gated_cin_0 = (INJECT1_0 == "YES") ? 1'b0 : CIN;
 	assign S0 = LUT4_0 ^ gated_cin_0;
 
@@ -37,9 +43,13 @@ module CCU2C(input CIN, A0, B0, C0, D0, A1, B1, C1, D1,
 
 	// Second half
 	wire LUT4_1, LUT2_1;
+`ifdef _ABC
+	assign LUT4_1 = INIT1[{D1, C1, B1, A1}];
+	assign LUT2_1 = INIT1[{2'b00, B1, A1}];
+`else
 	LUT4 #(.INIT(INIT1)) lut4_1(.A(A1), .B(B1), .C(C1), .D(D1), .Z(LUT4_1));
 	LUT2 #(.INIT(INIT1[3:0])) lut2_1(.A(A1), .B(B1), .Z(LUT2_1));
-
+`endif
 	wire gated_cin_1 = (INJECT1_1 == "YES") ? 1'b0 : cout_0;
 	assign S1 = LUT4_1 ^ gated_cin_1;
 
@@ -90,13 +100,13 @@ module TRELLIS_RAM16X2 (
 endmodule
 
 // ---------------------------------------
-
+(* abc_box_id=3, lib_whitebox *)
 module PFUMX (input ALUT, BLUT, C0, output Z);
 	assign Z = C0 ? ALUT : BLUT;
 endmodule
 
 // ---------------------------------------
-
+(* abc_box_id=2 *)
 module TRELLIS_DPR16X4 (
 	input [3:0] DI,
 	input [3:0] WAD,
@@ -203,7 +213,7 @@ endmodule
 
 // ---------------------------------------
 
-module TRELLIS_FF(input CLK, LSR, CE, DI, M, output reg Q);
+module TRELLIS_FF(input CLK, LSR, CE, DI, M, (* abc_flop_q *) output reg Q);
 	parameter GSR = "ENABLED";
 	parameter [127:0] CEMUX = "1";
 	parameter CLKMUX = "CLK";
@@ -464,13 +474,13 @@ module DP16KD(
   input ADA13, ADA12, ADA11, ADA10, ADA9, ADA8, ADA7, ADA6, ADA5, ADA4, ADA3, ADA2, ADA1, ADA0,
   input CEA, OCEA, CLKA, WEA, RSTA,
   input CSA2, CSA1, CSA0,
-  output DOA17, DOA16, DOA15, DOA14, DOA13, DOA12, DOA11, DOA10, DOA9, DOA8, DOA7, DOA6, DOA5, DOA4, DOA3, DOA2, DOA1, DOA0,
+  (* abc_flop_q *)  output DOA17, DOA16, DOA15, DOA14, DOA13, DOA12, DOA11, DOA10, DOA9, DOA8, DOA7, DOA6, DOA5, DOA4, DOA3, DOA2, DOA1, DOA0,
 
   input DIB17, DIB16, DIB15, DIB14, DIB13, DIB12, DIB11, DIB10, DIB9, DIB8, DIB7, DIB6, DIB5, DIB4, DIB3, DIB2, DIB1, DIB0,
   input ADB13, ADB12, ADB11, ADB10, ADB9, ADB8, ADB7, ADB6, ADB5, ADB4, ADB3, ADB2, ADB1, ADB0,
   input CEB, OCEB, CLKB, WEB, RSTB,
   input CSB2, CSB1, CSB0,
-  output DOB17, DOB16, DOB15, DOB14, DOB13, DOB12, DOB11, DOB10, DOB9, DOB8, DOB7, DOB6, DOB5, DOB4, DOB3, DOB2, DOB1, DOB0
+  (* abc_flop_q *)  output DOB17, DOB16, DOB15, DOB14, DOB13, DOB12, DOB11, DOB10, DOB9, DOB8, DOB7, DOB6, DOB5, DOB4, DOB3, DOB2, DOB1, DOB0
 );
   parameter DATA_WIDTH_A = 18;
   parameter DATA_WIDTH_B = 18;
diff --git a/techlibs/ecp5/synth_ecp5.cc b/techlibs/ecp5/synth_ecp5.cc
index c6e12248e..b271500f1 100644
--- a/techlibs/ecp5/synth_ecp5.cc
+++ b/techlibs/ecp5/synth_ecp5.cc
@@ -82,6 +82,9 @@ struct SynthEcp5Pass : public ScriptPass
 		log("    -abc2\n");
 		log("        run two passes of 'abc' for slightly improved logic density\n");
 		log("\n");
+		log("    -abc9\n");
+		log("        use new ABC9 flow (EXPERIMENTAL)\n");
+		log("\n");
 		log("    -vpr\n");
 		log("        generate an output netlist (and BLIF file) suitable for VPR\n");
 		log("        (this feature is experimental and incomplete)\n");
@@ -93,7 +96,7 @@ struct SynthEcp5Pass : public ScriptPass
 	}
 
 	string top_opt, blif_file, edif_file, json_file;
-	bool noccu2, nodffe, nobram, nodram, nomux, flatten, retime, abc2, vpr;
+	bool noccu2, nodffe, nobram, nodram, nomux, flatten, retime, abc2, abc9, vpr;
 
 	void clear_flags() YS_OVERRIDE
 	{
@@ -110,6 +113,7 @@ struct SynthEcp5Pass : public ScriptPass
 		retime = false;
 		abc2 = false;
 		vpr = false;
+		abc9 = false;
 	}
 
 	void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
@@ -184,6 +188,10 @@ struct SynthEcp5Pass : public ScriptPass
 				vpr = true;
 				continue;
 			}
+			if (args[argidx] == "-abc9") {
+				abc9 = true;
+				continue;
+			}
 			break;
 		}
 		extra_args(args, argidx, design);
@@ -203,7 +211,7 @@ struct SynthEcp5Pass : public ScriptPass
 	{
 		if (check_label("begin"))
 		{
-			run("read_verilog -lib +/ecp5/cells_sim.v +/ecp5/cells_bb.v");
+			run("read_verilog -D_ABC -lib +/ecp5/cells_sim.v +/ecp5/cells_bb.v");
 			run(stringf("hierarchy -check %s", help_mode ? "-top <top>" : top_opt.c_str()));
 		}
 
@@ -264,10 +272,15 @@ struct SynthEcp5Pass : public ScriptPass
 				run("abc", "      (only if -abc2)");
 			}
 			run("techmap -map +/ecp5/latches_map.v");
-			if (nomux)
-				run("abc -lut 4 -dress");
-			else
-				run("abc -lut 4:7 -dress");
+			if (abc9) {
+				run("abc9 -lut +/ecp5/abc_5g.lut -box +/ecp5/abc_5g.box -W 200");
+			} else {
+				if (nomux)
+					run("abc -lut 4 -dress");
+				else
+					run("abc -lut 4:7 -dress");
+			}
+
 			run("clean");
 		}
 
-- 
cgit v1.2.3


From ee428f73abdbbde95601e583db186d86a8fa6b91 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Fri, 14 Jun 2019 10:37:52 -0700
Subject: Remove WIP ABC9 flop support

---
 techlibs/ecp5/cells_sim.v | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

(limited to 'techlibs/ecp5')

diff --git a/techlibs/ecp5/cells_sim.v b/techlibs/ecp5/cells_sim.v
index 430aadbd7..d7184f980 100644
--- a/techlibs/ecp5/cells_sim.v
+++ b/techlibs/ecp5/cells_sim.v
@@ -213,7 +213,7 @@ endmodule
 
 // ---------------------------------------
 
-module TRELLIS_FF(input CLK, LSR, CE, DI, M, (* abc_flop_q *) output reg Q);
+module TRELLIS_FF(input CLK, LSR, CE, DI, M, output reg Q);
 	parameter GSR = "ENABLED";
 	parameter [127:0] CEMUX = "1";
 	parameter CLKMUX = "CLK";
@@ -474,13 +474,13 @@ module DP16KD(
   input ADA13, ADA12, ADA11, ADA10, ADA9, ADA8, ADA7, ADA6, ADA5, ADA4, ADA3, ADA2, ADA1, ADA0,
   input CEA, OCEA, CLKA, WEA, RSTA,
   input CSA2, CSA1, CSA0,
-  (* abc_flop_q *)  output DOA17, DOA16, DOA15, DOA14, DOA13, DOA12, DOA11, DOA10, DOA9, DOA8, DOA7, DOA6, DOA5, DOA4, DOA3, DOA2, DOA1, DOA0,
+  output DOA17, DOA16, DOA15, DOA14, DOA13, DOA12, DOA11, DOA10, DOA9, DOA8, DOA7, DOA6, DOA5, DOA4, DOA3, DOA2, DOA1, DOA0,
 
   input DIB17, DIB16, DIB15, DIB14, DIB13, DIB12, DIB11, DIB10, DIB9, DIB8, DIB7, DIB6, DIB5, DIB4, DIB3, DIB2, DIB1, DIB0,
   input ADB13, ADB12, ADB11, ADB10, ADB9, ADB8, ADB7, ADB6, ADB5, ADB4, ADB3, ADB2, ADB1, ADB0,
   input CEB, OCEB, CLKB, WEB, RSTB,
   input CSB2, CSB1, CSB0,
-  (* abc_flop_q *)  output DOB17, DOB16, DOB15, DOB14, DOB13, DOB12, DOB11, DOB10, DOB9, DOB8, DOB7, DOB6, DOB5, DOB4, DOB3, DOB2, DOB1, DOB0
+  output DOB17, DOB16, DOB15, DOB14, DOB13, DOB12, DOB11, DOB10, DOB9, DOB8, DOB7, DOB6, DOB5, DOB4, DOB3, DOB2, DOB1, DOB0
 );
   parameter DATA_WIDTH_A = 18;
   parameter DATA_WIDTH_B = 18;
-- 
cgit v1.2.3


From 94314ae2d5cbd06ba1457a8526f99c9ae01ff8fd Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Fri, 14 Jun 2019 10:42:30 -0700
Subject: Comment out dist RAM boxing on ECP5 for now

---
 techlibs/ecp5/cells_sim.v | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'techlibs/ecp5')

diff --git a/techlibs/ecp5/cells_sim.v b/techlibs/ecp5/cells_sim.v
index d7184f980..f66147323 100644
--- a/techlibs/ecp5/cells_sim.v
+++ b/techlibs/ecp5/cells_sim.v
@@ -106,7 +106,7 @@ module PFUMX (input ALUT, BLUT, C0, output Z);
 endmodule
 
 // ---------------------------------------
-(* abc_box_id=2 *)
+//(* abc_box_id=2 *)
 module TRELLIS_DPR16X4 (
 	input [3:0] DI,
 	input [3:0] WAD,
-- 
cgit v1.2.3


From b304744d1506ae5a672639b6baab43c9bce97f00 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Tue, 18 Jun 2019 09:50:37 -0700
Subject: Clean up

---
 techlibs/ecp5/cells_map.v | 10 ++++------
 1 file changed, 4 insertions(+), 6 deletions(-)

(limited to 'techlibs/ecp5')

diff --git a/techlibs/ecp5/cells_map.v b/techlibs/ecp5/cells_map.v
index 53a89e8a3..b504d51e2 100644
--- a/techlibs/ecp5/cells_map.v
+++ b/techlibs/ecp5/cells_map.v
@@ -70,6 +70,8 @@ module \$lut (A, Y);
     parameter WIDTH = 0;
     parameter LUT = 0;
 
+    input [WIDTH-1:0] A;
+    output Y;
 
     // Need to swap input ordering, and fix init accordingly,
     // to match ABC's expectation of LUT inputs in non-decreasing
@@ -86,19 +88,15 @@ module \$lut (A, Y);
     endfunction
 
     function [2**P_WIDTH-1:0] permute_init;
-        input [2**P_WIDTH-1:0] orig;
         integer i;
         begin
             permute_init = 0;
             for (i = 0; i < 2**P_WIDTH; i = i + 1)
-                permute_init[i] = orig[permute_index(i)];
+                permute_init[i] = LUT[permute_index(i)];
         end
     endfunction
 
-    parameter [2**P_WIDTH-1:0] P_LUT = permute_init(LUT);
-
-    input [WIDTH-1:0] A;
-    output Y;
+    parameter [2**P_WIDTH-1:0] P_LUT = permute_init();
 
     generate
         if (WIDTH == 1) begin
-- 
cgit v1.2.3


From a0d3d2bb41cd11b5b33620e16cb67c6568b16847 Mon Sep 17 00:00:00 2001
From: David Shah <dave@ds0.me>
Date: Fri, 21 Jun 2019 09:44:13 +0100
Subject: ecp5: Improve mapping of $alu when BI is used

Signed-off-by: David Shah <dave@ds0.me>
---
 techlibs/ecp5/arith_map.v | 9 +++++----
 1 file changed, 5 insertions(+), 4 deletions(-)

(limited to 'techlibs/ecp5')

diff --git a/techlibs/ecp5/arith_map.v b/techlibs/ecp5/arith_map.v
index eb7947601..17bde0497 100644
--- a/techlibs/ecp5/arith_map.v
+++ b/techlibs/ecp5/arith_map.v
@@ -50,20 +50,21 @@ module _80_ecp5_alu (A, B, CI, BI, X, Y, CO);
 
 	wire [Y_WIDTH2-1:0] AA = A_buf;
 	wire [Y_WIDTH2-1:0] BB = BI ? ~B_buf : B_buf;
+	wire [Y_WIDTH2-1:0] BX = B_buf;
 	wire [Y_WIDTH2-1:0] C = {CO, CI};
 	wire [Y_WIDTH2-1:0] FCO, Y1;
 
 	genvar i;
 	generate for (i = 0; i < Y_WIDTH2; i = i + 2) begin:slice
 		CCU2C #(
-			.INIT0(16'b0110011010101010),
-			.INIT1(16'b0110011010101010),
+			.INIT0(16'b1001011010101010),
+			.INIT1(16'b1001011010101010),
 			.INJECT1_0("NO"),
 			.INJECT1_1("NO")
 	   ) ccu2c_i (
 			.CIN(C[i]),
-			.A0(AA[i]), .B0(BB[i]), .C0(1'b0), .D0(1'b1),
-			.A1(AA[i+1]), .B1(BB[i+1]), .C1(1'b0), .D1(1'b1),
+			.A0(AA[i]), .B0(BX[i]), .C0(BI), .D0(1'b1),
+			.A1(AA[i+1]), .B1(BX[i+1]), .C1(BI), .D1(1'b1),
 			.S0(Y[i]), .S1(Y1[i]),
 			.COUT(FCO[i])
 		);
-- 
cgit v1.2.3


From 6027549464bf91cee4d4bcbe9586e719dce78c80 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Sat, 22 Jun 2019 14:33:47 -0700
Subject: Add comments to ecp5 box

---
 techlibs/ecp5/abc_5g.box | 6 ++++++
 1 file changed, 6 insertions(+)

(limited to 'techlibs/ecp5')

diff --git a/techlibs/ecp5/abc_5g.box b/techlibs/ecp5/abc_5g.box
index 72af6d9cb..15e26b5d5 100644
--- a/techlibs/ecp5/abc_5g.box
+++ b/techlibs/ecp5/abc_5g.box
@@ -1,5 +1,11 @@
+# NB: Inputs/Outputs must be ordered alphabetically
+#     (with exceptions for carry in/out)
+
 # Box 1 : CCU2C (2xCARRY + 2xLUT4)
 # Outputs: S0, S1, COUT
+#   (NB: carry chain input/output must be last
+#        input/output and have been moved there
+#        overriding the alphabetical ordering)
 # name  ID   w/b   ins    outs
 CCU2C   1      1   9      3
 
-- 
cgit v1.2.3


From ca0225fcfaa8c9c68647034351a1569464959edf Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Mon, 24 Jun 2019 21:55:54 -0700
Subject: Re-enable dist RAM boxes for ECP5

---
 techlibs/ecp5/cells_sim.v | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'techlibs/ecp5')

diff --git a/techlibs/ecp5/cells_sim.v b/techlibs/ecp5/cells_sim.v
index f66147323..567942482 100644
--- a/techlibs/ecp5/cells_sim.v
+++ b/techlibs/ecp5/cells_sim.v
@@ -106,7 +106,7 @@ module PFUMX (input ALUT, BLUT, C0, output Z);
 endmodule
 
 // ---------------------------------------
-//(* abc_box_id=2 *)
+(* abc_box_id=2, abc_scc_break="D" *)
 module TRELLIS_DPR16X4 (
 	input [3:0] DI,
 	input [3:0] WAD,
-- 
cgit v1.2.3


From a4a7e63d84dee73554d53587f38409e25db84b66 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Mon, 24 Jun 2019 22:10:28 -0700
Subject: Revert "Re-enable dist RAM boxes for ECP5"

This reverts commit ca0225fcfaa8c9c68647034351a1569464959edf.
---
 techlibs/ecp5/cells_sim.v | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'techlibs/ecp5')

diff --git a/techlibs/ecp5/cells_sim.v b/techlibs/ecp5/cells_sim.v
index 567942482..f66147323 100644
--- a/techlibs/ecp5/cells_sim.v
+++ b/techlibs/ecp5/cells_sim.v
@@ -106,7 +106,7 @@ module PFUMX (input ALUT, BLUT, C0, output Z);
 endmodule
 
 // ---------------------------------------
-(* abc_box_id=2, abc_scc_break="D" *)
+//(* abc_box_id=2 *)
 module TRELLIS_DPR16X4 (
 	input [3:0] DI,
 	input [3:0] WAD,
-- 
cgit v1.2.3


From 4fadb471a3028487d4b05b3e343b3be49349f78b Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Mon, 24 Jun 2019 22:12:50 -0700
Subject: Re-enable dist RAM boxes for ECP5

---
 techlibs/ecp5/cells_sim.v | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'techlibs/ecp5')

diff --git a/techlibs/ecp5/cells_sim.v b/techlibs/ecp5/cells_sim.v
index f66147323..0239d1afe 100644
--- a/techlibs/ecp5/cells_sim.v
+++ b/techlibs/ecp5/cells_sim.v
@@ -106,7 +106,7 @@ module PFUMX (input ALUT, BLUT, C0, output Z);
 endmodule
 
 // ---------------------------------------
-//(* abc_box_id=2 *)
+(* abc_box_id=2, abc_scc_break="DI" *)
 module TRELLIS_DPR16X4 (
 	input [3:0] DI,
 	input [3:0] WAD,
-- 
cgit v1.2.3


From 4ce329aefd34c53ab2b96cd79540c3e528661037 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Wed, 26 Jun 2019 09:33:48 -0700
Subject: synth_ecp5 rename -nomux to -nowidelut, but preserve former

---
 techlibs/ecp5/synth_ecp5.cc | 12 ++++++------
 1 file changed, 6 insertions(+), 6 deletions(-)

(limited to 'techlibs/ecp5')

diff --git a/techlibs/ecp5/synth_ecp5.cc b/techlibs/ecp5/synth_ecp5.cc
index c6e12248e..01222e55c 100644
--- a/techlibs/ecp5/synth_ecp5.cc
+++ b/techlibs/ecp5/synth_ecp5.cc
@@ -76,7 +76,7 @@ struct SynthEcp5Pass : public ScriptPass
 		log("    -nodram\n");
 		log("        do not use distributed RAM cells in output netlist\n");
 		log("\n");
-		log("    -nomux\n");
+		log("    -nowidelut\n");
 		log("        do not use PFU muxes to implement LUTs larger than LUT4s\n");
 		log("\n");
 		log("    -abc2\n");
@@ -93,7 +93,7 @@ struct SynthEcp5Pass : public ScriptPass
 	}
 
 	string top_opt, blif_file, edif_file, json_file;
-	bool noccu2, nodffe, nobram, nodram, nomux, flatten, retime, abc2, vpr;
+	bool noccu2, nodffe, nobram, nodram, nowidelut, flatten, retime, abc2, vpr;
 
 	void clear_flags() YS_OVERRIDE
 	{
@@ -105,7 +105,7 @@ struct SynthEcp5Pass : public ScriptPass
 		nodffe = false;
 		nobram = false;
 		nodram = false;
-		nomux = false;
+		nowidelut = false;
 		flatten = true;
 		retime = false;
 		abc2 = false;
@@ -172,8 +172,8 @@ struct SynthEcp5Pass : public ScriptPass
 				nodram = true;
 				continue;
 			}
-			if (args[argidx] == "-nomux") {
-				nomux = true;
+			if (args[argidx] == "-nowidelut" || args[argidx] == "-nomux") {
+				nowidelut = true;
 				continue;
 			}
 			if (args[argidx] == "-abc2") {
@@ -264,7 +264,7 @@ struct SynthEcp5Pass : public ScriptPass
 				run("abc", "      (only if -abc2)");
 			}
 			run("techmap -map +/ecp5/latches_map.v");
-			if (nomux)
+			if (nowidelut)
 				run("abc -lut 4 -dress");
 			else
 				run("abc -lut 4:7 -dress");
-- 
cgit v1.2.3


From 988e6163abae4ed0a01952c221d17f70bed9c244 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Wed, 26 Jun 2019 10:23:29 -0700
Subject: Add _nowide variants of LUT libraries in -nowidelut flows

---
 techlibs/ecp5/abc_5g_nowide.lut | 12 ++++++++++++
 techlibs/ecp5/synth_ecp5.cc     |  5 ++++-
 2 files changed, 16 insertions(+), 1 deletion(-)
 create mode 100644 techlibs/ecp5/abc_5g_nowide.lut

(limited to 'techlibs/ecp5')

diff --git a/techlibs/ecp5/abc_5g_nowide.lut b/techlibs/ecp5/abc_5g_nowide.lut
new file mode 100644
index 000000000..60352d892
--- /dev/null
+++ b/techlibs/ecp5/abc_5g_nowide.lut
@@ -0,0 +1,12 @@
+# ECP5-5G LUT library for ABC
+# Note that ECP5 architecture assigns difference
+# in LUT input delay to interconnect, so this is
+# considered too
+
+
+# Simple LUTs
+#  area  D    C    B    A
+1  1     141
+2  1     141  275
+3  1     141  275  379
+4  1     141  275  379  379
diff --git a/techlibs/ecp5/synth_ecp5.cc b/techlibs/ecp5/synth_ecp5.cc
index c80ad0b08..f16a47f01 100644
--- a/techlibs/ecp5/synth_ecp5.cc
+++ b/techlibs/ecp5/synth_ecp5.cc
@@ -273,7 +273,10 @@ struct SynthEcp5Pass : public ScriptPass
 			}
 			run("techmap -map +/ecp5/latches_map.v");
 			if (abc9) {
-				run("abc9 -lut +/ecp5/abc_5g.lut -box +/ecp5/abc_5g.box -W 200");
+				if (nowidelut)
+					run("abc9 -lut +/ecp5/abc_5g_nowide.lut -box +/ecp5/abc_5g.box -W 200");
+				else
+					run("abc9 -lut +/ecp5/abc_5g.lut -box +/ecp5/abc_5g.box -W 200");
 			} else {
 				if (nowidelut)
 					run("abc -lut 4 -dress");
-- 
cgit v1.2.3


From a7a88109f5b750862b8e45c194e8094fd32b8a5f Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Wed, 26 Jun 2019 20:00:15 -0700
Subject: Update comment on boxes

---
 techlibs/ecp5/abc_5g.box | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

(limited to 'techlibs/ecp5')

diff --git a/techlibs/ecp5/abc_5g.box b/techlibs/ecp5/abc_5g.box
index 15e26b5d5..5309aca87 100644
--- a/techlibs/ecp5/abc_5g.box
+++ b/techlibs/ecp5/abc_5g.box
@@ -4,8 +4,9 @@
 # Box 1 : CCU2C (2xCARRY + 2xLUT4)
 # Outputs: S0, S1, COUT
 #   (NB: carry chain input/output must be last
-#        input/output and have been moved there
-#        overriding the alphabetical ordering)
+#        input/output and bus has been moved
+#        there overriding the otherwise
+#        alphabetical ordering)
 # name  ID   w/b   ins    outs
 CCU2C   1      1   9      3
 
-- 
cgit v1.2.3


From 4de25a1949c14f4c343eae957b9402b5ddb574c9 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Wed, 26 Jun 2019 20:02:19 -0700
Subject: Add WE to ECP5 dist RAM's abc_scc_break too

---
 techlibs/ecp5/cells_sim.v | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'techlibs/ecp5')

diff --git a/techlibs/ecp5/cells_sim.v b/techlibs/ecp5/cells_sim.v
index 0239d1afe..b678a14da 100644
--- a/techlibs/ecp5/cells_sim.v
+++ b/techlibs/ecp5/cells_sim.v
@@ -106,7 +106,7 @@ module PFUMX (input ALUT, BLUT, C0, output Z);
 endmodule
 
 // ---------------------------------------
-(* abc_box_id=2, abc_scc_break="DI" *)
+(* abc_box_id=2, abc_scc_break="DI,WRE" *)
 module TRELLIS_DPR16X4 (
 	input [3:0] DI,
 	input [3:0] WAD,
-- 
cgit v1.2.3


From 6c256b8cda66e2ba128d5fa3ba344fe4717711f8 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Thu, 27 Jun 2019 11:20:15 -0700
Subject: Merge origin/master

---
 techlibs/ecp5/cells_map.v | 40 +++++++++++++++++++-
 techlibs/ecp5/cells_sim.v | 94 ++++++++++++++++++++++++++---------------------
 2 files changed, 91 insertions(+), 43 deletions(-)

(limited to 'techlibs/ecp5')

diff --git a/techlibs/ecp5/cells_map.v b/techlibs/ecp5/cells_map.v
index b504d51e2..6985fbbc8 100644
--- a/techlibs/ecp5/cells_map.v
+++ b/techlibs/ecp5/cells_map.v
@@ -47,6 +47,28 @@ module  \$__DFFSE_NP1 (input D, C, E, R, output Q); TRELLIS_FF #(.GSR("DISABLED"
 module  \$__DFFSE_PP0 (input D, C, E, R, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("LSR_OVER_CE"))  _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(R), .DI(D), .Q(Q)); endmodule
 module  \$__DFFSE_PP1 (input D, C, E, R, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("LSR_OVER_CE"))  _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(R), .DI(D), .Q(Q)); endmodule
 
+// TODO: Diamond flip-flops
+// module FD1P3AX(); endmodule
+// module FD1P3AY(); endmodule
+// module FD1P3BX(); endmodule
+// module FD1P3DX(); endmodule
+// module FD1P3IX(); endmodule
+// module FD1P3JX(); endmodule
+// module FD1S3AX(); endmodule
+// module FD1S3AY(); endmodule
+module FD1S3BX(input PD, D, CK, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("1"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("ASYNC"))  _TECHMAP_REPLACE_ (.CLK(CK), .LSR(PD), .DI(D), .Q(Q)); endmodule
+module FD1S3DX(input CD, D, CK, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("1"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("ASYNC"))  _TECHMAP_REPLACE_ (.CLK(CK), .LSR(CD), .DI(D), .Q(Q)); endmodule
+module FD1S3IX(input CD, D, CK, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("1"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("LSR_OVER_CE"))  _TECHMAP_REPLACE_ (.CLK(CK), .LSR(CD), .DI(D), .Q(Q)); endmodule
+module FD1S3JX(input PD, D, CK, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("1"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("LSR_OVER_CE"))  _TECHMAP_REPLACE_ (.CLK(CK), .LSR(PD), .DI(D), .Q(Q)); endmodule
+// module FL1P3AY(); endmodule
+// module FL1P3AZ(); endmodule
+// module FL1P3BX(); endmodule
+// module FL1P3DX(); endmodule
+// module FL1P3IY(); endmodule
+// module FL1P3JY(); endmodule
+// module FL1S3AX(); endmodule
+// module FL1S3AY(); endmodule
+
 // Diamond I/O buffers
 module IB   (input I, output O); (* PULLMODE="NONE" *) TRELLIS_IO #(.DIR("INPUT")) _TECHMAP_REPLACE_ (.B(I), .O(O)); endmodule
 module IBPU (input I, output O); (* PULLMODE="UP"   *) TRELLIS_IO #(.DIR("INPUT"))   _TECHMAP_REPLACE_ (.B(I), .O(O)); endmodule
@@ -62,8 +84,22 @@ module BBPD (input I, T, output O, inout B); (* PULLMODE="DOWN" *) TRELLIS_IO #(
 module ILVDS(input A, AN, output Z); TRELLIS_IO #(.DIR("INPUT"))  _TECHMAP_REPLACE_ (.B(A), .O(Z)); endmodule
 module OLVDS(input A, output Z, ZN); TRELLIS_IO #(.DIR("OUTPUT")) _TECHMAP_REPLACE_ (.B(Z), .I(A)); endmodule
 
-// For Diamond compatibility, FIXME: add all Diamond flipflop mappings
-module FD1S3BX(input PD, D, CK, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("1"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("ASYNC"))  _TECHMAP_REPLACE_ (.CLK(CK), .LSR(PD), .DI(D), .Q(Q)); endmodule
+// Diamond I/O registers
+module IFS1P3BX(input PD, D, SP, SCLK, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("1"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("ASYNC"))  _TECHMAP_REPLACE_ (.CLK(SCLK), .LSR(PD), .CE(SP), .DI(D), .Q(Q)); endmodule
+module IFS1P3DX(input CD, D, SP, SCLK, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("1"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("ASYNC"))  _TECHMAP_REPLACE_ (.CLK(SCLK), .LSR(CD), .CE(SP), .DI(D), .Q(Q)); endmodule
+module IFS1P3IX(input CD, D, SP, SCLK, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("1"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("LSR_OVER_CE"))  _TECHMAP_REPLACE_ (.CLK(SCLK), .LSR(CD), .CE(SP), .DI(D), .Q(Q)); endmodule
+module IFS1P3JX(input PD, D, SP, SCLK, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("1"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("LSR_OVER_CE"))  _TECHMAP_REPLACE_ (.CLK(SCLK), .LSR(PD), .CE(SP), .DI(D), .Q(Q)); endmodule
+
+module OFS1P3BX(input PD, D, SP, SCLK, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("1"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("ASYNC"))  _TECHMAP_REPLACE_ (.CLK(SCLK), .LSR(PD), .CE(SP), .DI(D), .Q(Q)); endmodule
+module OFS1P3DX(input CD, D, SP, SCLK, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("1"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("ASYNC"))  _TECHMAP_REPLACE_ (.CLK(SCLK), .LSR(CD), .CE(SP), .DI(D), .Q(Q)); endmodule
+module OFS1P3IX(input CD, D, SP, SCLK, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("1"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("LSR_OVER_CE"))  _TECHMAP_REPLACE_ (.CLK(SCLK), .LSR(CD), .CE(SP), .DI(D), .Q(Q)); endmodule
+module OFS1P3JX(input PD, D, SP, SCLK, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("1"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("LSR_OVER_CE"))  _TECHMAP_REPLACE_ (.CLK(SCLK), .LSR(PD), .CE(SP), .DI(D), .Q(Q)); endmodule
+
+// TODO: Diamond I/O latches
+// module IFS1S1B(input PD, D, SCLK, output Q); endmodule
+// module IFS1S1D(input CD, D, SCLK, output Q); endmodule
+// module IFS1S1I(input PD, D, SCLK, output Q); endmodule
+// module IFS1S1J(input CD, D, SCLK, output Q); endmodule
 
 `ifndef NO_LUT
 module \$lut (A, Y);
diff --git a/techlibs/ecp5/cells_sim.v b/techlibs/ecp5/cells_sim.v
index b678a14da..08ae0a112 100644
--- a/techlibs/ecp5/cells_sim.v
+++ b/techlibs/ecp5/cells_sim.v
@@ -260,18 +260,6 @@ module TRELLIS_FF(input CLK, LSR, CE, DI, M, output reg Q);
 	endgenerate
 endmodule
 
-// ---------------------------------------
-
-module OBZ(input I, T, output O);
-assign O = T ? 1'bz : I;
-endmodule
-
-// ---------------------------------------
-
-module IB(input I, output O);
-assign O = I;
-endmodule
-
 // ---------------------------------------
 (* keep *)
 module TRELLIS_IO(
@@ -303,19 +291,6 @@ endmodule
 
 // ---------------------------------------
 
-module OB(input I, output O);
-assign O = I;
-endmodule
-
-// ---------------------------------------
-
-module BB(input I, T, output O, inout B);
-assign B = T ? 1'bz : I;
-assign O = B;
-endmodule
-
-// ---------------------------------------
-
 module INV(input A, output Z);
 	assign Z = !A;
 endmodule
@@ -568,19 +543,56 @@ module DP16KD(
   parameter INITVAL_3F = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
 endmodule
 
-// For Diamond compatibility, FIXME: add all Diamond flipflop mappings
-module FD1S3BX(input PD, D, CK, output Q);
-	TRELLIS_FF #(
-		.GSR("DISABLED"),
-		.CEMUX("1"),
-		.CLKMUX("CLK"),
-		.LSRMUX("LSR"),
-		.REGSET("SET"),
-		.SRMODE("ASYNC")
-	) tff_i (
-		.CLK(CK),
-		.LSR(PD),
-		.DI(D),
-		.Q(Q)
-	);
-endmodule
+// TODO: Diamond flip-flops
+// module FD1P3AX(); endmodule
+// module FD1P3AY(); endmodule
+// module FD1P3BX(); endmodule
+// module FD1P3DX(); endmodule
+// module FD1P3IX(); endmodule
+// module FD1P3JX(); endmodule
+// module FD1S3AX(); endmodule
+// module FD1S3AY(); endmodule
+module FD1S3BX(input PD, D, CK, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("1"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("ASYNC"))  tff (.CLK(CK), .LSR(PD), .DI(D), .Q(Q)); endmodule
+module FD1S3DX(input CD, D, CK, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("1"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("ASYNC"))  tff (.CLK(CK), .LSR(CD), .DI(D), .Q(Q)); endmodule
+module FD1S3IX(input CD, D, CK, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("1"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("LSR_OVER_CE"))  tff (.CLK(CK), .LSR(CD), .DI(D), .Q(Q)); endmodule
+module FD1S3JX(input PD, D, CK, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("1"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("LSR_OVER_CE"))  tff (.CLK(CK), .LSR(PD), .DI(D), .Q(Q)); endmodule
+// module FL1P3AY(); endmodule
+// module FL1P3AZ(); endmodule
+// module FL1P3BX(); endmodule
+// module FL1P3DX(); endmodule
+// module FL1P3IY(); endmodule
+// module FL1P3JY(); endmodule
+// module FL1S3AX(); endmodule
+// module FL1S3AY(); endmodule
+
+// Diamond I/O buffers
+module IB   (input I, output O); (* PULLMODE="NONE" *) TRELLIS_IO #(.DIR("INPUT")) tio (.B(I), .O(O)); endmodule
+module IBPU (input I, output O); (* PULLMODE="UP"   *) TRELLIS_IO #(.DIR("INPUT"))   tio (.B(I), .O(O)); endmodule
+module IBPD (input I, output O); (* PULLMODE="DOWN" *) TRELLIS_IO #(.DIR("INPUT")) tio (.B(I), .O(O)); endmodule
+module OB   (input I, output O); (* PULLMODE="NONE" *) TRELLIS_IO #(.DIR("OUTPUT")) tio (.B(O), .I(I)); endmodule
+module OBZ  (input I, T, output O); (* PULLMODE="NONE" *) TRELLIS_IO #(.DIR("OUTPUT")) tio (.B(O), .I(I), .T(T)); endmodule
+module OBZPU(input I, T, output O); (* PULLMODE="UP"   *) TRELLIS_IO #(.DIR("OUTPUT"))   tio (.B(O), .I(I), .T(T)); endmodule
+module OBZPD(input I, T, output O); (* PULLMODE="DOWN" *) TRELLIS_IO #(.DIR("OUTPUT")) tio (.B(O), .I(I), .T(T)); endmodule
+module OBCO (input I, output OT, OC); OLVDS olvds (.A(I), .Z(OT), .ZN(OC)); endmodule
+module BB   (input I, T, output O, inout B); (* PULLMODE="NONE" *) TRELLIS_IO #(.DIR("BIDIR")) tio (.B(B), .I(I), .O(O), .T(T)); endmodule
+module BBPU (input I, T, output O, inout B); (* PULLMODE="UP"   *) TRELLIS_IO #(.DIR("BIDIR"))   tio (.B(B), .I(I), .O(O), .T(T)); endmodule
+module BBPD (input I, T, output O, inout B); (* PULLMODE="DOWN" *) TRELLIS_IO #(.DIR("BIDIR")) tio (.B(B), .I(I), .O(O), .T(T)); endmodule
+module ILVDS(input A, AN, output Z); TRELLIS_IO #(.DIR("INPUT"))  tio (.B(A), .O(Z)); endmodule
+module OLVDS(input A, output Z, ZN); TRELLIS_IO #(.DIR("OUTPUT")) tio (.B(Z), .I(A)); endmodule
+
+// Diamond I/O registers
+module IFS1P3BX(input PD, D, SP, SCLK, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("1"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("ASYNC"))  tff (.CLK(SCLK), .LSR(PD), .CE(SP), .DI(D), .Q(Q)); endmodule
+module IFS1P3DX(input CD, D, SP, SCLK, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("1"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("ASYNC"))  tff (.CLK(SCLK), .LSR(CD), .CE(SP), .DI(D), .Q(Q)); endmodule
+module IFS1P3IX(input CD, D, SP, SCLK, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("1"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("LSR_OVER_CE"))  tff (.CLK(SCLK), .LSR(CD), .CE(SP), .DI(D), .Q(Q)); endmodule
+module IFS1P3JX(input PD, D, SP, SCLK, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("1"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("LSR_OVER_CE"))  tff (.CLK(SCLK), .LSR(PD), .CE(SP), .DI(D), .Q(Q)); endmodule
+
+module OFS1P3BX(input PD, D, SP, SCLK, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("1"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("ASYNC"))  tff (.CLK(SCLK), .LSR(PD), .CE(SP), .DI(D), .Q(Q)); endmodule
+module OFS1P3DX(input CD, D, SP, SCLK, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("1"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("ASYNC"))  tff (.CLK(SCLK), .LSR(CD), .CE(SP), .DI(D), .Q(Q)); endmodule
+module OFS1P3IX(input CD, D, SP, SCLK, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("1"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("LSR_OVER_CE"))  tff (.CLK(SCLK), .LSR(CD), .CE(SP), .DI(D), .Q(Q)); endmodule
+module OFS1P3JX(input PD, D, SP, SCLK, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("1"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("LSR_OVER_CE"))  tff (.CLK(SCLK), .LSR(PD), .CE(SP), .DI(D), .Q(Q)); endmodule
+
+// TODO: Diamond I/O latches
+// module IFS1S1B(input PD, D, SCLK, output Q); endmodule
+// module IFS1S1D(input CD, D, SCLK, output Q); endmodule
+// module IFS1S1I(input PD, D, SCLK, output Q); endmodule
+// module IFS1S1J(input CD, D, SCLK, output Q); endmodule
-- 
cgit v1.2.3


From 9398921af1d21b47aa291d240a1f274418adcaf2 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Thu, 27 Jun 2019 16:07:14 -0700
Subject: Refactor for one "abc_carry" attribute on module

---
 techlibs/ecp5/cells_sim.v | 8 +++-----
 1 file changed, 3 insertions(+), 5 deletions(-)

(limited to 'techlibs/ecp5')

diff --git a/techlibs/ecp5/cells_sim.v b/techlibs/ecp5/cells_sim.v
index 08ae0a112..98f915777 100644
--- a/techlibs/ecp5/cells_sim.v
+++ b/techlibs/ecp5/cells_sim.v
@@ -15,11 +15,9 @@ module L6MUX21 (input D0, D1, SD, output Z);
 endmodule
 
 // ---------------------------------------
-(* abc_box_id=1, abc_carry, lib_whitebox *)
-module CCU2C((* abc_carry_in *) input CIN,
-			   input A0, B0, C0, D0, A1, B1, C1, D1,
-	           output S0, S1,
-	         (* abc_carry_out *) output COUT);
+(* abc_box_id=1, abc_carry="CIN,COUT", lib_whitebox *)
+module CCU2C(input CIN, A0, B0, C0, D0, A1, B1, C1, D1,
+	           output S0, S1, COUT);
 
 	parameter [15:0] INIT0 = 16'h0000;
 	parameter [15:0] INIT1 = 16'h0000;
-- 
cgit v1.2.3


From b9ddee0c87ef3f089995d734ad7f5ea1c65eedce Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Fri, 28 Jun 2019 09:45:40 -0700
Subject: Fix DO4 typo

---
 techlibs/ecp5/abc_5g.box | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'techlibs/ecp5')

diff --git a/techlibs/ecp5/abc_5g.box b/techlibs/ecp5/abc_5g.box
index 5309aca87..c757d137d 100644
--- a/techlibs/ecp5/abc_5g.box
+++ b/techlibs/ecp5/abc_5g.box
@@ -16,7 +16,7 @@ CCU2C   1      1   9      3
 516  516  516  516  412   412  278  278  43
 
 # Box 2 : TRELLIS_DPR16X4 (16x4 dist ram)
-# Outputs: DO0, DO1, DO2, DO3, DO4
+# Outputs: DO0, DO1, DO2, DO3
 # name            ID  w/b   ins   outs
 TRELLIS_DPR16X4   2     0   14    4
 
-- 
cgit v1.2.3


From 0318860b93f7fa4eee148597811c77d67171e5d3 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Fri, 28 Jun 2019 09:45:48 -0700
Subject: Add write address to abc_scc_break of ECP5 dist RAM

---
 techlibs/ecp5/cells_sim.v | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'techlibs/ecp5')

diff --git a/techlibs/ecp5/cells_sim.v b/techlibs/ecp5/cells_sim.v
index 98f915777..acfb6960e 100644
--- a/techlibs/ecp5/cells_sim.v
+++ b/techlibs/ecp5/cells_sim.v
@@ -104,7 +104,7 @@ module PFUMX (input ALUT, BLUT, C0, output Z);
 endmodule
 
 // ---------------------------------------
-(* abc_box_id=2, abc_scc_break="DI,WRE" *)
+(* abc_box_id=2, abc_scc_break="DI,WAD,WRE" *)
 module TRELLIS_DPR16X4 (
 	input [3:0] DI,
 	input [3:0] WAD,
-- 
cgit v1.2.3


From 3f87575cb6cdace3de8dbe1b494e4d29a478878e Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Fri, 28 Jun 2019 09:46:36 -0700
Subject: Disable boxing of ECP5 dist RAM due to regression

---
 techlibs/ecp5/cells_sim.v | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'techlibs/ecp5')

diff --git a/techlibs/ecp5/cells_sim.v b/techlibs/ecp5/cells_sim.v
index acfb6960e..ca88d0a5b 100644
--- a/techlibs/ecp5/cells_sim.v
+++ b/techlibs/ecp5/cells_sim.v
@@ -104,7 +104,7 @@ module PFUMX (input ALUT, BLUT, C0, output Z);
 endmodule
 
 // ---------------------------------------
-(* abc_box_id=2, abc_scc_break="DI,WAD,WRE" *)
+//(* abc_box_id=2, abc_scc_break="DI,WAD,WRE" *)
 module TRELLIS_DPR16X4 (
 	input [3:0] DI,
 	input [3:0] WAD,
-- 
cgit v1.2.3


From dd8d264bf5b4a3d8230caf5ec7160f971131b33c Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Sat, 29 Jun 2019 19:37:04 -0700
Subject: install *_nowide.lut files

---
 techlibs/ecp5/Makefile.inc | 1 +
 1 file changed, 1 insertion(+)

(limited to 'techlibs/ecp5')

diff --git a/techlibs/ecp5/Makefile.inc b/techlibs/ecp5/Makefile.inc
index eee3b418f..ff39ba4fe 100644
--- a/techlibs/ecp5/Makefile.inc
+++ b/techlibs/ecp5/Makefile.inc
@@ -13,6 +13,7 @@ $(eval $(call add_share_file,share/ecp5,techlibs/ecp5/latches_map.v))
 
 $(eval $(call add_share_file,share/ecp5,techlibs/ecp5/abc_5g.box))
 $(eval $(call add_share_file,share/ecp5,techlibs/ecp5/abc_5g.lut))
+$(eval $(call add_share_file,share/ecp5,techlibs/ecp5/abc_5g_nowide.lut))
 
 EXTRA_OBJS += techlibs/ecp5/brams_init.mk techlibs/ecp5/brams_connect.mk
 .SECONDARY: techlibs/ecp5/brams_init.mk techlibs/ecp5/brams_connect.mk
-- 
cgit v1.2.3


From 27b27b8781ab8d57aa85a432aba7e914570feffb Mon Sep 17 00:00:00 2001
From: David Shah <dave@ds0.me>
Date: Tue, 9 Jul 2019 22:26:10 +0100
Subject: synth_ecp5: Fix typo in copyright header

Signed-off-by: David Shah <dave@ds0.me>
---
 techlibs/ecp5/synth_ecp5.cc | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'techlibs/ecp5')

diff --git a/techlibs/ecp5/synth_ecp5.cc b/techlibs/ecp5/synth_ecp5.cc
index f16a47f01..3b0c2ea9e 100644
--- a/techlibs/ecp5/synth_ecp5.cc
+++ b/techlibs/ecp5/synth_ecp5.cc
@@ -2,7 +2,7 @@
  *  yosys -- Yosys Open SYnthesis Suite
  *
  *  Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
- *  Copyright (C) 2018 Clifford Wolf <dave@ds0.me>
+ *  Copyright (C) 2018 David Shah <dave@ds0.me>
  *
  *  Permission to use, copy, modify, and/or distribute this software for any
  *  purpose with or without fee is hereby granted, provided that the above
-- 
cgit v1.2.3


From 6bbd286e033ed25bb49684316a86d6227dec4cd7 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Wed, 10 Jul 2019 12:47:48 -0700
Subject: Error out if -abc9 and -retime specified

---
 techlibs/ecp5/synth_ecp5.cc | 3 +++
 1 file changed, 3 insertions(+)

(limited to 'techlibs/ecp5')

diff --git a/techlibs/ecp5/synth_ecp5.cc b/techlibs/ecp5/synth_ecp5.cc
index 3b0c2ea9e..9f409ca51 100644
--- a/techlibs/ecp5/synth_ecp5.cc
+++ b/techlibs/ecp5/synth_ecp5.cc
@@ -199,6 +199,9 @@ struct SynthEcp5Pass : public ScriptPass
 		if (!design->full_selection())
 			log_cmd_error("This command only operates on fully selected designs!\n");
 
+		if (abc9 && retime)
+				log_cmd_error("-retime option not currently compatible with -abc9!\n");
+
 		log_header(design, "Executing SYNTH_ECP5 pass.\n");
 		log_push();
 
-- 
cgit v1.2.3


From ba099bfe9befccc42df99d2930fdbc686152187c Mon Sep 17 00:00:00 2001
From: whitequark <whitequark@whitequark.org>
Date: Thu, 11 Jul 2019 10:56:59 +0000
Subject: synth_{ice40,ecp5}: more sensible pass label naming.

---
 techlibs/ecp5/synth_ecp5.cc | 10 +++++++---
 1 file changed, 7 insertions(+), 3 deletions(-)

(limited to 'techlibs/ecp5')

diff --git a/techlibs/ecp5/synth_ecp5.cc b/techlibs/ecp5/synth_ecp5.cc
index 9f409ca51..3d189a9f1 100644
--- a/techlibs/ecp5/synth_ecp5.cc
+++ b/techlibs/ecp5/synth_ecp5.cc
@@ -231,23 +231,27 @@ struct SynthEcp5Pass : public ScriptPass
 			run("synth -run coarse");
 		}
 
-		if (!nobram && check_label("bram", "(skip if -nobram)"))
+		if (!nobram && check_label("map_bram", "(skip if -nobram)"))
 		{
 			run("memory_bram -rules +/ecp5/bram.txt");
 			run("techmap -map +/ecp5/brams_map.v");
 		}
 
-		if (!nodram && check_label("dram", "(skip if -nodram)"))
+		if (!nodram && check_label("map_dram", "(skip if -nodram)"))
 		{
 			run("memory_bram -rules +/ecp5/dram.txt");
 			run("techmap -map +/ecp5/drams_map.v");
 		}
 
-		if (check_label("fine"))
+		if (check_label("map_ffram"))
 		{
 			run("opt -fast -mux_undef -undriven -fine");
 			run("memory_map");
 			run("opt -undriven -fine");
+		}
+
+		if (check_label("map_gates"))
+		{
 			if (noccu2)
 				run("techmap");
 			else
-- 
cgit v1.2.3


From 698ab9beeed7ee585117cc1e5f5126a9092942df Mon Sep 17 00:00:00 2001
From: whitequark <whitequark@whitequark.org>
Date: Tue, 16 Jul 2019 20:44:55 +0000
Subject: synth_ecp5: rename dram to lutram everywhere.

---
 techlibs/ecp5/Makefile.inc  |  4 ++--
 techlibs/ecp5/dram.txt      | 17 -----------------
 techlibs/ecp5/drams_map.v   | 28 ----------------------------
 techlibs/ecp5/lutram.txt    | 17 +++++++++++++++++
 techlibs/ecp5/lutrams_map.v | 28 ++++++++++++++++++++++++++++
 techlibs/ecp5/synth_ecp5.cc | 22 +++++++++++-----------
 6 files changed, 58 insertions(+), 58 deletions(-)
 delete mode 100644 techlibs/ecp5/dram.txt
 delete mode 100644 techlibs/ecp5/drams_map.v
 create mode 100644 techlibs/ecp5/lutram.txt
 create mode 100644 techlibs/ecp5/lutrams_map.v

(limited to 'techlibs/ecp5')

diff --git a/techlibs/ecp5/Makefile.inc b/techlibs/ecp5/Makefile.inc
index ff39ba4fe..73e18112f 100644
--- a/techlibs/ecp5/Makefile.inc
+++ b/techlibs/ecp5/Makefile.inc
@@ -4,8 +4,8 @@ OBJS += techlibs/ecp5/synth_ecp5.o techlibs/ecp5/ecp5_ffinit.o
 $(eval $(call add_share_file,share/ecp5,techlibs/ecp5/cells_map.v))
 $(eval $(call add_share_file,share/ecp5,techlibs/ecp5/cells_sim.v))
 $(eval $(call add_share_file,share/ecp5,techlibs/ecp5/cells_bb.v))
-$(eval $(call add_share_file,share/ecp5,techlibs/ecp5/drams_map.v))
-$(eval $(call add_share_file,share/ecp5,techlibs/ecp5/dram.txt))
+$(eval $(call add_share_file,share/ecp5,techlibs/ecp5/lutrams_map.v))
+$(eval $(call add_share_file,share/ecp5,techlibs/ecp5/lutram.txt))
 $(eval $(call add_share_file,share/ecp5,techlibs/ecp5/brams_map.v))
 $(eval $(call add_share_file,share/ecp5,techlibs/ecp5/bram.txt))
 $(eval $(call add_share_file,share/ecp5,techlibs/ecp5/arith_map.v))
diff --git a/techlibs/ecp5/dram.txt b/techlibs/ecp5/dram.txt
deleted file mode 100644
index b94357429..000000000
--- a/techlibs/ecp5/dram.txt
+++ /dev/null
@@ -1,17 +0,0 @@
-bram $__TRELLIS_DPR16X4
-  init 1
-  abits 4
-  dbits 4
-  groups 2
-  ports  1 1
-  wrmode 0 1
-  enable 0 1
-  transp 0 0
-  clocks 0 1
-  clkpol 0 2
-endbram
-
-match $__TRELLIS_DPR16X4
-  make_outreg
-  min wports 1
-endmatch
diff --git a/techlibs/ecp5/drams_map.v b/techlibs/ecp5/drams_map.v
deleted file mode 100644
index 3b3de831f..000000000
--- a/techlibs/ecp5/drams_map.v
+++ /dev/null
@@ -1,28 +0,0 @@
-module \$__TRELLIS_DPR16X4 (CLK1, A1ADDR, A1DATA, B1ADDR, B1DATA, B1EN);
-	parameter [63:0] INIT = 64'bx;
-	parameter CLKPOL2 = 1;
-	input CLK1;
-
-	input [3:0] A1ADDR;
-	output [3:0] A1DATA;
-
-	input [3:0] B1ADDR;
-	input [3:0] B1DATA;
-	input B1EN;
-
-	localparam WCKMUX = CLKPOL2 ? "WCK" : "INV";
-
-	TRELLIS_DPR16X4 #(
-		.INITVAL(INIT),
-		.WCKMUX(WCKMUX),
-		.WREMUX("WRE")
-	) _TECHMAP_REPLACE_ (
-		.RAD(A1ADDR),
-		.DO(A1DATA),
-
-		.WAD(B1ADDR),
-		.DI(B1DATA),
-		.WCK(CLK1),
-		.WRE(B1EN)
-	);
-endmodule
diff --git a/techlibs/ecp5/lutram.txt b/techlibs/ecp5/lutram.txt
new file mode 100644
index 000000000..b94357429
--- /dev/null
+++ b/techlibs/ecp5/lutram.txt
@@ -0,0 +1,17 @@
+bram $__TRELLIS_DPR16X4
+  init 1
+  abits 4
+  dbits 4
+  groups 2
+  ports  1 1
+  wrmode 0 1
+  enable 0 1
+  transp 0 0
+  clocks 0 1
+  clkpol 0 2
+endbram
+
+match $__TRELLIS_DPR16X4
+  make_outreg
+  min wports 1
+endmatch
diff --git a/techlibs/ecp5/lutrams_map.v b/techlibs/ecp5/lutrams_map.v
new file mode 100644
index 000000000..3b3de831f
--- /dev/null
+++ b/techlibs/ecp5/lutrams_map.v
@@ -0,0 +1,28 @@
+module \$__TRELLIS_DPR16X4 (CLK1, A1ADDR, A1DATA, B1ADDR, B1DATA, B1EN);
+	parameter [63:0] INIT = 64'bx;
+	parameter CLKPOL2 = 1;
+	input CLK1;
+
+	input [3:0] A1ADDR;
+	output [3:0] A1DATA;
+
+	input [3:0] B1ADDR;
+	input [3:0] B1DATA;
+	input B1EN;
+
+	localparam WCKMUX = CLKPOL2 ? "WCK" : "INV";
+
+	TRELLIS_DPR16X4 #(
+		.INITVAL(INIT),
+		.WCKMUX(WCKMUX),
+		.WREMUX("WRE")
+	) _TECHMAP_REPLACE_ (
+		.RAD(A1ADDR),
+		.DO(A1DATA),
+
+		.WAD(B1ADDR),
+		.DI(B1DATA),
+		.WCK(CLK1),
+		.WRE(B1EN)
+	);
+endmodule
diff --git a/techlibs/ecp5/synth_ecp5.cc b/techlibs/ecp5/synth_ecp5.cc
index 3d189a9f1..143d1f95c 100644
--- a/techlibs/ecp5/synth_ecp5.cc
+++ b/techlibs/ecp5/synth_ecp5.cc
@@ -71,10 +71,10 @@ struct SynthEcp5Pass : public ScriptPass
 		log("        do not use flipflops with CE in output netlist\n");
 		log("\n");
 		log("    -nobram\n");
-		log("        do not use BRAM cells in output netlist\n");
+		log("        do not use block RAM cells in output netlist\n");
 		log("\n");
-		log("    -nodram\n");
-		log("        do not use distributed RAM cells in output netlist\n");
+		log("    -nolutram\n");
+		log("        do not use LUT RAM cells in output netlist\n");
 		log("\n");
 		log("    -nowidelut\n");
 		log("        do not use PFU muxes to implement LUTs larger than LUT4s\n");
@@ -96,7 +96,7 @@ struct SynthEcp5Pass : public ScriptPass
 	}
 
 	string top_opt, blif_file, edif_file, json_file;
-	bool noccu2, nodffe, nobram, nodram, nowidelut, flatten, retime, abc2, abc9, vpr;
+	bool noccu2, nodffe, nobram, nolutram, nowidelut, flatten, retime, abc2, abc9, vpr;
 
 	void clear_flags() YS_OVERRIDE
 	{
@@ -107,7 +107,7 @@ struct SynthEcp5Pass : public ScriptPass
 		noccu2 = false;
 		nodffe = false;
 		nobram = false;
-		nodram = false;
+		nolutram = false;
 		nowidelut = false;
 		flatten = true;
 		retime = false;
@@ -172,11 +172,11 @@ struct SynthEcp5Pass : public ScriptPass
 				nobram = true;
 				continue;
 			}
-			if (args[argidx] == "-nodram") {
-				nodram = true;
+			if (args[argidx] == "-nolutram" || /*deprecated alias*/ args[argidx] == "-nodram") {
+				nolutram = true;
 				continue;
 			}
-			if (args[argidx] == "-nowidelut" || args[argidx] == "-nomux") {
+			if (args[argidx] == "-nowidelut" || /*deprecated alias*/ args[argidx] == "-nomux") {
 				nowidelut = true;
 				continue;
 			}
@@ -237,10 +237,10 @@ struct SynthEcp5Pass : public ScriptPass
 			run("techmap -map +/ecp5/brams_map.v");
 		}
 
-		if (!nodram && check_label("map_dram", "(skip if -nodram)"))
+		if (!nolutram && check_label("map_lutram", "(skip if -nolutram)"))
 		{
-			run("memory_bram -rules +/ecp5/dram.txt");
-			run("techmap -map +/ecp5/drams_map.v");
+			run("memory_bram -rules +/ecp5/lutram.txt");
+			run("techmap -map +/ecp5/lutrams_map.v");
 		}
 
 		if (check_label("map_ffram"))
-- 
cgit v1.2.3


From a36fd8582e52524a292702fa88b94ee40fc8acc4 Mon Sep 17 00:00:00 2001
From: David Shah <dave@ds0.me>
Date: Wed, 7 Aug 2019 14:19:31 +0100
Subject: ecp5: Make cells_sim.v consistent with nextpnr

Signed-off-by: David Shah <dave@ds0.me>
---
 techlibs/ecp5/cells_sim.v | 345 ++++++++++++++++++++++++++++++++--------------
 1 file changed, 244 insertions(+), 101 deletions(-)

(limited to 'techlibs/ecp5')

diff --git a/techlibs/ecp5/cells_sim.v b/techlibs/ecp5/cells_sim.v
index ca88d0a5b..3d343b315 100644
--- a/techlibs/ecp5/cells_sim.v
+++ b/techlibs/ecp5/cells_sim.v
@@ -333,6 +333,31 @@ module TRELLIS_SLICE(
 	parameter [127:0] CCU2_INJECT1_0 = "NO";
 	parameter [127:0] CCU2_INJECT1_1 = "NO";
 	parameter WREMUX = "WRE";
+	parameter WCKMUX = "WCK";
+
+	parameter A0MUX = "A0";
+	parameter A1MUX = "A1";
+	parameter B0MUX = "B0";
+	parameter B1MUX = "B1";
+	parameter C0MUX = "C0";
+	parameter C1MUX = "C1";
+	parameter D0MUX = "D0";
+	parameter D1MUX = "D1";
+
+	wire A0m, B0m, C0m, D0m;
+	wire A1m, B1m, C1m, D1m;
+
+	generate
+		if (A0MUX == "1") assign A0m = 1'b1; else assign A0m = A0;
+		if (B0MUX == "1") assign B0m = 1'b1; else assign B0m = B0;
+		if (C0MUX == "1") assign C0m = 1'b1; else assign C0m = C0;
+		if (D0MUX == "1") assign D0m = 1'b1; else assign D0m = D0;
+		if (A1MUX == "1") assign A1m = 1'b1; else assign A1m = A1;
+		if (B1MUX == "1") assign B1m = 1'b1; else assign B1m = B1;
+		if (C1MUX == "1") assign C1m = 1'b1; else assign C1m = C1;
+		if (D1MUX == "1") assign D1m = 1'b1; else assign D1m = D1;
+
+	endgenerate
 
 	function [15:0] permute_initval;
 		input [15:0] initval;
@@ -350,13 +375,13 @@ module TRELLIS_SLICE(
 			LUT4 #(
 				.INIT(LUT0_INITVAL)
 			) lut4_0 (
-				.A(A0), .B(B0), .C(C0), .D(D0),
+				.A(A0m), .B(B0m), .C(C0m), .D(D0m),
 				.Z(F0)
 			);
 			LUT4 #(
 				.INIT(LUT1_INITVAL)
 			) lut4_1 (
-				.A(A1), .B(B1), .C(C1), .D(D1),
+				.A(A1m), .B(B1m), .C(C1m), .D(D1m),
 				.Z(F1)
 			);
 			// LUT expansion muxes
@@ -370,20 +395,20 @@ module TRELLIS_SLICE(
 				.INJECT1_1(CCU2_INJECT1_1)
 		  ) ccu2c_i (
 				.CIN(FCI),
-				.A0(A0), .B0(B0), .C0(C0), .D0(D0),
-				.A1(A1), .B1(B1), .C1(C1), .D1(D1),
+				.A0(A0m), .B0(B0m), .C0(C0m), .D0(D0m),
+				.A1(A1m), .B1(B1m), .C1(C1m), .D1(D1m),
 				.S0(F0), .S1(F1),
 				.COUT(FCO)
 			);
 		end else if (MODE == "RAMW") begin
-			assign WDO0 = C1;
-			assign WDO1 = A1;
-			assign WDO2 = D1;
-			assign WDO3 = B1;
-			assign WADO0 = D0;
-			assign WADO1 = B0;
-			assign WADO2 = C0;
-			assign WADO3 = A0;
+			assign WDO0 = C1m;
+			assign WDO1 = A1m;
+			assign WDO2 = D1m;
+			assign WDO3 = B1m;
+			assign WADO0 = D0m;
+			assign WADO1 = B0m;
+			assign WADO2 = C0m;
+			assign WADO3 = A0m;
 		end else if (MODE == "DPRAM") begin
 			TRELLIS_RAM16X2 #(
 				.INITVAL_0(permute_initval(LUT0_INITVAL)),
@@ -393,17 +418,19 @@ module TRELLIS_SLICE(
 				.DI0(WD0), .DI1(WD1),
 				.WAD0(WAD0), .WAD1(WAD1), .WAD2(WAD2), .WAD3(WAD3),
 				.WRE(WRE), .WCK(WCK),
-				.RAD0(D0), .RAD1(B0), .RAD2(C0), .RAD3(A0),
+				.RAD0(D0m), .RAD1(B0m), .RAD2(C0m), .RAD3(A0m),
 				.DO0(F0), .DO1(F1)
 			);
 			// TODO: confirm RAD and INITVAL ordering
 			// DPRAM mode contract?
+`ifdef FORMAL
 			always @(*) begin
-				assert(A0==A1);
-				assert(B0==B1);
-				assert(C0==C1);
-				assert(D0==D1);
+				assert(A0m==A1m);
+				assert(B0m==B1m);
+				assert(C0m==C1m);
+				assert(D0m==D1m);
 			end
+`endif
 		end else begin
 			ERROR_UNKNOWN_SLICE_MODE error();
 		end
@@ -455,90 +482,206 @@ module DP16KD(
   input CSB2, CSB1, CSB0,
   output DOB17, DOB16, DOB15, DOB14, DOB13, DOB12, DOB11, DOB10, DOB9, DOB8, DOB7, DOB6, DOB5, DOB4, DOB3, DOB2, DOB1, DOB0
 );
-  parameter DATA_WIDTH_A = 18;
-  parameter DATA_WIDTH_B = 18;
-
-  parameter REGMODE_A = "NOREG";
-  parameter REGMODE_B = "NOREG";
-
-  parameter RESETMODE = "SYNC";
-  parameter ASYNC_RESET_RELEASE = "SYNC";
-
-  parameter CSDECODE_A = "0b000";
-  parameter CSDECODE_B = "0b000";
-
-  parameter WRITEMODE_A = "NORMAL";
-  parameter WRITEMODE_B = "NORMAL";
-
-  parameter CLKAMUX = "CLKA";
-  parameter CLKBMUX = "CLKB";
-
-  parameter GSR = "ENABLED";
-
-  parameter INITVAL_00 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
-  parameter INITVAL_01 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
-  parameter INITVAL_02 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
-  parameter INITVAL_03 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
-  parameter INITVAL_04 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
-  parameter INITVAL_05 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
-  parameter INITVAL_06 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
-  parameter INITVAL_07 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
-  parameter INITVAL_08 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
-  parameter INITVAL_09 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
-  parameter INITVAL_0A = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
-  parameter INITVAL_0B = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
-  parameter INITVAL_0C = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
-  parameter INITVAL_0D = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
-  parameter INITVAL_0E = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
-  parameter INITVAL_0F = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
-  parameter INITVAL_10 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
-  parameter INITVAL_11 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
-  parameter INITVAL_12 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
-  parameter INITVAL_13 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
-  parameter INITVAL_14 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
-  parameter INITVAL_15 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
-  parameter INITVAL_16 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
-  parameter INITVAL_17 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
-  parameter INITVAL_18 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
-  parameter INITVAL_19 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
-  parameter INITVAL_1A = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
-  parameter INITVAL_1B = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
-  parameter INITVAL_1C = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
-  parameter INITVAL_1D = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
-  parameter INITVAL_1E = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
-  parameter INITVAL_1F = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
-  parameter INITVAL_20 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
-  parameter INITVAL_21 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
-  parameter INITVAL_22 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
-  parameter INITVAL_23 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
-  parameter INITVAL_24 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
-  parameter INITVAL_25 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
-  parameter INITVAL_26 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
-  parameter INITVAL_27 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
-  parameter INITVAL_28 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
-  parameter INITVAL_29 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
-  parameter INITVAL_2A = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
-  parameter INITVAL_2B = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
-  parameter INITVAL_2C = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
-  parameter INITVAL_2D = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
-  parameter INITVAL_2E = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
-  parameter INITVAL_2F = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
-  parameter INITVAL_30 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
-  parameter INITVAL_31 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
-  parameter INITVAL_32 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
-  parameter INITVAL_33 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
-  parameter INITVAL_34 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
-  parameter INITVAL_35 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
-  parameter INITVAL_36 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
-  parameter INITVAL_37 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
-  parameter INITVAL_38 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
-  parameter INITVAL_39 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
-  parameter INITVAL_3A = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
-  parameter INITVAL_3B = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
-  parameter INITVAL_3C = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
-  parameter INITVAL_3D = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
-  parameter INITVAL_3E = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
-  parameter INITVAL_3F = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+	parameter DATA_WIDTH_A = 18;
+	parameter DATA_WIDTH_B = 18;
+
+	parameter REGMODE_A = "NOREG";
+	parameter REGMODE_B = "NOREG";
+
+	parameter RESETMODE = "SYNC";
+	parameter ASYNC_RESET_RELEASE = "SYNC";
+
+	parameter CSDECODE_A = "0b000";
+	parameter CSDECODE_B = "0b000";
+
+	parameter WRITEMODE_A = "NORMAL";
+	parameter WRITEMODE_B = "NORMAL";
+
+	parameter DIA17MUX = "DIA17";
+	parameter DIA16MUX = "DIA16";
+	parameter DIA15MUX = "DIA15";
+	parameter DIA14MUX = "DIA14";
+	parameter DIA13MUX = "DIA13";
+	parameter DIA12MUX = "DIA12";
+	parameter DIA11MUX = "DIA11";
+	parameter DIA10MUX = "DIA10";
+	parameter DIA9MUX = "DIA9";
+	parameter DIA8MUX = "DIA8";
+	parameter DIA7MUX = "DIA7";
+	parameter DIA6MUX = "DIA6";
+	parameter DIA5MUX = "DIA5";
+	parameter DIA4MUX = "DIA4";
+	parameter DIA3MUX = "DIA3";
+	parameter DIA2MUX = "DIA2";
+	parameter DIA1MUX = "DIA1";
+	parameter DIA0MUX = "DIA0";
+	parameter ADA13MUX = "ADA13";
+	parameter ADA12MUX = "ADA12";
+	parameter ADA11MUX = "ADA11";
+	parameter ADA10MUX = "ADA10";
+	parameter ADA9MUX = "ADA9";
+	parameter ADA8MUX = "ADA8";
+	parameter ADA7MUX = "ADA7";
+	parameter ADA6MUX = "ADA6";
+	parameter ADA5MUX = "ADA5";
+	parameter ADA4MUX = "ADA4";
+	parameter ADA3MUX = "ADA3";
+	parameter ADA2MUX = "ADA2";
+	parameter ADA1MUX = "ADA1";
+	parameter ADA0MUX = "ADA0";
+	parameter CEAMUX = "CEA";
+	parameter OCEAMUX = "OCEA";
+	parameter CLKAMUX = "CLKA";
+	parameter WEAMUX = "WEA";
+	parameter RSTAMUX = "RSTA";
+	parameter CSA2MUX = "CSA2";
+	parameter CSA1MUX = "CSA1";
+	parameter CSA0MUX = "CSA0";
+	parameter DOA17MUX = "DOA17";
+	parameter DOA16MUX = "DOA16";
+	parameter DOA15MUX = "DOA15";
+	parameter DOA14MUX = "DOA14";
+	parameter DOA13MUX = "DOA13";
+	parameter DOA12MUX = "DOA12";
+	parameter DOA11MUX = "DOA11";
+	parameter DOA10MUX = "DOA10";
+	parameter DOA9MUX = "DOA9";
+	parameter DOA8MUX = "DOA8";
+	parameter DOA7MUX = "DOA7";
+	parameter DOA6MUX = "DOA6";
+	parameter DOA5MUX = "DOA5";
+	parameter DOA4MUX = "DOA4";
+	parameter DOA3MUX = "DOA3";
+	parameter DOA2MUX = "DOA2";
+	parameter DOA1MUX = "DOA1";
+	parameter DOA0MUX = "DOA0";
+	parameter DIB17MUX = "DIB17";
+	parameter DIB16MUX = "DIB16";
+	parameter DIB15MUX = "DIB15";
+	parameter DIB14MUX = "DIB14";
+	parameter DIB13MUX = "DIB13";
+	parameter DIB12MUX = "DIB12";
+	parameter DIB11MUX = "DIB11";
+	parameter DIB10MUX = "DIB10";
+	parameter DIB9MUX = "DIB9";
+	parameter DIB8MUX = "DIB8";
+	parameter DIB7MUX = "DIB7";
+	parameter DIB6MUX = "DIB6";
+	parameter DIB5MUX = "DIB5";
+	parameter DIB4MUX = "DIB4";
+	parameter DIB3MUX = "DIB3";
+	parameter DIB2MUX = "DIB2";
+	parameter DIB1MUX = "DIB1";
+	parameter DIB0MUX = "DIB0";
+	parameter ADB13MUX = "ADB13";
+	parameter ADB12MUX = "ADB12";
+	parameter ADB11MUX = "ADB11";
+	parameter ADB10MUX = "ADB10";
+	parameter ADB9MUX = "ADB9";
+	parameter ADB8MUX = "ADB8";
+	parameter ADB7MUX = "ADB7";
+	parameter ADB6MUX = "ADB6";
+	parameter ADB5MUX = "ADB5";
+	parameter ADB4MUX = "ADB4";
+	parameter ADB3MUX = "ADB3";
+	parameter ADB2MUX = "ADB2";
+	parameter ADB1MUX = "ADB1";
+	parameter ADB0MUX = "ADB0";
+	parameter CEBMUX = "CEB";
+	parameter OCEBMUX = "OCEB";
+	parameter CLKBMUX = "CLKB";
+	parameter WEBMUX = "WEB";
+	parameter RSTBMUX = "RSTB";
+	parameter CSB2MUX = "CSB2";
+	parameter CSB1MUX = "CSB1";
+	parameter CSB0MUX = "CSB0";
+	parameter DOB17MUX = "DOB17";
+	parameter DOB16MUX = "DOB16";
+	parameter DOB15MUX = "DOB15";
+	parameter DOB14MUX = "DOB14";
+	parameter DOB13MUX = "DOB13";
+	parameter DOB12MUX = "DOB12";
+	parameter DOB11MUX = "DOB11";
+	parameter DOB10MUX = "DOB10";
+	parameter DOB9MUX = "DOB9";
+	parameter DOB8MUX = "DOB8";
+	parameter DOB7MUX = "DOB7";
+	parameter DOB6MUX = "DOB6";
+	parameter DOB5MUX = "DOB5";
+	parameter DOB4MUX = "DOB4";
+	parameter DOB3MUX = "DOB3";
+	parameter DOB2MUX = "DOB2";
+	parameter DOB1MUX = "DOB1";
+	parameter DOB0MUX = "DOB0";
+
+	parameter WID = 0;
+
+	parameter GSR = "ENABLED";
+
+	parameter INITVAL_00 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+	parameter INITVAL_01 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+	parameter INITVAL_02 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+	parameter INITVAL_03 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+	parameter INITVAL_04 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+	parameter INITVAL_05 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+	parameter INITVAL_06 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+	parameter INITVAL_07 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+	parameter INITVAL_08 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+	parameter INITVAL_09 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+	parameter INITVAL_0A = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+	parameter INITVAL_0B = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+	parameter INITVAL_0C = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+	parameter INITVAL_0D = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+	parameter INITVAL_0E = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+	parameter INITVAL_0F = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+	parameter INITVAL_10 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+	parameter INITVAL_11 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+	parameter INITVAL_12 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+	parameter INITVAL_13 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+	parameter INITVAL_14 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+	parameter INITVAL_15 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+	parameter INITVAL_16 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+	parameter INITVAL_17 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+	parameter INITVAL_18 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+	parameter INITVAL_19 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+	parameter INITVAL_1A = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+	parameter INITVAL_1B = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+	parameter INITVAL_1C = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+	parameter INITVAL_1D = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+	parameter INITVAL_1E = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+	parameter INITVAL_1F = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+	parameter INITVAL_20 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+	parameter INITVAL_21 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+	parameter INITVAL_22 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+	parameter INITVAL_23 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+	parameter INITVAL_24 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+	parameter INITVAL_25 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+	parameter INITVAL_26 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+	parameter INITVAL_27 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+	parameter INITVAL_28 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+	parameter INITVAL_29 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+	parameter INITVAL_2A = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+	parameter INITVAL_2B = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+	parameter INITVAL_2C = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+	parameter INITVAL_2D = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+	parameter INITVAL_2E = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+	parameter INITVAL_2F = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+	parameter INITVAL_30 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+	parameter INITVAL_31 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+	parameter INITVAL_32 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+	parameter INITVAL_33 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+	parameter INITVAL_34 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+	parameter INITVAL_35 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+	parameter INITVAL_36 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+	parameter INITVAL_37 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+	parameter INITVAL_38 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+	parameter INITVAL_39 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+	parameter INITVAL_3A = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+	parameter INITVAL_3B = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+	parameter INITVAL_3C = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+	parameter INITVAL_3D = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+	parameter INITVAL_3E = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+	parameter INITVAL_3F = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
 endmodule
 
 // TODO: Diamond flip-flops
-- 
cgit v1.2.3


From 1c57b1e7ea0128aebef8e78bcf4de9aaf9e42c6a Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Fri, 16 Aug 2019 15:56:57 -0700
Subject: Update abc_* attr in ecp5 and ice40

---
 techlibs/ecp5/cells_sim.v | 22 +++++++++++++---------
 1 file changed, 13 insertions(+), 9 deletions(-)

(limited to 'techlibs/ecp5')

diff --git a/techlibs/ecp5/cells_sim.v b/techlibs/ecp5/cells_sim.v
index 3d343b315..864a3550f 100644
--- a/techlibs/ecp5/cells_sim.v
+++ b/techlibs/ecp5/cells_sim.v
@@ -15,10 +15,13 @@ module L6MUX21 (input D0, D1, SD, output Z);
 endmodule
 
 // ---------------------------------------
-(* abc_box_id=1, abc_carry="CIN,COUT", lib_whitebox *)
-module CCU2C(input CIN, A0, B0, C0, D0, A1, B1, C1, D1,
-	           output S0, S1, COUT);
-
+(* abc_box_id=1, lib_whitebox *)
+module CCU2C(
+	(* abc_carry_in *) input CIN,
+	input  A0, B0, C0, D0, A1, B1, C1, D1,
+	output S0, S1,
+	(* abc_carry_out *) output COUT
+);
 	parameter [15:0] INIT0 = 16'h0000;
 	parameter [15:0] INIT1 = 16'h0000;
 	parameter INJECT1_0 = "YES";
@@ -104,12 +107,13 @@ module PFUMX (input ALUT, BLUT, C0, output Z);
 endmodule
 
 // ---------------------------------------
-//(* abc_box_id=2, abc_scc_break="DI,WAD,WRE" *)
+//(* abc_box_id=2 *)
 module TRELLIS_DPR16X4 (
-	input [3:0] DI,
-	input [3:0] WAD,
-	input WRE, WCK,
-	input [3:0] RAD,
+	(* abc_scc_break *) input [3:0] DI,
+	(* abc_scc_break *) input [3:0] WAD,
+	(* abc_scc_break *) input       WRE,
+	input        WCK,
+	input  [3:0] RAD,
 	output [3:0] DO
 );
 	parameter WCKMUX = "WCK";
-- 
cgit v1.2.3


From d81a090d89d87837d3e18f9c724fe5c89ddf1f64 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Mon, 19 Aug 2019 09:56:17 -0700
Subject: Unify abc_carry_{in,out} into abc_carry and use port dir, as @mithro

---
 techlibs/ecp5/cells_sim.v | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

(limited to 'techlibs/ecp5')

diff --git a/techlibs/ecp5/cells_sim.v b/techlibs/ecp5/cells_sim.v
index 864a3550f..2fcb0369e 100644
--- a/techlibs/ecp5/cells_sim.v
+++ b/techlibs/ecp5/cells_sim.v
@@ -17,10 +17,10 @@ endmodule
 // ---------------------------------------
 (* abc_box_id=1, lib_whitebox *)
 module CCU2C(
-	(* abc_carry_in *) input CIN,
+	(* abc_carry *) input CIN,
 	input  A0, B0, C0, D0, A1, B1, C1, D1,
 	output S0, S1,
-	(* abc_carry_out *) output COUT
+	(* abc_carry *) output COUT
 );
 	parameter [15:0] INIT0 = 16'h0000;
 	parameter [15:0] INIT1 = 16'h0000;
-- 
cgit v1.2.3


From 55acf3120fa47bb95be8a6551738f4f9b1c70a21 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Tue, 20 Aug 2019 18:59:03 -0700
Subject: ecp5 to use abc_map.v and _unmap.v

---
 techlibs/ecp5/Makefile.inc  |  3 +++
 techlibs/ecp5/abc_5g.box    | 18 +++++++++---------
 techlibs/ecp5/abc_map.v     | 24 ++++++++++++++++++++++++
 techlibs/ecp5/abc_model.v   | 18 ++++++++++++++++++
 techlibs/ecp5/abc_unmap.v   | 25 +++++++++++++++++++++++++
 techlibs/ecp5/cells_sim.v   |  7 +++----
 techlibs/ecp5/synth_ecp5.cc |  8 +++++++-
 7 files changed, 89 insertions(+), 14 deletions(-)
 create mode 100644 techlibs/ecp5/abc_map.v
 create mode 100644 techlibs/ecp5/abc_model.v
 create mode 100644 techlibs/ecp5/abc_unmap.v

(limited to 'techlibs/ecp5')

diff --git a/techlibs/ecp5/Makefile.inc b/techlibs/ecp5/Makefile.inc
index 73e18112f..cffd5c3a4 100644
--- a/techlibs/ecp5/Makefile.inc
+++ b/techlibs/ecp5/Makefile.inc
@@ -11,6 +11,9 @@ $(eval $(call add_share_file,share/ecp5,techlibs/ecp5/bram.txt))
 $(eval $(call add_share_file,share/ecp5,techlibs/ecp5/arith_map.v))
 $(eval $(call add_share_file,share/ecp5,techlibs/ecp5/latches_map.v))
 
+$(eval $(call add_share_file,share/ecp5,techlibs/ecp5/abc_map.v))
+$(eval $(call add_share_file,share/ecp5,techlibs/ecp5/abc_unmap.v))
+$(eval $(call add_share_file,share/ecp5,techlibs/ecp5/abc_model.v))
 $(eval $(call add_share_file,share/ecp5,techlibs/ecp5/abc_5g.box))
 $(eval $(call add_share_file,share/ecp5,techlibs/ecp5/abc_5g.lut))
 $(eval $(call add_share_file,share/ecp5,techlibs/ecp5/abc_5g_nowide.lut))
diff --git a/techlibs/ecp5/abc_5g.box b/techlibs/ecp5/abc_5g.box
index c757d137d..66ebe196a 100644
--- a/techlibs/ecp5/abc_5g.box
+++ b/techlibs/ecp5/abc_5g.box
@@ -15,16 +15,16 @@ CCU2C   1      1   9      3
 630  379  630  379  526   275  392  141  273
 516  516  516  516  412   412  278  278  43
 
-# Box 2 : TRELLIS_DPR16X4 (16x4 dist ram)
+# Box 2 : TRELLIS_DPR16X4_COMB (16x4 dist ram)
 # Outputs: DO0, DO1, DO2, DO3
-# name            ID  w/b   ins   outs
-TRELLIS_DPR16X4   2     0   14    4
-
-#DI0   DI1   DI2   DI3   RAD0   RAD1   RAD2   RAD3   WAD0    WAD1   WAD2   WAD3  WCK   WRE
--      -     -     -     141    379    275    379    -       -      -      -     -     -
--      -     -     -     141    379    275    379    -       -      -      -     -     -
--      -     -     -     141    379    275    379    -       -      -      -     -     -
--      -     -     -     141    379    275    379    -       -      -      -     -     -
+# name               ID  w/b   ins   outs
+$__ABC_RAM16X2_COMB  2     0   8    4
+
+#A0   A1   A2   A3   RAD0   RAD1   RAD2   RAD3
+0     0    0    0    141    379    275    379
+0     0    0    0    141    379    275    379
+0     0    0    0    141    379    275    379
+0     0    0    0    141    379    275    379
 
 # Box 3 : PFUMX (MUX2)
 # Outputs: Z
diff --git a/techlibs/ecp5/abc_map.v b/techlibs/ecp5/abc_map.v
new file mode 100644
index 000000000..e8187ed18
--- /dev/null
+++ b/techlibs/ecp5/abc_map.v
@@ -0,0 +1,24 @@
+// ---------------------------------------
+
+module TRELLIS_DPR16X4 (
+	input  [3:0] DI,
+	input  [3:0] WAD,
+	input        WRE,
+	input        WCK,
+	input  [3:0] RAD,
+	output [3:0] DO
+);
+	parameter WCKMUX = "WCK";
+	parameter WREMUX = "WRE";
+	parameter [63:0] INITVAL = 64'h0000000000000000;
+    wire [3:0] \$DO ;
+
+    \$__ABC_DPR16X4_SEQ #(
+      .WCKMUX(WCKMUX), .WREMUX(WREMUX), .INITVAL(INITVAL)
+    ) _TECHMAP_REPLACE_ (
+      .DI(DI), .WAD(WAD), .WRE(WRE), .WCK(WCK),
+      .RAD(RAD), .DO(\$DO )
+    );
+
+    \$__ABC_DPR16X4_COMB do (.A(\$DO ), .S(RAD), .Y(DO));
+endmodule
diff --git a/techlibs/ecp5/abc_model.v b/techlibs/ecp5/abc_model.v
new file mode 100644
index 000000000..4eb923cb1
--- /dev/null
+++ b/techlibs/ecp5/abc_model.v
@@ -0,0 +1,18 @@
+// ---------------------------------------
+
+(* abc_box_id=2 *)
+module \$__ABC_DPR16X4_COMB (input [3:0] A, S, output [3:0] Y);
+endmodule
+
+module \$__ABC_DPR16X4_SEQ (
+	input  [3:0] DI,
+	input  [3:0] WAD,
+	input        WRE,
+	input        WCK,
+	input  [3:0] RAD,
+	output [3:0] DO
+);
+	parameter WCKMUX = "WCK";
+	parameter WREMUX = "WRE";
+	parameter [63:0] INITVAL = 64'h0000000000000000;
+endmodule
diff --git a/techlibs/ecp5/abc_unmap.v b/techlibs/ecp5/abc_unmap.v
new file mode 100644
index 000000000..0f918c202
--- /dev/null
+++ b/techlibs/ecp5/abc_unmap.v
@@ -0,0 +1,25 @@
+// ---------------------------------------
+
+module \$__ABC_DPR16X4_COMB (input [3:0] A, S, output [3:0] Y);
+    assign Y = A;
+endmodule
+
+module \$__ABC_DPR16X4_SEQ (
+	input  [3:0] DI,
+	input  [3:0] WAD,
+	input        WRE,
+	input        WCK,
+	input  [3:0] RAD,
+	output [3:0] DO
+);
+	parameter WCKMUX = "WCK";
+	parameter WREMUX = "WRE";
+	parameter [63:0] INITVAL = 64'h0000000000000000;
+
+    TRELLIS_DPR16X4 #(
+      .WCKMUX(WCKMUX), .WREMUX(WREMUX), .INITVAL(INITVAL)
+    ) _TECHMAP_REPLACE_ (
+      .DI(DI), .WAD(WAD), .WRE(WRE), .WCK(WCK),
+      .RAD(RAD), .DO(DO)
+    );
+endmodule
diff --git a/techlibs/ecp5/cells_sim.v b/techlibs/ecp5/cells_sim.v
index 2fcb0369e..f79a27312 100644
--- a/techlibs/ecp5/cells_sim.v
+++ b/techlibs/ecp5/cells_sim.v
@@ -107,11 +107,10 @@ module PFUMX (input ALUT, BLUT, C0, output Z);
 endmodule
 
 // ---------------------------------------
-//(* abc_box_id=2 *)
 module TRELLIS_DPR16X4 (
-	(* abc_scc_break *) input [3:0] DI,
-	(* abc_scc_break *) input [3:0] WAD,
-	(* abc_scc_break *) input       WRE,
+	input  [3:0] DI,
+	input  [3:0] WAD,
+	input        WRE,
 	input        WCK,
 	input  [3:0] RAD,
 	output [3:0] DO
diff --git a/techlibs/ecp5/synth_ecp5.cc b/techlibs/ecp5/synth_ecp5.cc
index 143d1f95c..93e1cd5b5 100644
--- a/techlibs/ecp5/synth_ecp5.cc
+++ b/techlibs/ecp5/synth_ecp5.cc
@@ -278,12 +278,18 @@ struct SynthEcp5Pass : public ScriptPass
 			if (abc2 || help_mode) {
 				run("abc", "      (only if -abc2)");
 			}
-			run("techmap -map +/ecp5/latches_map.v");
+			std::string techmap_args = "-map +/ecp5/latches_map.v";
+			if (abc9)
+				techmap_args += " -map +/ecp5/abc_map.v";
+			run("techmap " + techmap_args);
+
 			if (abc9) {
+				run("read_verilog -icells -lib +/ecp5/abc_model.v");
 				if (nowidelut)
 					run("abc9 -lut +/ecp5/abc_5g_nowide.lut -box +/ecp5/abc_5g.box -W 200");
 				else
 					run("abc9 -lut +/ecp5/abc_5g.lut -box +/ecp5/abc_5g.box -W 200");
+				run("techmap -map +/ecp5/abc_unmap.v");
 			} else {
 				if (nowidelut)
 					run("abc -lut 4 -dress");
-- 
cgit v1.2.3


From d46dc9c5b4362c1e333979cbbac4f3567904fee5 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Tue, 20 Aug 2019 19:18:36 -0700
Subject: ecp5 to use -max_iter 1

---
 techlibs/ecp5/abc_map.v     | 2 +-
 techlibs/ecp5/cells_sim.v   | 2 +-
 techlibs/ecp5/synth_ecp5.cc | 3 +--
 3 files changed, 3 insertions(+), 4 deletions(-)

(limited to 'techlibs/ecp5')

diff --git a/techlibs/ecp5/abc_map.v b/techlibs/ecp5/abc_map.v
index e8187ed18..ffd25f06d 100644
--- a/techlibs/ecp5/abc_map.v
+++ b/techlibs/ecp5/abc_map.v
@@ -13,7 +13,7 @@ module TRELLIS_DPR16X4 (
 	parameter [63:0] INITVAL = 64'h0000000000000000;
     wire [3:0] \$DO ;
 
-    \$__ABC_DPR16X4_SEQ #(
+    TRELLIS_DPR16X4 #(
       .WCKMUX(WCKMUX), .WREMUX(WREMUX), .INITVAL(INITVAL)
     ) _TECHMAP_REPLACE_ (
       .DI(DI), .WAD(WAD), .WRE(WRE), .WCK(WCK),
diff --git a/techlibs/ecp5/cells_sim.v b/techlibs/ecp5/cells_sim.v
index f79a27312..24de0c3c2 100644
--- a/techlibs/ecp5/cells_sim.v
+++ b/techlibs/ecp5/cells_sim.v
@@ -113,7 +113,7 @@ module TRELLIS_DPR16X4 (
 	input        WRE,
 	input        WCK,
 	input  [3:0] RAD,
-	output [3:0] DO
+	/* (* abc_arrival=<TODO> *) */ output [3:0] DO
 );
 	parameter WCKMUX = "WCK";
 	parameter WREMUX = "WRE";
diff --git a/techlibs/ecp5/synth_ecp5.cc b/techlibs/ecp5/synth_ecp5.cc
index 93e1cd5b5..b1d3160ba 100644
--- a/techlibs/ecp5/synth_ecp5.cc
+++ b/techlibs/ecp5/synth_ecp5.cc
@@ -280,11 +280,10 @@ struct SynthEcp5Pass : public ScriptPass
 			}
 			std::string techmap_args = "-map +/ecp5/latches_map.v";
 			if (abc9)
-				techmap_args += " -map +/ecp5/abc_map.v";
+				techmap_args += " -map +/ecp5/abc_map.v -max_iter 1";
 			run("techmap " + techmap_args);
 
 			if (abc9) {
-				run("read_verilog -icells -lib +/ecp5/abc_model.v");
 				if (nowidelut)
 					run("abc9 -lut +/ecp5/abc_5g_nowide.lut -box +/ecp5/abc_5g.box -W 200");
 				else
-- 
cgit v1.2.3


From 6b1b03d9f771addbd54358299faad181b589c9f8 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Tue, 20 Aug 2019 19:20:17 -0700
Subject: ecp5: remove DPR16X4 from abc_unmap.v

---
 techlibs/ecp5/abc_unmap.v | 20 --------------------
 1 file changed, 20 deletions(-)

(limited to 'techlibs/ecp5')

diff --git a/techlibs/ecp5/abc_unmap.v b/techlibs/ecp5/abc_unmap.v
index 0f918c202..d43cdd93f 100644
--- a/techlibs/ecp5/abc_unmap.v
+++ b/techlibs/ecp5/abc_unmap.v
@@ -3,23 +3,3 @@
 module \$__ABC_DPR16X4_COMB (input [3:0] A, S, output [3:0] Y);
     assign Y = A;
 endmodule
-
-module \$__ABC_DPR16X4_SEQ (
-	input  [3:0] DI,
-	input  [3:0] WAD,
-	input        WRE,
-	input        WCK,
-	input  [3:0] RAD,
-	output [3:0] DO
-);
-	parameter WCKMUX = "WCK";
-	parameter WREMUX = "WRE";
-	parameter [63:0] INITVAL = 64'h0000000000000000;
-
-    TRELLIS_DPR16X4 #(
-      .WCKMUX(WCKMUX), .WREMUX(WREMUX), .INITVAL(INITVAL)
-    ) _TECHMAP_REPLACE_ (
-      .DI(DI), .WAD(WAD), .WRE(WRE), .WCK(WCK),
-      .RAD(RAD), .DO(DO)
-    );
-endmodule
-- 
cgit v1.2.3


From a270af00cc133ac03ec97cf81ed0a7146b7b225e Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Fri, 23 Aug 2019 11:21:44 -0700
Subject: Put abc_* attributes above port

---
 techlibs/ecp5/cells_sim.v | 15 ++++++++++-----
 1 file changed, 10 insertions(+), 5 deletions(-)

(limited to 'techlibs/ecp5')

diff --git a/techlibs/ecp5/cells_sim.v b/techlibs/ecp5/cells_sim.v
index 2fcb0369e..dc8334acb 100644
--- a/techlibs/ecp5/cells_sim.v
+++ b/techlibs/ecp5/cells_sim.v
@@ -17,10 +17,12 @@ endmodule
 // ---------------------------------------
 (* abc_box_id=1, lib_whitebox *)
 module CCU2C(
-	(* abc_carry *) input CIN,
+	(* abc_carry *)
+	input  CIN,
 	input  A0, B0, C0, D0, A1, B1, C1, D1,
 	output S0, S1,
-	(* abc_carry *) output COUT
+	(* abc_carry *)
+	output COUT
 );
 	parameter [15:0] INIT0 = 16'h0000;
 	parameter [15:0] INIT1 = 16'h0000;
@@ -109,9 +111,12 @@ endmodule
 // ---------------------------------------
 //(* abc_box_id=2 *)
 module TRELLIS_DPR16X4 (
-	(* abc_scc_break *) input [3:0] DI,
-	(* abc_scc_break *) input [3:0] WAD,
-	(* abc_scc_break *) input       WRE,
+	(* abc_scc_break *)
+	input  [3:0] DI,
+	(* abc_scc_break *)
+	input  [3:0] WAD,
+	(* abc_scc_break *)
+	input        WRE,
 	input        WCK,
 	input  [3:0] RAD,
 	output [3:0] DO
-- 
cgit v1.2.3


From 85d39653ac62fa4f1f809fb71b0df82a8bd01dfc Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Fri, 23 Aug 2019 13:20:29 -0700
Subject: Remove unused model

---
 techlibs/ecp5/abc_model.v | 13 -------------
 1 file changed, 13 deletions(-)

(limited to 'techlibs/ecp5')

diff --git a/techlibs/ecp5/abc_model.v b/techlibs/ecp5/abc_model.v
index 4eb923cb1..56a733b75 100644
--- a/techlibs/ecp5/abc_model.v
+++ b/techlibs/ecp5/abc_model.v
@@ -3,16 +3,3 @@
 (* abc_box_id=2 *)
 module \$__ABC_DPR16X4_COMB (input [3:0] A, S, output [3:0] Y);
 endmodule
-
-module \$__ABC_DPR16X4_SEQ (
-	input  [3:0] DI,
-	input  [3:0] WAD,
-	input        WRE,
-	input        WCK,
-	input  [3:0] RAD,
-	output [3:0] DO
-);
-	parameter WCKMUX = "WCK";
-	parameter WREMUX = "WRE";
-	parameter [63:0] INITVAL = 64'h0000000000000000;
-endmodule
-- 
cgit v1.2.3


From 455da572723e4f19ddc1d636b700a5fe1e975fbb Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Fri, 23 Aug 2019 13:21:21 -0700
Subject: Fix spacing

---
 techlibs/ecp5/cells_sim.v | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'techlibs/ecp5')

diff --git a/techlibs/ecp5/cells_sim.v b/techlibs/ecp5/cells_sim.v
index e2bf3c854..01b10f392 100644
--- a/techlibs/ecp5/cells_sim.v
+++ b/techlibs/ecp5/cells_sim.v
@@ -116,7 +116,7 @@ module TRELLIS_DPR16X4 (
 	input        WCK,
 	input  [3:0] RAD,
 	/* (* abc_arrival=<TODO> *) */
-    output [3:0] DO
+	output [3:0] DO
 );
 	parameter WCKMUX = "WCK";
 	parameter WREMUX = "WRE";
-- 
cgit v1.2.3


From fc001b473187f13fa0e6f01063ffc9640fb11ef8 Mon Sep 17 00:00:00 2001
From: David Shah <dave@ds0.me>
Date: Tue, 27 Aug 2019 13:07:06 +0100
Subject: ecp5: Add GSR support

Signed-off-by: David Shah <dave@ds0.me>
---
 techlibs/ecp5/Makefile.inc  |   3 +-
 techlibs/ecp5/brams_map.v   |  10 ++--
 techlibs/ecp5/cells_bb.v    |  20 +++++++
 techlibs/ecp5/cells_map.v   |  96 +++++++++++++++----------------
 techlibs/ecp5/ecp5_gsr.cc   | 135 ++++++++++++++++++++++++++++++++++++++++++++
 techlibs/ecp5/synth_ecp5.cc |   2 +
 6 files changed, 212 insertions(+), 54 deletions(-)
 create mode 100644 techlibs/ecp5/ecp5_gsr.cc

(limited to 'techlibs/ecp5')

diff --git a/techlibs/ecp5/Makefile.inc b/techlibs/ecp5/Makefile.inc
index 73e18112f..c41d16076 100644
--- a/techlibs/ecp5/Makefile.inc
+++ b/techlibs/ecp5/Makefile.inc
@@ -1,5 +1,6 @@
 
-OBJS += techlibs/ecp5/synth_ecp5.o techlibs/ecp5/ecp5_ffinit.o
+OBJS += techlibs/ecp5/synth_ecp5.o techlibs/ecp5/ecp5_ffinit.o \
+        techlibs/ecp5/ecp5_gsr.o
 
 $(eval $(call add_share_file,share/ecp5,techlibs/ecp5/cells_map.v))
 $(eval $(call add_share_file,share/ecp5,techlibs/ecp5/cells_sim.v))
diff --git a/techlibs/ecp5/brams_map.v b/techlibs/ecp5/brams_map.v
index b2c136863..0353cbadb 100644
--- a/techlibs/ecp5/brams_map.v
+++ b/techlibs/ecp5/brams_map.v
@@ -33,7 +33,7 @@ module \$__ECP5_DP16KD (CLK2, CLK3, A1ADDR, A1DATA, A1EN, B1ADDR, B1DATA, B1EN);
 			.CLKBMUX(CLKBMUX),
 			.WRITEMODE_A(WRITEMODE_A),
 			.WRITEMODE_B("READBEFOREWRITE"),
-			.GSR("DISABLED")
+			.GSR("AUTO")
 		) _TECHMAP_REPLACE_ (
 			`include "bram_conn_1.vh"
 			.CLKA(CLK2), .CLKB(CLK3),
@@ -50,7 +50,7 @@ module \$__ECP5_DP16KD (CLK2, CLK3, A1ADDR, A1DATA, A1EN, B1ADDR, B1DATA, B1EN);
 			.CLKBMUX(CLKBMUX),
 			.WRITEMODE_A(WRITEMODE_A),
 			.WRITEMODE_B("READBEFOREWRITE"),
-			.GSR("DISABLED")
+			.GSR("AUTO")
 		) _TECHMAP_REPLACE_ (
 			`include "bram_conn_2.vh"
 			.CLKA(CLK2), .CLKB(CLK3),
@@ -67,7 +67,7 @@ module \$__ECP5_DP16KD (CLK2, CLK3, A1ADDR, A1DATA, A1EN, B1ADDR, B1DATA, B1EN);
 			.CLKBMUX(CLKBMUX),
 			.WRITEMODE_A(WRITEMODE_A),
 			.WRITEMODE_B("READBEFOREWRITE"),
-			.GSR("DISABLED")
+			.GSR("AUTO")
 		) _TECHMAP_REPLACE_ (
 			`include "bram_conn_4.vh"
 			.CLKA(CLK2), .CLKB(CLK3),
@@ -84,7 +84,7 @@ module \$__ECP5_DP16KD (CLK2, CLK3, A1ADDR, A1DATA, A1EN, B1ADDR, B1DATA, B1EN);
 			.CLKBMUX(CLKBMUX),
 			.WRITEMODE_A(WRITEMODE_A),
 			.WRITEMODE_B("READBEFOREWRITE"),
-			.GSR("DISABLED")
+			.GSR("AUTO")
 		) _TECHMAP_REPLACE_ (
 			`include "bram_conn_9.vh"
 			.CLKA(CLK2), .CLKB(CLK3),
@@ -101,7 +101,7 @@ module \$__ECP5_DP16KD (CLK2, CLK3, A1ADDR, A1DATA, A1EN, B1ADDR, B1DATA, B1EN);
 			.CLKBMUX(CLKBMUX),
 			.WRITEMODE_A(WRITEMODE_A),
 			.WRITEMODE_B("READBEFOREWRITE"),
-			.GSR("DISABLED")
+			.GSR("AUTO")
 		) _TECHMAP_REPLACE_ (
 			`include "bram_conn_18.vh"
 			.CLKA(CLK2), .CLKB(CLK3),
diff --git a/techlibs/ecp5/cells_bb.v b/techlibs/ecp5/cells_bb.v
index 223e19b9e..8557053b6 100644
--- a/techlibs/ecp5/cells_bb.v
+++ b/techlibs/ecp5/cells_bb.v
@@ -664,3 +664,23 @@ module PCSCLKDIV (
 );
 	parameter GSR = "DISABLED";
 endmodule
+
+// Note: this module is not marked keep as we want it swept away in synth (sim use only)
+(* blackbox *)
+module PUR (
+	input PUR
+);
+	parameter RST_PULSE = 1;
+endmodule
+
+(* blackbox, keep *)
+module GSR (
+	input GSR
+);
+endmodule
+
+(* blackbox, keep *)
+module SGSR (
+	input GSR, CLK
+);
+endmodule
\ No newline at end of file
diff --git a/techlibs/ecp5/cells_map.v b/techlibs/ecp5/cells_map.v
index 6985fbbc8..0a92d906d 100644
--- a/techlibs/ecp5/cells_map.v
+++ b/techlibs/ecp5/cells_map.v
@@ -1,51 +1,51 @@
-module  \$_DFF_N_ (input D, C, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("1"), .CLKMUX("INV"), .LSRMUX("LSR"), .REGSET("RESET"))  _TECHMAP_REPLACE_ (.CLK(C), .LSR(1'b0), .DI(D), .Q(Q)); endmodule
-module  \$_DFF_P_ (input D, C, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("1"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("RESET"))  _TECHMAP_REPLACE_ (.CLK(C), .LSR(1'b0), .DI(D), .Q(Q)); endmodule
-
-module  \$_DFFE_NN_ (input D, C, E, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("INV"), .CLKMUX("INV"), .LSRMUX("LSR"), .REGSET("RESET"))  _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(1'b0), .DI(D), .Q(Q)); endmodule
-module  \$_DFFE_PN_ (input D, C, E, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("INV"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("RESET"))  _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(1'b0), .DI(D), .Q(Q)); endmodule
-
-module  \$_DFFE_NP_ (input D, C, E, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("CE"), .CLKMUX("INV"), .LSRMUX("LSR"), .REGSET("RESET"))  _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(1'b0), .DI(D), .Q(Q)); endmodule
-module  \$_DFFE_PP_ (input D, C, E, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("RESET"))  _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(1'b0), .DI(D), .Q(Q)); endmodule
-
-module  \$_DFF_NN0_ (input D, C, R, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("1"), .CLKMUX("INV"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("ASYNC"))  _TECHMAP_REPLACE_ (.CLK(C), .LSR(!R), .DI(D), .Q(Q)); endmodule
-module  \$_DFF_NN1_ (input D, C, R, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("1"), .CLKMUX("INV"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("ASYNC"))  _TECHMAP_REPLACE_ (.CLK(C), .LSR(!R), .DI(D), .Q(Q)); endmodule
-module  \$_DFF_PN0_ (input D, C, R, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("1"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("ASYNC"))  _TECHMAP_REPLACE_ (.CLK(C), .LSR(!R), .DI(D), .Q(Q)); endmodule
-module  \$_DFF_PN1_ (input D, C, R, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("1"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("ASYNC"))  _TECHMAP_REPLACE_ (.CLK(C), .LSR(!R), .DI(D), .Q(Q)); endmodule
-
-module  \$_DFF_NP0_ (input D, C, R, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("1"), .CLKMUX("INV"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("ASYNC"))  _TECHMAP_REPLACE_ (.CLK(C), .LSR(R), .DI(D), .Q(Q)); endmodule
-module  \$_DFF_NP1_ (input D, C, R, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("1"), .CLKMUX("INV"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("ASYNC"))  _TECHMAP_REPLACE_ (.CLK(C), .LSR(R), .DI(D), .Q(Q)); endmodule
-module  \$_DFF_PP0_ (input D, C, R, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("1"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("ASYNC"))  _TECHMAP_REPLACE_ (.CLK(C), .LSR(R), .DI(D), .Q(Q)); endmodule
-module  \$_DFF_PP1_ (input D, C, R, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("1"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("ASYNC"))  _TECHMAP_REPLACE_ (.CLK(C), .LSR(R), .DI(D), .Q(Q)); endmodule
-
-module  \$__DFFS_NN0_ (input D, C, R, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("1"), .CLKMUX("INV"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("LSR_OVER_CE"))  _TECHMAP_REPLACE_ (.CLK(C), .LSR(!R), .DI(D), .Q(Q)); endmodule
-module  \$__DFFS_NN1_ (input D, C, R, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("1"), .CLKMUX("INV"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("LSR_OVER_CE"))  _TECHMAP_REPLACE_ (.CLK(C), .LSR(!R), .DI(D), .Q(Q)); endmodule
-module  \$__DFFS_PN0_ (input D, C, R, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("1"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("LSR_OVER_CE"))  _TECHMAP_REPLACE_ (.CLK(C), .LSR(!R), .DI(D), .Q(Q)); endmodule
-module  \$__DFFS_PN1_ (input D, C, R, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("1"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("LSR_OVER_CE"))  _TECHMAP_REPLACE_ (.CLK(C), .LSR(!R), .DI(D), .Q(Q)); endmodule
-
-module  \$__DFFS_NP0_ (input D, C, R, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("1"), .CLKMUX("INV"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("LSR_OVER_CE"))  _TECHMAP_REPLACE_ (.CLK(C), .LSR(R), .DI(D), .Q(Q)); endmodule
-module  \$__DFFS_NP1_ (input D, C, R, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("1"), .CLKMUX("INV"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("LSR_OVER_CE"))  _TECHMAP_REPLACE_ (.CLK(C), .LSR(R), .DI(D), .Q(Q)); endmodule
-module  \$__DFFS_PP0_ (input D, C, R, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("1"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("LSR_OVER_CE"))  _TECHMAP_REPLACE_ (.CLK(C), .LSR(R), .DI(D), .Q(Q)); endmodule
-module  \$__DFFS_PP1_ (input D, C, R, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("1"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("LSR_OVER_CE"))  _TECHMAP_REPLACE_ (.CLK(C), .LSR(R), .DI(D), .Q(Q)); endmodule
-
-module  \$__DFFE_NN0 (input D, C, E, R, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("CE"), .CLKMUX("INV"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("ASYNC"))  _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(!R), .DI(D), .Q(Q)); endmodule
-module  \$__DFFE_NN1 (input D, C, E, R, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("CE"), .CLKMUX("INV"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("ASYNC"))  _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(!R), .DI(D), .Q(Q)); endmodule
-module  \$__DFFE_PN0 (input D, C, E, R, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("ASYNC"))  _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(!R), .DI(D), .Q(Q)); endmodule
-module  \$__DFFE_PN1 (input D, C, E, R, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("ASYNC"))  _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(!R), .DI(D), .Q(Q)); endmodule
-
-module  \$__DFFE_NP0 (input D, C, E, R, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("CE"), .CLKMUX("INV"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("ASYNC"))  _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(R), .DI(D), .Q(Q)); endmodule
-module  \$__DFFE_NP1 (input D, C, E, R, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("CE"), .CLKMUX("INV"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("ASYNC"))  _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(R), .DI(D), .Q(Q)); endmodule
-module  \$__DFFE_PP0 (input D, C, E, R, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("ASYNC"))  _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(R), .DI(D), .Q(Q)); endmodule
-module  \$__DFFE_PP1 (input D, C, E, R, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("ASYNC"))  _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(R), .DI(D), .Q(Q)); endmodule
-
-module  \$__DFFSE_NN0 (input D, C, E, R, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("CE"), .CLKMUX("INV"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("LSR_OVER_CE"))  _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(!R), .DI(D), .Q(Q)); endmodule
-module  \$__DFFSE_NN1 (input D, C, E, R, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("CE"), .CLKMUX("INV"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("LSR_OVER_CE"))  _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(!R), .DI(D), .Q(Q)); endmodule
-module  \$__DFFSE_PN0 (input D, C, E, R, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("LSR_OVER_CE"))  _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(!R), .DI(D), .Q(Q)); endmodule
-module  \$__DFFSE_PN1 (input D, C, E, R, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("LSR_OVER_CE"))  _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(!R), .DI(D), .Q(Q)); endmodule
-
-module  \$__DFFSE_NP0 (input D, C, E, R, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("CE"), .CLKMUX("INV"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("LSR_OVER_CE"))  _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(R), .DI(D), .Q(Q)); endmodule
-module  \$__DFFSE_NP1 (input D, C, E, R, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("CE"), .CLKMUX("INV"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("LSR_OVER_CE"))  _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(R), .DI(D), .Q(Q)); endmodule
-module  \$__DFFSE_PP0 (input D, C, E, R, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("LSR_OVER_CE"))  _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(R), .DI(D), .Q(Q)); endmodule
-module  \$__DFFSE_PP1 (input D, C, E, R, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("LSR_OVER_CE"))  _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(R), .DI(D), .Q(Q)); endmodule
+module  \$_DFF_N_ (input D, C, output Q); TRELLIS_FF #(.GSR("AUTO"), .CEMUX("1"), .CLKMUX("INV"), .LSRMUX("LSR"), .REGSET("RESET"))  _TECHMAP_REPLACE_ (.CLK(C), .LSR(1'b0), .DI(D), .Q(Q)); endmodule
+module  \$_DFF_P_ (input D, C, output Q); TRELLIS_FF #(.GSR("AUTO"), .CEMUX("1"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("RESET"))  _TECHMAP_REPLACE_ (.CLK(C), .LSR(1'b0), .DI(D), .Q(Q)); endmodule
+
+module  \$_DFFE_NN_ (input D, C, E, output Q); TRELLIS_FF #(.GSR("AUTO"), .CEMUX("INV"), .CLKMUX("INV"), .LSRMUX("LSR"), .REGSET("RESET"))  _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(1'b0), .DI(D), .Q(Q)); endmodule
+module  \$_DFFE_PN_ (input D, C, E, output Q); TRELLIS_FF #(.GSR("AUTO"), .CEMUX("INV"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("RESET"))  _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(1'b0), .DI(D), .Q(Q)); endmodule
+
+module  \$_DFFE_NP_ (input D, C, E, output Q); TRELLIS_FF #(.GSR("AUTO"), .CEMUX("CE"), .CLKMUX("INV"), .LSRMUX("LSR"), .REGSET("RESET"))  _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(1'b0), .DI(D), .Q(Q)); endmodule
+module  \$_DFFE_PP_ (input D, C, E, output Q); TRELLIS_FF #(.GSR("AUTO"), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("RESET"))  _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(1'b0), .DI(D), .Q(Q)); endmodule
+
+module  \$_DFF_NN0_ (input D, C, R, output Q); TRELLIS_FF #(.GSR("AUTO"), .CEMUX("1"), .CLKMUX("INV"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("ASYNC"))  _TECHMAP_REPLACE_ (.CLK(C), .LSR(!R), .DI(D), .Q(Q)); endmodule
+module  \$_DFF_NN1_ (input D, C, R, output Q); TRELLIS_FF #(.GSR("AUTO"), .CEMUX("1"), .CLKMUX("INV"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("ASYNC"))  _TECHMAP_REPLACE_ (.CLK(C), .LSR(!R), .DI(D), .Q(Q)); endmodule
+module  \$_DFF_PN0_ (input D, C, R, output Q); TRELLIS_FF #(.GSR("AUTO"), .CEMUX("1"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("ASYNC"))  _TECHMAP_REPLACE_ (.CLK(C), .LSR(!R), .DI(D), .Q(Q)); endmodule
+module  \$_DFF_PN1_ (input D, C, R, output Q); TRELLIS_FF #(.GSR("AUTO"), .CEMUX("1"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("ASYNC"))  _TECHMAP_REPLACE_ (.CLK(C), .LSR(!R), .DI(D), .Q(Q)); endmodule
+
+module  \$_DFF_NP0_ (input D, C, R, output Q); TRELLIS_FF #(.GSR("AUTO"), .CEMUX("1"), .CLKMUX("INV"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("ASYNC"))  _TECHMAP_REPLACE_ (.CLK(C), .LSR(R), .DI(D), .Q(Q)); endmodule
+module  \$_DFF_NP1_ (input D, C, R, output Q); TRELLIS_FF #(.GSR("AUTO"), .CEMUX("1"), .CLKMUX("INV"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("ASYNC"))  _TECHMAP_REPLACE_ (.CLK(C), .LSR(R), .DI(D), .Q(Q)); endmodule
+module  \$_DFF_PP0_ (input D, C, R, output Q); TRELLIS_FF #(.GSR("AUTO"), .CEMUX("1"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("ASYNC"))  _TECHMAP_REPLACE_ (.CLK(C), .LSR(R), .DI(D), .Q(Q)); endmodule
+module  \$_DFF_PP1_ (input D, C, R, output Q); TRELLIS_FF #(.GSR("AUTO"), .CEMUX("1"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("ASYNC"))  _TECHMAP_REPLACE_ (.CLK(C), .LSR(R), .DI(D), .Q(Q)); endmodule
+
+module  \$__DFFS_NN0_ (input D, C, R, output Q); TRELLIS_FF #(.GSR("AUTO"), .CEMUX("1"), .CLKMUX("INV"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("LSR_OVER_CE"))  _TECHMAP_REPLACE_ (.CLK(C), .LSR(!R), .DI(D), .Q(Q)); endmodule
+module  \$__DFFS_NN1_ (input D, C, R, output Q); TRELLIS_FF #(.GSR("AUTO"), .CEMUX("1"), .CLKMUX("INV"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("LSR_OVER_CE"))  _TECHMAP_REPLACE_ (.CLK(C), .LSR(!R), .DI(D), .Q(Q)); endmodule
+module  \$__DFFS_PN0_ (input D, C, R, output Q); TRELLIS_FF #(.GSR("AUTO"), .CEMUX("1"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("LSR_OVER_CE"))  _TECHMAP_REPLACE_ (.CLK(C), .LSR(!R), .DI(D), .Q(Q)); endmodule
+module  \$__DFFS_PN1_ (input D, C, R, output Q); TRELLIS_FF #(.GSR("AUTO"), .CEMUX("1"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("LSR_OVER_CE"))  _TECHMAP_REPLACE_ (.CLK(C), .LSR(!R), .DI(D), .Q(Q)); endmodule
+
+module  \$__DFFS_NP0_ (input D, C, R, output Q); TRELLIS_FF #(.GSR("AUTO"), .CEMUX("1"), .CLKMUX("INV"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("LSR_OVER_CE"))  _TECHMAP_REPLACE_ (.CLK(C), .LSR(R), .DI(D), .Q(Q)); endmodule
+module  \$__DFFS_NP1_ (input D, C, R, output Q); TRELLIS_FF #(.GSR("AUTO"), .CEMUX("1"), .CLKMUX("INV"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("LSR_OVER_CE"))  _TECHMAP_REPLACE_ (.CLK(C), .LSR(R), .DI(D), .Q(Q)); endmodule
+module  \$__DFFS_PP0_ (input D, C, R, output Q); TRELLIS_FF #(.GSR("AUTO"), .CEMUX("1"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("LSR_OVER_CE"))  _TECHMAP_REPLACE_ (.CLK(C), .LSR(R), .DI(D), .Q(Q)); endmodule
+module  \$__DFFS_PP1_ (input D, C, R, output Q); TRELLIS_FF #(.GSR("AUTO"), .CEMUX("1"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("LSR_OVER_CE"))  _TECHMAP_REPLACE_ (.CLK(C), .LSR(R), .DI(D), .Q(Q)); endmodule
+
+module  \$__DFFE_NN0 (input D, C, E, R, output Q); TRELLIS_FF #(.GSR("AUTO"), .CEMUX("CE"), .CLKMUX("INV"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("ASYNC"))  _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(!R), .DI(D), .Q(Q)); endmodule
+module  \$__DFFE_NN1 (input D, C, E, R, output Q); TRELLIS_FF #(.GSR("AUTO"), .CEMUX("CE"), .CLKMUX("INV"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("ASYNC"))  _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(!R), .DI(D), .Q(Q)); endmodule
+module  \$__DFFE_PN0 (input D, C, E, R, output Q); TRELLIS_FF #(.GSR("AUTO"), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("ASYNC"))  _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(!R), .DI(D), .Q(Q)); endmodule
+module  \$__DFFE_PN1 (input D, C, E, R, output Q); TRELLIS_FF #(.GSR("AUTO"), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("ASYNC"))  _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(!R), .DI(D), .Q(Q)); endmodule
+
+module  \$__DFFE_NP0 (input D, C, E, R, output Q); TRELLIS_FF #(.GSR("AUTO"), .CEMUX("CE"), .CLKMUX("INV"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("ASYNC"))  _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(R), .DI(D), .Q(Q)); endmodule
+module  \$__DFFE_NP1 (input D, C, E, R, output Q); TRELLIS_FF #(.GSR("AUTO"), .CEMUX("CE"), .CLKMUX("INV"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("ASYNC"))  _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(R), .DI(D), .Q(Q)); endmodule
+module  \$__DFFE_PP0 (input D, C, E, R, output Q); TRELLIS_FF #(.GSR("AUTO"), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("ASYNC"))  _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(R), .DI(D), .Q(Q)); endmodule
+module  \$__DFFE_PP1 (input D, C, E, R, output Q); TRELLIS_FF #(.GSR("AUTO"), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("ASYNC"))  _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(R), .DI(D), .Q(Q)); endmodule
+
+module  \$__DFFSE_NN0 (input D, C, E, R, output Q); TRELLIS_FF #(.GSR("AUTO"), .CEMUX("CE"), .CLKMUX("INV"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("LSR_OVER_CE"))  _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(!R), .DI(D), .Q(Q)); endmodule
+module  \$__DFFSE_NN1 (input D, C, E, R, output Q); TRELLIS_FF #(.GSR("AUTO"), .CEMUX("CE"), .CLKMUX("INV"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("LSR_OVER_CE"))  _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(!R), .DI(D), .Q(Q)); endmodule
+module  \$__DFFSE_PN0 (input D, C, E, R, output Q); TRELLIS_FF #(.GSR("AUTO"), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("LSR_OVER_CE"))  _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(!R), .DI(D), .Q(Q)); endmodule
+module  \$__DFFSE_PN1 (input D, C, E, R, output Q); TRELLIS_FF #(.GSR("AUTO"), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("LSR_OVER_CE"))  _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(!R), .DI(D), .Q(Q)); endmodule
+
+module  \$__DFFSE_NP0 (input D, C, E, R, output Q); TRELLIS_FF #(.GSR("AUTO"), .CEMUX("CE"), .CLKMUX("INV"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("LSR_OVER_CE"))  _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(R), .DI(D), .Q(Q)); endmodule
+module  \$__DFFSE_NP1 (input D, C, E, R, output Q); TRELLIS_FF #(.GSR("AUTO"), .CEMUX("CE"), .CLKMUX("INV"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("LSR_OVER_CE"))  _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(R), .DI(D), .Q(Q)); endmodule
+module  \$__DFFSE_PP0 (input D, C, E, R, output Q); TRELLIS_FF #(.GSR("AUTO"), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("LSR_OVER_CE"))  _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(R), .DI(D), .Q(Q)); endmodule
+module  \$__DFFSE_PP1 (input D, C, E, R, output Q); TRELLIS_FF #(.GSR("AUTO"), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("LSR_OVER_CE"))  _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(R), .DI(D), .Q(Q)); endmodule
 
 // TODO: Diamond flip-flops
 // module FD1P3AX(); endmodule
diff --git a/techlibs/ecp5/ecp5_gsr.cc b/techlibs/ecp5/ecp5_gsr.cc
new file mode 100644
index 000000000..8b8927d31
--- /dev/null
+++ b/techlibs/ecp5/ecp5_gsr.cc
@@ -0,0 +1,135 @@
+/*
+ *  yosys -- Yosys Open SYnthesis Suite
+ *
+ *  Copyright (C) 2012  Clifford Wolf <clifford@clifford.at>
+ *  Copyright (C) 2019  David Shah <david@symbioticeda.com>
+ *
+ *  Permission to use, copy, modify, and/or distribute this software for any
+ *  purpose with or without fee is hereby granted, provided that the above
+ *  copyright notice and this permission notice appear in all copies.
+ *
+ *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ */
+
+#include "kernel/yosys.h"
+#include "kernel/sigtools.h"
+
+USING_YOSYS_NAMESPACE
+PRIVATE_NAMESPACE_BEGIN
+
+struct Ecp5GsrPass : public Pass {
+	Ecp5GsrPass() : Pass("ecp5_gsr", "ECP5: handle GSR") { }
+	void help() YS_OVERRIDE
+	{
+		//   |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
+		log("\n");
+		log("    ecp5_gsr [options] [selection]\n");
+		log("\n");
+		log("Trim active low async resets connected to GSR and resolve GSR parameter,\n");
+		log("if a GSR or SGSR primitive is used in the design.\n");
+		log("\n");
+		log("If any cell has the GSR parameter set to \"AUTO\", this will be resolved\n");
+		log("to \"ENABLED\" if a GSR primitive is present and the (* nogsr *) attribute\n");
+		log("is not set, otherwise it will be resolved to \"DISABLED\".\n");
+		log("\n");
+	}
+	void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
+	{
+		log_header(design, "Executing ECP5_GSR pass (implement FF init values).\n");
+
+		size_t argidx;
+		for (argidx = 1; argidx < args.size(); argidx++)
+		{
+			// if (args[argidx] == "-singleton") {
+			// 	singleton_mode = true;
+			// 	continue;
+			// }
+			break;
+		}
+		extra_args(args, argidx, design);
+
+		for (auto module : design->selected_modules())
+		{
+			log("Handling GSR in %s.\n", log_id(module));
+
+			SigMap sigmap(module);
+
+			SigBit gsr;
+			bool found_gsr = false;
+
+			for (auto cell : module->selected_cells())
+			{
+				if (cell->type != ID(GSR) && cell->type != ID(SGSR))
+					continue;
+				if (found_gsr)
+					log_error("Found more than one GSR or SGSR cell in module %s.\n", log_id(module));
+				found_gsr = true;
+				SigSpec sig_gsr = cell->getPort(ID(GSR));
+				if (GetSize(sig_gsr) < 1)
+					log_error("GSR cell %s has disconnected GSR input.\n", log_id(cell));
+				gsr = sigmap(sig_gsr[0]);
+			}
+
+			// Resolve GSR parameter
+
+			for (auto cell : module->selected_cells())
+			{
+				if (!cell->hasParam(ID(GSR)) || cell->getParam(ID(GSR)).decode_string() != "AUTO")
+					continue;
+				
+				bool gsren = found_gsr;
+				if (cell->get_bool_attribute("\\nogsr"))
+					gsren = false;
+				cell->setParam(ID(GSR), gsren ? Const("ENABLED") : Const("DISABLED"));
+				
+			}
+
+			if (!found_gsr)
+				continue;
+
+			// For finding active low FF inputs
+			pool<SigBit> inverted_gsr;
+
+			log_debug("GSR net in module %s is %s.\n", log_id(module), log_signal(gsr));
+			for (auto cell : module->selected_cells())
+			{
+				if (cell->type != ID($_NOT_))
+					continue;
+				SigSpec sig_a = cell->getPort(ID(A)), sig_y = cell->getPort(ID(Y));
+				if (GetSize(sig_a) < 1 || GetSize(sig_y) < 1)
+					continue;
+				SigBit a = sigmap(sig_a[0]);
+				if (a == gsr)
+					inverted_gsr.insert(sigmap(sig_y[0]));
+			}
+
+			for (auto cell : module->selected_cells())
+			{
+				if (cell->type != ID(TRELLIS_FF))
+					continue;
+				if (!cell->hasParam(ID(GSR)) || cell->getParam(ID(GSR)).decode_string() != "ENABLED")
+					continue;
+				if (!cell->hasParam(ID(SRMODE)) || cell->getParam(ID(SRMODE)).decode_string() != "ASYNC")
+					continue;
+				SigSpec sig_lsr = cell->getPort(ID(LSR));
+				if (GetSize(sig_lsr) < 1)
+					continue;
+				SigBit lsr = sigmap(sig_lsr[0]);
+				if (!inverted_gsr.count(lsr))
+					continue;
+				cell->setParam(ID(SRMODE), Const("SYNC"));
+				cell->unsetPort(ID(LSR));
+			}
+
+		}
+	}
+} Ecp5GsrPass;
+
+PRIVATE_NAMESPACE_END
diff --git a/techlibs/ecp5/synth_ecp5.cc b/techlibs/ecp5/synth_ecp5.cc
index 143d1f95c..a8075e86e 100644
--- a/techlibs/ecp5/synth_ecp5.cc
+++ b/techlibs/ecp5/synth_ecp5.cc
@@ -271,6 +271,8 @@ struct SynthEcp5Pass : public ScriptPass
 			run("opt_expr -undriven -mux_undef");
 			run("simplemap");
 			run("ecp5_ffinit");
+			run("ecp5_gsr");
+			run("opt_clean");
 		}
 
 		if (check_label("map_luts"))
-- 
cgit v1.2.3


From 7e2825a2a4ad9c44fc7c0e7b45c1f926bc896ee5 Mon Sep 17 00:00:00 2001
From: whitequark <whitequark@whitequark.org>
Date: Fri, 30 Aug 2019 09:42:33 +0000
Subject: ecp5: fix CEMUX on IFS/OFS primitives.

---
 techlibs/ecp5/cells_map.v | 18 +++++++++---------
 techlibs/ecp5/cells_sim.v | 18 +++++++++---------
 2 files changed, 18 insertions(+), 18 deletions(-)

(limited to 'techlibs/ecp5')

diff --git a/techlibs/ecp5/cells_map.v b/techlibs/ecp5/cells_map.v
index 0a92d906d..3fc874d94 100644
--- a/techlibs/ecp5/cells_map.v
+++ b/techlibs/ecp5/cells_map.v
@@ -85,15 +85,15 @@ module ILVDS(input A, AN, output Z); TRELLIS_IO #(.DIR("INPUT"))  _TECHMAP_REPLA
 module OLVDS(input A, output Z, ZN); TRELLIS_IO #(.DIR("OUTPUT")) _TECHMAP_REPLACE_ (.B(Z), .I(A)); endmodule
 
 // Diamond I/O registers
-module IFS1P3BX(input PD, D, SP, SCLK, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("1"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("ASYNC"))  _TECHMAP_REPLACE_ (.CLK(SCLK), .LSR(PD), .CE(SP), .DI(D), .Q(Q)); endmodule
-module IFS1P3DX(input CD, D, SP, SCLK, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("1"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("ASYNC"))  _TECHMAP_REPLACE_ (.CLK(SCLK), .LSR(CD), .CE(SP), .DI(D), .Q(Q)); endmodule
-module IFS1P3IX(input CD, D, SP, SCLK, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("1"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("LSR_OVER_CE"))  _TECHMAP_REPLACE_ (.CLK(SCLK), .LSR(CD), .CE(SP), .DI(D), .Q(Q)); endmodule
-module IFS1P3JX(input PD, D, SP, SCLK, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("1"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("LSR_OVER_CE"))  _TECHMAP_REPLACE_ (.CLK(SCLK), .LSR(PD), .CE(SP), .DI(D), .Q(Q)); endmodule
-
-module OFS1P3BX(input PD, D, SP, SCLK, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("1"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("ASYNC"))  _TECHMAP_REPLACE_ (.CLK(SCLK), .LSR(PD), .CE(SP), .DI(D), .Q(Q)); endmodule
-module OFS1P3DX(input CD, D, SP, SCLK, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("1"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("ASYNC"))  _TECHMAP_REPLACE_ (.CLK(SCLK), .LSR(CD), .CE(SP), .DI(D), .Q(Q)); endmodule
-module OFS1P3IX(input CD, D, SP, SCLK, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("1"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("LSR_OVER_CE"))  _TECHMAP_REPLACE_ (.CLK(SCLK), .LSR(CD), .CE(SP), .DI(D), .Q(Q)); endmodule
-module OFS1P3JX(input PD, D, SP, SCLK, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("1"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("LSR_OVER_CE"))  _TECHMAP_REPLACE_ (.CLK(SCLK), .LSR(PD), .CE(SP), .DI(D), .Q(Q)); endmodule
+module IFS1P3BX(input PD, D, SP, SCLK, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("ASYNC"))  _TECHMAP_REPLACE_ (.CLK(SCLK), .LSR(PD), .CE(SP), .DI(D), .Q(Q)); endmodule
+module IFS1P3DX(input CD, D, SP, SCLK, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("ASYNC"))  _TECHMAP_REPLACE_ (.CLK(SCLK), .LSR(CD), .CE(SP), .DI(D), .Q(Q)); endmodule
+module IFS1P3IX(input CD, D, SP, SCLK, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("LSR_OVER_CE"))  _TECHMAP_REPLACE_ (.CLK(SCLK), .LSR(CD), .CE(SP), .DI(D), .Q(Q)); endmodule
+module IFS1P3JX(input PD, D, SP, SCLK, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("LSR_OVER_CE"))  _TECHMAP_REPLACE_ (.CLK(SCLK), .LSR(PD), .CE(SP), .DI(D), .Q(Q)); endmodule
+
+module OFS1P3BX(input PD, D, SP, SCLK, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("ASYNC"))  _TECHMAP_REPLACE_ (.CLK(SCLK), .LSR(PD), .CE(SP), .DI(D), .Q(Q)); endmodule
+module OFS1P3DX(input CD, D, SP, SCLK, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("ASYNC"))  _TECHMAP_REPLACE_ (.CLK(SCLK), .LSR(CD), .CE(SP), .DI(D), .Q(Q)); endmodule
+module OFS1P3IX(input CD, D, SP, SCLK, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("LSR_OVER_CE"))  _TECHMAP_REPLACE_ (.CLK(SCLK), .LSR(CD), .CE(SP), .DI(D), .Q(Q)); endmodule
+module OFS1P3JX(input PD, D, SP, SCLK, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("LSR_OVER_CE"))  _TECHMAP_REPLACE_ (.CLK(SCLK), .LSR(PD), .CE(SP), .DI(D), .Q(Q)); endmodule
 
 // TODO: Diamond I/O latches
 // module IFS1S1B(input PD, D, SCLK, output Q); endmodule
diff --git a/techlibs/ecp5/cells_sim.v b/techlibs/ecp5/cells_sim.v
index dc8334acb..16697c2f7 100644
--- a/techlibs/ecp5/cells_sim.v
+++ b/techlibs/ecp5/cells_sim.v
@@ -731,15 +731,15 @@ module ILVDS(input A, AN, output Z); TRELLIS_IO #(.DIR("INPUT"))  tio (.B(A), .O
 module OLVDS(input A, output Z, ZN); TRELLIS_IO #(.DIR("OUTPUT")) tio (.B(Z), .I(A)); endmodule
 
 // Diamond I/O registers
-module IFS1P3BX(input PD, D, SP, SCLK, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("1"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("ASYNC"))  tff (.CLK(SCLK), .LSR(PD), .CE(SP), .DI(D), .Q(Q)); endmodule
-module IFS1P3DX(input CD, D, SP, SCLK, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("1"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("ASYNC"))  tff (.CLK(SCLK), .LSR(CD), .CE(SP), .DI(D), .Q(Q)); endmodule
-module IFS1P3IX(input CD, D, SP, SCLK, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("1"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("LSR_OVER_CE"))  tff (.CLK(SCLK), .LSR(CD), .CE(SP), .DI(D), .Q(Q)); endmodule
-module IFS1P3JX(input PD, D, SP, SCLK, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("1"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("LSR_OVER_CE"))  tff (.CLK(SCLK), .LSR(PD), .CE(SP), .DI(D), .Q(Q)); endmodule
-
-module OFS1P3BX(input PD, D, SP, SCLK, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("1"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("ASYNC"))  tff (.CLK(SCLK), .LSR(PD), .CE(SP), .DI(D), .Q(Q)); endmodule
-module OFS1P3DX(input CD, D, SP, SCLK, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("1"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("ASYNC"))  tff (.CLK(SCLK), .LSR(CD), .CE(SP), .DI(D), .Q(Q)); endmodule
-module OFS1P3IX(input CD, D, SP, SCLK, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("1"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("LSR_OVER_CE"))  tff (.CLK(SCLK), .LSR(CD), .CE(SP), .DI(D), .Q(Q)); endmodule
-module OFS1P3JX(input PD, D, SP, SCLK, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("1"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("LSR_OVER_CE"))  tff (.CLK(SCLK), .LSR(PD), .CE(SP), .DI(D), .Q(Q)); endmodule
+module IFS1P3BX(input PD, D, SP, SCLK, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("ASYNC"))  tff (.CLK(SCLK), .LSR(PD), .CE(SP), .DI(D), .Q(Q)); endmodule
+module IFS1P3DX(input CD, D, SP, SCLK, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("ASYNC"))  tff (.CLK(SCLK), .LSR(CD), .CE(SP), .DI(D), .Q(Q)); endmodule
+module IFS1P3IX(input CD, D, SP, SCLK, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("LSR_OVER_CE"))  tff (.CLK(SCLK), .LSR(CD), .CE(SP), .DI(D), .Q(Q)); endmodule
+module IFS1P3JX(input PD, D, SP, SCLK, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("LSR_OVER_CE"))  tff (.CLK(SCLK), .LSR(PD), .CE(SP), .DI(D), .Q(Q)); endmodule
+
+module OFS1P3BX(input PD, D, SP, SCLK, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("ASYNC"))  tff (.CLK(SCLK), .LSR(PD), .CE(SP), .DI(D), .Q(Q)); endmodule
+module OFS1P3DX(input CD, D, SP, SCLK, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("ASYNC"))  tff (.CLK(SCLK), .LSR(CD), .CE(SP), .DI(D), .Q(Q)); endmodule
+module OFS1P3IX(input CD, D, SP, SCLK, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("LSR_OVER_CE"))  tff (.CLK(SCLK), .LSR(CD), .CE(SP), .DI(D), .Q(Q)); endmodule
+module OFS1P3JX(input PD, D, SP, SCLK, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("LSR_OVER_CE"))  tff (.CLK(SCLK), .LSR(PD), .CE(SP), .DI(D), .Q(Q)); endmodule
 
 // TODO: Diamond I/O latches
 // module IFS1S1B(input PD, D, SCLK, output Q); endmodule
-- 
cgit v1.2.3


From 6fa8ce93e673177b50888aa94d7f1c8b221d9b10 Mon Sep 17 00:00:00 2001
From: whitequark <whitequark@whitequark.org>
Date: Fri, 30 Aug 2019 09:54:48 +0000
Subject: ecp5: add missing FD primitives.

---
 techlibs/ecp5/cells_map.v | 74 ++++++++++++++++++++++++-----------------------
 techlibs/ecp5/cells_sim.v | 74 ++++++++++++++++++++++++-----------------------
 2 files changed, 76 insertions(+), 72 deletions(-)

(limited to 'techlibs/ecp5')

diff --git a/techlibs/ecp5/cells_map.v b/techlibs/ecp5/cells_map.v
index 3fc874d94..100a3e377 100644
--- a/techlibs/ecp5/cells_map.v
+++ b/techlibs/ecp5/cells_map.v
@@ -47,19 +47,21 @@ module  \$__DFFSE_NP1 (input D, C, E, R, output Q); TRELLIS_FF #(.GSR("AUTO"), .
 module  \$__DFFSE_PP0 (input D, C, E, R, output Q); TRELLIS_FF #(.GSR("AUTO"), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("LSR_OVER_CE"))  _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(R), .DI(D), .Q(Q)); endmodule
 module  \$__DFFSE_PP1 (input D, C, E, R, output Q); TRELLIS_FF #(.GSR("AUTO"), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("LSR_OVER_CE"))  _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(R), .DI(D), .Q(Q)); endmodule
 
-// TODO: Diamond flip-flops
-// module FD1P3AX(); endmodule
-// module FD1P3AY(); endmodule
-// module FD1P3BX(); endmodule
-// module FD1P3DX(); endmodule
-// module FD1P3IX(); endmodule
-// module FD1P3JX(); endmodule
-// module FD1S3AX(); endmodule
-// module FD1S3AY(); endmodule
-module FD1S3BX(input PD, D, CK, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("1"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("ASYNC"))  _TECHMAP_REPLACE_ (.CLK(CK), .LSR(PD), .DI(D), .Q(Q)); endmodule
-module FD1S3DX(input CD, D, CK, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("1"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("ASYNC"))  _TECHMAP_REPLACE_ (.CLK(CK), .LSR(CD), .DI(D), .Q(Q)); endmodule
-module FD1S3IX(input CD, D, CK, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("1"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("LSR_OVER_CE"))  _TECHMAP_REPLACE_ (.CLK(CK), .LSR(CD), .DI(D), .Q(Q)); endmodule
-module FD1S3JX(input PD, D, CK, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("1"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("LSR_OVER_CE"))  _TECHMAP_REPLACE_ (.CLK(CK), .LSR(PD), .DI(D), .Q(Q)); endmodule
+// Diamond flip-flops
+module FD1P3AX(input     D, SP, CK, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("ASYNC"))        _TECHMAP_REPLACE_ (.CLK(CK), .LSR(0),  .CE(SP), .DI(D), .Q(Q)); endmodule
+module FD1P3AY(input     D, SP, CK, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("SET"),   .SRMODE("ASYNC"))        _TECHMAP_REPLACE_ (.CLK(CK), .LSR(0),  .CE(SP), .DI(D), .Q(Q)); endmodule
+module FD1P3BX(input PD, D, SP, CK, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("SET"),   .SRMODE("ASYNC"))        _TECHMAP_REPLACE_ (.CLK(CK), .LSR(PD), .CE(SP), .DI(D), .Q(Q)); endmodule
+module FD1P3DX(input CD, D, SP, CK, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("ASYNC"))        _TECHMAP_REPLACE_ (.CLK(CK), .LSR(CD), .CE(SP), .DI(D), .Q(Q)); endmodule
+module FD1P3IX(input CD, D, SP, CK, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("LSR_OVER_CE"))  _TECHMAP_REPLACE_ (.CLK(CK), .LSR(CD), .CE(SP), .DI(D), .Q(Q)); endmodule
+module FD1P3JX(input PD, D, SP, CK, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("SET"),   .SRMODE("LSR_OVER_CE"))  _TECHMAP_REPLACE_ (.CLK(CK), .LSR(PD), .CE(SP), .DI(D), .Q(Q)); endmodule
+module FD1S3AX(input     D,     CK, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("1"),  .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("ASYNC"))        _TECHMAP_REPLACE_ (.CLK(CK), .LSR(0),           .DI(D), .Q(Q)); endmodule
+module FD1S3AY(input     D,     CK, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("1"),  .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("SET"),   .SRMODE("ASYNC"))        _TECHMAP_REPLACE_ (.CLK(CK), .LSR(0),           .DI(D), .Q(Q)); endmodule
+module FD1S3BX(input PD, D,     CK, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("1"),  .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("SET"),   .SRMODE("ASYNC"))        _TECHMAP_REPLACE_ (.CLK(CK), .LSR(PD),          .DI(D), .Q(Q)); endmodule
+module FD1S3DX(input CD, D,     CK, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("1"),  .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("ASYNC"))        _TECHMAP_REPLACE_ (.CLK(CK), .LSR(CD),          .DI(D), .Q(Q)); endmodule
+module FD1S3IX(input CD, D,     CK, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("1"),  .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("LSR_OVER_CE"))  _TECHMAP_REPLACE_ (.CLK(CK), .LSR(CD),          .DI(D), .Q(Q)); endmodule
+module FD1S3JX(input PD, D,     CK, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("1"),  .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("SET"),   .SRMODE("LSR_OVER_CE"))  _TECHMAP_REPLACE_ (.CLK(CK), .LSR(PD),          .DI(D), .Q(Q)); endmodule
+
+// TODO: Diamond latches
 // module FL1P3AY(); endmodule
 // module FL1P3AZ(); endmodule
 // module FL1P3BX(); endmodule
@@ -69,31 +71,16 @@ module FD1S3JX(input PD, D, CK, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX
 // module FL1S3AX(); endmodule
 // module FL1S3AY(); endmodule
 
-// Diamond I/O buffers
-module IB   (input I, output O); (* PULLMODE="NONE" *) TRELLIS_IO #(.DIR("INPUT")) _TECHMAP_REPLACE_ (.B(I), .O(O)); endmodule
-module IBPU (input I, output O); (* PULLMODE="UP"   *) TRELLIS_IO #(.DIR("INPUT"))   _TECHMAP_REPLACE_ (.B(I), .O(O)); endmodule
-module IBPD (input I, output O); (* PULLMODE="DOWN" *) TRELLIS_IO #(.DIR("INPUT")) _TECHMAP_REPLACE_ (.B(I), .O(O)); endmodule
-module OB   (input I, output O); (* PULLMODE="NONE" *) TRELLIS_IO #(.DIR("OUTPUT")) _TECHMAP_REPLACE_ (.B(O), .I(I)); endmodule
-module OBZ  (input I, T, output O); (* PULLMODE="NONE" *) TRELLIS_IO #(.DIR("OUTPUT")) _TECHMAP_REPLACE_ (.B(O), .I(I), .T(T)); endmodule
-module OBZPU(input I, T, output O); (* PULLMODE="UP"   *) TRELLIS_IO #(.DIR("OUTPUT"))   _TECHMAP_REPLACE_ (.B(O), .I(I), .T(T)); endmodule
-module OBZPD(input I, T, output O); (* PULLMODE="DOWN" *) TRELLIS_IO #(.DIR("OUTPUT")) _TECHMAP_REPLACE_ (.B(O), .I(I), .T(T)); endmodule
-module OBCO (input I, output OT, OC); OLVDS _TECHMAP_REPLACE_ (.A(I), .Z(OT), .ZN(OC)); endmodule
-module BB   (input I, T, output O, inout B); (* PULLMODE="NONE" *) TRELLIS_IO #(.DIR("BIDIR")) _TECHMAP_REPLACE_ (.B(B), .I(I), .O(O), .T(T)); endmodule
-module BBPU (input I, T, output O, inout B); (* PULLMODE="UP"   *) TRELLIS_IO #(.DIR("BIDIR"))   _TECHMAP_REPLACE_ (.B(B), .I(I), .O(O), .T(T)); endmodule
-module BBPD (input I, T, output O, inout B); (* PULLMODE="DOWN" *) TRELLIS_IO #(.DIR("BIDIR")) _TECHMAP_REPLACE_ (.B(B), .I(I), .O(O), .T(T)); endmodule
-module ILVDS(input A, AN, output Z); TRELLIS_IO #(.DIR("INPUT"))  _TECHMAP_REPLACE_ (.B(A), .O(Z)); endmodule
-module OLVDS(input A, output Z, ZN); TRELLIS_IO #(.DIR("OUTPUT")) _TECHMAP_REPLACE_ (.B(Z), .I(A)); endmodule
-
 // Diamond I/O registers
-module IFS1P3BX(input PD, D, SP, SCLK, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("ASYNC"))  _TECHMAP_REPLACE_ (.CLK(SCLK), .LSR(PD), .CE(SP), .DI(D), .Q(Q)); endmodule
-module IFS1P3DX(input CD, D, SP, SCLK, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("ASYNC"))  _TECHMAP_REPLACE_ (.CLK(SCLK), .LSR(CD), .CE(SP), .DI(D), .Q(Q)); endmodule
-module IFS1P3IX(input CD, D, SP, SCLK, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("LSR_OVER_CE"))  _TECHMAP_REPLACE_ (.CLK(SCLK), .LSR(CD), .CE(SP), .DI(D), .Q(Q)); endmodule
-module IFS1P3JX(input PD, D, SP, SCLK, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("LSR_OVER_CE"))  _TECHMAP_REPLACE_ (.CLK(SCLK), .LSR(PD), .CE(SP), .DI(D), .Q(Q)); endmodule
+module IFS1P3BX(input PD, D, SP, SCLK, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("SET"),   .SRMODE("ASYNC"))       _TECHMAP_REPLACE_ (.CLK(SCLK), .LSR(PD), .CE(SP), .DI(D), .Q(Q)); endmodule
+module IFS1P3DX(input CD, D, SP, SCLK, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("ASYNC"))       _TECHMAP_REPLACE_ (.CLK(SCLK), .LSR(CD), .CE(SP), .DI(D), .Q(Q)); endmodule
+module IFS1P3IX(input CD, D, SP, SCLK, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("LSR_OVER_CE")) _TECHMAP_REPLACE_ (.CLK(SCLK), .LSR(CD), .CE(SP), .DI(D), .Q(Q)); endmodule
+module IFS1P3JX(input PD, D, SP, SCLK, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("SET"),   .SRMODE("LSR_OVER_CE")) _TECHMAP_REPLACE_ (.CLK(SCLK), .LSR(PD), .CE(SP), .DI(D), .Q(Q)); endmodule
 
-module OFS1P3BX(input PD, D, SP, SCLK, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("ASYNC"))  _TECHMAP_REPLACE_ (.CLK(SCLK), .LSR(PD), .CE(SP), .DI(D), .Q(Q)); endmodule
-module OFS1P3DX(input CD, D, SP, SCLK, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("ASYNC"))  _TECHMAP_REPLACE_ (.CLK(SCLK), .LSR(CD), .CE(SP), .DI(D), .Q(Q)); endmodule
-module OFS1P3IX(input CD, D, SP, SCLK, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("LSR_OVER_CE"))  _TECHMAP_REPLACE_ (.CLK(SCLK), .LSR(CD), .CE(SP), .DI(D), .Q(Q)); endmodule
-module OFS1P3JX(input PD, D, SP, SCLK, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("LSR_OVER_CE"))  _TECHMAP_REPLACE_ (.CLK(SCLK), .LSR(PD), .CE(SP), .DI(D), .Q(Q)); endmodule
+module OFS1P3BX(input PD, D, SP, SCLK, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("SET"),   .SRMODE("ASYNC"))       _TECHMAP_REPLACE_ (.CLK(SCLK), .LSR(PD), .CE(SP), .DI(D), .Q(Q)); endmodule
+module OFS1P3DX(input CD, D, SP, SCLK, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("ASYNC"))       _TECHMAP_REPLACE_ (.CLK(SCLK), .LSR(CD), .CE(SP), .DI(D), .Q(Q)); endmodule
+module OFS1P3IX(input CD, D, SP, SCLK, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("LSR_OVER_CE")) _TECHMAP_REPLACE_ (.CLK(SCLK), .LSR(CD), .CE(SP), .DI(D), .Q(Q)); endmodule
+module OFS1P3JX(input PD, D, SP, SCLK, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("SET"),   .SRMODE("LSR_OVER_CE")) _TECHMAP_REPLACE_ (.CLK(SCLK), .LSR(PD), .CE(SP), .DI(D), .Q(Q)); endmodule
 
 // TODO: Diamond I/O latches
 // module IFS1S1B(input PD, D, SCLK, output Q); endmodule
@@ -101,6 +88,21 @@ module OFS1P3JX(input PD, D, SP, SCLK, output Q); TRELLIS_FF #(.GSR("DISABLED"),
 // module IFS1S1I(input PD, D, SCLK, output Q); endmodule
 // module IFS1S1J(input CD, D, SCLK, output Q); endmodule
 
+// Diamond I/O buffers
+module IB   (input I,     output O); (* PULLMODE="NONE" *) TRELLIS_IO #(.DIR("INPUT"))  _TECHMAP_REPLACE_ (.B(I), .O(O)); endmodule
+module IBPU (input I,     output O); (* PULLMODE="UP"   *) TRELLIS_IO #(.DIR("INPUT"))  _TECHMAP_REPLACE_ (.B(I), .O(O)); endmodule
+module IBPD (input I,     output O); (* PULLMODE="DOWN" *) TRELLIS_IO #(.DIR("INPUT"))  _TECHMAP_REPLACE_ (.B(I), .O(O)); endmodule
+module OB   (input I,     output O); (* PULLMODE="NONE" *) TRELLIS_IO #(.DIR("OUTPUT")) _TECHMAP_REPLACE_ (.B(O), .I(I)); endmodule
+module OBZ  (input I, T,  output O); (* PULLMODE="NONE" *) TRELLIS_IO #(.DIR("OUTPUT")) _TECHMAP_REPLACE_ (.B(O), .I(I), .T(T)); endmodule
+module OBZPU(input I, T,  output O); (* PULLMODE="UP"   *) TRELLIS_IO #(.DIR("OUTPUT")) _TECHMAP_REPLACE_ (.B(O), .I(I), .T(T)); endmodule
+module OBZPD(input I, T,  output O); (* PULLMODE="DOWN" *) TRELLIS_IO #(.DIR("OUTPUT")) _TECHMAP_REPLACE_ (.B(O), .I(I), .T(T)); endmodule
+module OBCO (input I,     output OT, OC); OLVDS olvds (.A(I), .Z(OT), .ZN(OC)); endmodule
+module BB   (input I, T,  output O, inout B); (* PULLMODE="NONE" *) TRELLIS_IO #(.DIR("BIDIR")) _TECHMAP_REPLACE_ (.B(B), .I(I), .O(O), .T(T)); endmodule
+module BBPU (input I, T,  output O, inout B); (* PULLMODE="UP"   *) TRELLIS_IO #(.DIR("BIDIR")) _TECHMAP_REPLACE_ (.B(B), .I(I), .O(O), .T(T)); endmodule
+module BBPD (input I, T,  output O, inout B); (* PULLMODE="DOWN" *) TRELLIS_IO #(.DIR("BIDIR")) _TECHMAP_REPLACE_ (.B(B), .I(I), .O(O), .T(T)); endmodule
+module ILVDS(input A, AN, output Z    ); TRELLIS_IO #(.DIR("INPUT"))  _TECHMAP_REPLACE_ (.B(A), .O(Z)); endmodule
+module OLVDS(input A,     output Z, ZN); TRELLIS_IO #(.DIR("OUTPUT")) _TECHMAP_REPLACE_ (.B(Z), .I(A)); endmodule
+
 `ifndef NO_LUT
 module \$lut (A, Y);
     parameter WIDTH = 0;
diff --git a/techlibs/ecp5/cells_sim.v b/techlibs/ecp5/cells_sim.v
index 16697c2f7..50b6012e9 100644
--- a/techlibs/ecp5/cells_sim.v
+++ b/techlibs/ecp5/cells_sim.v
@@ -693,19 +693,21 @@ module DP16KD(
 	parameter INITVAL_3F = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
 endmodule
 
-// TODO: Diamond flip-flops
-// module FD1P3AX(); endmodule
-// module FD1P3AY(); endmodule
-// module FD1P3BX(); endmodule
-// module FD1P3DX(); endmodule
-// module FD1P3IX(); endmodule
-// module FD1P3JX(); endmodule
-// module FD1S3AX(); endmodule
-// module FD1S3AY(); endmodule
-module FD1S3BX(input PD, D, CK, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("1"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("ASYNC"))  tff (.CLK(CK), .LSR(PD), .DI(D), .Q(Q)); endmodule
-module FD1S3DX(input CD, D, CK, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("1"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("ASYNC"))  tff (.CLK(CK), .LSR(CD), .DI(D), .Q(Q)); endmodule
-module FD1S3IX(input CD, D, CK, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("1"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("LSR_OVER_CE"))  tff (.CLK(CK), .LSR(CD), .DI(D), .Q(Q)); endmodule
-module FD1S3JX(input PD, D, CK, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("1"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("LSR_OVER_CE"))  tff (.CLK(CK), .LSR(PD), .DI(D), .Q(Q)); endmodule
+// Diamond flip-flops
+module FD1P3AX(input     D, SP, CK, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("ASYNC"))        _TECHMAP_REPLACE_ (.CLK(CK), .LSR(0),  .CE(SP), .DI(D), .Q(Q)); endmodule
+module FD1P3AY(input     D, SP, CK, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("SET"),   .SRMODE("ASYNC"))        _TECHMAP_REPLACE_ (.CLK(CK), .LSR(0),  .CE(SP), .DI(D), .Q(Q)); endmodule
+module FD1P3BX(input PD, D, SP, CK, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("SET"),   .SRMODE("ASYNC"))        _TECHMAP_REPLACE_ (.CLK(CK), .LSR(PD), .CE(SP), .DI(D), .Q(Q)); endmodule
+module FD1P3DX(input CD, D, SP, CK, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("ASYNC"))        _TECHMAP_REPLACE_ (.CLK(CK), .LSR(CD), .CE(SP), .DI(D), .Q(Q)); endmodule
+module FD1P3IX(input CD, D, SP, CK, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("LSR_OVER_CE"))  _TECHMAP_REPLACE_ (.CLK(CK), .LSR(CD), .CE(SP), .DI(D), .Q(Q)); endmodule
+module FD1P3JX(input PD, D, SP, CK, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("SET"),   .SRMODE("LSR_OVER_CE"))  _TECHMAP_REPLACE_ (.CLK(CK), .LSR(PD), .CE(SP), .DI(D), .Q(Q)); endmodule
+module FD1S3AX(input     D,     CK, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("1"),  .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("ASYNC"))        _TECHMAP_REPLACE_ (.CLK(CK), .LSR(0),           .DI(D), .Q(Q)); endmodule
+module FD1S3AY(input     D,     CK, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("1"),  .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("SET"),   .SRMODE("ASYNC"))        _TECHMAP_REPLACE_ (.CLK(CK), .LSR(0),           .DI(D), .Q(Q)); endmodule
+module FD1S3BX(input PD, D,     CK, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("1"),  .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("SET"),   .SRMODE("ASYNC"))        _TECHMAP_REPLACE_ (.CLK(CK), .LSR(PD),          .DI(D), .Q(Q)); endmodule
+module FD1S3DX(input CD, D,     CK, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("1"),  .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("ASYNC"))        _TECHMAP_REPLACE_ (.CLK(CK), .LSR(CD),          .DI(D), .Q(Q)); endmodule
+module FD1S3IX(input CD, D,     CK, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("1"),  .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("LSR_OVER_CE"))  _TECHMAP_REPLACE_ (.CLK(CK), .LSR(CD),          .DI(D), .Q(Q)); endmodule
+module FD1S3JX(input PD, D,     CK, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("1"),  .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("SET"),   .SRMODE("LSR_OVER_CE"))  _TECHMAP_REPLACE_ (.CLK(CK), .LSR(PD),          .DI(D), .Q(Q)); endmodule
+
+// TODO: Diamond latches
 // module FL1P3AY(); endmodule
 // module FL1P3AZ(); endmodule
 // module FL1P3BX(); endmodule
@@ -715,34 +717,34 @@ module FD1S3JX(input PD, D, CK, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX
 // module FL1S3AX(); endmodule
 // module FL1S3AY(); endmodule
 
-// Diamond I/O buffers
-module IB   (input I, output O); (* PULLMODE="NONE" *) TRELLIS_IO #(.DIR("INPUT")) tio (.B(I), .O(O)); endmodule
-module IBPU (input I, output O); (* PULLMODE="UP"   *) TRELLIS_IO #(.DIR("INPUT"))   tio (.B(I), .O(O)); endmodule
-module IBPD (input I, output O); (* PULLMODE="DOWN" *) TRELLIS_IO #(.DIR("INPUT")) tio (.B(I), .O(O)); endmodule
-module OB   (input I, output O); (* PULLMODE="NONE" *) TRELLIS_IO #(.DIR("OUTPUT")) tio (.B(O), .I(I)); endmodule
-module OBZ  (input I, T, output O); (* PULLMODE="NONE" *) TRELLIS_IO #(.DIR("OUTPUT")) tio (.B(O), .I(I), .T(T)); endmodule
-module OBZPU(input I, T, output O); (* PULLMODE="UP"   *) TRELLIS_IO #(.DIR("OUTPUT"))   tio (.B(O), .I(I), .T(T)); endmodule
-module OBZPD(input I, T, output O); (* PULLMODE="DOWN" *) TRELLIS_IO #(.DIR("OUTPUT")) tio (.B(O), .I(I), .T(T)); endmodule
-module OBCO (input I, output OT, OC); OLVDS olvds (.A(I), .Z(OT), .ZN(OC)); endmodule
-module BB   (input I, T, output O, inout B); (* PULLMODE="NONE" *) TRELLIS_IO #(.DIR("BIDIR")) tio (.B(B), .I(I), .O(O), .T(T)); endmodule
-module BBPU (input I, T, output O, inout B); (* PULLMODE="UP"   *) TRELLIS_IO #(.DIR("BIDIR"))   tio (.B(B), .I(I), .O(O), .T(T)); endmodule
-module BBPD (input I, T, output O, inout B); (* PULLMODE="DOWN" *) TRELLIS_IO #(.DIR("BIDIR")) tio (.B(B), .I(I), .O(O), .T(T)); endmodule
-module ILVDS(input A, AN, output Z); TRELLIS_IO #(.DIR("INPUT"))  tio (.B(A), .O(Z)); endmodule
-module OLVDS(input A, output Z, ZN); TRELLIS_IO #(.DIR("OUTPUT")) tio (.B(Z), .I(A)); endmodule
-
 // Diamond I/O registers
-module IFS1P3BX(input PD, D, SP, SCLK, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("ASYNC"))  tff (.CLK(SCLK), .LSR(PD), .CE(SP), .DI(D), .Q(Q)); endmodule
-module IFS1P3DX(input CD, D, SP, SCLK, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("ASYNC"))  tff (.CLK(SCLK), .LSR(CD), .CE(SP), .DI(D), .Q(Q)); endmodule
-module IFS1P3IX(input CD, D, SP, SCLK, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("LSR_OVER_CE"))  tff (.CLK(SCLK), .LSR(CD), .CE(SP), .DI(D), .Q(Q)); endmodule
-module IFS1P3JX(input PD, D, SP, SCLK, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("LSR_OVER_CE"))  tff (.CLK(SCLK), .LSR(PD), .CE(SP), .DI(D), .Q(Q)); endmodule
+module IFS1P3BX(input PD, D, SP, SCLK, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("SET"),   .SRMODE("ASYNC"))       _TECHMAP_REPLACE_ (.CLK(SCLK), .LSR(PD), .CE(SP), .DI(D), .Q(Q)); endmodule
+module IFS1P3DX(input CD, D, SP, SCLK, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("ASYNC"))       _TECHMAP_REPLACE_ (.CLK(SCLK), .LSR(CD), .CE(SP), .DI(D), .Q(Q)); endmodule
+module IFS1P3IX(input CD, D, SP, SCLK, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("LSR_OVER_CE")) _TECHMAP_REPLACE_ (.CLK(SCLK), .LSR(CD), .CE(SP), .DI(D), .Q(Q)); endmodule
+module IFS1P3JX(input PD, D, SP, SCLK, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("SET"),   .SRMODE("LSR_OVER_CE")) _TECHMAP_REPLACE_ (.CLK(SCLK), .LSR(PD), .CE(SP), .DI(D), .Q(Q)); endmodule
 
-module OFS1P3BX(input PD, D, SP, SCLK, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("ASYNC"))  tff (.CLK(SCLK), .LSR(PD), .CE(SP), .DI(D), .Q(Q)); endmodule
-module OFS1P3DX(input CD, D, SP, SCLK, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("ASYNC"))  tff (.CLK(SCLK), .LSR(CD), .CE(SP), .DI(D), .Q(Q)); endmodule
-module OFS1P3IX(input CD, D, SP, SCLK, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("LSR_OVER_CE"))  tff (.CLK(SCLK), .LSR(CD), .CE(SP), .DI(D), .Q(Q)); endmodule
-module OFS1P3JX(input PD, D, SP, SCLK, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("LSR_OVER_CE"))  tff (.CLK(SCLK), .LSR(PD), .CE(SP), .DI(D), .Q(Q)); endmodule
+module OFS1P3BX(input PD, D, SP, SCLK, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("SET"),   .SRMODE("ASYNC"))       _TECHMAP_REPLACE_ (.CLK(SCLK), .LSR(PD), .CE(SP), .DI(D), .Q(Q)); endmodule
+module OFS1P3DX(input CD, D, SP, SCLK, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("ASYNC"))       _TECHMAP_REPLACE_ (.CLK(SCLK), .LSR(CD), .CE(SP), .DI(D), .Q(Q)); endmodule
+module OFS1P3IX(input CD, D, SP, SCLK, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("LSR_OVER_CE")) _TECHMAP_REPLACE_ (.CLK(SCLK), .LSR(CD), .CE(SP), .DI(D), .Q(Q)); endmodule
+module OFS1P3JX(input PD, D, SP, SCLK, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("SET"),   .SRMODE("LSR_OVER_CE")) _TECHMAP_REPLACE_ (.CLK(SCLK), .LSR(PD), .CE(SP), .DI(D), .Q(Q)); endmodule
 
 // TODO: Diamond I/O latches
 // module IFS1S1B(input PD, D, SCLK, output Q); endmodule
 // module IFS1S1D(input CD, D, SCLK, output Q); endmodule
 // module IFS1S1I(input PD, D, SCLK, output Q); endmodule
 // module IFS1S1J(input CD, D, SCLK, output Q); endmodule
+
+// Diamond I/O buffers
+module IB   (input I,     output O); (* PULLMODE="NONE" *) TRELLIS_IO #(.DIR("INPUT"))  _TECHMAP_REPLACE_ (.B(I), .O(O)); endmodule
+module IBPU (input I,     output O); (* PULLMODE="UP"   *) TRELLIS_IO #(.DIR("INPUT"))  _TECHMAP_REPLACE_ (.B(I), .O(O)); endmodule
+module IBPD (input I,     output O); (* PULLMODE="DOWN" *) TRELLIS_IO #(.DIR("INPUT"))  _TECHMAP_REPLACE_ (.B(I), .O(O)); endmodule
+module OB   (input I,     output O); (* PULLMODE="NONE" *) TRELLIS_IO #(.DIR("OUTPUT")) _TECHMAP_REPLACE_ (.B(O), .I(I)); endmodule
+module OBZ  (input I, T,  output O); (* PULLMODE="NONE" *) TRELLIS_IO #(.DIR("OUTPUT")) _TECHMAP_REPLACE_ (.B(O), .I(I), .T(T)); endmodule
+module OBZPU(input I, T,  output O); (* PULLMODE="UP"   *) TRELLIS_IO #(.DIR("OUTPUT")) _TECHMAP_REPLACE_ (.B(O), .I(I), .T(T)); endmodule
+module OBZPD(input I, T,  output O); (* PULLMODE="DOWN" *) TRELLIS_IO #(.DIR("OUTPUT")) _TECHMAP_REPLACE_ (.B(O), .I(I), .T(T)); endmodule
+module OBCO (input I,     output OT, OC); OLVDS olvds (.A(I), .Z(OT), .ZN(OC)); endmodule
+module BB   (input I, T,  output O, inout B); (* PULLMODE="NONE" *) TRELLIS_IO #(.DIR("BIDIR")) _TECHMAP_REPLACE_ (.B(B), .I(I), .O(O), .T(T)); endmodule
+module BBPU (input I, T,  output O, inout B); (* PULLMODE="UP"   *) TRELLIS_IO #(.DIR("BIDIR")) _TECHMAP_REPLACE_ (.B(B), .I(I), .O(O), .T(T)); endmodule
+module BBPD (input I, T,  output O, inout B); (* PULLMODE="DOWN" *) TRELLIS_IO #(.DIR("BIDIR")) _TECHMAP_REPLACE_ (.B(B), .I(I), .O(O), .T(T)); endmodule
+module ILVDS(input A, AN, output Z    ); TRELLIS_IO #(.DIR("INPUT"))  _TECHMAP_REPLACE_ (.B(A), .O(Z)); endmodule
+module OLVDS(input A,     output Z, ZN); TRELLIS_IO #(.DIR("OUTPUT")) _TECHMAP_REPLACE_ (.B(Z), .I(A)); endmodule
-- 
cgit v1.2.3


From 1e6b60d563f8e51c521cae81de5d66bff40b943f Mon Sep 17 00:00:00 2001
From: whitequark <whitequark@whitequark.org>
Date: Fri, 30 Aug 2019 09:56:19 +0000
Subject: ecp5: allow (and enable by default) GSR on FD/IFS/OFS primitives.

---
 techlibs/ecp5/cells_map.v | 55 +++++++++++++++++------------------------------
 1 file changed, 20 insertions(+), 35 deletions(-)

(limited to 'techlibs/ecp5')

diff --git a/techlibs/ecp5/cells_map.v b/techlibs/ecp5/cells_map.v
index 100a3e377..7c5f140c6 100644
--- a/techlibs/ecp5/cells_map.v
+++ b/techlibs/ecp5/cells_map.v
@@ -48,18 +48,18 @@ module  \$__DFFSE_PP0 (input D, C, E, R, output Q); TRELLIS_FF #(.GSR("AUTO"), .
 module  \$__DFFSE_PP1 (input D, C, E, R, output Q); TRELLIS_FF #(.GSR("AUTO"), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("LSR_OVER_CE"))  _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(R), .DI(D), .Q(Q)); endmodule
 
 // Diamond flip-flops
-module FD1P3AX(input     D, SP, CK, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("ASYNC"))        _TECHMAP_REPLACE_ (.CLK(CK), .LSR(0),  .CE(SP), .DI(D), .Q(Q)); endmodule
-module FD1P3AY(input     D, SP, CK, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("SET"),   .SRMODE("ASYNC"))        _TECHMAP_REPLACE_ (.CLK(CK), .LSR(0),  .CE(SP), .DI(D), .Q(Q)); endmodule
-module FD1P3BX(input PD, D, SP, CK, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("SET"),   .SRMODE("ASYNC"))        _TECHMAP_REPLACE_ (.CLK(CK), .LSR(PD), .CE(SP), .DI(D), .Q(Q)); endmodule
-module FD1P3DX(input CD, D, SP, CK, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("ASYNC"))        _TECHMAP_REPLACE_ (.CLK(CK), .LSR(CD), .CE(SP), .DI(D), .Q(Q)); endmodule
-module FD1P3IX(input CD, D, SP, CK, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("LSR_OVER_CE"))  _TECHMAP_REPLACE_ (.CLK(CK), .LSR(CD), .CE(SP), .DI(D), .Q(Q)); endmodule
-module FD1P3JX(input PD, D, SP, CK, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("SET"),   .SRMODE("LSR_OVER_CE"))  _TECHMAP_REPLACE_ (.CLK(CK), .LSR(PD), .CE(SP), .DI(D), .Q(Q)); endmodule
-module FD1S3AX(input     D,     CK, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("1"),  .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("ASYNC"))        _TECHMAP_REPLACE_ (.CLK(CK), .LSR(0),           .DI(D), .Q(Q)); endmodule
-module FD1S3AY(input     D,     CK, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("1"),  .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("SET"),   .SRMODE("ASYNC"))        _TECHMAP_REPLACE_ (.CLK(CK), .LSR(0),           .DI(D), .Q(Q)); endmodule
-module FD1S3BX(input PD, D,     CK, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("1"),  .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("SET"),   .SRMODE("ASYNC"))        _TECHMAP_REPLACE_ (.CLK(CK), .LSR(PD),          .DI(D), .Q(Q)); endmodule
-module FD1S3DX(input CD, D,     CK, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("1"),  .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("ASYNC"))        _TECHMAP_REPLACE_ (.CLK(CK), .LSR(CD),          .DI(D), .Q(Q)); endmodule
-module FD1S3IX(input CD, D,     CK, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("1"),  .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("LSR_OVER_CE"))  _TECHMAP_REPLACE_ (.CLK(CK), .LSR(CD),          .DI(D), .Q(Q)); endmodule
-module FD1S3JX(input PD, D,     CK, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("1"),  .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("SET"),   .SRMODE("LSR_OVER_CE"))  _TECHMAP_REPLACE_ (.CLK(CK), .LSR(PD),          .DI(D), .Q(Q)); endmodule
+module FD1P3AX(input     D, SP, CK, output Q); parameter GSR = "ENABLED"; TRELLIS_FF #(.GSR(GSR), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("ASYNC"))        _TECHMAP_REPLACE_ (.CLK(CK), .LSR(0),  .CE(SP), .DI(D), .Q(Q)); endmodule
+module FD1P3AY(input     D, SP, CK, output Q); parameter GSR = "ENABLED"; TRELLIS_FF #(.GSR(GSR), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("SET"),   .SRMODE("ASYNC"))        _TECHMAP_REPLACE_ (.CLK(CK), .LSR(0),  .CE(SP), .DI(D), .Q(Q)); endmodule
+module FD1P3BX(input PD, D, SP, CK, output Q); parameter GSR = "ENABLED"; TRELLIS_FF #(.GSR(GSR), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("SET"),   .SRMODE("ASYNC"))        _TECHMAP_REPLACE_ (.CLK(CK), .LSR(PD), .CE(SP), .DI(D), .Q(Q)); endmodule
+module FD1P3DX(input CD, D, SP, CK, output Q); parameter GSR = "ENABLED"; TRELLIS_FF #(.GSR(GSR), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("ASYNC"))        _TECHMAP_REPLACE_ (.CLK(CK), .LSR(CD), .CE(SP), .DI(D), .Q(Q)); endmodule
+module FD1P3IX(input CD, D, SP, CK, output Q); parameter GSR = "ENABLED"; TRELLIS_FF #(.GSR(GSR), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("LSR_OVER_CE"))  _TECHMAP_REPLACE_ (.CLK(CK), .LSR(CD), .CE(SP), .DI(D), .Q(Q)); endmodule
+module FD1P3JX(input PD, D, SP, CK, output Q); parameter GSR = "ENABLED"; TRELLIS_FF #(.GSR(GSR), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("SET"),   .SRMODE("LSR_OVER_CE"))  _TECHMAP_REPLACE_ (.CLK(CK), .LSR(PD), .CE(SP), .DI(D), .Q(Q)); endmodule
+module FD1S3AX(input     D,     CK, output Q); parameter GSR = "ENABLED"; TRELLIS_FF #(.GSR(GSR), .CEMUX("1"),  .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("ASYNC"))        _TECHMAP_REPLACE_ (.CLK(CK), .LSR(0),           .DI(D), .Q(Q)); endmodule
+module FD1S3AY(input     D,     CK, output Q); parameter GSR = "ENABLED"; TRELLIS_FF #(.GSR(GSR), .CEMUX("1"),  .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("SET"),   .SRMODE("ASYNC"))        _TECHMAP_REPLACE_ (.CLK(CK), .LSR(0),           .DI(D), .Q(Q)); endmodule
+module FD1S3BX(input PD, D,     CK, output Q); parameter GSR = "ENABLED"; TRELLIS_FF #(.GSR(GSR), .CEMUX("1"),  .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("SET"),   .SRMODE("ASYNC"))        _TECHMAP_REPLACE_ (.CLK(CK), .LSR(PD),          .DI(D), .Q(Q)); endmodule
+module FD1S3DX(input CD, D,     CK, output Q); parameter GSR = "ENABLED"; TRELLIS_FF #(.GSR(GSR), .CEMUX("1"),  .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("ASYNC"))        _TECHMAP_REPLACE_ (.CLK(CK), .LSR(CD),          .DI(D), .Q(Q)); endmodule
+module FD1S3IX(input CD, D,     CK, output Q); parameter GSR = "ENABLED"; TRELLIS_FF #(.GSR(GSR), .CEMUX("1"),  .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("LSR_OVER_CE"))  _TECHMAP_REPLACE_ (.CLK(CK), .LSR(CD),          .DI(D), .Q(Q)); endmodule
+module FD1S3JX(input PD, D,     CK, output Q); parameter GSR = "ENABLED"; TRELLIS_FF #(.GSR(GSR), .CEMUX("1"),  .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("SET"),   .SRMODE("LSR_OVER_CE"))  _TECHMAP_REPLACE_ (.CLK(CK), .LSR(PD),          .DI(D), .Q(Q)); endmodule
 
 // TODO: Diamond latches
 // module FL1P3AY(); endmodule
@@ -72,15 +72,15 @@ module FD1S3JX(input PD, D,     CK, output Q); TRELLIS_FF #(.GSR("DISABLED"), .C
 // module FL1S3AY(); endmodule
 
 // Diamond I/O registers
-module IFS1P3BX(input PD, D, SP, SCLK, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("SET"),   .SRMODE("ASYNC"))       _TECHMAP_REPLACE_ (.CLK(SCLK), .LSR(PD), .CE(SP), .DI(D), .Q(Q)); endmodule
-module IFS1P3DX(input CD, D, SP, SCLK, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("ASYNC"))       _TECHMAP_REPLACE_ (.CLK(SCLK), .LSR(CD), .CE(SP), .DI(D), .Q(Q)); endmodule
-module IFS1P3IX(input CD, D, SP, SCLK, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("LSR_OVER_CE")) _TECHMAP_REPLACE_ (.CLK(SCLK), .LSR(CD), .CE(SP), .DI(D), .Q(Q)); endmodule
-module IFS1P3JX(input PD, D, SP, SCLK, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("SET"),   .SRMODE("LSR_OVER_CE")) _TECHMAP_REPLACE_ (.CLK(SCLK), .LSR(PD), .CE(SP), .DI(D), .Q(Q)); endmodule
+module IFS1P3BX(input PD, D, SP, SCLK, output Q); parameter GSR = "ENABLED"; TRELLIS_FF #(.GSR(GSR), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("SET"),   .SRMODE("ASYNC"))       _TECHMAP_REPLACE_ (.CLK(SCLK), .LSR(PD), .CE(SP), .DI(D), .Q(Q)); endmodule
+module IFS1P3DX(input CD, D, SP, SCLK, output Q); parameter GSR = "ENABLED"; TRELLIS_FF #(.GSR(GSR), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("ASYNC"))       _TECHMAP_REPLACE_ (.CLK(SCLK), .LSR(CD), .CE(SP), .DI(D), .Q(Q)); endmodule
+module IFS1P3IX(input CD, D, SP, SCLK, output Q); parameter GSR = "ENABLED"; TRELLIS_FF #(.GSR(GSR), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("LSR_OVER_CE")) _TECHMAP_REPLACE_ (.CLK(SCLK), .LSR(CD), .CE(SP), .DI(D), .Q(Q)); endmodule
+module IFS1P3JX(input PD, D, SP, SCLK, output Q); parameter GSR = "ENABLED"; TRELLIS_FF #(.GSR(GSR), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("SET"),   .SRMODE("LSR_OVER_CE")) _TECHMAP_REPLACE_ (.CLK(SCLK), .LSR(PD), .CE(SP), .DI(D), .Q(Q)); endmodule
 
-module OFS1P3BX(input PD, D, SP, SCLK, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("SET"),   .SRMODE("ASYNC"))       _TECHMAP_REPLACE_ (.CLK(SCLK), .LSR(PD), .CE(SP), .DI(D), .Q(Q)); endmodule
-module OFS1P3DX(input CD, D, SP, SCLK, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("ASYNC"))       _TECHMAP_REPLACE_ (.CLK(SCLK), .LSR(CD), .CE(SP), .DI(D), .Q(Q)); endmodule
-module OFS1P3IX(input CD, D, SP, SCLK, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("LSR_OVER_CE")) _TECHMAP_REPLACE_ (.CLK(SCLK), .LSR(CD), .CE(SP), .DI(D), .Q(Q)); endmodule
-module OFS1P3JX(input PD, D, SP, SCLK, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("SET"),   .SRMODE("LSR_OVER_CE")) _TECHMAP_REPLACE_ (.CLK(SCLK), .LSR(PD), .CE(SP), .DI(D), .Q(Q)); endmodule
+module OFS1P3BX(input PD, D, SP, SCLK, output Q); parameter GSR = "ENABLED"; TRELLIS_FF #(.GSR(GSR), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("SET"),   .SRMODE("ASYNC"))       _TECHMAP_REPLACE_ (.CLK(SCLK), .LSR(PD), .CE(SP), .DI(D), .Q(Q)); endmodule
+module OFS1P3DX(input CD, D, SP, SCLK, output Q); parameter GSR = "ENABLED"; TRELLIS_FF #(.GSR(GSR), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("ASYNC"))       _TECHMAP_REPLACE_ (.CLK(SCLK), .LSR(CD), .CE(SP), .DI(D), .Q(Q)); endmodule
+module OFS1P3IX(input CD, D, SP, SCLK, output Q); parameter GSR = "ENABLED"; TRELLIS_FF #(.GSR(GSR), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("LSR_OVER_CE")) _TECHMAP_REPLACE_ (.CLK(SCLK), .LSR(CD), .CE(SP), .DI(D), .Q(Q)); endmodule
+module OFS1P3JX(input PD, D, SP, SCLK, output Q); parameter GSR = "ENABLED"; TRELLIS_FF #(.GSR(GSR), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("SET"),   .SRMODE("LSR_OVER_CE")) _TECHMAP_REPLACE_ (.CLK(SCLK), .LSR(PD), .CE(SP), .DI(D), .Q(Q)); endmodule
 
 // TODO: Diamond I/O latches
 // module IFS1S1B(input PD, D, SCLK, output Q); endmodule
@@ -88,21 +88,6 @@ module OFS1P3JX(input PD, D, SP, SCLK, output Q); TRELLIS_FF #(.GSR("DISABLED"),
 // module IFS1S1I(input PD, D, SCLK, output Q); endmodule
 // module IFS1S1J(input CD, D, SCLK, output Q); endmodule
 
-// Diamond I/O buffers
-module IB   (input I,     output O); (* PULLMODE="NONE" *) TRELLIS_IO #(.DIR("INPUT"))  _TECHMAP_REPLACE_ (.B(I), .O(O)); endmodule
-module IBPU (input I,     output O); (* PULLMODE="UP"   *) TRELLIS_IO #(.DIR("INPUT"))  _TECHMAP_REPLACE_ (.B(I), .O(O)); endmodule
-module IBPD (input I,     output O); (* PULLMODE="DOWN" *) TRELLIS_IO #(.DIR("INPUT"))  _TECHMAP_REPLACE_ (.B(I), .O(O)); endmodule
-module OB   (input I,     output O); (* PULLMODE="NONE" *) TRELLIS_IO #(.DIR("OUTPUT")) _TECHMAP_REPLACE_ (.B(O), .I(I)); endmodule
-module OBZ  (input I, T,  output O); (* PULLMODE="NONE" *) TRELLIS_IO #(.DIR("OUTPUT")) _TECHMAP_REPLACE_ (.B(O), .I(I), .T(T)); endmodule
-module OBZPU(input I, T,  output O); (* PULLMODE="UP"   *) TRELLIS_IO #(.DIR("OUTPUT")) _TECHMAP_REPLACE_ (.B(O), .I(I), .T(T)); endmodule
-module OBZPD(input I, T,  output O); (* PULLMODE="DOWN" *) TRELLIS_IO #(.DIR("OUTPUT")) _TECHMAP_REPLACE_ (.B(O), .I(I), .T(T)); endmodule
-module OBCO (input I,     output OT, OC); OLVDS olvds (.A(I), .Z(OT), .ZN(OC)); endmodule
-module BB   (input I, T,  output O, inout B); (* PULLMODE="NONE" *) TRELLIS_IO #(.DIR("BIDIR")) _TECHMAP_REPLACE_ (.B(B), .I(I), .O(O), .T(T)); endmodule
-module BBPU (input I, T,  output O, inout B); (* PULLMODE="UP"   *) TRELLIS_IO #(.DIR("BIDIR")) _TECHMAP_REPLACE_ (.B(B), .I(I), .O(O), .T(T)); endmodule
-module BBPD (input I, T,  output O, inout B); (* PULLMODE="DOWN" *) TRELLIS_IO #(.DIR("BIDIR")) _TECHMAP_REPLACE_ (.B(B), .I(I), .O(O), .T(T)); endmodule
-module ILVDS(input A, AN, output Z    ); TRELLIS_IO #(.DIR("INPUT"))  _TECHMAP_REPLACE_ (.B(A), .O(Z)); endmodule
-module OLVDS(input A,     output Z, ZN); TRELLIS_IO #(.DIR("OUTPUT")) _TECHMAP_REPLACE_ (.B(Z), .I(A)); endmodule
-
 `ifndef NO_LUT
 module \$lut (A, Y);
     parameter WIDTH = 0;
-- 
cgit v1.2.3


From d9c621f9d1e1f8e38fc38e78ab8c1bf48282fd01 Mon Sep 17 00:00:00 2001
From: whitequark <whitequark@whitequark.org>
Date: Fri, 30 Aug 2019 10:05:09 +0000
Subject: ecp5: deduplicate Diamond FD/IFS/OFS/IO primitives.

---
 techlibs/ecp5/Makefile.inc |  2 ++
 techlibs/ecp5/cells_ff.vh  | 40 ++++++++++++++++++++++++++++++++
 techlibs/ecp5/cells_io.vh  | 14 ++++++++++++
 techlibs/ecp5/cells_map.v  | 42 ++--------------------------------
 techlibs/ecp5/cells_sim.v  | 57 ++--------------------------------------------
 5 files changed, 60 insertions(+), 95 deletions(-)
 create mode 100644 techlibs/ecp5/cells_ff.vh
 create mode 100644 techlibs/ecp5/cells_io.vh

(limited to 'techlibs/ecp5')

diff --git a/techlibs/ecp5/Makefile.inc b/techlibs/ecp5/Makefile.inc
index c41d16076..2143acae6 100644
--- a/techlibs/ecp5/Makefile.inc
+++ b/techlibs/ecp5/Makefile.inc
@@ -2,6 +2,8 @@
 OBJS += techlibs/ecp5/synth_ecp5.o techlibs/ecp5/ecp5_ffinit.o \
         techlibs/ecp5/ecp5_gsr.o
 
+$(eval $(call add_share_file,share/ecp5,techlibs/ecp5/cells_ff.vh))
+$(eval $(call add_share_file,share/ecp5,techlibs/ecp5/cells_io.vh))
 $(eval $(call add_share_file,share/ecp5,techlibs/ecp5/cells_map.v))
 $(eval $(call add_share_file,share/ecp5,techlibs/ecp5/cells_sim.v))
 $(eval $(call add_share_file,share/ecp5,techlibs/ecp5/cells_bb.v))
diff --git a/techlibs/ecp5/cells_ff.vh b/techlibs/ecp5/cells_ff.vh
new file mode 100644
index 000000000..0c9689ebd
--- /dev/null
+++ b/techlibs/ecp5/cells_ff.vh
@@ -0,0 +1,40 @@
+// Diamond flip-flops
+module FD1P3AX(input     D, SP, CK, output Q); parameter GSR = "ENABLED"; TRELLIS_FF #(.GSR(GSR), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("ASYNC"))        _TECHMAP_REPLACE_ (.CLK(CK), .LSR(0),  .CE(SP), .DI(D), .Q(Q)); endmodule
+module FD1P3AY(input     D, SP, CK, output Q); parameter GSR = "ENABLED"; TRELLIS_FF #(.GSR(GSR), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("SET"),   .SRMODE("ASYNC"))        _TECHMAP_REPLACE_ (.CLK(CK), .LSR(0),  .CE(SP), .DI(D), .Q(Q)); endmodule
+module FD1P3BX(input PD, D, SP, CK, output Q); parameter GSR = "ENABLED"; TRELLIS_FF #(.GSR(GSR), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("SET"),   .SRMODE("ASYNC"))        _TECHMAP_REPLACE_ (.CLK(CK), .LSR(PD), .CE(SP), .DI(D), .Q(Q)); endmodule
+module FD1P3DX(input CD, D, SP, CK, output Q); parameter GSR = "ENABLED"; TRELLIS_FF #(.GSR(GSR), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("ASYNC"))        _TECHMAP_REPLACE_ (.CLK(CK), .LSR(CD), .CE(SP), .DI(D), .Q(Q)); endmodule
+module FD1P3IX(input CD, D, SP, CK, output Q); parameter GSR = "ENABLED"; TRELLIS_FF #(.GSR(GSR), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("LSR_OVER_CE"))  _TECHMAP_REPLACE_ (.CLK(CK), .LSR(CD), .CE(SP), .DI(D), .Q(Q)); endmodule
+module FD1P3JX(input PD, D, SP, CK, output Q); parameter GSR = "ENABLED"; TRELLIS_FF #(.GSR(GSR), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("SET"),   .SRMODE("LSR_OVER_CE"))  _TECHMAP_REPLACE_ (.CLK(CK), .LSR(PD), .CE(SP), .DI(D), .Q(Q)); endmodule
+module FD1S3AX(input     D,     CK, output Q); parameter GSR = "ENABLED"; TRELLIS_FF #(.GSR(GSR), .CEMUX("1"),  .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("ASYNC"))        _TECHMAP_REPLACE_ (.CLK(CK), .LSR(0),           .DI(D), .Q(Q)); endmodule
+module FD1S3AY(input     D,     CK, output Q); parameter GSR = "ENABLED"; TRELLIS_FF #(.GSR(GSR), .CEMUX("1"),  .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("SET"),   .SRMODE("ASYNC"))        _TECHMAP_REPLACE_ (.CLK(CK), .LSR(0),           .DI(D), .Q(Q)); endmodule
+module FD1S3BX(input PD, D,     CK, output Q); parameter GSR = "ENABLED"; TRELLIS_FF #(.GSR(GSR), .CEMUX("1"),  .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("SET"),   .SRMODE("ASYNC"))        _TECHMAP_REPLACE_ (.CLK(CK), .LSR(PD),          .DI(D), .Q(Q)); endmodule
+module FD1S3DX(input CD, D,     CK, output Q); parameter GSR = "ENABLED"; TRELLIS_FF #(.GSR(GSR), .CEMUX("1"),  .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("ASYNC"))        _TECHMAP_REPLACE_ (.CLK(CK), .LSR(CD),          .DI(D), .Q(Q)); endmodule
+module FD1S3IX(input CD, D,     CK, output Q); parameter GSR = "ENABLED"; TRELLIS_FF #(.GSR(GSR), .CEMUX("1"),  .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("LSR_OVER_CE"))  _TECHMAP_REPLACE_ (.CLK(CK), .LSR(CD),          .DI(D), .Q(Q)); endmodule
+module FD1S3JX(input PD, D,     CK, output Q); parameter GSR = "ENABLED"; TRELLIS_FF #(.GSR(GSR), .CEMUX("1"),  .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("SET"),   .SRMODE("LSR_OVER_CE"))  _TECHMAP_REPLACE_ (.CLK(CK), .LSR(PD),          .DI(D), .Q(Q)); endmodule
+
+// TODO: Diamond latches
+// module FL1P3AY(); endmodule
+// module FL1P3AZ(); endmodule
+// module FL1P3BX(); endmodule
+// module FL1P3DX(); endmodule
+// module FL1P3IY(); endmodule
+// module FL1P3JY(); endmodule
+// module FL1S3AX(); endmodule
+// module FL1S3AY(); endmodule
+
+// Diamond I/O registers
+module IFS1P3BX(input PD, D, SP, SCLK, output Q); parameter GSR = "ENABLED"; TRELLIS_FF #(.GSR(GSR), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("SET"),   .SRMODE("ASYNC"))       _TECHMAP_REPLACE_ (.CLK(SCLK), .LSR(PD), .CE(SP), .DI(D), .Q(Q)); endmodule
+module IFS1P3DX(input CD, D, SP, SCLK, output Q); parameter GSR = "ENABLED"; TRELLIS_FF #(.GSR(GSR), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("ASYNC"))       _TECHMAP_REPLACE_ (.CLK(SCLK), .LSR(CD), .CE(SP), .DI(D), .Q(Q)); endmodule
+module IFS1P3IX(input CD, D, SP, SCLK, output Q); parameter GSR = "ENABLED"; TRELLIS_FF #(.GSR(GSR), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("LSR_OVER_CE")) _TECHMAP_REPLACE_ (.CLK(SCLK), .LSR(CD), .CE(SP), .DI(D), .Q(Q)); endmodule
+module IFS1P3JX(input PD, D, SP, SCLK, output Q); parameter GSR = "ENABLED"; TRELLIS_FF #(.GSR(GSR), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("SET"),   .SRMODE("LSR_OVER_CE")) _TECHMAP_REPLACE_ (.CLK(SCLK), .LSR(PD), .CE(SP), .DI(D), .Q(Q)); endmodule
+
+module OFS1P3BX(input PD, D, SP, SCLK, output Q); parameter GSR = "ENABLED"; TRELLIS_FF #(.GSR(GSR), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("SET"),   .SRMODE("ASYNC"))       _TECHMAP_REPLACE_ (.CLK(SCLK), .LSR(PD), .CE(SP), .DI(D), .Q(Q)); endmodule
+module OFS1P3DX(input CD, D, SP, SCLK, output Q); parameter GSR = "ENABLED"; TRELLIS_FF #(.GSR(GSR), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("ASYNC"))       _TECHMAP_REPLACE_ (.CLK(SCLK), .LSR(CD), .CE(SP), .DI(D), .Q(Q)); endmodule
+module OFS1P3IX(input CD, D, SP, SCLK, output Q); parameter GSR = "ENABLED"; TRELLIS_FF #(.GSR(GSR), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("LSR_OVER_CE")) _TECHMAP_REPLACE_ (.CLK(SCLK), .LSR(CD), .CE(SP), .DI(D), .Q(Q)); endmodule
+module OFS1P3JX(input PD, D, SP, SCLK, output Q); parameter GSR = "ENABLED"; TRELLIS_FF #(.GSR(GSR), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("SET"),   .SRMODE("LSR_OVER_CE")) _TECHMAP_REPLACE_ (.CLK(SCLK), .LSR(PD), .CE(SP), .DI(D), .Q(Q)); endmodule
+
+// TODO: Diamond I/O latches
+// module IFS1S1B(input PD, D, SCLK, output Q); endmodule
+// module IFS1S1D(input CD, D, SCLK, output Q); endmodule
+// module IFS1S1I(input PD, D, SCLK, output Q); endmodule
+// module IFS1S1J(input CD, D, SCLK, output Q); endmodule
diff --git a/techlibs/ecp5/cells_io.vh b/techlibs/ecp5/cells_io.vh
new file mode 100644
index 000000000..02e66e8a5
--- /dev/null
+++ b/techlibs/ecp5/cells_io.vh
@@ -0,0 +1,14 @@
+// Diamond I/O buffers
+module IB   (input I,     output O); (* PULLMODE="NONE" *) TRELLIS_IO #(.DIR("INPUT"))  _TECHMAP_REPLACE_ (.B(I), .O(O)); endmodule
+module IBPU (input I,     output O); (* PULLMODE="UP"   *) TRELLIS_IO #(.DIR("INPUT"))  _TECHMAP_REPLACE_ (.B(I), .O(O)); endmodule
+module IBPD (input I,     output O); (* PULLMODE="DOWN" *) TRELLIS_IO #(.DIR("INPUT"))  _TECHMAP_REPLACE_ (.B(I), .O(O)); endmodule
+module OB   (input I,     output O); (* PULLMODE="NONE" *) TRELLIS_IO #(.DIR("OUTPUT")) _TECHMAP_REPLACE_ (.B(O), .I(I)); endmodule
+module OBZ  (input I, T,  output O); (* PULLMODE="NONE" *) TRELLIS_IO #(.DIR("OUTPUT")) _TECHMAP_REPLACE_ (.B(O), .I(I), .T(T)); endmodule
+module OBZPU(input I, T,  output O); (* PULLMODE="UP"   *) TRELLIS_IO #(.DIR("OUTPUT")) _TECHMAP_REPLACE_ (.B(O), .I(I), .T(T)); endmodule
+module OBZPD(input I, T,  output O); (* PULLMODE="DOWN" *) TRELLIS_IO #(.DIR("OUTPUT")) _TECHMAP_REPLACE_ (.B(O), .I(I), .T(T)); endmodule
+module OBCO (input I,     output OT, OC); OLVDS olvds (.A(I), .Z(OT), .ZN(OC)); endmodule
+module BB   (input I, T,  output O, inout B); (* PULLMODE="NONE" *) TRELLIS_IO #(.DIR("BIDIR")) _TECHMAP_REPLACE_ (.B(B), .I(I), .O(O), .T(T)); endmodule
+module BBPU (input I, T,  output O, inout B); (* PULLMODE="UP"   *) TRELLIS_IO #(.DIR("BIDIR")) _TECHMAP_REPLACE_ (.B(B), .I(I), .O(O), .T(T)); endmodule
+module BBPD (input I, T,  output O, inout B); (* PULLMODE="DOWN" *) TRELLIS_IO #(.DIR("BIDIR")) _TECHMAP_REPLACE_ (.B(B), .I(I), .O(O), .T(T)); endmodule
+module ILVDS(input A, AN, output Z    ); TRELLIS_IO #(.DIR("INPUT"))  _TECHMAP_REPLACE_ (.B(A), .O(Z)); endmodule
+module OLVDS(input A,     output Z, ZN); TRELLIS_IO #(.DIR("OUTPUT")) _TECHMAP_REPLACE_ (.B(Z), .I(A)); endmodule
diff --git a/techlibs/ecp5/cells_map.v b/techlibs/ecp5/cells_map.v
index 7c5f140c6..71ae9237b 100644
--- a/techlibs/ecp5/cells_map.v
+++ b/techlibs/ecp5/cells_map.v
@@ -47,46 +47,8 @@ module  \$__DFFSE_NP1 (input D, C, E, R, output Q); TRELLIS_FF #(.GSR("AUTO"), .
 module  \$__DFFSE_PP0 (input D, C, E, R, output Q); TRELLIS_FF #(.GSR("AUTO"), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("LSR_OVER_CE"))  _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(R), .DI(D), .Q(Q)); endmodule
 module  \$__DFFSE_PP1 (input D, C, E, R, output Q); TRELLIS_FF #(.GSR("AUTO"), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("LSR_OVER_CE"))  _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(R), .DI(D), .Q(Q)); endmodule
 
-// Diamond flip-flops
-module FD1P3AX(input     D, SP, CK, output Q); parameter GSR = "ENABLED"; TRELLIS_FF #(.GSR(GSR), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("ASYNC"))        _TECHMAP_REPLACE_ (.CLK(CK), .LSR(0),  .CE(SP), .DI(D), .Q(Q)); endmodule
-module FD1P3AY(input     D, SP, CK, output Q); parameter GSR = "ENABLED"; TRELLIS_FF #(.GSR(GSR), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("SET"),   .SRMODE("ASYNC"))        _TECHMAP_REPLACE_ (.CLK(CK), .LSR(0),  .CE(SP), .DI(D), .Q(Q)); endmodule
-module FD1P3BX(input PD, D, SP, CK, output Q); parameter GSR = "ENABLED"; TRELLIS_FF #(.GSR(GSR), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("SET"),   .SRMODE("ASYNC"))        _TECHMAP_REPLACE_ (.CLK(CK), .LSR(PD), .CE(SP), .DI(D), .Q(Q)); endmodule
-module FD1P3DX(input CD, D, SP, CK, output Q); parameter GSR = "ENABLED"; TRELLIS_FF #(.GSR(GSR), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("ASYNC"))        _TECHMAP_REPLACE_ (.CLK(CK), .LSR(CD), .CE(SP), .DI(D), .Q(Q)); endmodule
-module FD1P3IX(input CD, D, SP, CK, output Q); parameter GSR = "ENABLED"; TRELLIS_FF #(.GSR(GSR), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("LSR_OVER_CE"))  _TECHMAP_REPLACE_ (.CLK(CK), .LSR(CD), .CE(SP), .DI(D), .Q(Q)); endmodule
-module FD1P3JX(input PD, D, SP, CK, output Q); parameter GSR = "ENABLED"; TRELLIS_FF #(.GSR(GSR), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("SET"),   .SRMODE("LSR_OVER_CE"))  _TECHMAP_REPLACE_ (.CLK(CK), .LSR(PD), .CE(SP), .DI(D), .Q(Q)); endmodule
-module FD1S3AX(input     D,     CK, output Q); parameter GSR = "ENABLED"; TRELLIS_FF #(.GSR(GSR), .CEMUX("1"),  .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("ASYNC"))        _TECHMAP_REPLACE_ (.CLK(CK), .LSR(0),           .DI(D), .Q(Q)); endmodule
-module FD1S3AY(input     D,     CK, output Q); parameter GSR = "ENABLED"; TRELLIS_FF #(.GSR(GSR), .CEMUX("1"),  .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("SET"),   .SRMODE("ASYNC"))        _TECHMAP_REPLACE_ (.CLK(CK), .LSR(0),           .DI(D), .Q(Q)); endmodule
-module FD1S3BX(input PD, D,     CK, output Q); parameter GSR = "ENABLED"; TRELLIS_FF #(.GSR(GSR), .CEMUX("1"),  .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("SET"),   .SRMODE("ASYNC"))        _TECHMAP_REPLACE_ (.CLK(CK), .LSR(PD),          .DI(D), .Q(Q)); endmodule
-module FD1S3DX(input CD, D,     CK, output Q); parameter GSR = "ENABLED"; TRELLIS_FF #(.GSR(GSR), .CEMUX("1"),  .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("ASYNC"))        _TECHMAP_REPLACE_ (.CLK(CK), .LSR(CD),          .DI(D), .Q(Q)); endmodule
-module FD1S3IX(input CD, D,     CK, output Q); parameter GSR = "ENABLED"; TRELLIS_FF #(.GSR(GSR), .CEMUX("1"),  .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("LSR_OVER_CE"))  _TECHMAP_REPLACE_ (.CLK(CK), .LSR(CD),          .DI(D), .Q(Q)); endmodule
-module FD1S3JX(input PD, D,     CK, output Q); parameter GSR = "ENABLED"; TRELLIS_FF #(.GSR(GSR), .CEMUX("1"),  .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("SET"),   .SRMODE("LSR_OVER_CE"))  _TECHMAP_REPLACE_ (.CLK(CK), .LSR(PD),          .DI(D), .Q(Q)); endmodule
-
-// TODO: Diamond latches
-// module FL1P3AY(); endmodule
-// module FL1P3AZ(); endmodule
-// module FL1P3BX(); endmodule
-// module FL1P3DX(); endmodule
-// module FL1P3IY(); endmodule
-// module FL1P3JY(); endmodule
-// module FL1S3AX(); endmodule
-// module FL1S3AY(); endmodule
-
-// Diamond I/O registers
-module IFS1P3BX(input PD, D, SP, SCLK, output Q); parameter GSR = "ENABLED"; TRELLIS_FF #(.GSR(GSR), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("SET"),   .SRMODE("ASYNC"))       _TECHMAP_REPLACE_ (.CLK(SCLK), .LSR(PD), .CE(SP), .DI(D), .Q(Q)); endmodule
-module IFS1P3DX(input CD, D, SP, SCLK, output Q); parameter GSR = "ENABLED"; TRELLIS_FF #(.GSR(GSR), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("ASYNC"))       _TECHMAP_REPLACE_ (.CLK(SCLK), .LSR(CD), .CE(SP), .DI(D), .Q(Q)); endmodule
-module IFS1P3IX(input CD, D, SP, SCLK, output Q); parameter GSR = "ENABLED"; TRELLIS_FF #(.GSR(GSR), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("LSR_OVER_CE")) _TECHMAP_REPLACE_ (.CLK(SCLK), .LSR(CD), .CE(SP), .DI(D), .Q(Q)); endmodule
-module IFS1P3JX(input PD, D, SP, SCLK, output Q); parameter GSR = "ENABLED"; TRELLIS_FF #(.GSR(GSR), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("SET"),   .SRMODE("LSR_OVER_CE")) _TECHMAP_REPLACE_ (.CLK(SCLK), .LSR(PD), .CE(SP), .DI(D), .Q(Q)); endmodule
-
-module OFS1P3BX(input PD, D, SP, SCLK, output Q); parameter GSR = "ENABLED"; TRELLIS_FF #(.GSR(GSR), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("SET"),   .SRMODE("ASYNC"))       _TECHMAP_REPLACE_ (.CLK(SCLK), .LSR(PD), .CE(SP), .DI(D), .Q(Q)); endmodule
-module OFS1P3DX(input CD, D, SP, SCLK, output Q); parameter GSR = "ENABLED"; TRELLIS_FF #(.GSR(GSR), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("ASYNC"))       _TECHMAP_REPLACE_ (.CLK(SCLK), .LSR(CD), .CE(SP), .DI(D), .Q(Q)); endmodule
-module OFS1P3IX(input CD, D, SP, SCLK, output Q); parameter GSR = "ENABLED"; TRELLIS_FF #(.GSR(GSR), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("LSR_OVER_CE")) _TECHMAP_REPLACE_ (.CLK(SCLK), .LSR(CD), .CE(SP), .DI(D), .Q(Q)); endmodule
-module OFS1P3JX(input PD, D, SP, SCLK, output Q); parameter GSR = "ENABLED"; TRELLIS_FF #(.GSR(GSR), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("SET"),   .SRMODE("LSR_OVER_CE")) _TECHMAP_REPLACE_ (.CLK(SCLK), .LSR(PD), .CE(SP), .DI(D), .Q(Q)); endmodule
-
-// TODO: Diamond I/O latches
-// module IFS1S1B(input PD, D, SCLK, output Q); endmodule
-// module IFS1S1D(input CD, D, SCLK, output Q); endmodule
-// module IFS1S1I(input PD, D, SCLK, output Q); endmodule
-// module IFS1S1J(input CD, D, SCLK, output Q); endmodule
+`include "cells_ff.vh"
+`include "cells_io.vh"
 
 `ifndef NO_LUT
 module \$lut (A, Y);
diff --git a/techlibs/ecp5/cells_sim.v b/techlibs/ecp5/cells_sim.v
index 50b6012e9..ba5b9c715 100644
--- a/techlibs/ecp5/cells_sim.v
+++ b/techlibs/ecp5/cells_sim.v
@@ -693,58 +693,5 @@ module DP16KD(
 	parameter INITVAL_3F = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
 endmodule
 
-// Diamond flip-flops
-module FD1P3AX(input     D, SP, CK, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("ASYNC"))        _TECHMAP_REPLACE_ (.CLK(CK), .LSR(0),  .CE(SP), .DI(D), .Q(Q)); endmodule
-module FD1P3AY(input     D, SP, CK, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("SET"),   .SRMODE("ASYNC"))        _TECHMAP_REPLACE_ (.CLK(CK), .LSR(0),  .CE(SP), .DI(D), .Q(Q)); endmodule
-module FD1P3BX(input PD, D, SP, CK, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("SET"),   .SRMODE("ASYNC"))        _TECHMAP_REPLACE_ (.CLK(CK), .LSR(PD), .CE(SP), .DI(D), .Q(Q)); endmodule
-module FD1P3DX(input CD, D, SP, CK, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("ASYNC"))        _TECHMAP_REPLACE_ (.CLK(CK), .LSR(CD), .CE(SP), .DI(D), .Q(Q)); endmodule
-module FD1P3IX(input CD, D, SP, CK, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("LSR_OVER_CE"))  _TECHMAP_REPLACE_ (.CLK(CK), .LSR(CD), .CE(SP), .DI(D), .Q(Q)); endmodule
-module FD1P3JX(input PD, D, SP, CK, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("SET"),   .SRMODE("LSR_OVER_CE"))  _TECHMAP_REPLACE_ (.CLK(CK), .LSR(PD), .CE(SP), .DI(D), .Q(Q)); endmodule
-module FD1S3AX(input     D,     CK, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("1"),  .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("ASYNC"))        _TECHMAP_REPLACE_ (.CLK(CK), .LSR(0),           .DI(D), .Q(Q)); endmodule
-module FD1S3AY(input     D,     CK, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("1"),  .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("SET"),   .SRMODE("ASYNC"))        _TECHMAP_REPLACE_ (.CLK(CK), .LSR(0),           .DI(D), .Q(Q)); endmodule
-module FD1S3BX(input PD, D,     CK, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("1"),  .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("SET"),   .SRMODE("ASYNC"))        _TECHMAP_REPLACE_ (.CLK(CK), .LSR(PD),          .DI(D), .Q(Q)); endmodule
-module FD1S3DX(input CD, D,     CK, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("1"),  .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("ASYNC"))        _TECHMAP_REPLACE_ (.CLK(CK), .LSR(CD),          .DI(D), .Q(Q)); endmodule
-module FD1S3IX(input CD, D,     CK, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("1"),  .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("LSR_OVER_CE"))  _TECHMAP_REPLACE_ (.CLK(CK), .LSR(CD),          .DI(D), .Q(Q)); endmodule
-module FD1S3JX(input PD, D,     CK, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("1"),  .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("SET"),   .SRMODE("LSR_OVER_CE"))  _TECHMAP_REPLACE_ (.CLK(CK), .LSR(PD),          .DI(D), .Q(Q)); endmodule
-
-// TODO: Diamond latches
-// module FL1P3AY(); endmodule
-// module FL1P3AZ(); endmodule
-// module FL1P3BX(); endmodule
-// module FL1P3DX(); endmodule
-// module FL1P3IY(); endmodule
-// module FL1P3JY(); endmodule
-// module FL1S3AX(); endmodule
-// module FL1S3AY(); endmodule
-
-// Diamond I/O registers
-module IFS1P3BX(input PD, D, SP, SCLK, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("SET"),   .SRMODE("ASYNC"))       _TECHMAP_REPLACE_ (.CLK(SCLK), .LSR(PD), .CE(SP), .DI(D), .Q(Q)); endmodule
-module IFS1P3DX(input CD, D, SP, SCLK, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("ASYNC"))       _TECHMAP_REPLACE_ (.CLK(SCLK), .LSR(CD), .CE(SP), .DI(D), .Q(Q)); endmodule
-module IFS1P3IX(input CD, D, SP, SCLK, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("LSR_OVER_CE")) _TECHMAP_REPLACE_ (.CLK(SCLK), .LSR(CD), .CE(SP), .DI(D), .Q(Q)); endmodule
-module IFS1P3JX(input PD, D, SP, SCLK, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("SET"),   .SRMODE("LSR_OVER_CE")) _TECHMAP_REPLACE_ (.CLK(SCLK), .LSR(PD), .CE(SP), .DI(D), .Q(Q)); endmodule
-
-module OFS1P3BX(input PD, D, SP, SCLK, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("SET"),   .SRMODE("ASYNC"))       _TECHMAP_REPLACE_ (.CLK(SCLK), .LSR(PD), .CE(SP), .DI(D), .Q(Q)); endmodule
-module OFS1P3DX(input CD, D, SP, SCLK, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("ASYNC"))       _TECHMAP_REPLACE_ (.CLK(SCLK), .LSR(CD), .CE(SP), .DI(D), .Q(Q)); endmodule
-module OFS1P3IX(input CD, D, SP, SCLK, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("LSR_OVER_CE")) _TECHMAP_REPLACE_ (.CLK(SCLK), .LSR(CD), .CE(SP), .DI(D), .Q(Q)); endmodule
-module OFS1P3JX(input PD, D, SP, SCLK, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("SET"),   .SRMODE("LSR_OVER_CE")) _TECHMAP_REPLACE_ (.CLK(SCLK), .LSR(PD), .CE(SP), .DI(D), .Q(Q)); endmodule
-
-// TODO: Diamond I/O latches
-// module IFS1S1B(input PD, D, SCLK, output Q); endmodule
-// module IFS1S1D(input CD, D, SCLK, output Q); endmodule
-// module IFS1S1I(input PD, D, SCLK, output Q); endmodule
-// module IFS1S1J(input CD, D, SCLK, output Q); endmodule
-
-// Diamond I/O buffers
-module IB   (input I,     output O); (* PULLMODE="NONE" *) TRELLIS_IO #(.DIR("INPUT"))  _TECHMAP_REPLACE_ (.B(I), .O(O)); endmodule
-module IBPU (input I,     output O); (* PULLMODE="UP"   *) TRELLIS_IO #(.DIR("INPUT"))  _TECHMAP_REPLACE_ (.B(I), .O(O)); endmodule
-module IBPD (input I,     output O); (* PULLMODE="DOWN" *) TRELLIS_IO #(.DIR("INPUT"))  _TECHMAP_REPLACE_ (.B(I), .O(O)); endmodule
-module OB   (input I,     output O); (* PULLMODE="NONE" *) TRELLIS_IO #(.DIR("OUTPUT")) _TECHMAP_REPLACE_ (.B(O), .I(I)); endmodule
-module OBZ  (input I, T,  output O); (* PULLMODE="NONE" *) TRELLIS_IO #(.DIR("OUTPUT")) _TECHMAP_REPLACE_ (.B(O), .I(I), .T(T)); endmodule
-module OBZPU(input I, T,  output O); (* PULLMODE="UP"   *) TRELLIS_IO #(.DIR("OUTPUT")) _TECHMAP_REPLACE_ (.B(O), .I(I), .T(T)); endmodule
-module OBZPD(input I, T,  output O); (* PULLMODE="DOWN" *) TRELLIS_IO #(.DIR("OUTPUT")) _TECHMAP_REPLACE_ (.B(O), .I(I), .T(T)); endmodule
-module OBCO (input I,     output OT, OC); OLVDS olvds (.A(I), .Z(OT), .ZN(OC)); endmodule
-module BB   (input I, T,  output O, inout B); (* PULLMODE="NONE" *) TRELLIS_IO #(.DIR("BIDIR")) _TECHMAP_REPLACE_ (.B(B), .I(I), .O(O), .T(T)); endmodule
-module BBPU (input I, T,  output O, inout B); (* PULLMODE="UP"   *) TRELLIS_IO #(.DIR("BIDIR")) _TECHMAP_REPLACE_ (.B(B), .I(I), .O(O), .T(T)); endmodule
-module BBPD (input I, T,  output O, inout B); (* PULLMODE="DOWN" *) TRELLIS_IO #(.DIR("BIDIR")) _TECHMAP_REPLACE_ (.B(B), .I(I), .O(O), .T(T)); endmodule
-module ILVDS(input A, AN, output Z    ); TRELLIS_IO #(.DIR("INPUT"))  _TECHMAP_REPLACE_ (.B(A), .O(Z)); endmodule
-module OLVDS(input A,     output Z, ZN); TRELLIS_IO #(.DIR("OUTPUT")) _TECHMAP_REPLACE_ (.B(Z), .I(A)); endmodule
+`include "cells_ff.vh"
+`include "cells_io.vh"
-- 
cgit v1.2.3


From 91b46ed81670de621af2d88a4da32005a17a2f16 Mon Sep 17 00:00:00 2001
From: David Shah <dave@ds0.me>
Date: Fri, 30 Aug 2019 13:25:55 +0100
Subject: ecp5: Add simulation equivalence check for Diamond FF implementations

Signed-off-by: David Shah <dave@ds0.me>
---
 techlibs/ecp5/cells_sim.v               |  4 ++
 techlibs/ecp5/tests/.gitignore          |  1 +
 techlibs/ecp5/tests/test_diamond_ffs.py | 82 +++++++++++++++++++++++++++++++++
 3 files changed, 87 insertions(+)
 create mode 100644 techlibs/ecp5/tests/.gitignore
 create mode 100644 techlibs/ecp5/tests/test_diamond_ffs.py

(limited to 'techlibs/ecp5')

diff --git a/techlibs/ecp5/cells_sim.v b/techlibs/ecp5/cells_sim.v
index ba5b9c715..75a1aad1f 100644
--- a/techlibs/ecp5/cells_sim.v
+++ b/techlibs/ecp5/cells_sim.v
@@ -693,5 +693,9 @@ module DP16KD(
 	parameter INITVAL_3F = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
 endmodule
 
+`ifndef NO_INCLUDES
+
 `include "cells_ff.vh"
 `include "cells_io.vh"
+
+`endif
diff --git a/techlibs/ecp5/tests/.gitignore b/techlibs/ecp5/tests/.gitignore
new file mode 100644
index 000000000..0e18132cc
--- /dev/null
+++ b/techlibs/ecp5/tests/.gitignore
@@ -0,0 +1 @@
+work_*
diff --git a/techlibs/ecp5/tests/test_diamond_ffs.py b/techlibs/ecp5/tests/test_diamond_ffs.py
new file mode 100644
index 000000000..1ed85ce8b
--- /dev/null
+++ b/techlibs/ecp5/tests/test_diamond_ffs.py
@@ -0,0 +1,82 @@
+import os
+import subprocess
+
+if not os.path.exists("work_ff"):
+	os.mkdir("work_ff")
+
+modules = []
+
+with open("../cells_ff.vh", "r") as f:
+	with open("work_ff/cells_ff_gate.v", "w") as g:
+		for line in f:
+			if not line.startswith("module"):
+				g.write(line)
+				continue
+			else:
+				spidx = line.find(" ")
+				bridx = line.find("(")
+				modname = line[spidx+1 : bridx]
+				g.write("module %s_gate" % modname)
+				g.write(line[bridx:])
+				inpidx = line.find("input ")
+				outpidx = line.find(", output")
+				modules.append((modname, [x.strip() for x in line[inpidx+6:outpidx].split(",")]))
+
+with open("work_ff/testbench.v", "w") as f:
+	print("""
+`timescale 1ns/ 1ps
+
+module testbench;
+reg pur = 0, clk, rst, cen, d;
+
+// Needed for Diamond sim models
+GSR GSR_INST (.GSR(1'b1));
+PUR PUR_INST (.PUR(pur));
+
+
+initial begin
+	$dumpfile("work_ff/ffs.vcd");
+	$dumpvars(0, testbench);
+	#5;
+	pur = 1;
+	#95;
+	repeat (2500) begin
+		{clk, rst, cen, d} = $random;
+		#10;
+		check_outputs;
+		#1;
+	end
+	$finish;
+end
+	""", file=f)
+
+	for modname, inputs in modules:
+		print("    wire %s_gold_q, %s_gate_q;"  % (modname, modname), file=f)
+		portconns = []
+		for inp in inputs:
+			if inp in ("SCLK", "CK"):
+				portconns.append(".%s(clk)" % inp)
+			elif inp in ("CD", "PD"):
+				portconns.append(".%s(rst)" % inp)
+			elif inp == "SP":
+				portconns.append(".%s(cen)" % inp)
+			elif inp == "D":
+				portconns.append(".%s(d)" % inp)
+			else:
+				assert False
+		portconns.append(".Q(%s_gold_q)" % modname)
+		print("    %s %s_gold_i (%s);" % (modname, modname, ", ".join(portconns)), file=f)
+		portconns[-1] = (".Q(%s_gate_q)" % modname)
+		print("    %s_gate %s_gate_i (%s);" % (modname, modname, ", ".join(portconns)), file=f)
+		print("", file=f)
+	print("    task check_outputs;", file=f)
+	print("        begin", file=f)
+	print("             if (%s_gold_q != %s_gate_q) $display(\"MISMATCH at %%1t:  %s_gold_q=%%b, %s_gate_q=%%b\", $time, %s_gold_q, %s_gate_q);" %
+			(modname, modname, modname, modname, modname, modname), file=f)
+	print("        end", file=f)
+	print("    endtask", file=f)
+	print("endmodule", file=f)
+
+diamond_models = "/usr/local/diamond/3.10_x64/cae_library/simulation/verilog/ecp5u"
+subprocess.call(["iverilog", "-s", "testbench", "-o", "work_ff/testbench", "-Dmixed_hdl", "-DNO_INCLUDES", "-y", diamond_models, "work_ff/cells_ff_gate.v", "../cells_sim.v", "work_ff/testbench.v"])
+subprocess.call(["vvp", "work_ff/testbench"])
-- 
cgit v1.2.3


From 90b44113d89cd1f028e7805e0990dae43e2efa6f Mon Sep 17 00:00:00 2001
From: David Shah <dave@ds0.me>
Date: Sat, 31 Aug 2019 09:58:46 +0100
Subject: ecp5_gsr: Fix typo

Signed-off-by: David Shah <dave@ds0.me>
---
 techlibs/ecp5/ecp5_gsr.cc | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'techlibs/ecp5')

diff --git a/techlibs/ecp5/ecp5_gsr.cc b/techlibs/ecp5/ecp5_gsr.cc
index 8b8927d31..2bc714b6f 100644
--- a/techlibs/ecp5/ecp5_gsr.cc
+++ b/techlibs/ecp5/ecp5_gsr.cc
@@ -124,7 +124,7 @@ struct Ecp5GsrPass : public Pass {
 				SigBit lsr = sigmap(sig_lsr[0]);
 				if (!inverted_gsr.count(lsr))
 					continue;
-				cell->setParam(ID(SRMODE), Const("SYNC"));
+				cell->setParam(ID(SRMODE), Const("LSR_OVER_CE"));
 				cell->unsetPort(ID(LSR));
 			}
 
-- 
cgit v1.2.3


From a3c16a05657e639a04d647a15af56b6fbce25e17 Mon Sep 17 00:00:00 2001
From: Miodrag Milanovic <mmicko@gmail.com>
Date: Sat, 31 Aug 2019 11:12:06 +0200
Subject: Fix TRELLIS_FF simulation model

---
 techlibs/ecp5/cells_sim.v | 13 +++++++------
 1 file changed, 7 insertions(+), 6 deletions(-)

(limited to 'techlibs/ecp5')

diff --git a/techlibs/ecp5/cells_sim.v b/techlibs/ecp5/cells_sim.v
index 75a1aad1f..5bdb8395e 100644
--- a/techlibs/ecp5/cells_sim.v
+++ b/techlibs/ecp5/cells_sim.v
@@ -229,14 +229,15 @@ module TRELLIS_FF(input CLK, LSR, CE, DI, M, output reg Q);
 	parameter REGSET = "RESET";
 	parameter [127:0] LSRMODE = "LSR";
 
-	reg muxce;
-	always @(*)
+	wire muxce;
+	generate
 		case (CEMUX)
-			"1": muxce = 1'b1;
-			"0": muxce = 1'b0;
-			"INV": muxce = ~CE;
-			default: muxce = CE;
+			"1": assign muxce = 1'b1;
+			"0": assign muxce = 1'b0;
+			"INV": assign muxce = ~CE;
+			default: assign muxce = CE;
 		endcase
+	endgenerate
 
 	wire muxlsr = (LSRMUX == "INV") ? ~LSR : LSR;
 	wire muxclk = (CLKMUX == "INV") ? ~CLK : CLK;
-- 
cgit v1.2.3


From 696f854801619644e42f437894847ace96594a6b Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Mon, 2 Sep 2019 12:15:11 -0700
Subject: Rename box

---
 techlibs/ecp5/abc_5g.box | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'techlibs/ecp5')

diff --git a/techlibs/ecp5/abc_5g.box b/techlibs/ecp5/abc_5g.box
index 66ebe196a..a336b4a85 100644
--- a/techlibs/ecp5/abc_5g.box
+++ b/techlibs/ecp5/abc_5g.box
@@ -18,7 +18,7 @@ CCU2C   1      1   9      3
 # Box 2 : TRELLIS_DPR16X4_COMB (16x4 dist ram)
 # Outputs: DO0, DO1, DO2, DO3
 # name               ID  w/b   ins   outs
-$__ABC_RAM16X2_COMB  2     0   8    4
+$__ABC_DPR16X4_COMB  2     0   8    4
 
 #A0   A1   A2   A3   RAD0   RAD1   RAD2   RAD3
 0     0    0    0    141    379    275    379
-- 
cgit v1.2.3