From 269ff450f55f4354c82db1b98f8eb722317d9250 Mon Sep 17 00:00:00 2001
From: David Shah <dave@ds0.me>
Date: Mon, 8 Jul 2019 15:40:12 +0100
Subject: Add mul2dsp multiplier splitting rule and ECP5 mapping

Signed-off-by: David Shah <dave@ds0.me>
---
 techlibs/ecp5/Makefile.inc  |  1 +
 techlibs/ecp5/dsp_map.v     | 10 ++++++++++
 techlibs/ecp5/synth_ecp5.cc | 33 +++++++++++++++++++++++++++++++--
 3 files changed, 42 insertions(+), 2 deletions(-)
 create mode 100644 techlibs/ecp5/dsp_map.v

(limited to 'techlibs/ecp5')

diff --git a/techlibs/ecp5/Makefile.inc b/techlibs/ecp5/Makefile.inc
index ff39ba4fe..a2f5cadee 100644
--- a/techlibs/ecp5/Makefile.inc
+++ b/techlibs/ecp5/Makefile.inc
@@ -10,6 +10,7 @@ $(eval $(call add_share_file,share/ecp5,techlibs/ecp5/brams_map.v))
 $(eval $(call add_share_file,share/ecp5,techlibs/ecp5/bram.txt))
 $(eval $(call add_share_file,share/ecp5,techlibs/ecp5/arith_map.v))
 $(eval $(call add_share_file,share/ecp5,techlibs/ecp5/latches_map.v))
+$(eval $(call add_share_file,share/ecp5,techlibs/ecp5/dsp_map.v))
 
 $(eval $(call add_share_file,share/ecp5,techlibs/ecp5/abc_5g.box))
 $(eval $(call add_share_file,share/ecp5,techlibs/ecp5/abc_5g.lut))
diff --git a/techlibs/ecp5/dsp_map.v b/techlibs/ecp5/dsp_map.v
new file mode 100644
index 000000000..22e30574c
--- /dev/null
+++ b/techlibs/ecp5/dsp_map.v
@@ -0,0 +1,10 @@
+module \$__MUL18X18 (input [17:0] A, input [17:0] B, output [35:0] OUT);
+	MULT18X18D mult_i(
+		.A0(A[0]), .A1(A[1]), .A2(A[2]), .A3(A[3]), .A4(A[4]), .A5(A[5]), .A6(A[6]), .A7(A[7]), .A8(A[8]), .A9(A[9]), .A10(A[10]), .A11(A[11]), .A12(A[12]), .A13(A[13]), .A14(A[14]), .A15(A[15]), .A16(A[16]), .A17(A[17]),
+		.B0(B[0]), .B1(B[1]), .B2(B[2]), .B3(B[3]), .B4(B[4]), .B5(B[5]), .B6(B[6]), .B7(B[7]), .B8(B[8]), .B9(B[9]), .B10(B[10]), .B11(B[11]), .B12(B[12]), .B13(B[13]), .B14(B[14]), .B15(B[15]), .B16(B[16]), .B17(B[17]),
+		.C17(1'b0), .C16(1'b0), .C15(1'b0), .C14(1'b0), .C13(1'b0), .C12(1'b0), .C11(1'b0), .C10(1'b0), .C9(1'b0), .C8(1'b0), .C7(1'b0), .C6(1'b0), .C5(1'b0), .C4(1'b0), .C3(1'b0), .C2(1'b0), .C1(1'b0), .C0(1'b0),
+		.SIGNEDA(1'b0), .SIGNEDB(1'b0), .SOURCEA(1'b0), .SOURCEB(1'b0),
+
+		.P0(OUT[0]), .P1(OUT[1]), .P2(OUT[2]), .P3(OUT[3]), .P4(OUT[4]), .P5(OUT[5]), .P6(OUT[6]), .P7(OUT[7]), .P8(OUT[8]), .P9(OUT[9]), .P10(OUT[10]), .P11(OUT[11]), .P12(OUT[12]), .P13(OUT[13]), .P14(OUT[14]), .P15(OUT[15]), .P16(OUT[16]), .P17(OUT[17]), .P18(OUT[18]), .P19(OUT[19]), .P20(OUT[20]), .P21(OUT[21]), .P22(OUT[22]), .P23(OUT[23]), .P24(OUT[24]), .P25(OUT[25]), .P26(OUT[26]), .P27(OUT[27]), .P28(OUT[28]), .P29(OUT[29]), .P30(OUT[30]), .P31(OUT[31]), .P32(OUT[32]), .P33(OUT[33]), .P34(OUT[34]), .P35(OUT[35])
+	);
+endmodule
\ No newline at end of file
diff --git a/techlibs/ecp5/synth_ecp5.cc b/techlibs/ecp5/synth_ecp5.cc
index f16a47f01..3b4185930 100644
--- a/techlibs/ecp5/synth_ecp5.cc
+++ b/techlibs/ecp5/synth_ecp5.cc
@@ -89,6 +89,9 @@ struct SynthEcp5Pass : public ScriptPass
 		log("        generate an output netlist (and BLIF file) suitable for VPR\n");
 		log("        (this feature is experimental and incomplete)\n");
 		log("\n");
+		log("    -dsp\n");
+		log("        map multipliers to MULT18X18D (EXPERIMENTAL)\n");
+		log("\n");
 		log("\n");
 		log("The following commands are executed by this synthesis command:\n");
 		help_script();
@@ -96,7 +99,7 @@ struct SynthEcp5Pass : public ScriptPass
 	}
 
 	string top_opt, blif_file, edif_file, json_file;
-	bool noccu2, nodffe, nobram, nodram, nowidelut, flatten, retime, abc2, abc9, vpr;
+	bool noccu2, nodffe, nobram, nodram, nowidelut, flatten, retime, abc2, abc9, dsp, vpr;
 
 	void clear_flags() YS_OVERRIDE
 	{
@@ -114,6 +117,7 @@ struct SynthEcp5Pass : public ScriptPass
 		abc2 = false;
 		vpr = false;
 		abc9 = false;
+		dsp = false;
 	}
 
 	void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
@@ -192,6 +196,10 @@ struct SynthEcp5Pass : public ScriptPass
 				abc9 = true;
 				continue;
 			}
+			if (args[argidx] == "-dsp") {
+				dsp = true;
+				continue;
+			}
 			break;
 		}
 		extra_args(args, argidx, design);
@@ -225,7 +233,28 @@ struct SynthEcp5Pass : public ScriptPass
 
 		if (check_label("coarse"))
 		{
-			run("synth -run coarse");
+			run("opt_expr");
+			run("opt_clean");
+			run("check");
+			run("opt");
+			run("wreduce");
+			run("peepopt");
+			run("opt_clean");
+			run("share");
+			run("techmap -map +/cmp2lut.v -D LUT_WIDTH=4");
+			run("opt_expr");
+			run("opt_clean");
+			if (dsp) {
+				run("techmap -map +/mul2dsp.v -D DSP_A_MAXWIDTH=18 -D DSP_B_MAXWIDTH=18 -D DSP_NAME=$__MUL18X18");
+				run("clean");
+				run("techmap -map +/ecp5/dsp_map.v");
+			}
+			run("alumacc");
+			run("opt");
+			run("fsm");
+			run("opt -fast");
+			run("memory -nomap");
+			run("opt_clean");
 		}
 
 		if (!nobram && check_label("bram", "(skip if -nobram)"))
-- 
cgit v1.2.3


From c865559f9540c29cb9c6302edc8b4a2620c0b49d Mon Sep 17 00:00:00 2001
From: David Shah <dave@ds0.me>
Date: Mon, 8 Jul 2019 19:15:25 +0100
Subject: xc7: Map combinational DSP48E1s

Signed-off-by: David Shah <dave@ds0.me>
---
 techlibs/ecp5/dsp_map.v | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

(limited to 'techlibs/ecp5')

diff --git a/techlibs/ecp5/dsp_map.v b/techlibs/ecp5/dsp_map.v
index 22e30574c..5f7755afb 100644
--- a/techlibs/ecp5/dsp_map.v
+++ b/techlibs/ecp5/dsp_map.v
@@ -1,5 +1,5 @@
 module \$__MUL18X18 (input [17:0] A, input [17:0] B, output [35:0] OUT);
-	MULT18X18D mult_i(
+	MULT18X18D _TECHMAP_REPLACE_ (
 		.A0(A[0]), .A1(A[1]), .A2(A[2]), .A3(A[3]), .A4(A[4]), .A5(A[5]), .A6(A[6]), .A7(A[7]), .A8(A[8]), .A9(A[9]), .A10(A[10]), .A11(A[11]), .A12(A[12]), .A13(A[13]), .A14(A[14]), .A15(A[15]), .A16(A[16]), .A17(A[17]),
 		.B0(B[0]), .B1(B[1]), .B2(B[2]), .B3(B[3]), .B4(B[4]), .B5(B[5]), .B6(B[6]), .B7(B[7]), .B8(B[8]), .B9(B[9]), .B10(B[10]), .B11(B[11]), .B12(B[12]), .B13(B[13]), .B14(B[14]), .B15(B[15]), .B16(B[16]), .B17(B[17]),
 		.C17(1'b0), .C16(1'b0), .C15(1'b0), .C14(1'b0), .C13(1'b0), .C12(1'b0), .C11(1'b0), .C10(1'b0), .C9(1'b0), .C8(1'b0), .C7(1'b0), .C6(1'b0), .C5(1'b0), .C4(1'b0), .C3(1'b0), .C2(1'b0), .C1(1'b0), .C0(1'b0),
@@ -7,4 +7,4 @@ module \$__MUL18X18 (input [17:0] A, input [17:0] B, output [35:0] OUT);
 
 		.P0(OUT[0]), .P1(OUT[1]), .P2(OUT[2]), .P3(OUT[3]), .P4(OUT[4]), .P5(OUT[5]), .P6(OUT[6]), .P7(OUT[7]), .P8(OUT[8]), .P9(OUT[9]), .P10(OUT[10]), .P11(OUT[11]), .P12(OUT[12]), .P13(OUT[13]), .P14(OUT[14]), .P15(OUT[15]), .P16(OUT[16]), .P17(OUT[17]), .P18(OUT[18]), .P19(OUT[19]), .P20(OUT[20]), .P21(OUT[21]), .P22(OUT[22]), .P23(OUT[23]), .P24(OUT[24]), .P25(OUT[25]), .P26(OUT[26]), .P27(OUT[27]), .P28(OUT[28]), .P29(OUT[29]), .P30(OUT[30]), .P31(OUT[31]), .P32(OUT[32]), .P33(OUT[33]), .P34(OUT[34]), .P35(OUT[35])
 	);
-endmodule
\ No newline at end of file
+endmodule
-- 
cgit v1.2.3


From 42f8e68e76a3717cf4ad29c36f0a9a801cde52c1 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Mon, 15 Jul 2019 14:45:47 -0700
Subject: OUT port to Y in generic DSP

---
 techlibs/ecp5/dsp_map.v | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

(limited to 'techlibs/ecp5')

diff --git a/techlibs/ecp5/dsp_map.v b/techlibs/ecp5/dsp_map.v
index 5f7755afb..24e28869e 100644
--- a/techlibs/ecp5/dsp_map.v
+++ b/techlibs/ecp5/dsp_map.v
@@ -1,10 +1,10 @@
-module \$__MUL18X18 (input [17:0] A, input [17:0] B, output [35:0] OUT);
+module \$__MUL18X18 (input [17:0] A, input [17:0] B, output [35:0] Y);
 	MULT18X18D _TECHMAP_REPLACE_ (
 		.A0(A[0]), .A1(A[1]), .A2(A[2]), .A3(A[3]), .A4(A[4]), .A5(A[5]), .A6(A[6]), .A7(A[7]), .A8(A[8]), .A9(A[9]), .A10(A[10]), .A11(A[11]), .A12(A[12]), .A13(A[13]), .A14(A[14]), .A15(A[15]), .A16(A[16]), .A17(A[17]),
 		.B0(B[0]), .B1(B[1]), .B2(B[2]), .B3(B[3]), .B4(B[4]), .B5(B[5]), .B6(B[6]), .B7(B[7]), .B8(B[8]), .B9(B[9]), .B10(B[10]), .B11(B[11]), .B12(B[12]), .B13(B[13]), .B14(B[14]), .B15(B[15]), .B16(B[16]), .B17(B[17]),
 		.C17(1'b0), .C16(1'b0), .C15(1'b0), .C14(1'b0), .C13(1'b0), .C12(1'b0), .C11(1'b0), .C10(1'b0), .C9(1'b0), .C8(1'b0), .C7(1'b0), .C6(1'b0), .C5(1'b0), .C4(1'b0), .C3(1'b0), .C2(1'b0), .C1(1'b0), .C0(1'b0),
 		.SIGNEDA(1'b0), .SIGNEDB(1'b0), .SOURCEA(1'b0), .SOURCEB(1'b0),
 
-		.P0(OUT[0]), .P1(OUT[1]), .P2(OUT[2]), .P3(OUT[3]), .P4(OUT[4]), .P5(OUT[5]), .P6(OUT[6]), .P7(OUT[7]), .P8(OUT[8]), .P9(OUT[9]), .P10(OUT[10]), .P11(OUT[11]), .P12(OUT[12]), .P13(OUT[13]), .P14(OUT[14]), .P15(OUT[15]), .P16(OUT[16]), .P17(OUT[17]), .P18(OUT[18]), .P19(OUT[19]), .P20(OUT[20]), .P21(OUT[21]), .P22(OUT[22]), .P23(OUT[23]), .P24(OUT[24]), .P25(OUT[25]), .P26(OUT[26]), .P27(OUT[27]), .P28(OUT[28]), .P29(OUT[29]), .P30(OUT[30]), .P31(OUT[31]), .P32(OUT[32]), .P33(OUT[33]), .P34(OUT[34]), .P35(OUT[35])
+		.P0(Y[0]), .P1(Y[1]), .P2(Y[2]), .P3(Y[3]), .P4(Y[4]), .P5(Y[5]), .P6(Y[6]), .P7(Y[7]), .P8(Y[8]), .P9(Y[9]), .P10(Y[10]), .P11(Y[11]), .P12(Y[12]), .P13(Y[13]), .P14(Y[14]), .P15(Y[15]), .P16(Y[16]), .P17(Y[17]), .P18(Y[18]), .P19(Y[19]), .P20(Y[20]), .P21(Y[21]), .P22(Y[22]), .P23(Y[23]), .P24(Y[24]), .P25(Y[25]), .P26(Y[26]), .P27(Y[27]), .P28(Y[28]), .P29(Y[29]), .P30(Y[30]), .P31(Y[31]), .P32(Y[32]), .P33(Y[33]), .P34(Y[34]), .P35(Y[35])
 	);
 endmodule
-- 
cgit v1.2.3


From cb84ed23263f8cad8f878a327061ac2c990af812 Mon Sep 17 00:00:00 2001
From: David Shah <dave@ds0.me>
Date: Thu, 8 Aug 2019 15:14:09 +0100
Subject: ecp5: Bring up to date with mul2dsp changes

Signed-off-by: David Shah <dave@ds0.me>
---
 techlibs/ecp5/dsp_map.v     | 9 ++++++++-
 techlibs/ecp5/synth_ecp5.cc | 3 ++-
 2 files changed, 10 insertions(+), 2 deletions(-)

(limited to 'techlibs/ecp5')

diff --git a/techlibs/ecp5/dsp_map.v b/techlibs/ecp5/dsp_map.v
index 24e28869e..cb95ddb1c 100644
--- a/techlibs/ecp5/dsp_map.v
+++ b/techlibs/ecp5/dsp_map.v
@@ -1,9 +1,16 @@
 module \$__MUL18X18 (input [17:0] A, input [17:0] B, output [35:0] Y);
+
+	parameter A_WIDTH = 18;
+	parameter B_WIDTH = 18;
+	parameter Y_WIDTH = 36;
+	parameter A_SIGNED = 0;
+	parameter B_SIGNED = 0;
+
 	MULT18X18D _TECHMAP_REPLACE_ (
 		.A0(A[0]), .A1(A[1]), .A2(A[2]), .A3(A[3]), .A4(A[4]), .A5(A[5]), .A6(A[6]), .A7(A[7]), .A8(A[8]), .A9(A[9]), .A10(A[10]), .A11(A[11]), .A12(A[12]), .A13(A[13]), .A14(A[14]), .A15(A[15]), .A16(A[16]), .A17(A[17]),
 		.B0(B[0]), .B1(B[1]), .B2(B[2]), .B3(B[3]), .B4(B[4]), .B5(B[5]), .B6(B[6]), .B7(B[7]), .B8(B[8]), .B9(B[9]), .B10(B[10]), .B11(B[11]), .B12(B[12]), .B13(B[13]), .B14(B[14]), .B15(B[15]), .B16(B[16]), .B17(B[17]),
 		.C17(1'b0), .C16(1'b0), .C15(1'b0), .C14(1'b0), .C13(1'b0), .C12(1'b0), .C11(1'b0), .C10(1'b0), .C9(1'b0), .C8(1'b0), .C7(1'b0), .C6(1'b0), .C5(1'b0), .C4(1'b0), .C3(1'b0), .C2(1'b0), .C1(1'b0), .C0(1'b0),
-		.SIGNEDA(1'b0), .SIGNEDB(1'b0), .SOURCEA(1'b0), .SOURCEB(1'b0),
+		.SIGNEDA(A_SIGNED), .SIGNEDB(B_SIGNED), .SOURCEA(1'b0), .SOURCEB(1'b0),
 
 		.P0(Y[0]), .P1(Y[1]), .P2(Y[2]), .P3(Y[3]), .P4(Y[4]), .P5(Y[5]), .P6(Y[6]), .P7(Y[7]), .P8(Y[8]), .P9(Y[9]), .P10(Y[10]), .P11(Y[11]), .P12(Y[12]), .P13(Y[13]), .P14(Y[14]), .P15(Y[15]), .P16(Y[16]), .P17(Y[17]), .P18(Y[18]), .P19(Y[19]), .P20(Y[20]), .P21(Y[21]), .P22(Y[22]), .P23(Y[23]), .P24(Y[24]), .P25(Y[25]), .P26(Y[26]), .P27(Y[27]), .P28(Y[28]), .P29(Y[29]), .P30(Y[30]), .P31(Y[31]), .P32(Y[32]), .P33(Y[33]), .P34(Y[34]), .P35(Y[35])
 	);
diff --git a/techlibs/ecp5/synth_ecp5.cc b/techlibs/ecp5/synth_ecp5.cc
index 3129ba929..7be377280 100644
--- a/techlibs/ecp5/synth_ecp5.cc
+++ b/techlibs/ecp5/synth_ecp5.cc
@@ -248,9 +248,10 @@ struct SynthEcp5Pass : public ScriptPass
 			run("opt_expr");
 			run("opt_clean");
 			if (dsp) {
-				run("techmap -map +/mul2dsp.v -D DSP_A_MAXWIDTH=18 -D DSP_B_MAXWIDTH=18 -D DSP_NAME=$__MUL18X18");
+				run("techmap -map +/mul2dsp.v -D DSP_A_MAXWIDTH=18 -D DSP_B_MAXWIDTH=18  -D DSP_A_MINWIDTH=2 -D DSP_B_MINWIDTH=2  -D DSP_NAME=$__MUL18X18");
 				run("clean");
 				run("techmap -map +/ecp5/dsp_map.v");
+				run("chtype -set $mul t:$__soft_mul","(if -dsp)");
 			}
 			run("alumacc");
 			run("opt");
-- 
cgit v1.2.3


From 0492b8b5412683392bc19ad7f15ba6c14e6668f8 Mon Sep 17 00:00:00 2001
From: David Shah <dave@ds0.me>
Date: Thu, 8 Aug 2019 15:18:59 +0100
Subject: ecp5: Replace '-dsp' with inverse logic '-nodsp' to match
 synth_xilinx

Signed-off-by: David Shah <dave@ds0.me>
---
 techlibs/ecp5/synth_ecp5.cc | 22 +++++++++++-----------
 1 file changed, 11 insertions(+), 11 deletions(-)

(limited to 'techlibs/ecp5')

diff --git a/techlibs/ecp5/synth_ecp5.cc b/techlibs/ecp5/synth_ecp5.cc
index 7be377280..1a5359e85 100644
--- a/techlibs/ecp5/synth_ecp5.cc
+++ b/techlibs/ecp5/synth_ecp5.cc
@@ -89,8 +89,8 @@ struct SynthEcp5Pass : public ScriptPass
 		log("        generate an output netlist (and BLIF file) suitable for VPR\n");
 		log("        (this feature is experimental and incomplete)\n");
 		log("\n");
-		log("    -dsp\n");
-		log("        map multipliers to MULT18X18D (EXPERIMENTAL)\n");
+		log("    -nodsp\n");
+		log("        do not map multipliers to MULT18X18D\n");
 		log("\n");
 		log("\n");
 		log("The following commands are executed by this synthesis command:\n");
@@ -99,7 +99,7 @@ struct SynthEcp5Pass : public ScriptPass
 	}
 
 	string top_opt, blif_file, edif_file, json_file;
-	bool noccu2, nodffe, nobram, nolutram, nowidelut, flatten, retime, abc2, abc9, dsp, vpr;
+	bool noccu2, nodffe, nobram, nolutram, nowidelut, flatten, retime, abc2, abc9, nodsp, vpr;
 
 	void clear_flags() YS_OVERRIDE
 	{
@@ -117,7 +117,7 @@ struct SynthEcp5Pass : public ScriptPass
 		abc2 = false;
 		vpr = false;
 		abc9 = false;
-		dsp = false;
+		nodsp = false;
 	}
 
 	void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
@@ -196,8 +196,8 @@ struct SynthEcp5Pass : public ScriptPass
 				abc9 = true;
 				continue;
 			}
-			if (args[argidx] == "-dsp") {
-				dsp = true;
+			if (args[argidx] == "-nodsp") {
+				nodsp = true;
 				continue;
 			}
 			break;
@@ -247,11 +247,11 @@ struct SynthEcp5Pass : public ScriptPass
 			run("techmap -map +/cmp2lut.v -D LUT_WIDTH=4");
 			run("opt_expr");
 			run("opt_clean");
-			if (dsp) {
-				run("techmap -map +/mul2dsp.v -D DSP_A_MAXWIDTH=18 -D DSP_B_MAXWIDTH=18  -D DSP_A_MINWIDTH=2 -D DSP_B_MINWIDTH=2  -D DSP_NAME=$__MUL18X18");
-				run("clean");
-				run("techmap -map +/ecp5/dsp_map.v");
-				run("chtype -set $mul t:$__soft_mul","(if -dsp)");
+			if (!nodsp) {
+				run("techmap -map +/mul2dsp.v -D DSP_A_MAXWIDTH=18 -D DSP_B_MAXWIDTH=18  -D DSP_A_MINWIDTH=2 -D DSP_B_MINWIDTH=2  -D DSP_NAME=$__MUL18X18", "(unless -nodsp)");
+				run("clean", "(unless -nodsp)");
+				run("techmap -map +/ecp5/dsp_map.v", "(unless -nodsp)");
+				run("chtype -set $mul t:$__soft_mul", "(unless -nodsp)");
 			}
 			run("alumacc");
 			run("opt");
-- 
cgit v1.2.3


From 55acf3120fa47bb95be8a6551738f4f9b1c70a21 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Tue, 20 Aug 2019 18:59:03 -0700
Subject: ecp5 to use abc_map.v and _unmap.v

---
 techlibs/ecp5/Makefile.inc  |  3 +++
 techlibs/ecp5/abc_5g.box    | 18 +++++++++---------
 techlibs/ecp5/abc_map.v     | 24 ++++++++++++++++++++++++
 techlibs/ecp5/abc_model.v   | 18 ++++++++++++++++++
 techlibs/ecp5/abc_unmap.v   | 25 +++++++++++++++++++++++++
 techlibs/ecp5/cells_sim.v   |  7 +++----
 techlibs/ecp5/synth_ecp5.cc |  8 +++++++-
 7 files changed, 89 insertions(+), 14 deletions(-)
 create mode 100644 techlibs/ecp5/abc_map.v
 create mode 100644 techlibs/ecp5/abc_model.v
 create mode 100644 techlibs/ecp5/abc_unmap.v

(limited to 'techlibs/ecp5')

diff --git a/techlibs/ecp5/Makefile.inc b/techlibs/ecp5/Makefile.inc
index 73e18112f..cffd5c3a4 100644
--- a/techlibs/ecp5/Makefile.inc
+++ b/techlibs/ecp5/Makefile.inc
@@ -11,6 +11,9 @@ $(eval $(call add_share_file,share/ecp5,techlibs/ecp5/bram.txt))
 $(eval $(call add_share_file,share/ecp5,techlibs/ecp5/arith_map.v))
 $(eval $(call add_share_file,share/ecp5,techlibs/ecp5/latches_map.v))
 
+$(eval $(call add_share_file,share/ecp5,techlibs/ecp5/abc_map.v))
+$(eval $(call add_share_file,share/ecp5,techlibs/ecp5/abc_unmap.v))
+$(eval $(call add_share_file,share/ecp5,techlibs/ecp5/abc_model.v))
 $(eval $(call add_share_file,share/ecp5,techlibs/ecp5/abc_5g.box))
 $(eval $(call add_share_file,share/ecp5,techlibs/ecp5/abc_5g.lut))
 $(eval $(call add_share_file,share/ecp5,techlibs/ecp5/abc_5g_nowide.lut))
diff --git a/techlibs/ecp5/abc_5g.box b/techlibs/ecp5/abc_5g.box
index c757d137d..66ebe196a 100644
--- a/techlibs/ecp5/abc_5g.box
+++ b/techlibs/ecp5/abc_5g.box
@@ -15,16 +15,16 @@ CCU2C   1      1   9      3
 630  379  630  379  526   275  392  141  273
 516  516  516  516  412   412  278  278  43
 
-# Box 2 : TRELLIS_DPR16X4 (16x4 dist ram)
+# Box 2 : TRELLIS_DPR16X4_COMB (16x4 dist ram)
 # Outputs: DO0, DO1, DO2, DO3
-# name            ID  w/b   ins   outs
-TRELLIS_DPR16X4   2     0   14    4
-
-#DI0   DI1   DI2   DI3   RAD0   RAD1   RAD2   RAD3   WAD0    WAD1   WAD2   WAD3  WCK   WRE
--      -     -     -     141    379    275    379    -       -      -      -     -     -
--      -     -     -     141    379    275    379    -       -      -      -     -     -
--      -     -     -     141    379    275    379    -       -      -      -     -     -
--      -     -     -     141    379    275    379    -       -      -      -     -     -
+# name               ID  w/b   ins   outs
+$__ABC_RAM16X2_COMB  2     0   8    4
+
+#A0   A1   A2   A3   RAD0   RAD1   RAD2   RAD3
+0     0    0    0    141    379    275    379
+0     0    0    0    141    379    275    379
+0     0    0    0    141    379    275    379
+0     0    0    0    141    379    275    379
 
 # Box 3 : PFUMX (MUX2)
 # Outputs: Z
diff --git a/techlibs/ecp5/abc_map.v b/techlibs/ecp5/abc_map.v
new file mode 100644
index 000000000..e8187ed18
--- /dev/null
+++ b/techlibs/ecp5/abc_map.v
@@ -0,0 +1,24 @@
+// ---------------------------------------
+
+module TRELLIS_DPR16X4 (
+	input  [3:0] DI,
+	input  [3:0] WAD,
+	input        WRE,
+	input        WCK,
+	input  [3:0] RAD,
+	output [3:0] DO
+);
+	parameter WCKMUX = "WCK";
+	parameter WREMUX = "WRE";
+	parameter [63:0] INITVAL = 64'h0000000000000000;
+    wire [3:0] \$DO ;
+
+    \$__ABC_DPR16X4_SEQ #(
+      .WCKMUX(WCKMUX), .WREMUX(WREMUX), .INITVAL(INITVAL)
+    ) _TECHMAP_REPLACE_ (
+      .DI(DI), .WAD(WAD), .WRE(WRE), .WCK(WCK),
+      .RAD(RAD), .DO(\$DO )
+    );
+
+    \$__ABC_DPR16X4_COMB do (.A(\$DO ), .S(RAD), .Y(DO));
+endmodule
diff --git a/techlibs/ecp5/abc_model.v b/techlibs/ecp5/abc_model.v
new file mode 100644
index 000000000..4eb923cb1
--- /dev/null
+++ b/techlibs/ecp5/abc_model.v
@@ -0,0 +1,18 @@
+// ---------------------------------------
+
+(* abc_box_id=2 *)
+module \$__ABC_DPR16X4_COMB (input [3:0] A, S, output [3:0] Y);
+endmodule
+
+module \$__ABC_DPR16X4_SEQ (
+	input  [3:0] DI,
+	input  [3:0] WAD,
+	input        WRE,
+	input        WCK,
+	input  [3:0] RAD,
+	output [3:0] DO
+);
+	parameter WCKMUX = "WCK";
+	parameter WREMUX = "WRE";
+	parameter [63:0] INITVAL = 64'h0000000000000000;
+endmodule
diff --git a/techlibs/ecp5/abc_unmap.v b/techlibs/ecp5/abc_unmap.v
new file mode 100644
index 000000000..0f918c202
--- /dev/null
+++ b/techlibs/ecp5/abc_unmap.v
@@ -0,0 +1,25 @@
+// ---------------------------------------
+
+module \$__ABC_DPR16X4_COMB (input [3:0] A, S, output [3:0] Y);
+    assign Y = A;
+endmodule
+
+module \$__ABC_DPR16X4_SEQ (
+	input  [3:0] DI,
+	input  [3:0] WAD,
+	input        WRE,
+	input        WCK,
+	input  [3:0] RAD,
+	output [3:0] DO
+);
+	parameter WCKMUX = "WCK";
+	parameter WREMUX = "WRE";
+	parameter [63:0] INITVAL = 64'h0000000000000000;
+
+    TRELLIS_DPR16X4 #(
+      .WCKMUX(WCKMUX), .WREMUX(WREMUX), .INITVAL(INITVAL)
+    ) _TECHMAP_REPLACE_ (
+      .DI(DI), .WAD(WAD), .WRE(WRE), .WCK(WCK),
+      .RAD(RAD), .DO(DO)
+    );
+endmodule
diff --git a/techlibs/ecp5/cells_sim.v b/techlibs/ecp5/cells_sim.v
index 2fcb0369e..f79a27312 100644
--- a/techlibs/ecp5/cells_sim.v
+++ b/techlibs/ecp5/cells_sim.v
@@ -107,11 +107,10 @@ module PFUMX (input ALUT, BLUT, C0, output Z);
 endmodule
 
 // ---------------------------------------
-//(* abc_box_id=2 *)
 module TRELLIS_DPR16X4 (
-	(* abc_scc_break *) input [3:0] DI,
-	(* abc_scc_break *) input [3:0] WAD,
-	(* abc_scc_break *) input       WRE,
+	input  [3:0] DI,
+	input  [3:0] WAD,
+	input        WRE,
 	input        WCK,
 	input  [3:0] RAD,
 	output [3:0] DO
diff --git a/techlibs/ecp5/synth_ecp5.cc b/techlibs/ecp5/synth_ecp5.cc
index 143d1f95c..93e1cd5b5 100644
--- a/techlibs/ecp5/synth_ecp5.cc
+++ b/techlibs/ecp5/synth_ecp5.cc
@@ -278,12 +278,18 @@ struct SynthEcp5Pass : public ScriptPass
 			if (abc2 || help_mode) {
 				run("abc", "      (only if -abc2)");
 			}
-			run("techmap -map +/ecp5/latches_map.v");
+			std::string techmap_args = "-map +/ecp5/latches_map.v";
+			if (abc9)
+				techmap_args += " -map +/ecp5/abc_map.v";
+			run("techmap " + techmap_args);
+
 			if (abc9) {
+				run("read_verilog -icells -lib +/ecp5/abc_model.v");
 				if (nowidelut)
 					run("abc9 -lut +/ecp5/abc_5g_nowide.lut -box +/ecp5/abc_5g.box -W 200");
 				else
 					run("abc9 -lut +/ecp5/abc_5g.lut -box +/ecp5/abc_5g.box -W 200");
+				run("techmap -map +/ecp5/abc_unmap.v");
 			} else {
 				if (nowidelut)
 					run("abc -lut 4 -dress");
-- 
cgit v1.2.3


From d46dc9c5b4362c1e333979cbbac4f3567904fee5 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Tue, 20 Aug 2019 19:18:36 -0700
Subject: ecp5 to use -max_iter 1

---
 techlibs/ecp5/abc_map.v     | 2 +-
 techlibs/ecp5/cells_sim.v   | 2 +-
 techlibs/ecp5/synth_ecp5.cc | 3 +--
 3 files changed, 3 insertions(+), 4 deletions(-)

(limited to 'techlibs/ecp5')

diff --git a/techlibs/ecp5/abc_map.v b/techlibs/ecp5/abc_map.v
index e8187ed18..ffd25f06d 100644
--- a/techlibs/ecp5/abc_map.v
+++ b/techlibs/ecp5/abc_map.v
@@ -13,7 +13,7 @@ module TRELLIS_DPR16X4 (
 	parameter [63:0] INITVAL = 64'h0000000000000000;
     wire [3:0] \$DO ;
 
-    \$__ABC_DPR16X4_SEQ #(
+    TRELLIS_DPR16X4 #(
       .WCKMUX(WCKMUX), .WREMUX(WREMUX), .INITVAL(INITVAL)
     ) _TECHMAP_REPLACE_ (
       .DI(DI), .WAD(WAD), .WRE(WRE), .WCK(WCK),
diff --git a/techlibs/ecp5/cells_sim.v b/techlibs/ecp5/cells_sim.v
index f79a27312..24de0c3c2 100644
--- a/techlibs/ecp5/cells_sim.v
+++ b/techlibs/ecp5/cells_sim.v
@@ -113,7 +113,7 @@ module TRELLIS_DPR16X4 (
 	input        WRE,
 	input        WCK,
 	input  [3:0] RAD,
-	output [3:0] DO
+	/* (* abc_arrival=<TODO> *) */ output [3:0] DO
 );
 	parameter WCKMUX = "WCK";
 	parameter WREMUX = "WRE";
diff --git a/techlibs/ecp5/synth_ecp5.cc b/techlibs/ecp5/synth_ecp5.cc
index 93e1cd5b5..b1d3160ba 100644
--- a/techlibs/ecp5/synth_ecp5.cc
+++ b/techlibs/ecp5/synth_ecp5.cc
@@ -280,11 +280,10 @@ struct SynthEcp5Pass : public ScriptPass
 			}
 			std::string techmap_args = "-map +/ecp5/latches_map.v";
 			if (abc9)
-				techmap_args += " -map +/ecp5/abc_map.v";
+				techmap_args += " -map +/ecp5/abc_map.v -max_iter 1";
 			run("techmap " + techmap_args);
 
 			if (abc9) {
-				run("read_verilog -icells -lib +/ecp5/abc_model.v");
 				if (nowidelut)
 					run("abc9 -lut +/ecp5/abc_5g_nowide.lut -box +/ecp5/abc_5g.box -W 200");
 				else
-- 
cgit v1.2.3


From 6b1b03d9f771addbd54358299faad181b589c9f8 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Tue, 20 Aug 2019 19:20:17 -0700
Subject: ecp5: remove DPR16X4 from abc_unmap.v

---
 techlibs/ecp5/abc_unmap.v | 20 --------------------
 1 file changed, 20 deletions(-)

(limited to 'techlibs/ecp5')

diff --git a/techlibs/ecp5/abc_unmap.v b/techlibs/ecp5/abc_unmap.v
index 0f918c202..d43cdd93f 100644
--- a/techlibs/ecp5/abc_unmap.v
+++ b/techlibs/ecp5/abc_unmap.v
@@ -3,23 +3,3 @@
 module \$__ABC_DPR16X4_COMB (input [3:0] A, S, output [3:0] Y);
     assign Y = A;
 endmodule
-
-module \$__ABC_DPR16X4_SEQ (
-	input  [3:0] DI,
-	input  [3:0] WAD,
-	input        WRE,
-	input        WCK,
-	input  [3:0] RAD,
-	output [3:0] DO
-);
-	parameter WCKMUX = "WCK";
-	parameter WREMUX = "WRE";
-	parameter [63:0] INITVAL = 64'h0000000000000000;
-
-    TRELLIS_DPR16X4 #(
-      .WCKMUX(WCKMUX), .WREMUX(WREMUX), .INITVAL(INITVAL)
-    ) _TECHMAP_REPLACE_ (
-      .DI(DI), .WAD(WAD), .WRE(WRE), .WCK(WCK),
-      .RAD(RAD), .DO(DO)
-    );
-endmodule
-- 
cgit v1.2.3


From 85d39653ac62fa4f1f809fb71b0df82a8bd01dfc Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Fri, 23 Aug 2019 13:20:29 -0700
Subject: Remove unused model

---
 techlibs/ecp5/abc_model.v | 13 -------------
 1 file changed, 13 deletions(-)

(limited to 'techlibs/ecp5')

diff --git a/techlibs/ecp5/abc_model.v b/techlibs/ecp5/abc_model.v
index 4eb923cb1..56a733b75 100644
--- a/techlibs/ecp5/abc_model.v
+++ b/techlibs/ecp5/abc_model.v
@@ -3,16 +3,3 @@
 (* abc_box_id=2 *)
 module \$__ABC_DPR16X4_COMB (input [3:0] A, S, output [3:0] Y);
 endmodule
-
-module \$__ABC_DPR16X4_SEQ (
-	input  [3:0] DI,
-	input  [3:0] WAD,
-	input        WRE,
-	input        WCK,
-	input  [3:0] RAD,
-	output [3:0] DO
-);
-	parameter WCKMUX = "WCK";
-	parameter WREMUX = "WRE";
-	parameter [63:0] INITVAL = 64'h0000000000000000;
-endmodule
-- 
cgit v1.2.3


From 455da572723e4f19ddc1d636b700a5fe1e975fbb Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Fri, 23 Aug 2019 13:21:21 -0700
Subject: Fix spacing

---
 techlibs/ecp5/cells_sim.v | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'techlibs/ecp5')

diff --git a/techlibs/ecp5/cells_sim.v b/techlibs/ecp5/cells_sim.v
index e2bf3c854..01b10f392 100644
--- a/techlibs/ecp5/cells_sim.v
+++ b/techlibs/ecp5/cells_sim.v
@@ -116,7 +116,7 @@ module TRELLIS_DPR16X4 (
 	input        WCK,
 	input  [3:0] RAD,
 	/* (* abc_arrival=<TODO> *) */
-    output [3:0] DO
+	output [3:0] DO
 );
 	parameter WCKMUX = "WCK";
 	parameter WREMUX = "WRE";
-- 
cgit v1.2.3


From 696f854801619644e42f437894847ace96594a6b Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Mon, 2 Sep 2019 12:15:11 -0700
Subject: Rename box

---
 techlibs/ecp5/abc_5g.box | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'techlibs/ecp5')

diff --git a/techlibs/ecp5/abc_5g.box b/techlibs/ecp5/abc_5g.box
index 66ebe196a..a336b4a85 100644
--- a/techlibs/ecp5/abc_5g.box
+++ b/techlibs/ecp5/abc_5g.box
@@ -18,7 +18,7 @@ CCU2C   1      1   9      3
 # Box 2 : TRELLIS_DPR16X4_COMB (16x4 dist ram)
 # Outputs: DO0, DO1, DO2, DO3
 # name               ID  w/b   ins   outs
-$__ABC_RAM16X2_COMB  2     0   8    4
+$__ABC_DPR16X4_COMB  2     0   8    4
 
 #A0   A1   A2   A3   RAD0   RAD1   RAD2   RAD3
 0     0    0    0    141    379    275    379
-- 
cgit v1.2.3


From 84825f937827f3e8fd3702a7ea85b8997ac74534 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Thu, 26 Sep 2019 10:45:14 -0700
Subject: Combine 'flatten' & 'coarse' labels in synth_ecp5 so proc run once

---
 techlibs/ecp5/synth_ecp5.cc | 13 ++++---------
 1 file changed, 4 insertions(+), 9 deletions(-)

(limited to 'techlibs/ecp5')

diff --git a/techlibs/ecp5/synth_ecp5.cc b/techlibs/ecp5/synth_ecp5.cc
index 0a3dcc62c..1f5b1cb6b 100644
--- a/techlibs/ecp5/synth_ecp5.cc
+++ b/techlibs/ecp5/synth_ecp5.cc
@@ -226,16 +226,13 @@ struct SynthEcp5Pass : public ScriptPass
 			run(stringf("hierarchy -check %s", help_mode ? "-top <top>" : top_opt.c_str()));
 		}
 
-		if (flatten && check_label("flatten", "(unless -noflatten)"))
+		if (check_label("coarse"))
 		{
 			run("proc");
-			run("flatten");
+			if (flatten || help_mode)
+				run("flatten");
 			run("tribuf -logic");
 			run("deminout");
-		}
-
-		if (check_label("coarse"))
-		{
 			run("opt_expr");
 			run("opt_clean");
 			run("check");
@@ -248,9 +245,7 @@ struct SynthEcp5Pass : public ScriptPass
 			run("opt_expr");
 			run("opt_clean");
 			if (!nodsp) {
-				run("techmap -map +/mul2dsp.v -D DSP_A_MAXWIDTH=18 -D DSP_B_MAXWIDTH=18  -D DSP_A_MINWIDTH=2 -D DSP_B_MINWIDTH=2  -D DSP_NAME=$__MUL18X18", "(unless -nodsp)");
-				run("clean", "(unless -nodsp)");
-				run("techmap -map +/ecp5/dsp_map.v", "(unless -nodsp)");
+				run("techmap -map +/mul2dsp.v -map +/ecp5/dsp_map.v -D DSP_A_MAXWIDTH=18 -D DSP_B_MAXWIDTH=18  -D DSP_A_MINWIDTH=2 -D DSP_B_MINWIDTH=2  -D DSP_NAME=$__MUL18X18", "(unless -nodsp)");
 				run("chtype -set $mul t:$__soft_mul", "(unless -nodsp)");
 			}
 			run("alumacc");
-- 
cgit v1.2.3


From 7a1538cd36b45fd3c397dd0414de37af768ad89e Mon Sep 17 00:00:00 2001
From: David Shah <dave@ds0.me>
Date: Tue, 1 Oct 2019 13:46:36 +0100
Subject: ecp5: Add support for mapping 36-bit wide PDP BRAMs

Signed-off-by: David Shah <dave@ds0.me>
---
 techlibs/ecp5/.gitignore       |  1 +
 techlibs/ecp5/Makefile.inc     |  2 +
 techlibs/ecp5/bram.txt         | 23 ++++++++++
 techlibs/ecp5/brams_connect.py | 20 +++++++++
 techlibs/ecp5/brams_map.v      | 42 ++++++++++++++++++
 techlibs/ecp5/cells_bb.v       | 96 +++++++++++++++++++++++++++++++++++++++++-
 6 files changed, 183 insertions(+), 1 deletion(-)

(limited to 'techlibs/ecp5')

diff --git a/techlibs/ecp5/.gitignore b/techlibs/ecp5/.gitignore
index 54c329735..9d4723264 100644
--- a/techlibs/ecp5/.gitignore
+++ b/techlibs/ecp5/.gitignore
@@ -6,4 +6,5 @@ bram_conn_2.vh
 bram_conn_4.vh
 bram_conn_9.vh
 bram_conn_18.vh
+bram_conn_36.vh
 brams_connect.mk
diff --git a/techlibs/ecp5/Makefile.inc b/techlibs/ecp5/Makefile.inc
index 80eee5004..b03da164c 100644
--- a/techlibs/ecp5/Makefile.inc
+++ b/techlibs/ecp5/Makefile.inc
@@ -44,6 +44,7 @@ techlibs/ecp5/bram_conn_2.vh: techlibs/ecp5/brams_connect.mk
 techlibs/ecp5/bram_conn_4.vh: techlibs/ecp5/brams_connect.mk
 techlibs/ecp5/bram_conn_9.vh: techlibs/ecp5/brams_connect.mk
 techlibs/ecp5/bram_conn_18.vh: techlibs/ecp5/brams_connect.mk
+techlibs/ecp5/bram_conn_36.vh: techlibs/ecp5/brams_connect.mk
 
 $(eval $(call add_gen_share_file,share/ecp5,techlibs/ecp5/bram_init_1_2_4.vh))
 $(eval $(call add_gen_share_file,share/ecp5,techlibs/ecp5/bram_init_9_18_36.vh))
@@ -53,3 +54,4 @@ $(eval $(call add_gen_share_file,share/ecp5,techlibs/ecp5/bram_conn_2.vh))
 $(eval $(call add_gen_share_file,share/ecp5,techlibs/ecp5/bram_conn_4.vh))
 $(eval $(call add_gen_share_file,share/ecp5,techlibs/ecp5/bram_conn_9.vh))
 $(eval $(call add_gen_share_file,share/ecp5,techlibs/ecp5/bram_conn_18.vh))
+$(eval $(call add_gen_share_file,share/ecp5,techlibs/ecp5/bram_conn_36.vh))
diff --git a/techlibs/ecp5/bram.txt b/techlibs/ecp5/bram.txt
index f223a42b8..570960489 100644
--- a/techlibs/ecp5/bram.txt
+++ b/techlibs/ecp5/bram.txt
@@ -1,3 +1,18 @@
+bram $__ECP5_PDPW16KD
+  init 1
+
+  abits 9
+  dbits 36
+
+  groups 2
+  ports 1 1
+  wrmode 1 0
+  enable 4 1
+  transp 0 0
+  clocks 2 3
+  clkpol 2 3
+endbram
+
 bram $__ECP5_DP16KD
   init 1
 
@@ -22,6 +37,14 @@ bram $__ECP5_DP16KD
   clkpol 2 3
 endbram
 
+match $__ECP5_PDPW16KD
+  min bits 2048
+  min efficiency 5
+  shuffle_enable B
+  make_transp
+  or_next_if_better
+endmatch
+
 match $__ECP5_DP16KD
   min bits 2048
   min efficiency 5
diff --git a/techlibs/ecp5/brams_connect.py b/techlibs/ecp5/brams_connect.py
index f86dcfcf0..098607c59 100755
--- a/techlibs/ecp5/brams_connect.py
+++ b/techlibs/ecp5/brams_connect.py
@@ -10,6 +10,18 @@ def write_bus_ports(f, ada_bits, adb_bits, dia_bits, dob_bits):
     print("    %s," % ", ".join(dia_conn), file=f)
     print("    %s," % ", ".join(dob_conn), file=f)
 
+def write_bus_ports_pdp(f, adw_bits, adr_bits, di_bits, do_bits, be_bits):
+    adw_conn = [".ADW%d(%s)" % (i, adw_bits[i]) for i in range(len(adw_bits))]
+    adr_conn = [".ADR%d(%s)" % (i, adr_bits[i]) for i in range(len(adr_bits))]
+    di_conn = [".DI%d(%s)" % (i, di_bits[i]) for i in range(len(di_bits))]
+    do_conn = [".DO%d(%s)" % (i, do_bits[i]) for i in range(len(do_bits))]
+    be_conn = [".BE%d(%s)" % (i, be_bits[i]) for i in range(len(be_bits))]
+    print("    %s," % ", ".join(adw_conn), file=f)
+    print("    %s," % ", ".join(adr_conn), file=f)
+    print("    %s," % ", ".join(di_conn), file=f)
+    print("    %s," % ", ".join(do_conn), file=f)
+    print("    %s," % ", ".join(be_conn), file=f)
+
 with open("techlibs/ecp5/bram_conn_1.vh", "w") as f:
     ada_bits = ["A1ADDR[%d]" % i for i in range(14)]
     adb_bits = ["B1ADDR[%d]" % i for i in range(14)]
@@ -44,3 +56,11 @@ with open("techlibs/ecp5/bram_conn_18.vh", "w") as f:
     dia_bits = ["A1DATA[%d]" % i for i in range(18)]
     dob_bits = ["B1DATA[%d]" % i for i in range(18)]
     write_bus_ports(f, ada_bits, adb_bits, dia_bits, dob_bits)
+
+with open("techlibs/ecp5/bram_conn_36.vh", "w") as f:
+    adw_bits = ["A1ADDR[%d]" % i for i in range(9)]
+    adr_bits = ["1'b0", "1'b0", "1'b0", "1'b0", "1'b0"] + ["B1ADDR[%d]" % i for i in range(9)]
+    di_bits = ["A1DATA[%d]" % i for i in range(36)]
+    do_bits = ["B1DATA[%d]" % (i + 18) for i in range(18)] + ["B1DATA[%d]" % i for i in range(18)]
+    be_bits = ["A1EN[%d]" % i for i in range(4)]
+    write_bus_ports_pdp(f, adw_bits, adr_bits, di_bits, do_bits, be_bits)
diff --git a/techlibs/ecp5/brams_map.v b/techlibs/ecp5/brams_map.v
index 0353cbadb..310aedaf2 100644
--- a/techlibs/ecp5/brams_map.v
+++ b/techlibs/ecp5/brams_map.v
@@ -113,3 +113,45 @@ module \$__ECP5_DP16KD (CLK2, CLK3, A1ADDR, A1DATA, A1EN, B1ADDR, B1DATA, B1EN);
 		wire TECHMAP_FAIL = 1'b1;
 	end endgenerate
 endmodule
+
+module \$__ECP5_PDPW16KD (CLK2, CLK3, A1ADDR, A1DATA, A1EN, B1ADDR, B1DATA, B1EN);
+	parameter CFG_ABITS = 9;
+	parameter CFG_DBITS = 36;
+	parameter CFG_ENABLE_A = 4;
+
+	parameter CLKPOL2 = 1;
+	parameter CLKPOL3 = 1;
+	parameter [18431:0] INIT = 18432'bx;
+
+	input CLK2;
+	input CLK3;
+
+	input [CFG_ABITS-1:0] A1ADDR;
+	input [CFG_DBITS-1:0] A1DATA;
+	input [CFG_ENABLE_A-1:0] A1EN;
+
+	input [CFG_ABITS-1:0] B1ADDR;
+	output [CFG_DBITS-1:0] B1DATA;
+	input B1EN;
+
+	localparam CLKWMUX = CLKPOL2 ? "CLKA" : "INV";
+	localparam CLKRMUX = CLKPOL3 ? "CLKB" : "INV";
+
+	localparam WRITEMODE_A = TRANSP2 ? "WRITETHROUGH" : "READBEFOREWRITE";
+
+	PDPW16KD #(
+		`include "bram_init_9_18_36.vh"
+		.DATA_WIDTH_W(36),
+		.DATA_WIDTH_R(36),
+		.CLKWMUX(CLKWMUX),
+		.CLKRMUX(CLKRMUX),
+		.GSR("AUTO")
+	) _TECHMAP_REPLACE_ (
+		`include "bram_conn_36.vh"
+		.CLKW(CLK2), .CLKR(CLK3),
+		.CEW(1'b1),
+		.CER(B1EN), .OCER(1'b1),
+		.RST(1'b0)
+	);
+
+endmodule
diff --git a/techlibs/ecp5/cells_bb.v b/techlibs/ecp5/cells_bb.v
index 8557053b6..0a5046db2 100644
--- a/techlibs/ecp5/cells_bb.v
+++ b/techlibs/ecp5/cells_bb.v
@@ -683,4 +683,98 @@ endmodule
 module SGSR (
 	input GSR, CLK
 );
-endmodule
\ No newline at end of file
+endmodule
+
+
+(* blackbox *)
+module PDPW16KD (
+	input DI35, DI34, DI33, DI32, DI31, DI30, DI29, DI28, DI27, DI26, DI25, DI24, DI23, DI22, DI21, DI20, DI19, DI18,
+	input DI17, DI16, DI15, DI14, DI13, DI12, DI11, DI10, DI9, DI8, DI7, DI6, DI5, DI4, DI3, DI2, DI1, DI0,
+	input ADW8, ADW7, ADW6, ADW5, ADW4, ADW3, ADW2, ADW1, ADW0,
+	input BE3,  BE2,  BE1, BE0, CEW, CLKW, CSW2, CSW1, CSW0,
+	input ADR13, ADR12, ADR11, ADR10, ADR9, ADR8, ADR7, ADR6, ADR5, ADR4, ADR3, ADR2, ADR1, ADR0,
+	input CER, OCER, CLKR, CSR2, CSR1, CSR0, RST,
+	output DO35, DO34, DO33, DO32, DO31, DO30, DO29, DO28, DO27, DO26, DO25, DO24, DO23, DO22, DO21, DO20, DO19, DO18,
+	output DO17, DO16, DO15, DO14, DO13, DO12, DO11, DO10, DO9, DO8, DO7, DO6, DO5, DO4, DO3, DO2, DO1, DO0
+);
+	parameter DATA_WIDTH_W = 36;
+	parameter DATA_WIDTH_R = 36;
+	parameter GSR = "ENABLED";
+
+	parameter REGMODE = "NOREG";
+
+	parameter RESETMODE = "SYNC";
+	parameter ASYNC_RESET_RELEASE = "SYNC";
+
+	parameter CSDECODE_W = "0b000";
+	parameter CSDECODE_R = "0b000";
+
+	parameter INITVAL_00 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+	parameter INITVAL_01 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+	parameter INITVAL_02 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+	parameter INITVAL_03 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+	parameter INITVAL_04 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+	parameter INITVAL_05 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+	parameter INITVAL_06 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+	parameter INITVAL_07 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+	parameter INITVAL_08 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+	parameter INITVAL_09 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+	parameter INITVAL_0A = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+	parameter INITVAL_0B = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+	parameter INITVAL_0C = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+	parameter INITVAL_0D = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+	parameter INITVAL_0E = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+	parameter INITVAL_0F = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+	parameter INITVAL_10 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+	parameter INITVAL_11 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+	parameter INITVAL_12 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+	parameter INITVAL_13 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+	parameter INITVAL_14 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+	parameter INITVAL_15 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+	parameter INITVAL_16 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+	parameter INITVAL_17 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+	parameter INITVAL_18 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+	parameter INITVAL_19 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+	parameter INITVAL_1A = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+	parameter INITVAL_1B = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+	parameter INITVAL_1C = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+	parameter INITVAL_1D = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+	parameter INITVAL_1E = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+	parameter INITVAL_1F = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+	parameter INITVAL_20 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+	parameter INITVAL_21 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+	parameter INITVAL_22 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+	parameter INITVAL_23 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+	parameter INITVAL_24 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+	parameter INITVAL_25 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+	parameter INITVAL_26 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+	parameter INITVAL_27 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+	parameter INITVAL_28 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+	parameter INITVAL_29 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+	parameter INITVAL_2A = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+	parameter INITVAL_2B = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+	parameter INITVAL_2C = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+	parameter INITVAL_2D = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+	parameter INITVAL_2E = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+	parameter INITVAL_2F = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+	parameter INITVAL_30 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+	parameter INITVAL_31 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+	parameter INITVAL_32 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+	parameter INITVAL_33 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+	parameter INITVAL_34 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+	parameter INITVAL_35 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+	parameter INITVAL_36 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+	parameter INITVAL_37 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+	parameter INITVAL_38 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+	parameter INITVAL_39 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+	parameter INITVAL_3A = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+	parameter INITVAL_3B = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+	parameter INITVAL_3C = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+	parameter INITVAL_3D = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+	parameter INITVAL_3E = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+	parameter INITVAL_3F = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+	parameter INIT_DATA = "STATIC";
+	parameter CLKWMUX = "CLKW";
+	parameter CLKRMUX = "CLKR";
+
+endmodule
-- 
cgit v1.2.3


From b424d374db354141afe1f42eead3347e5cb86a04 Mon Sep 17 00:00:00 2001
From: David Shah <dave@ds0.me>
Date: Tue, 1 Oct 2019 14:14:46 +0100
Subject: ecp5: Fix shuffle_enable port

Signed-off-by: David Shah <dave@ds0.me>
---
 techlibs/ecp5/bram.txt | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

(limited to 'techlibs/ecp5')

diff --git a/techlibs/ecp5/bram.txt b/techlibs/ecp5/bram.txt
index 570960489..777ccaa2e 100644
--- a/techlibs/ecp5/bram.txt
+++ b/techlibs/ecp5/bram.txt
@@ -40,7 +40,7 @@ endbram
 match $__ECP5_PDPW16KD
   min bits 2048
   min efficiency 5
-  shuffle_enable B
+  shuffle_enable A
   make_transp
   or_next_if_better
 endmatch
@@ -48,5 +48,5 @@ endmatch
 match $__ECP5_DP16KD
   min bits 2048
   min efficiency 5
-  shuffle_enable B
+  shuffle_enable A
 endmatch
-- 
cgit v1.2.3


From 9fef1df3c1431cff2e097a10a502f77f04986a60 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Fri, 4 Oct 2019 10:48:44 -0700
Subject: Panic over. Model was elsewhere. Re-arrange for consistency

---
 techlibs/ecp5/synth_ecp5.cc | 1 +
 1 file changed, 1 insertion(+)

(limited to 'techlibs/ecp5')

diff --git a/techlibs/ecp5/synth_ecp5.cc b/techlibs/ecp5/synth_ecp5.cc
index 1f5b1cb6b..67d2f483c 100644
--- a/techlibs/ecp5/synth_ecp5.cc
+++ b/techlibs/ecp5/synth_ecp5.cc
@@ -311,6 +311,7 @@ struct SynthEcp5Pass : public ScriptPass
 			run("techmap " + techmap_args);
 
 			if (abc9) {
+				run("read_verilog -icells -lib +/ecp5/abc_model.v");
 				if (nowidelut)
 					run("abc9 -lut +/ecp5/abc_5g_nowide.lut -box +/ecp5/abc_5g.box -W 200");
 				else
-- 
cgit v1.2.3


From aae2b9fd9c8dc915fadacc24962436dd7aedff36 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Fri, 4 Oct 2019 11:04:10 -0700
Subject: Rename abc_* names/attributes to more precisely be abc9_*

---
 techlibs/ecp5/Makefile.inc       | 12 +++++------
 techlibs/ecp5/abc9_5g.box        | 43 ++++++++++++++++++++++++++++++++++++++++
 techlibs/ecp5/abc9_5g.lut        | 25 +++++++++++++++++++++++
 techlibs/ecp5/abc9_5g_nowide.lut | 12 +++++++++++
 techlibs/ecp5/abc9_map.v         | 24 ++++++++++++++++++++++
 techlibs/ecp5/abc9_model.v       |  5 +++++
 techlibs/ecp5/abc9_unmap.v       |  5 +++++
 techlibs/ecp5/abc_5g.box         | 43 ----------------------------------------
 techlibs/ecp5/abc_5g.lut         | 25 -----------------------
 techlibs/ecp5/abc_5g_nowide.lut  | 12 -----------
 techlibs/ecp5/abc_map.v          | 24 ----------------------
 techlibs/ecp5/abc_model.v        |  5 -----
 techlibs/ecp5/abc_unmap.v        |  5 -----
 techlibs/ecp5/cells_sim.v        | 12 +++++------
 techlibs/ecp5/synth_ecp5.cc      | 10 +++++-----
 15 files changed, 131 insertions(+), 131 deletions(-)
 create mode 100644 techlibs/ecp5/abc9_5g.box
 create mode 100644 techlibs/ecp5/abc9_5g.lut
 create mode 100644 techlibs/ecp5/abc9_5g_nowide.lut
 create mode 100644 techlibs/ecp5/abc9_map.v
 create mode 100644 techlibs/ecp5/abc9_model.v
 create mode 100644 techlibs/ecp5/abc9_unmap.v
 delete mode 100644 techlibs/ecp5/abc_5g.box
 delete mode 100644 techlibs/ecp5/abc_5g.lut
 delete mode 100644 techlibs/ecp5/abc_5g_nowide.lut
 delete mode 100644 techlibs/ecp5/abc_map.v
 delete mode 100644 techlibs/ecp5/abc_model.v
 delete mode 100644 techlibs/ecp5/abc_unmap.v

(limited to 'techlibs/ecp5')

diff --git a/techlibs/ecp5/Makefile.inc b/techlibs/ecp5/Makefile.inc
index b03da164c..5832d07ee 100644
--- a/techlibs/ecp5/Makefile.inc
+++ b/techlibs/ecp5/Makefile.inc
@@ -15,12 +15,12 @@ $(eval $(call add_share_file,share/ecp5,techlibs/ecp5/arith_map.v))
 $(eval $(call add_share_file,share/ecp5,techlibs/ecp5/latches_map.v))
 $(eval $(call add_share_file,share/ecp5,techlibs/ecp5/dsp_map.v))
 
-$(eval $(call add_share_file,share/ecp5,techlibs/ecp5/abc_map.v))
-$(eval $(call add_share_file,share/ecp5,techlibs/ecp5/abc_unmap.v))
-$(eval $(call add_share_file,share/ecp5,techlibs/ecp5/abc_model.v))
-$(eval $(call add_share_file,share/ecp5,techlibs/ecp5/abc_5g.box))
-$(eval $(call add_share_file,share/ecp5,techlibs/ecp5/abc_5g.lut))
-$(eval $(call add_share_file,share/ecp5,techlibs/ecp5/abc_5g_nowide.lut))
+$(eval $(call add_share_file,share/ecp5,techlibs/ecp5/abc9_map.v))
+$(eval $(call add_share_file,share/ecp5,techlibs/ecp5/abc9_unmap.v))
+$(eval $(call add_share_file,share/ecp5,techlibs/ecp5/abc9_model.v))
+$(eval $(call add_share_file,share/ecp5,techlibs/ecp5/abc9_5g.box))
+$(eval $(call add_share_file,share/ecp5,techlibs/ecp5/abc9_5g.lut))
+$(eval $(call add_share_file,share/ecp5,techlibs/ecp5/abc9_5g_nowide.lut))
 
 EXTRA_OBJS += techlibs/ecp5/brams_init.mk techlibs/ecp5/brams_connect.mk
 .SECONDARY: techlibs/ecp5/brams_init.mk techlibs/ecp5/brams_connect.mk
diff --git a/techlibs/ecp5/abc9_5g.box b/techlibs/ecp5/abc9_5g.box
new file mode 100644
index 000000000..2bc945a54
--- /dev/null
+++ b/techlibs/ecp5/abc9_5g.box
@@ -0,0 +1,43 @@
+# NB: Inputs/Outputs must be ordered alphabetically
+#     (with exceptions for carry in/out)
+
+# Box 1 : CCU2C (2xCARRY + 2xLUT4)
+# Outputs: S0, S1, COUT
+#   (NB: carry chain input/output must be last
+#        input/output and bus has been moved
+#        there overriding the otherwise
+#        alphabetical ordering)
+# name  ID   w/b   ins    outs
+CCU2C   1      1   9      3
+
+#A0   A1   B0   B1   C0    C1  D0   D1   CIN
+379  -    379  -    275   -    141  -    257
+630  379  630  379  526   275  392  141  273
+516  516  516  516  412   412  278  278  43
+
+# Box 2 : TRELLIS_DPR16X4_COMB (16x4 dist ram)
+# Outputs: DO0, DO1, DO2, DO3
+# name               ID  w/b   ins   outs
+$__ABC9_DPR16X4_COMB  2     0   8    4
+
+#A0   A1   A2   A3   RAD0   RAD1   RAD2   RAD3
+0     0    0    0    141    379    275    379
+0     0    0    0    141    379    275    379
+0     0    0    0    141    379    275    379
+0     0    0    0    141    379    275    379
+
+# Box 3 : PFUMX (MUX2)
+# Outputs: Z
+# name  ID   w/b   ins    outs
+PFUMX   3    1     3      1
+
+#ALUT  BLUT  C0
+98     98    151
+
+# Box 4 : L6MUX21 (MUX2)
+# Outputs: Z
+# name   ID   w/b   ins    outs
+L6MUX21  4    1     3      1
+
+#D0    D1    SD
+140    141   148
diff --git a/techlibs/ecp5/abc9_5g.lut b/techlibs/ecp5/abc9_5g.lut
new file mode 100644
index 000000000..e8aa9b35d
--- /dev/null
+++ b/techlibs/ecp5/abc9_5g.lut
@@ -0,0 +1,25 @@
+# ECP5-5G LUT library for ABC
+# Note that ECP5 architecture assigns difference
+# in LUT input delay to interconnect, so this is
+# considered too
+
+
+# Simple LUTs
+#  area  D    C    B    A
+1  1     141
+2  1     141  275
+3  1     141  275  379
+4  1     141  275  379  379
+
+# LUT5 = 2x LUT4 + PFUMX
+#  area  M0   D    C    B    A
+5  2     151  239  373  477  477
+
+# LUT6 = 2x LUT5 + MUX2
+#  area  M1   M0   D    C    B    A
+6  4     148  292  380  514  618  618
+
+# LUT7 = 2x LUT6 + MUX2
+#  area  M2   M1   M0   D    C    B    A
+7  8     148  289  433  521  655  759  759
+
diff --git a/techlibs/ecp5/abc9_5g_nowide.lut b/techlibs/ecp5/abc9_5g_nowide.lut
new file mode 100644
index 000000000..60352d892
--- /dev/null
+++ b/techlibs/ecp5/abc9_5g_nowide.lut
@@ -0,0 +1,12 @@
+# ECP5-5G LUT library for ABC
+# Note that ECP5 architecture assigns difference
+# in LUT input delay to interconnect, so this is
+# considered too
+
+
+# Simple LUTs
+#  area  D    C    B    A
+1  1     141
+2  1     141  275
+3  1     141  275  379
+4  1     141  275  379  379
diff --git a/techlibs/ecp5/abc9_map.v b/techlibs/ecp5/abc9_map.v
new file mode 100644
index 000000000..d8d70f9f6
--- /dev/null
+++ b/techlibs/ecp5/abc9_map.v
@@ -0,0 +1,24 @@
+// ---------------------------------------
+
+module TRELLIS_DPR16X4 (
+	input  [3:0] DI,
+	input  [3:0] WAD,
+	input        WRE,
+	input        WCK,
+	input  [3:0] RAD,
+	output [3:0] DO
+);
+	parameter WCKMUX = "WCK";
+	parameter WREMUX = "WRE";
+	parameter [63:0] INITVAL = 64'h0000000000000000;
+    wire [3:0] \$DO ;
+
+    TRELLIS_DPR16X4 #(
+      .WCKMUX(WCKMUX), .WREMUX(WREMUX), .INITVAL(INITVAL)
+    ) _TECHMAP_REPLACE_ (
+      .DI(DI), .WAD(WAD), .WRE(WRE), .WCK(WCK),
+      .RAD(RAD), .DO(\$DO )
+    );
+
+    \$__ABC9_DPR16X4_COMB do (.A(\$DO ), .S(RAD), .Y(DO));
+endmodule
diff --git a/techlibs/ecp5/abc9_model.v b/techlibs/ecp5/abc9_model.v
new file mode 100644
index 000000000..1dc8b5617
--- /dev/null
+++ b/techlibs/ecp5/abc9_model.v
@@ -0,0 +1,5 @@
+// ---------------------------------------
+
+(* abc9_box_id=2 *)
+module \$__ABC9_DPR16X4_COMB (input [3:0] A, S, output [3:0] Y);
+endmodule
diff --git a/techlibs/ecp5/abc9_unmap.v b/techlibs/ecp5/abc9_unmap.v
new file mode 100644
index 000000000..9ae143c46
--- /dev/null
+++ b/techlibs/ecp5/abc9_unmap.v
@@ -0,0 +1,5 @@
+// ---------------------------------------
+
+module \$__ABC9_DPR16X4_COMB (input [3:0] A, S, output [3:0] Y);
+    assign Y = A;
+endmodule
diff --git a/techlibs/ecp5/abc_5g.box b/techlibs/ecp5/abc_5g.box
deleted file mode 100644
index a336b4a85..000000000
--- a/techlibs/ecp5/abc_5g.box
+++ /dev/null
@@ -1,43 +0,0 @@
-# NB: Inputs/Outputs must be ordered alphabetically
-#     (with exceptions for carry in/out)
-
-# Box 1 : CCU2C (2xCARRY + 2xLUT4)
-# Outputs: S0, S1, COUT
-#   (NB: carry chain input/output must be last
-#        input/output and bus has been moved
-#        there overriding the otherwise
-#        alphabetical ordering)
-# name  ID   w/b   ins    outs
-CCU2C   1      1   9      3
-
-#A0   A1   B0   B1   C0    C1  D0   D1   CIN
-379  -    379  -    275   -    141  -    257
-630  379  630  379  526   275  392  141  273
-516  516  516  516  412   412  278  278  43
-
-# Box 2 : TRELLIS_DPR16X4_COMB (16x4 dist ram)
-# Outputs: DO0, DO1, DO2, DO3
-# name               ID  w/b   ins   outs
-$__ABC_DPR16X4_COMB  2     0   8    4
-
-#A0   A1   A2   A3   RAD0   RAD1   RAD2   RAD3
-0     0    0    0    141    379    275    379
-0     0    0    0    141    379    275    379
-0     0    0    0    141    379    275    379
-0     0    0    0    141    379    275    379
-
-# Box 3 : PFUMX (MUX2)
-# Outputs: Z
-# name  ID   w/b   ins    outs
-PFUMX   3    1     3      1
-
-#ALUT  BLUT  C0
-98     98    151
-
-# Box 4 : L6MUX21 (MUX2)
-# Outputs: Z
-# name   ID   w/b   ins    outs
-L6MUX21  4    1     3      1
-
-#D0    D1    SD
-140    141   148
diff --git a/techlibs/ecp5/abc_5g.lut b/techlibs/ecp5/abc_5g.lut
deleted file mode 100644
index e8aa9b35d..000000000
--- a/techlibs/ecp5/abc_5g.lut
+++ /dev/null
@@ -1,25 +0,0 @@
-# ECP5-5G LUT library for ABC
-# Note that ECP5 architecture assigns difference
-# in LUT input delay to interconnect, so this is
-# considered too
-
-
-# Simple LUTs
-#  area  D    C    B    A
-1  1     141
-2  1     141  275
-3  1     141  275  379
-4  1     141  275  379  379
-
-# LUT5 = 2x LUT4 + PFUMX
-#  area  M0   D    C    B    A
-5  2     151  239  373  477  477
-
-# LUT6 = 2x LUT5 + MUX2
-#  area  M1   M0   D    C    B    A
-6  4     148  292  380  514  618  618
-
-# LUT7 = 2x LUT6 + MUX2
-#  area  M2   M1   M0   D    C    B    A
-7  8     148  289  433  521  655  759  759
-
diff --git a/techlibs/ecp5/abc_5g_nowide.lut b/techlibs/ecp5/abc_5g_nowide.lut
deleted file mode 100644
index 60352d892..000000000
--- a/techlibs/ecp5/abc_5g_nowide.lut
+++ /dev/null
@@ -1,12 +0,0 @@
-# ECP5-5G LUT library for ABC
-# Note that ECP5 architecture assigns difference
-# in LUT input delay to interconnect, so this is
-# considered too
-
-
-# Simple LUTs
-#  area  D    C    B    A
-1  1     141
-2  1     141  275
-3  1     141  275  379
-4  1     141  275  379  379
diff --git a/techlibs/ecp5/abc_map.v b/techlibs/ecp5/abc_map.v
deleted file mode 100644
index ffd25f06d..000000000
--- a/techlibs/ecp5/abc_map.v
+++ /dev/null
@@ -1,24 +0,0 @@
-// ---------------------------------------
-
-module TRELLIS_DPR16X4 (
-	input  [3:0] DI,
-	input  [3:0] WAD,
-	input        WRE,
-	input        WCK,
-	input  [3:0] RAD,
-	output [3:0] DO
-);
-	parameter WCKMUX = "WCK";
-	parameter WREMUX = "WRE";
-	parameter [63:0] INITVAL = 64'h0000000000000000;
-    wire [3:0] \$DO ;
-
-    TRELLIS_DPR16X4 #(
-      .WCKMUX(WCKMUX), .WREMUX(WREMUX), .INITVAL(INITVAL)
-    ) _TECHMAP_REPLACE_ (
-      .DI(DI), .WAD(WAD), .WRE(WRE), .WCK(WCK),
-      .RAD(RAD), .DO(\$DO )
-    );
-
-    \$__ABC_DPR16X4_COMB do (.A(\$DO ), .S(RAD), .Y(DO));
-endmodule
diff --git a/techlibs/ecp5/abc_model.v b/techlibs/ecp5/abc_model.v
deleted file mode 100644
index 56a733b75..000000000
--- a/techlibs/ecp5/abc_model.v
+++ /dev/null
@@ -1,5 +0,0 @@
-// ---------------------------------------
-
-(* abc_box_id=2 *)
-module \$__ABC_DPR16X4_COMB (input [3:0] A, S, output [3:0] Y);
-endmodule
diff --git a/techlibs/ecp5/abc_unmap.v b/techlibs/ecp5/abc_unmap.v
deleted file mode 100644
index d43cdd93f..000000000
--- a/techlibs/ecp5/abc_unmap.v
+++ /dev/null
@@ -1,5 +0,0 @@
-// ---------------------------------------
-
-module \$__ABC_DPR16X4_COMB (input [3:0] A, S, output [3:0] Y);
-    assign Y = A;
-endmodule
diff --git a/techlibs/ecp5/cells_sim.v b/techlibs/ecp5/cells_sim.v
index db77dc127..f467218cc 100644
--- a/techlibs/ecp5/cells_sim.v
+++ b/techlibs/ecp5/cells_sim.v
@@ -9,19 +9,19 @@ module LUT4(input A, B, C, D, output Z);
 endmodule
 
 // ---------------------------------------
-(* abc_box_id=4, lib_whitebox *)
+(* abc9_box_id=4, lib_whitebox *)
 module L6MUX21 (input D0, D1, SD, output Z);
 	assign Z = SD ? D1 : D0;
 endmodule
 
 // ---------------------------------------
-(* abc_box_id=1, lib_whitebox *)
+(* abc9_box_id=1, lib_whitebox *)
 module CCU2C(
-	(* abc_carry *)
+	(* abc9_carry *)
 	input  CIN,
 	input  A0, B0, C0, D0, A1, B1, C1, D1,
 	output S0, S1,
-	(* abc_carry *)
+	(* abc9_carry *)
 	output COUT
 );
 	parameter [15:0] INIT0 = 16'h0000;
@@ -103,7 +103,7 @@ module TRELLIS_RAM16X2 (
 endmodule
 
 // ---------------------------------------
-(* abc_box_id=3, lib_whitebox *)
+(* abc9_box_id=3, lib_whitebox *)
 module PFUMX (input ALUT, BLUT, C0, output Z);
 	assign Z = C0 ? ALUT : BLUT;
 endmodule
@@ -115,7 +115,7 @@ module TRELLIS_DPR16X4 (
 	input        WRE,
 	input        WCK,
 	input  [3:0] RAD,
-	/* (* abc_arrival=<TODO> *) */
+	/* (* abc9_arrival=<TODO> *) */
 	output [3:0] DO
 );
 	parameter WCKMUX = "WCK";
diff --git a/techlibs/ecp5/synth_ecp5.cc b/techlibs/ecp5/synth_ecp5.cc
index 67d2f483c..80aa1dbc5 100644
--- a/techlibs/ecp5/synth_ecp5.cc
+++ b/techlibs/ecp5/synth_ecp5.cc
@@ -307,16 +307,16 @@ struct SynthEcp5Pass : public ScriptPass
 			}
 			std::string techmap_args = "-map +/ecp5/latches_map.v";
 			if (abc9)
-				techmap_args += " -map +/ecp5/abc_map.v -max_iter 1";
+				techmap_args += " -map +/ecp5/abc9_map.v -max_iter 1";
 			run("techmap " + techmap_args);
 
 			if (abc9) {
-				run("read_verilog -icells -lib +/ecp5/abc_model.v");
+				run("read_verilog -icells -lib +/ecp5/abc9_model.v");
 				if (nowidelut)
-					run("abc9 -lut +/ecp5/abc_5g_nowide.lut -box +/ecp5/abc_5g.box -W 200");
+					run("abc9 -lut +/ecp5/abc9_5g_nowide.lut -box +/ecp5/abc9_5g.box -W 200");
 				else
-					run("abc9 -lut +/ecp5/abc_5g.lut -box +/ecp5/abc_5g.box -W 200");
-				run("techmap -map +/ecp5/abc_unmap.v");
+					run("abc9 -lut +/ecp5/abc9_5g.lut -box +/ecp5/abc9_5g.box -W 200");
+				run("techmap -map +/ecp5/abc9_unmap.v");
 			} else {
 				if (nowidelut)
 					run("abc -lut 4 -dress");
-- 
cgit v1.2.3


From 3b44e80d4babb57f4b7c5325f666f0731a4d878b Mon Sep 17 00:00:00 2001
From: David Shah <dave@ds0.me>
Date: Thu, 10 Oct 2019 15:55:16 +0100
Subject: ecp5: Set syn_useioff on IO FFs to enable packing

Signed-off-by: David Shah <dave@ds0.me>
---
 techlibs/ecp5/cells_ff.vh | 16 ++++++++--------
 1 file changed, 8 insertions(+), 8 deletions(-)

(limited to 'techlibs/ecp5')

diff --git a/techlibs/ecp5/cells_ff.vh b/techlibs/ecp5/cells_ff.vh
index 0c9689ebd..501c1b3b2 100644
--- a/techlibs/ecp5/cells_ff.vh
+++ b/techlibs/ecp5/cells_ff.vh
@@ -23,15 +23,15 @@ module FD1S3JX(input PD, D,     CK, output Q); parameter GSR = "ENABLED"; TRELLI
 // module FL1S3AY(); endmodule
 
 // Diamond I/O registers
-module IFS1P3BX(input PD, D, SP, SCLK, output Q); parameter GSR = "ENABLED"; TRELLIS_FF #(.GSR(GSR), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("SET"),   .SRMODE("ASYNC"))       _TECHMAP_REPLACE_ (.CLK(SCLK), .LSR(PD), .CE(SP), .DI(D), .Q(Q)); endmodule
-module IFS1P3DX(input CD, D, SP, SCLK, output Q); parameter GSR = "ENABLED"; TRELLIS_FF #(.GSR(GSR), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("ASYNC"))       _TECHMAP_REPLACE_ (.CLK(SCLK), .LSR(CD), .CE(SP), .DI(D), .Q(Q)); endmodule
-module IFS1P3IX(input CD, D, SP, SCLK, output Q); parameter GSR = "ENABLED"; TRELLIS_FF #(.GSR(GSR), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("LSR_OVER_CE")) _TECHMAP_REPLACE_ (.CLK(SCLK), .LSR(CD), .CE(SP), .DI(D), .Q(Q)); endmodule
-module IFS1P3JX(input PD, D, SP, SCLK, output Q); parameter GSR = "ENABLED"; TRELLIS_FF #(.GSR(GSR), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("SET"),   .SRMODE("LSR_OVER_CE")) _TECHMAP_REPLACE_ (.CLK(SCLK), .LSR(PD), .CE(SP), .DI(D), .Q(Q)); endmodule
+module IFS1P3BX(input PD, D, SP, SCLK, output Q); parameter GSR = "ENABLED"; (* syn_useioff, ioff_dir="input" *) TRELLIS_FF #(.GSR(GSR), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("SET"),   .SRMODE("ASYNC"))       _TECHMAP_REPLACE_ (.CLK(SCLK), .LSR(PD), .CE(SP), .DI(D), .Q(Q)); endmodule
+module IFS1P3DX(input CD, D, SP, SCLK, output Q); parameter GSR = "ENABLED"; (* syn_useioff, ioff_dir="input" *) TRELLIS_FF #(.GSR(GSR), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("ASYNC"))       _TECHMAP_REPLACE_ (.CLK(SCLK), .LSR(CD), .CE(SP), .DI(D), .Q(Q)); endmodule
+module IFS1P3IX(input CD, D, SP, SCLK, output Q); parameter GSR = "ENABLED"; (* syn_useioff, ioff_dir="input" *) TRELLIS_FF #(.GSR(GSR), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("LSR_OVER_CE")) _TECHMAP_REPLACE_ (.CLK(SCLK), .LSR(CD), .CE(SP), .DI(D), .Q(Q)); endmodule
+module IFS1P3JX(input PD, D, SP, SCLK, output Q); parameter GSR = "ENABLED"; (* syn_useioff, ioff_dir="input" *) TRELLIS_FF #(.GSR(GSR), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("SET"),   .SRMODE("LSR_OVER_CE")) _TECHMAP_REPLACE_ (.CLK(SCLK), .LSR(PD), .CE(SP), .DI(D), .Q(Q)); endmodule
 
-module OFS1P3BX(input PD, D, SP, SCLK, output Q); parameter GSR = "ENABLED"; TRELLIS_FF #(.GSR(GSR), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("SET"),   .SRMODE("ASYNC"))       _TECHMAP_REPLACE_ (.CLK(SCLK), .LSR(PD), .CE(SP), .DI(D), .Q(Q)); endmodule
-module OFS1P3DX(input CD, D, SP, SCLK, output Q); parameter GSR = "ENABLED"; TRELLIS_FF #(.GSR(GSR), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("ASYNC"))       _TECHMAP_REPLACE_ (.CLK(SCLK), .LSR(CD), .CE(SP), .DI(D), .Q(Q)); endmodule
-module OFS1P3IX(input CD, D, SP, SCLK, output Q); parameter GSR = "ENABLED"; TRELLIS_FF #(.GSR(GSR), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("LSR_OVER_CE")) _TECHMAP_REPLACE_ (.CLK(SCLK), .LSR(CD), .CE(SP), .DI(D), .Q(Q)); endmodule
-module OFS1P3JX(input PD, D, SP, SCLK, output Q); parameter GSR = "ENABLED"; TRELLIS_FF #(.GSR(GSR), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("SET"),   .SRMODE("LSR_OVER_CE")) _TECHMAP_REPLACE_ (.CLK(SCLK), .LSR(PD), .CE(SP), .DI(D), .Q(Q)); endmodule
+module OFS1P3BX(input PD, D, SP, SCLK, output Q); parameter GSR = "ENABLED"; (* syn_useioff, ioff_dir="output" *) TRELLIS_FF #(.GSR(GSR), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("SET"),   .SRMODE("ASYNC"))       _TECHMAP_REPLACE_ (.CLK(SCLK), .LSR(PD), .CE(SP), .DI(D), .Q(Q)); endmodule
+module OFS1P3DX(input CD, D, SP, SCLK, output Q); parameter GSR = "ENABLED"; (* syn_useioff, ioff_dir="output" *) TRELLIS_FF #(.GSR(GSR), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("ASYNC"))       _TECHMAP_REPLACE_ (.CLK(SCLK), .LSR(CD), .CE(SP), .DI(D), .Q(Q)); endmodule
+module OFS1P3IX(input CD, D, SP, SCLK, output Q); parameter GSR = "ENABLED"; (* syn_useioff, ioff_dir="output" *) TRELLIS_FF #(.GSR(GSR), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("LSR_OVER_CE")) _TECHMAP_REPLACE_ (.CLK(SCLK), .LSR(CD), .CE(SP), .DI(D), .Q(Q)); endmodule
+module OFS1P3JX(input PD, D, SP, SCLK, output Q); parameter GSR = "ENABLED"; (* syn_useioff, ioff_dir="output" *) TRELLIS_FF #(.GSR(GSR), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("SET"),   .SRMODE("LSR_OVER_CE")) _TECHMAP_REPLACE_ (.CLK(SCLK), .LSR(PD), .CE(SP), .DI(D), .Q(Q)); endmodule
 
 // TODO: Diamond I/O latches
 // module IFS1S1B(input PD, D, SCLK, output Q); endmodule
-- 
cgit v1.2.3


From 7b1a6706d801773ec44d00bda0fd292c50fe39b7 Mon Sep 17 00:00:00 2001
From: David Shah <dave@ds0.me>
Date: Thu, 10 Oct 2019 15:58:31 +0100
Subject: ecp5: Add attrmvcp to copy syn_useioff to driving FF

Signed-off-by: David Shah <dave@ds0.me>
---
 techlibs/ecp5/synth_ecp5.cc | 1 +
 1 file changed, 1 insertion(+)

(limited to 'techlibs/ecp5')

diff --git a/techlibs/ecp5/synth_ecp5.cc b/techlibs/ecp5/synth_ecp5.cc
index 80aa1dbc5..a79dee31f 100644
--- a/techlibs/ecp5/synth_ecp5.cc
+++ b/techlibs/ecp5/synth_ecp5.cc
@@ -297,6 +297,7 @@ struct SynthEcp5Pass : public ScriptPass
 			run("simplemap");
 			run("ecp5_ffinit");
 			run("ecp5_gsr");
+			run("attrmvcp -copy -attr syn_useioff");
 			run("opt_clean");
 		}
 
-- 
cgit v1.2.3


From e1d4e683b42bb1b75acb4054a94610cdc9fec0e7 Mon Sep 17 00:00:00 2001
From: David Shah <dave@ds0.me>
Date: Fri, 11 Oct 2019 14:50:33 +0100
Subject: ecp5: Add ECLKBRIDGECS blackbox

Signed-off-by: David Shah <dave@ds0.me>
---
 techlibs/ecp5/cells_bb.v | 7 +++++++
 1 file changed, 7 insertions(+)

(limited to 'techlibs/ecp5')

diff --git a/techlibs/ecp5/cells_bb.v b/techlibs/ecp5/cells_bb.v
index 0a5046db2..ae124e7a3 100644
--- a/techlibs/ecp5/cells_bb.v
+++ b/techlibs/ecp5/cells_bb.v
@@ -333,6 +333,13 @@ module ECLKSYNCB(
 );
 endmodule
 
+(* blackbox *)
+module ECLKBRIDGECS(
+	input CLK0, CLK1, SEL,
+	output ECSOUT
+);
+endmodule
+
 (* blackbox *)
 module DCCA(
 	input CLKI, CE,
-- 
cgit v1.2.3


From 82f60ba938749ab20694f9070f1046e393f16f3c Mon Sep 17 00:00:00 2001
From: Sean Cross <sean@xobs.io>
Date: Sat, 19 Oct 2019 14:04:52 +0800
Subject: Makefile: don't assume python is called `python3`

On some architectures, notably on Windows, the official name for the
Python binary from python.org is `python`.  The build system assumes
that python is called `python3`, which breaks under this architecture.

There is already infrastructure in place to determine the name of the
Python binary when building PYOSYS.  Since Python is now always required
to build Yosys, enable this check universally which sets the
`PYTHON_EXECUTABLE` variable.

Then, reuse this variable in other Makefiles as necessary, rather than
hardcoding `python3` everywhere.

Signed-off-by: Sean Cross <sean@xobs.io>
---
 techlibs/ecp5/Makefile.inc | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

(limited to 'techlibs/ecp5')

diff --git a/techlibs/ecp5/Makefile.inc b/techlibs/ecp5/Makefile.inc
index 5832d07ee..46463f510 100644
--- a/techlibs/ecp5/Makefile.inc
+++ b/techlibs/ecp5/Makefile.inc
@@ -27,12 +27,12 @@ EXTRA_OBJS += techlibs/ecp5/brams_init.mk techlibs/ecp5/brams_connect.mk
 
 techlibs/ecp5/brams_init.mk: techlibs/ecp5/brams_init.py
 	$(Q) mkdir -p techlibs/ecp5
-	$(P) python3 $<
+	$(P) $(PYTHON_EXECUTABLE) $<
 	$(Q) touch $@
 
 techlibs/ecp5/brams_connect.mk: techlibs/ecp5/brams_connect.py
 	$(Q) mkdir -p techlibs/ecp5
-	$(P) python3 $<
+	$(P) $(PYTHON_EXECUTABLE) $<
 	$(Q) touch $@
 
 
-- 
cgit v1.2.3


From fa989e59e5a37d804d8a82050e022b8f4b7070d8 Mon Sep 17 00:00:00 2001
From: David Shah <dave@ds0.me>
Date: Sun, 20 Oct 2019 10:30:41 +0100
Subject: ecp5: Pass -nomfs to abc9

Fixes #1459

Signed-off-by: David Shah <dave@ds0.me>
---
 techlibs/ecp5/synth_ecp5.cc | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

(limited to 'techlibs/ecp5')

diff --git a/techlibs/ecp5/synth_ecp5.cc b/techlibs/ecp5/synth_ecp5.cc
index a79dee31f..800a8ce22 100644
--- a/techlibs/ecp5/synth_ecp5.cc
+++ b/techlibs/ecp5/synth_ecp5.cc
@@ -314,9 +314,9 @@ struct SynthEcp5Pass : public ScriptPass
 			if (abc9) {
 				run("read_verilog -icells -lib +/ecp5/abc9_model.v");
 				if (nowidelut)
-					run("abc9 -lut +/ecp5/abc9_5g_nowide.lut -box +/ecp5/abc9_5g.box -W 200");
+					run("abc9 -lut +/ecp5/abc9_5g_nowide.lut -box +/ecp5/abc9_5g.box -W 200 -nomfs");
 				else
-					run("abc9 -lut +/ecp5/abc9_5g.lut -box +/ecp5/abc9_5g.box -W 200");
+					run("abc9 -lut +/ecp5/abc9_5g.lut -box +/ecp5/abc9_5g.box -W 200 -nomfs");
 				run("techmap -map +/ecp5/abc9_unmap.v");
 			} else {
 				if (nowidelut)
-- 
cgit v1.2.3