From 3b44e80d4babb57f4b7c5325f666f0731a4d878b Mon Sep 17 00:00:00 2001 From: David Shah Date: Thu, 10 Oct 2019 15:55:16 +0100 Subject: ecp5: Set syn_useioff on IO FFs to enable packing Signed-off-by: David Shah --- techlibs/ecp5/cells_ff.vh | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) (limited to 'techlibs/ecp5') diff --git a/techlibs/ecp5/cells_ff.vh b/techlibs/ecp5/cells_ff.vh index 0c9689ebd..501c1b3b2 100644 --- a/techlibs/ecp5/cells_ff.vh +++ b/techlibs/ecp5/cells_ff.vh @@ -23,15 +23,15 @@ module FD1S3JX(input PD, D, CK, output Q); parameter GSR = "ENABLED"; TRELLI // module FL1S3AY(); endmodule // Diamond I/O registers -module IFS1P3BX(input PD, D, SP, SCLK, output Q); parameter GSR = "ENABLED"; TRELLIS_FF #(.GSR(GSR), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("ASYNC")) _TECHMAP_REPLACE_ (.CLK(SCLK), .LSR(PD), .CE(SP), .DI(D), .Q(Q)); endmodule -module IFS1P3DX(input CD, D, SP, SCLK, output Q); parameter GSR = "ENABLED"; TRELLIS_FF #(.GSR(GSR), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("ASYNC")) _TECHMAP_REPLACE_ (.CLK(SCLK), .LSR(CD), .CE(SP), .DI(D), .Q(Q)); endmodule -module IFS1P3IX(input CD, D, SP, SCLK, output Q); parameter GSR = "ENABLED"; TRELLIS_FF #(.GSR(GSR), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("LSR_OVER_CE")) _TECHMAP_REPLACE_ (.CLK(SCLK), .LSR(CD), .CE(SP), .DI(D), .Q(Q)); endmodule -module IFS1P3JX(input PD, D, SP, SCLK, output Q); parameter GSR = "ENABLED"; TRELLIS_FF #(.GSR(GSR), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("LSR_OVER_CE")) _TECHMAP_REPLACE_ (.CLK(SCLK), .LSR(PD), .CE(SP), .DI(D), .Q(Q)); endmodule +module IFS1P3BX(input PD, D, SP, SCLK, output Q); parameter GSR = "ENABLED"; (* syn_useioff, ioff_dir="input" *) TRELLIS_FF #(.GSR(GSR), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("ASYNC")) _TECHMAP_REPLACE_ (.CLK(SCLK), .LSR(PD), .CE(SP), .DI(D), .Q(Q)); endmodule +module IFS1P3DX(input CD, D, SP, SCLK, output Q); parameter GSR = "ENABLED"; (* syn_useioff, ioff_dir="input" *) TRELLIS_FF #(.GSR(GSR), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("ASYNC")) _TECHMAP_REPLACE_ (.CLK(SCLK), .LSR(CD), .CE(SP), .DI(D), .Q(Q)); endmodule +module IFS1P3IX(input CD, D, SP, SCLK, output Q); parameter GSR = "ENABLED"; (* syn_useioff, ioff_dir="input" *) TRELLIS_FF #(.GSR(GSR), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("LSR_OVER_CE")) _TECHMAP_REPLACE_ (.CLK(SCLK), .LSR(CD), .CE(SP), .DI(D), .Q(Q)); endmodule +module IFS1P3JX(input PD, D, SP, SCLK, output Q); parameter GSR = "ENABLED"; (* syn_useioff, ioff_dir="input" *) TRELLIS_FF #(.GSR(GSR), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("LSR_OVER_CE")) _TECHMAP_REPLACE_ (.CLK(SCLK), .LSR(PD), .CE(SP), .DI(D), .Q(Q)); endmodule -module OFS1P3BX(input PD, D, SP, SCLK, output Q); parameter GSR = "ENABLED"; TRELLIS_FF #(.GSR(GSR), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("ASYNC")) _TECHMAP_REPLACE_ (.CLK(SCLK), .LSR(PD), .CE(SP), .DI(D), .Q(Q)); endmodule -module OFS1P3DX(input CD, D, SP, SCLK, output Q); parameter GSR = "ENABLED"; TRELLIS_FF #(.GSR(GSR), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("ASYNC")) _TECHMAP_REPLACE_ (.CLK(SCLK), .LSR(CD), .CE(SP), .DI(D), .Q(Q)); endmodule -module OFS1P3IX(input CD, D, SP, SCLK, output Q); parameter GSR = "ENABLED"; TRELLIS_FF #(.GSR(GSR), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("LSR_OVER_CE")) _TECHMAP_REPLACE_ (.CLK(SCLK), .LSR(CD), .CE(SP), .DI(D), .Q(Q)); endmodule -module OFS1P3JX(input PD, D, SP, SCLK, output Q); parameter GSR = "ENABLED"; TRELLIS_FF #(.GSR(GSR), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("LSR_OVER_CE")) _TECHMAP_REPLACE_ (.CLK(SCLK), .LSR(PD), .CE(SP), .DI(D), .Q(Q)); endmodule +module OFS1P3BX(input PD, D, SP, SCLK, output Q); parameter GSR = "ENABLED"; (* syn_useioff, ioff_dir="output" *) TRELLIS_FF #(.GSR(GSR), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("ASYNC")) _TECHMAP_REPLACE_ (.CLK(SCLK), .LSR(PD), .CE(SP), .DI(D), .Q(Q)); endmodule +module OFS1P3DX(input CD, D, SP, SCLK, output Q); parameter GSR = "ENABLED"; (* syn_useioff, ioff_dir="output" *) TRELLIS_FF #(.GSR(GSR), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("ASYNC")) _TECHMAP_REPLACE_ (.CLK(SCLK), .LSR(CD), .CE(SP), .DI(D), .Q(Q)); endmodule +module OFS1P3IX(input CD, D, SP, SCLK, output Q); parameter GSR = "ENABLED"; (* syn_useioff, ioff_dir="output" *) TRELLIS_FF #(.GSR(GSR), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("LSR_OVER_CE")) _TECHMAP_REPLACE_ (.CLK(SCLK), .LSR(CD), .CE(SP), .DI(D), .Q(Q)); endmodule +module OFS1P3JX(input PD, D, SP, SCLK, output Q); parameter GSR = "ENABLED"; (* syn_useioff, ioff_dir="output" *) TRELLIS_FF #(.GSR(GSR), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("LSR_OVER_CE")) _TECHMAP_REPLACE_ (.CLK(SCLK), .LSR(PD), .CE(SP), .DI(D), .Q(Q)); endmodule // TODO: Diamond I/O latches // module IFS1S1B(input PD, D, SCLK, output Q); endmodule -- cgit v1.2.3 From 7b1a6706d801773ec44d00bda0fd292c50fe39b7 Mon Sep 17 00:00:00 2001 From: David Shah Date: Thu, 10 Oct 2019 15:58:31 +0100 Subject: ecp5: Add attrmvcp to copy syn_useioff to driving FF Signed-off-by: David Shah --- techlibs/ecp5/synth_ecp5.cc | 1 + 1 file changed, 1 insertion(+) (limited to 'techlibs/ecp5') diff --git a/techlibs/ecp5/synth_ecp5.cc b/techlibs/ecp5/synth_ecp5.cc index 80aa1dbc5..a79dee31f 100644 --- a/techlibs/ecp5/synth_ecp5.cc +++ b/techlibs/ecp5/synth_ecp5.cc @@ -297,6 +297,7 @@ struct SynthEcp5Pass : public ScriptPass run("simplemap"); run("ecp5_ffinit"); run("ecp5_gsr"); + run("attrmvcp -copy -attr syn_useioff"); run("opt_clean"); } -- cgit v1.2.3 From e1d4e683b42bb1b75acb4054a94610cdc9fec0e7 Mon Sep 17 00:00:00 2001 From: David Shah Date: Fri, 11 Oct 2019 14:50:33 +0100 Subject: ecp5: Add ECLKBRIDGECS blackbox Signed-off-by: David Shah --- techlibs/ecp5/cells_bb.v | 7 +++++++ 1 file changed, 7 insertions(+) (limited to 'techlibs/ecp5') diff --git a/techlibs/ecp5/cells_bb.v b/techlibs/ecp5/cells_bb.v index 0a5046db2..ae124e7a3 100644 --- a/techlibs/ecp5/cells_bb.v +++ b/techlibs/ecp5/cells_bb.v @@ -333,6 +333,13 @@ module ECLKSYNCB( ); endmodule +(* blackbox *) +module ECLKBRIDGECS( + input CLK0, CLK1, SEL, + output ECSOUT +); +endmodule + (* blackbox *) module DCCA( input CLKI, CE, -- cgit v1.2.3 From 82f60ba938749ab20694f9070f1046e393f16f3c Mon Sep 17 00:00:00 2001 From: Sean Cross Date: Sat, 19 Oct 2019 14:04:52 +0800 Subject: Makefile: don't assume python is called `python3` On some architectures, notably on Windows, the official name for the Python binary from python.org is `python`. The build system assumes that python is called `python3`, which breaks under this architecture. There is already infrastructure in place to determine the name of the Python binary when building PYOSYS. Since Python is now always required to build Yosys, enable this check universally which sets the `PYTHON_EXECUTABLE` variable. Then, reuse this variable in other Makefiles as necessary, rather than hardcoding `python3` everywhere. Signed-off-by: Sean Cross --- techlibs/ecp5/Makefile.inc | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'techlibs/ecp5') diff --git a/techlibs/ecp5/Makefile.inc b/techlibs/ecp5/Makefile.inc index 5832d07ee..46463f510 100644 --- a/techlibs/ecp5/Makefile.inc +++ b/techlibs/ecp5/Makefile.inc @@ -27,12 +27,12 @@ EXTRA_OBJS += techlibs/ecp5/brams_init.mk techlibs/ecp5/brams_connect.mk techlibs/ecp5/brams_init.mk: techlibs/ecp5/brams_init.py $(Q) mkdir -p techlibs/ecp5 - $(P) python3 $< + $(P) $(PYTHON_EXECUTABLE) $< $(Q) touch $@ techlibs/ecp5/brams_connect.mk: techlibs/ecp5/brams_connect.py $(Q) mkdir -p techlibs/ecp5 - $(P) python3 $< + $(P) $(PYTHON_EXECUTABLE) $< $(Q) touch $@ -- cgit v1.2.3 From fa989e59e5a37d804d8a82050e022b8f4b7070d8 Mon Sep 17 00:00:00 2001 From: David Shah Date: Sun, 20 Oct 2019 10:30:41 +0100 Subject: ecp5: Pass -nomfs to abc9 Fixes #1459 Signed-off-by: David Shah --- techlibs/ecp5/synth_ecp5.cc | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'techlibs/ecp5') diff --git a/techlibs/ecp5/synth_ecp5.cc b/techlibs/ecp5/synth_ecp5.cc index a79dee31f..800a8ce22 100644 --- a/techlibs/ecp5/synth_ecp5.cc +++ b/techlibs/ecp5/synth_ecp5.cc @@ -314,9 +314,9 @@ struct SynthEcp5Pass : public ScriptPass if (abc9) { run("read_verilog -icells -lib +/ecp5/abc9_model.v"); if (nowidelut) - run("abc9 -lut +/ecp5/abc9_5g_nowide.lut -box +/ecp5/abc9_5g.box -W 200"); + run("abc9 -lut +/ecp5/abc9_5g_nowide.lut -box +/ecp5/abc9_5g.box -W 200 -nomfs"); else - run("abc9 -lut +/ecp5/abc9_5g.lut -box +/ecp5/abc9_5g.box -W 200"); + run("abc9 -lut +/ecp5/abc9_5g.lut -box +/ecp5/abc9_5g.box -W 200 -nomfs"); run("techmap -map +/ecp5/abc9_unmap.v"); } else { if (nowidelut) -- cgit v1.2.3 From 51e4e29bb1f7c030b0cac351c522dc41f7587be2 Mon Sep 17 00:00:00 2001 From: David Shah Date: Fri, 15 Nov 2019 21:03:11 +0000 Subject: ecp5: Use new autoname pass for better cell/net names Signed-off-by: David Shah --- techlibs/ecp5/synth_ecp5.cc | 1 + 1 file changed, 1 insertion(+) (limited to 'techlibs/ecp5') diff --git a/techlibs/ecp5/synth_ecp5.cc b/techlibs/ecp5/synth_ecp5.cc index 800a8ce22..4cbb56ea1 100644 --- a/techlibs/ecp5/synth_ecp5.cc +++ b/techlibs/ecp5/synth_ecp5.cc @@ -339,6 +339,7 @@ struct SynthEcp5Pass : public ScriptPass if (check_label("check")) { + run("autoname"); run("hierarchy -check"); run("stat"); run("check -noinit"); -- cgit v1.2.3