From 71906fab51c60d22ee5b145df0429287ab9d2d65 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Fri, 27 Dec 2019 16:57:08 -0800
Subject: Nitpick cleanup for ecp5

---
 techlibs/ecp5/cells_sim.v   | 12 ++----------
 techlibs/ecp5/synth_ecp5.cc |  2 +-
 2 files changed, 3 insertions(+), 11 deletions(-)

(limited to 'techlibs/ecp5')

diff --git a/techlibs/ecp5/cells_sim.v b/techlibs/ecp5/cells_sim.v
index f467218cc..0d3ec4e5b 100644
--- a/techlibs/ecp5/cells_sim.v
+++ b/techlibs/ecp5/cells_sim.v
@@ -1,5 +1,6 @@
 // ---------------------------------------
 
+(* lib_whitebox *)
 module LUT4(input A, B, C, D, output Z);
     parameter [15:0] INIT = 16'h0000;
     wire [7:0] s3 = D ?     INIT[15:8] :     INIT[7:0];
@@ -31,13 +32,8 @@ module CCU2C(
 
 	// First half
 	wire LUT4_0, LUT2_0;
-`ifdef _ABC
-	assign LUT4_0 = INIT0[{D0, C0, B0, A0}];
-	assign LUT2_0 = INIT0[{2'b00, B0, A0}];
-`else
 	LUT4 #(.INIT(INIT0)) lut4_0(.A(A0), .B(B0), .C(C0), .D(D0), .Z(LUT4_0));
 	LUT2 #(.INIT(INIT0[3:0])) lut2_0(.A(A0), .B(B0), .Z(LUT2_0));
-`endif
 	wire gated_cin_0 = (INJECT1_0 == "YES") ? 1'b0 : CIN;
 	assign S0 = LUT4_0 ^ gated_cin_0;
 
@@ -46,13 +42,8 @@ module CCU2C(
 
 	// Second half
 	wire LUT4_1, LUT2_1;
-`ifdef _ABC
-	assign LUT4_1 = INIT1[{D1, C1, B1, A1}];
-	assign LUT2_1 = INIT1[{2'b00, B1, A1}];
-`else
 	LUT4 #(.INIT(INIT1)) lut4_1(.A(A1), .B(B1), .C(C1), .D(D1), .Z(LUT4_1));
 	LUT2 #(.INIT(INIT1[3:0])) lut2_1(.A(A1), .B(B1), .Z(LUT2_1));
-`endif
 	wire gated_cin_1 = (INJECT1_1 == "YES") ? 1'b0 : cout_0;
 	assign S1 = LUT4_1 ^ gated_cin_1;
 
@@ -209,6 +200,7 @@ endmodule
 
 // ---------------------------------------
 
+(* lib_whitebox *)
 module LUT2(input A, B, output Z);
     parameter [3:0] INIT = 4'h0;
     wire [1:0] s1 = B ?     INIT[ 3:2] :     INIT[1:0];
diff --git a/techlibs/ecp5/synth_ecp5.cc b/techlibs/ecp5/synth_ecp5.cc
index b71bb2395..a0ea6d1f9 100644
--- a/techlibs/ecp5/synth_ecp5.cc
+++ b/techlibs/ecp5/synth_ecp5.cc
@@ -230,7 +230,7 @@ struct SynthEcp5Pass : public ScriptPass
 	{
 		if (check_label("begin"))
 		{
-			run("read_verilog -D_ABC -lib +/ecp5/cells_sim.v +/ecp5/cells_bb.v");
+			run("read_verilog -lib +/ecp5/cells_sim.v +/ecp5/cells_bb.v");
 			run(stringf("hierarchy -check %s", help_mode ? "-top <top>" : top_opt.c_str()));
 		}
 
-- 
cgit v1.2.3


From aa6d06c1b5b0083096ad547b0ad2600fcdc854f4 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Mon, 30 Dec 2019 12:09:53 -0800
Subject: Revert "Revert "synth_* with -retime option now calls abc with -D 1
 as well""

This reverts commit 6008bb7002f874e5c748eaa2050e7b6c17b32745.
---
 techlibs/ecp5/synth_ecp5.cc | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'techlibs/ecp5')

diff --git a/techlibs/ecp5/synth_ecp5.cc b/techlibs/ecp5/synth_ecp5.cc
index a0ea6d1f9..24e300fa8 100644
--- a/techlibs/ecp5/synth_ecp5.cc
+++ b/techlibs/ecp5/synth_ecp5.cc
@@ -290,7 +290,7 @@ struct SynthEcp5Pass : public ScriptPass
 			else
 				run("techmap -map +/techmap.v -map +/ecp5/arith_map.v");
 			if (retime || help_mode)
-				run("abc -dff", "(only if -retime)");
+				run("abc -dff -D 1", "(only if -retime)");
 		}
 
 		if (check_label("map_ffs"))
-- 
cgit v1.2.3


From 79448f9be035c88589b4e9c0de6b2bdc5acbd4df Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Mon, 30 Dec 2019 12:11:45 -0800
Subject: Update doc that "-retime" calls abc with "-dff -D 1"

---
 techlibs/ecp5/synth_ecp5.cc | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'techlibs/ecp5')

diff --git a/techlibs/ecp5/synth_ecp5.cc b/techlibs/ecp5/synth_ecp5.cc
index 24e300fa8..1ecb9cac3 100644
--- a/techlibs/ecp5/synth_ecp5.cc
+++ b/techlibs/ecp5/synth_ecp5.cc
@@ -62,7 +62,7 @@ struct SynthEcp5Pass : public ScriptPass
 		log("        do not flatten design before synthesis\n");
 		log("\n");
 		log("    -retime\n");
-		log("        run 'abc' with -dff option\n");
+		log("        run 'abc' with '-dff -D 1' options\n");
 		log("\n");
 		log("    -noccu2\n");
 		log("        do not use CCU2 cells in output netlist\n");
-- 
cgit v1.2.3


From b2046a2114add3d24c0affd9d885b7ee320dba27 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Tue, 31 Dec 2019 18:29:29 -0800
Subject: Cleanup ecp5 boxes

---
 techlibs/ecp5/abc9_5g.box  | 41 +++++++++++++++++------------------------
 techlibs/ecp5/abc9_map.v   | 19 +++++++++++--------
 techlibs/ecp5/abc9_model.v |  2 +-
 techlibs/ecp5/abc9_unmap.v |  4 ++--
 4 files changed, 31 insertions(+), 35 deletions(-)

(limited to 'techlibs/ecp5')

diff --git a/techlibs/ecp5/abc9_5g.box b/techlibs/ecp5/abc9_5g.box
index 2bc945a54..5c7f52ab1 100644
--- a/techlibs/ecp5/abc9_5g.box
+++ b/techlibs/ecp5/abc9_5g.box
@@ -1,43 +1,36 @@
-# NB: Inputs/Outputs must be ordered alphabetically
-#     (with exceptions for carry in/out)
+# NB: Box inputs/outputs must each be in the same order
+#     as their corresponding module definition
+#     (with exceptions detailed below)
 
 # Box 1 : CCU2C (2xCARRY + 2xLUT4)
-# Outputs: S0, S1, COUT
-#   (NB: carry chain input/output must be last
-#        input/output and bus has been moved
-#        there overriding the otherwise
+#   (Exception: carry chain input/output must be the
+#        last input and output and the entire bus has been
+#        moved there overriding the otherwise
 #        alphabetical ordering)
 # name  ID   w/b   ins    outs
 CCU2C   1      1   9      3
-
-#A0   A1   B0   B1   C0    C1  D0   D1   CIN
-379  -    379  -    275   -    141  -    257
-630  379  630  379  526   275  392  141  273
-516  516  516  516  412   412  278  278  43
+#A0  B0   C0    D0   A1   B1   C1   D1   CIN
+379  379  275   141  -    -    -    -    257 # S0
+630  630  526   392  379  379  275  141  273 # S1
+516  516  412   278  516  516  412  278   43 # COUT
 
 # Box 2 : TRELLIS_DPR16X4_COMB (16x4 dist ram)
-# Outputs: DO0, DO1, DO2, DO3
 # name               ID  w/b   ins   outs
 $__ABC9_DPR16X4_COMB  2     0   8    4
-
-#A0   A1   A2   A3   RAD0   RAD1   RAD2   RAD3
-0     0    0    0    141    379    275    379
-0     0    0    0    141    379    275    379
-0     0    0    0    141    379    275    379
-0     0    0    0    141    379    275    379
+#$D0  $D1  $D2  $D3  RAD0   RAD1   RAD2   RAD3
+0     0    0    0    141    379    275    379 # DO0
+0     0    0    0    141    379    275    379 # DO1
+0     0    0    0    141    379    275    379 # DO2
+0     0    0    0    141    379    275    379 # DO3
 
 # Box 3 : PFUMX (MUX2)
-# Outputs: Z
 # name  ID   w/b   ins    outs
 PFUMX   3    1     3      1
-
 #ALUT  BLUT  C0
-98     98    151
+98     98    151 # Z
 
 # Box 4 : L6MUX21 (MUX2)
-# Outputs: Z
 # name   ID   w/b   ins    outs
 L6MUX21  4    1     3      1
-
 #D0    D1    SD
-140    141   148
+140    141   148 # Z
diff --git a/techlibs/ecp5/abc9_map.v b/techlibs/ecp5/abc9_map.v
index d8d70f9f6..113a35b91 100644
--- a/techlibs/ecp5/abc9_map.v
+++ b/techlibs/ecp5/abc9_map.v
@@ -1,24 +1,27 @@
 // ---------------------------------------
 
+// Attach a (combinatorial) black-box onto the output
+//   of this LUTRAM primitive to capture its
+//   asynchronous read behaviour
 module TRELLIS_DPR16X4 (
-	input  [3:0] DI,
-	input  [3:0] WAD,
-	input        WRE,
-	input        WCK,
-	input  [3:0] RAD,
+	(* techmap_autopurge *) input  [3:0] DI,
+	(* techmap_autopurge *) input  [3:0] WAD,
+	(* techmap_autopurge *) input        WRE,
+	(* techmap_autopurge *) input        WCK,
+	(* techmap_autopurge *) input  [3:0] RAD,
 	output [3:0] DO
 );
 	parameter WCKMUX = "WCK";
 	parameter WREMUX = "WRE";
 	parameter [63:0] INITVAL = 64'h0000000000000000;
-    wire [3:0] \$DO ;
+    wire [3:0] $DO;
 
     TRELLIS_DPR16X4 #(
       .WCKMUX(WCKMUX), .WREMUX(WREMUX), .INITVAL(INITVAL)
     ) _TECHMAP_REPLACE_ (
       .DI(DI), .WAD(WAD), .WRE(WRE), .WCK(WCK),
-      .RAD(RAD), .DO(\$DO )
+      .RAD(RAD), .DO($DO)
     );
 
-    \$__ABC9_DPR16X4_COMB do (.A(\$DO ), .S(RAD), .Y(DO));
+    $__ABC9_DPR16X4_COMB do (.$DO($DO), .RAD(RAD), .DO(DO));
 endmodule
diff --git a/techlibs/ecp5/abc9_model.v b/techlibs/ecp5/abc9_model.v
index 1dc8b5617..81e5cd070 100644
--- a/techlibs/ecp5/abc9_model.v
+++ b/techlibs/ecp5/abc9_model.v
@@ -1,5 +1,5 @@
 // ---------------------------------------
 
 (* abc9_box_id=2 *)
-module \$__ABC9_DPR16X4_COMB (input [3:0] A, S, output [3:0] Y);
+module \$__ABC9_DPR16X4_COMB (input [3:0] $DO, RAD, output [3:0] DO);
 endmodule
diff --git a/techlibs/ecp5/abc9_unmap.v b/techlibs/ecp5/abc9_unmap.v
index 9ae143c46..cbdffdaf1 100644
--- a/techlibs/ecp5/abc9_unmap.v
+++ b/techlibs/ecp5/abc9_unmap.v
@@ -1,5 +1,5 @@
 // ---------------------------------------
 
-module \$__ABC9_DPR16X4_COMB (input [3:0] A, S, output [3:0] Y);
-    assign Y = A;
+module \$__ABC9_DPR16X4_COMB (input [3:0] $DO, RAD, output [3:0] DO);
+    assign DO = $DO;
 endmodule
-- 
cgit v1.2.3


From f7793a29564881245239e81326e0c7afeb15f6e9 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Tue, 31 Dec 2019 18:42:11 -0800
Subject: Missing character

---
 techlibs/ecp5/abc9_5g.box | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'techlibs/ecp5')

diff --git a/techlibs/ecp5/abc9_5g.box b/techlibs/ecp5/abc9_5g.box
index 5c7f52ab1..f153a665e 100644
--- a/techlibs/ecp5/abc9_5g.box
+++ b/techlibs/ecp5/abc9_5g.box
@@ -17,7 +17,7 @@ CCU2C   1      1   9      3
 # Box 2 : TRELLIS_DPR16X4_COMB (16x4 dist ram)
 # name               ID  w/b   ins   outs
 $__ABC9_DPR16X4_COMB  2     0   8    4
-#$D0  $D1  $D2  $D3  RAD0   RAD1   RAD2   RAD3
+#$DO0 $DO1 $DO2 $DO3 RAD0   RAD1   RAD2   RAD3
 0     0    0    0    141    379    275    379 # DO0
 0     0    0    0    141    379    275    379 # DO1
 0     0    0    0    141    379    275    379 # DO2
-- 
cgit v1.2.3


From 550310e2647c7aac1e49b79d9ff912436103062f Mon Sep 17 00:00:00 2001
From: whitequark <whitequark@whitequark.org>
Date: Wed, 1 Jan 2020 12:30:00 +0000
Subject: Harmonize BRAM/LUTRAM descriptions across all of Yosys.
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

This commit:
  * renames all remaining instances of "DRAM" (which is ambiguous)
    to "LUTRAM" (which is not), finishing the work started in
    the commit 698ab9be;
  * renames memory rule files to brams.txt/lutrams.txt;
  * adds/renames script labels map_bram/map_lutram;
  * extracts where necessary script labels map_ffram and map_gates;
  * adds where necessary options -nobram/-nolutram.

The end result is that BRAM/LUTRAM/FFRAM aspects of every target
are now consistent with each other.

Per architecture:
  * anlogic: rename drams.txt→lutrams.txt, add -nolutram, add
    :map_lutram, :map_ffram, :map_gates
  * ecp5: rename bram.txt→brams.txt, lutram.txt→lutrams.txt
  * efinix: rename bram.txt→brams.txt, add -nobram, add :map_ffram,
    :map_gates
  * gowin: rename bram.txt→brams.txt, dram.txt→lutrams.txt,
    rename -nodram→-nolutram (-nodram still recognized), rename
    :bram→:map_bram, :dram→:map_lutram, add :map_ffram, :map_gates
---
 techlibs/ecp5/Makefile.inc  |  4 ++--
 techlibs/ecp5/bram.txt      | 52 ---------------------------------------------
 techlibs/ecp5/brams.txt     | 52 +++++++++++++++++++++++++++++++++++++++++++++
 techlibs/ecp5/lutram.txt    | 17 ---------------
 techlibs/ecp5/lutrams.txt   | 17 +++++++++++++++
 techlibs/ecp5/synth_ecp5.cc |  4 ++--
 6 files changed, 73 insertions(+), 73 deletions(-)
 delete mode 100644 techlibs/ecp5/bram.txt
 create mode 100644 techlibs/ecp5/brams.txt
 delete mode 100644 techlibs/ecp5/lutram.txt
 create mode 100644 techlibs/ecp5/lutrams.txt

(limited to 'techlibs/ecp5')

diff --git a/techlibs/ecp5/Makefile.inc b/techlibs/ecp5/Makefile.inc
index 46463f510..2c33f23b9 100644
--- a/techlibs/ecp5/Makefile.inc
+++ b/techlibs/ecp5/Makefile.inc
@@ -8,9 +8,9 @@ $(eval $(call add_share_file,share/ecp5,techlibs/ecp5/cells_map.v))
 $(eval $(call add_share_file,share/ecp5,techlibs/ecp5/cells_sim.v))
 $(eval $(call add_share_file,share/ecp5,techlibs/ecp5/cells_bb.v))
 $(eval $(call add_share_file,share/ecp5,techlibs/ecp5/lutrams_map.v))
-$(eval $(call add_share_file,share/ecp5,techlibs/ecp5/lutram.txt))
+$(eval $(call add_share_file,share/ecp5,techlibs/ecp5/lutrams.txt))
 $(eval $(call add_share_file,share/ecp5,techlibs/ecp5/brams_map.v))
-$(eval $(call add_share_file,share/ecp5,techlibs/ecp5/bram.txt))
+$(eval $(call add_share_file,share/ecp5,techlibs/ecp5/brams.txt))
 $(eval $(call add_share_file,share/ecp5,techlibs/ecp5/arith_map.v))
 $(eval $(call add_share_file,share/ecp5,techlibs/ecp5/latches_map.v))
 $(eval $(call add_share_file,share/ecp5,techlibs/ecp5/dsp_map.v))
diff --git a/techlibs/ecp5/bram.txt b/techlibs/ecp5/bram.txt
deleted file mode 100644
index 777ccaa2e..000000000
--- a/techlibs/ecp5/bram.txt
+++ /dev/null
@@ -1,52 +0,0 @@
-bram $__ECP5_PDPW16KD
-  init 1
-
-  abits 9
-  dbits 36
-
-  groups 2
-  ports 1 1
-  wrmode 1 0
-  enable 4 1
-  transp 0 0
-  clocks 2 3
-  clkpol 2 3
-endbram
-
-bram $__ECP5_DP16KD
-  init 1
-
-  abits 10 @a10d18
-  dbits 18 @a10d18
-  abits 11 @a11d9
-  dbits 9  @a11d9
-  abits 12 @a12d4
-  dbits 4  @a12d4
-  abits 13 @a13d2
-  dbits 2  @a13d2
-  abits 14 @a14d1
-  dbits 1  @a14d1
-
-  groups 2
-  ports 1 1
-  wrmode 1 0
-  enable 2 1 @a10d18
-  enable 1 1 @a11d9 @a12d4 @a13d2 @a14d1
-  transp 0 2
-  clocks 2 3
-  clkpol 2 3
-endbram
-
-match $__ECP5_PDPW16KD
-  min bits 2048
-  min efficiency 5
-  shuffle_enable A
-  make_transp
-  or_next_if_better
-endmatch
-
-match $__ECP5_DP16KD
-  min bits 2048
-  min efficiency 5
-  shuffle_enable A
-endmatch
diff --git a/techlibs/ecp5/brams.txt b/techlibs/ecp5/brams.txt
new file mode 100644
index 000000000..777ccaa2e
--- /dev/null
+++ b/techlibs/ecp5/brams.txt
@@ -0,0 +1,52 @@
+bram $__ECP5_PDPW16KD
+  init 1
+
+  abits 9
+  dbits 36
+
+  groups 2
+  ports 1 1
+  wrmode 1 0
+  enable 4 1
+  transp 0 0
+  clocks 2 3
+  clkpol 2 3
+endbram
+
+bram $__ECP5_DP16KD
+  init 1
+
+  abits 10 @a10d18
+  dbits 18 @a10d18
+  abits 11 @a11d9
+  dbits 9  @a11d9
+  abits 12 @a12d4
+  dbits 4  @a12d4
+  abits 13 @a13d2
+  dbits 2  @a13d2
+  abits 14 @a14d1
+  dbits 1  @a14d1
+
+  groups 2
+  ports 1 1
+  wrmode 1 0
+  enable 2 1 @a10d18
+  enable 1 1 @a11d9 @a12d4 @a13d2 @a14d1
+  transp 0 2
+  clocks 2 3
+  clkpol 2 3
+endbram
+
+match $__ECP5_PDPW16KD
+  min bits 2048
+  min efficiency 5
+  shuffle_enable A
+  make_transp
+  or_next_if_better
+endmatch
+
+match $__ECP5_DP16KD
+  min bits 2048
+  min efficiency 5
+  shuffle_enable A
+endmatch
diff --git a/techlibs/ecp5/lutram.txt b/techlibs/ecp5/lutram.txt
deleted file mode 100644
index b94357429..000000000
--- a/techlibs/ecp5/lutram.txt
+++ /dev/null
@@ -1,17 +0,0 @@
-bram $__TRELLIS_DPR16X4
-  init 1
-  abits 4
-  dbits 4
-  groups 2
-  ports  1 1
-  wrmode 0 1
-  enable 0 1
-  transp 0 0
-  clocks 0 1
-  clkpol 0 2
-endbram
-
-match $__TRELLIS_DPR16X4
-  make_outreg
-  min wports 1
-endmatch
diff --git a/techlibs/ecp5/lutrams.txt b/techlibs/ecp5/lutrams.txt
new file mode 100644
index 000000000..b94357429
--- /dev/null
+++ b/techlibs/ecp5/lutrams.txt
@@ -0,0 +1,17 @@
+bram $__TRELLIS_DPR16X4
+  init 1
+  abits 4
+  dbits 4
+  groups 2
+  ports  1 1
+  wrmode 0 1
+  enable 0 1
+  transp 0 0
+  clocks 0 1
+  clkpol 0 2
+endbram
+
+match $__TRELLIS_DPR16X4
+  make_outreg
+  min wports 1
+endmatch
diff --git a/techlibs/ecp5/synth_ecp5.cc b/techlibs/ecp5/synth_ecp5.cc
index a0ea6d1f9..3985da57a 100644
--- a/techlibs/ecp5/synth_ecp5.cc
+++ b/techlibs/ecp5/synth_ecp5.cc
@@ -266,13 +266,13 @@ struct SynthEcp5Pass : public ScriptPass
 
 		if (!nobram && check_label("map_bram", "(skip if -nobram)"))
 		{
-			run("memory_bram -rules +/ecp5/bram.txt");
+			run("memory_bram -rules +/ecp5/brams.txt");
 			run("techmap -map +/ecp5/brams_map.v");
 		}
 
 		if (!nolutram && check_label("map_lutram", "(skip if -nolutram)"))
 		{
-			run("memory_bram -rules +/ecp5/lutram.txt");
+			run("memory_bram -rules +/ecp5/lutrams.txt");
 			run("techmap -map +/ecp5/lutrams_map.v");
 		}
 
-- 
cgit v1.2.3