From f1764b4fe99807c445526774563a98224b642766 Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Mon, 8 Dec 2014 10:50:19 +0100
Subject: Added $dffe cell type

---
 techlibs/common/simlib.v  | 19 +++++++++++++++++++
 techlibs/common/techmap.v |  2 +-
 2 files changed, 20 insertions(+), 1 deletion(-)

(limited to 'techlibs/common')

diff --git a/techlibs/common/simlib.v b/techlibs/common/simlib.v
index 2d8088adb..e241cd3ce 100644
--- a/techlibs/common/simlib.v
+++ b/techlibs/common/simlib.v
@@ -1216,6 +1216,25 @@ end
 
 endmodule
 
+// --------------------------------------------------------
+
+module \$dffe (CLK, EN, D, Q);
+
+parameter WIDTH = 0;
+parameter CLK_POLARITY = 1'b1;
+parameter EN_POLARITY = 1'b1;
+
+input CLK, EN;
+input [WIDTH-1:0] D;
+output reg [WIDTH-1:0] Q;
+wire pos_clk = CLK == CLK_POLARITY;
+
+always @(posedge pos_clk) begin
+	if (EN == EN_POLARITY) Q <= D;
+end
+
+endmodule
+
 // --------------------------------------------------------
 `ifndef SIMLIB_NOSR
 
diff --git a/techlibs/common/techmap.v b/techlibs/common/techmap.v
index b6c075b67..cb39fb4b2 100644
--- a/techlibs/common/techmap.v
+++ b/techlibs/common/techmap.v
@@ -59,7 +59,7 @@ module _90_simplemap_various;
 endmodule
 
 (* techmap_simplemap *)
-(* techmap_celltype = "$sr $dff $adff $dffsr $dlatch" *)
+(* techmap_celltype = "$sr $dff $dffe $adff $dffsr $dlatch" *)
 module _90_simplemap_registers;
 endmodule
 
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