From f9a307a50b5ce67b67d2b53e8c1334ea23ffd997 Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Sat, 27 Sep 2014 16:17:53 +0200
Subject: namespace Yosys

---
 techlibs/common/synth.cc | 6 +++++-
 1 file changed, 5 insertions(+), 1 deletion(-)

(limited to 'techlibs/common')

diff --git a/techlibs/common/synth.cc b/techlibs/common/synth.cc
index 4ccacd30b..8b41a003d 100644
--- a/techlibs/common/synth.cc
+++ b/techlibs/common/synth.cc
@@ -22,7 +22,10 @@
 #include "kernel/rtlil.h"
 #include "kernel/log.h"
 
-static bool check_label(bool &active, std::string run_from, std::string run_to, std::string label)
+USING_YOSYS_NAMESPACE
+PRIVATE_NAMESPACE_BEGIN
+
+bool check_label(bool &active, std::string run_from, std::string run_to, std::string label)
 {
 	if (!run_from.empty() && run_from == run_to) {
 		active = (label == run_from);
@@ -154,3 +157,4 @@ struct SynthPass : public Pass {
 	}
 } SynthPass;
  
+PRIVATE_NAMESPACE_END
-- 
cgit v1.2.3


From c3e779a65f285afa123b990f3a717a7ae8e028f5 Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Fri, 3 Oct 2014 10:12:28 +0200
Subject: Added $_BUF_ cell type

---
 techlibs/common/simcells.v | 6 ++++++
 1 file changed, 6 insertions(+)

(limited to 'techlibs/common')

diff --git a/techlibs/common/simcells.v b/techlibs/common/simcells.v
index a2a377350..88566411a 100644
--- a/techlibs/common/simcells.v
+++ b/techlibs/common/simcells.v
@@ -25,6 +25,12 @@
  *
  */
 
+module  \$_BUF_ (A, Y);
+input A;
+output Y;
+assign Y = A;
+endmodule
+
 module  \$_NOT_ (A, Y);
 input A;
 output Y;
-- 
cgit v1.2.3


From ab28491f271e3b02ba58dabb4b7033bcf17b6c25 Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Fri, 31 Oct 2014 03:36:51 +0100
Subject: Added "opt -full" alias for all more aggressive optimizations

---
 techlibs/common/synth.cc | 8 ++++++--
 1 file changed, 6 insertions(+), 2 deletions(-)

(limited to 'techlibs/common')

diff --git a/techlibs/common/synth.cc b/techlibs/common/synth.cc
index 8b41a003d..c76b002cc 100644
--- a/techlibs/common/synth.cc
+++ b/techlibs/common/synth.cc
@@ -76,9 +76,11 @@ struct SynthPass : public Pass {
 		log("        opt_clean\n");
 		log("\n");
 		log("    fine:\n");
+		log("        opt -fast -full\n");
 		log("        memory_map\n");
+		log("        opt -full\n");
 		log("        techmap\n");
-		log("        opt -fast\n");
+		log("        opt -fast -full\n");
 	#ifdef YOSYS_ENABLE_ABC
 		log("        abc -fast\n");
 		log("        opt_clean\n");
@@ -144,9 +146,11 @@ struct SynthPass : public Pass {
 
 		if (check_label(active, run_from, run_to, "fine"))
 		{
+			Pass::call(design, "opt -fast -full");
 			Pass::call(design, "memory_map");
+			Pass::call(design, "opt -full");
 			Pass::call(design, "techmap");
-			Pass::call(design, "opt -fast");
+			Pass::call(design, "opt -fast -full");
 		#ifdef YOSYS_ENABLE_ABC
 			Pass::call(design, "abc -fast");
 			Pass::call(design, "opt_clean");
-- 
cgit v1.2.3


From 74ef92b9c888fd05f03b4f679ecda6b04249e498 Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Fri, 31 Oct 2014 03:46:27 +0100
Subject: Added "abc" label in synth script

---
 techlibs/common/synth.cc | 18 ++++++++++++------
 1 file changed, 12 insertions(+), 6 deletions(-)

(limited to 'techlibs/common')

diff --git a/techlibs/common/synth.cc b/techlibs/common/synth.cc
index c76b002cc..211b5905a 100644
--- a/techlibs/common/synth.cc
+++ b/techlibs/common/synth.cc
@@ -80,10 +80,12 @@ struct SynthPass : public Pass {
 		log("        memory_map\n");
 		log("        opt -full\n");
 		log("        techmap\n");
-		log("        opt -fast -full\n");
+		log("        opt -fast\n");
 	#ifdef YOSYS_ENABLE_ABC
+		log("\n");
+		log("    abc:\n");
 		log("        abc -fast\n");
-		log("        opt_clean\n");
+		log("        opt -fast\n");
 	#endif
 		log("\n");
 	}
@@ -150,12 +152,16 @@ struct SynthPass : public Pass {
 			Pass::call(design, "memory_map");
 			Pass::call(design, "opt -full");
 			Pass::call(design, "techmap");
-			Pass::call(design, "opt -fast -full");
-		#ifdef YOSYS_ENABLE_ABC
+			Pass::call(design, "opt -fast");
+		}
+
+	#ifdef YOSYS_ENABLE_ABC
+		if (check_label(active, run_from, run_to, "abc"))
+		{
 			Pass::call(design, "abc -fast");
-			Pass::call(design, "opt_clean");
-		#endif
+			Pass::call(design, "opt -fast");
 		}
+	#endif
 
 		log_pop();
 	}
-- 
cgit v1.2.3


From fad9cec47b3aa9fc3d413abee92cc8380d0c0dc4 Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Mon, 8 Dec 2014 10:43:38 +0100
Subject: Added $_DFFE_??_ cell types

---
 techlibs/common/simcells.v | 32 ++++++++++++++++++++++++++++++++
 1 file changed, 32 insertions(+)

(limited to 'techlibs/common')

diff --git a/techlibs/common/simcells.v b/techlibs/common/simcells.v
index 88566411a..eb62d7830 100644
--- a/techlibs/common/simcells.v
+++ b/techlibs/common/simcells.v
@@ -163,6 +163,38 @@ always @(posedge C) begin
 end
 endmodule
 
+module  \$_DFFE_NN_ (D, Q, C, E);
+input D, C, E;
+output reg Q;
+always @(negedge C) begin
+	if (!E) Q <= D;
+end
+endmodule
+
+module  \$_DFFE_NP_ (D, Q, C, E);
+input D, C, E;
+output reg Q;
+always @(negedge C) begin
+	if (E) Q <= D;
+end
+endmodule
+
+module  \$_DFFE_PN_ (D, Q, C, E);
+input D, C, E;
+output reg Q;
+always @(posedge C) begin
+	if (!E) Q <= D;
+end
+endmodule
+
+module  \$_DFFE_PP_ (D, Q, C, E);
+input D, C, E;
+output reg Q;
+always @(posedge C) begin
+	if (E) Q <= D;
+end
+endmodule
+
 module  \$_DFF_NN0_ (D, Q, C, R);
 input D, C, R;
 output reg Q;
-- 
cgit v1.2.3


From f1764b4fe99807c445526774563a98224b642766 Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Mon, 8 Dec 2014 10:50:19 +0100
Subject: Added $dffe cell type

---
 techlibs/common/simlib.v  | 19 +++++++++++++++++++
 techlibs/common/techmap.v |  2 +-
 2 files changed, 20 insertions(+), 1 deletion(-)

(limited to 'techlibs/common')

diff --git a/techlibs/common/simlib.v b/techlibs/common/simlib.v
index 2d8088adb..e241cd3ce 100644
--- a/techlibs/common/simlib.v
+++ b/techlibs/common/simlib.v
@@ -1216,6 +1216,25 @@ end
 
 endmodule
 
+// --------------------------------------------------------
+
+module \$dffe (CLK, EN, D, Q);
+
+parameter WIDTH = 0;
+parameter CLK_POLARITY = 1'b1;
+parameter EN_POLARITY = 1'b1;
+
+input CLK, EN;
+input [WIDTH-1:0] D;
+output reg [WIDTH-1:0] Q;
+wire pos_clk = CLK == CLK_POLARITY;
+
+always @(posedge pos_clk) begin
+	if (EN == EN_POLARITY) Q <= D;
+end
+
+endmodule
+
 // --------------------------------------------------------
 `ifndef SIMLIB_NOSR
 
diff --git a/techlibs/common/techmap.v b/techlibs/common/techmap.v
index b6c075b67..cb39fb4b2 100644
--- a/techlibs/common/techmap.v
+++ b/techlibs/common/techmap.v
@@ -59,7 +59,7 @@ module _90_simplemap_various;
 endmodule
 
 (* techmap_simplemap *)
-(* techmap_celltype = "$sr $dff $adff $dffsr $dlatch" *)
+(* techmap_celltype = "$sr $dff $dffe $adff $dffsr $dlatch" *)
 module _90_simplemap_registers;
 endmodule
 
-- 
cgit v1.2.3


From 72f500c950f002a229d0434e76b24b347d7c583c Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Fri, 12 Dec 2014 12:44:16 +0100
Subject: Removed UTF-8 chars from techmap.v

---
 techlibs/common/techmap.v | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'techlibs/common')

diff --git a/techlibs/common/techmap.v b/techlibs/common/techmap.v
index cb39fb4b2..7b5528560 100644
--- a/techlibs/common/techmap.v
+++ b/techlibs/common/techmap.v
@@ -207,7 +207,7 @@ module _90_lcu (P, G, CI, CO);
 		g[0] = g[0] | (p[0] & CI);
 
 		// [[CITE]] Brent Kung Adder
-		// R. P. Brent and H. T. Kung, “A Regular Layout for Parallel Adders”,
+		// R. P. Brent and H. T. Kung, "A Regular Layout for Parallel Adders",
 		// IEEE Transaction on Computers, Vol. C-31, No. 3, p. 260-264, March, 1982
 
 		// Main tree
-- 
cgit v1.2.3


From 4aa9fbbf3fe095220895dd2508ac6118b7382493 Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Wed, 24 Dec 2014 10:49:24 +0100
Subject: Improvements in simplemap api, added $ne $nex $eq $eqx support

---
 techlibs/common/techmap.v | 54 +++++------------------------------------------
 1 file changed, 5 insertions(+), 49 deletions(-)

(limited to 'techlibs/common')

diff --git a/techlibs/common/techmap.v b/techlibs/common/techmap.v
index 7b5528560..e0ecf0c48 100644
--- a/techlibs/common/techmap.v
+++ b/techlibs/common/techmap.v
@@ -53,6 +53,11 @@ endmodule
 module _90_simplemap_logic_ops;
 endmodule
 
+(* techmap_simplemap *)
+(* techmap_celltype = "$eq $eqx $ne $nex" *)
+module _90_simplemap_compare_ops;
+endmodule
+
 (* techmap_simplemap *)
 (* techmap_celltype = "$pos $slice $concat $mux" *)
 module _90_simplemap_various;
@@ -406,55 +411,6 @@ module _90_pow (A, B, Y);
 endmodule
 
 
-// --------------------------------------------------------
-// Equal and Not-Equal
-// --------------------------------------------------------
-
-(* techmap_celltype = "$eq $eqx" *)
-module _90_eq_eqx (A, B, Y);
-	parameter A_SIGNED = 0;
-	parameter B_SIGNED = 0;
-	parameter A_WIDTH = 1;
-	parameter B_WIDTH = 1;
-	parameter Y_WIDTH = 1;
-
-	localparam WIDTH = A_WIDTH > B_WIDTH ? A_WIDTH : B_WIDTH;
-
-	input [A_WIDTH-1:0] A;
-	input [B_WIDTH-1:0] B;
-	output [Y_WIDTH-1:0] Y;
-
-	wire carry, carry_sign;
-	wire [WIDTH-1:0] A_buf, B_buf;
-	\$pos #(.A_SIGNED(A_SIGNED), .A_WIDTH(A_WIDTH), .Y_WIDTH(WIDTH)) A_conv (.A(A), .Y(A_buf));
-	\$pos #(.A_SIGNED(B_SIGNED), .A_WIDTH(B_WIDTH), .Y_WIDTH(WIDTH)) B_conv (.A(B), .Y(B_buf));
-
-	assign Y = ~|(A_buf ^ B_buf);
-endmodule
-
-(* techmap_celltype = "$ne $nex" *)
-module _90_ne_nex (A, B, Y);
-	parameter A_SIGNED = 0;
-	parameter B_SIGNED = 0;
-	parameter A_WIDTH = 1;
-	parameter B_WIDTH = 1;
-	parameter Y_WIDTH = 1;
-
-	localparam WIDTH = A_WIDTH > B_WIDTH ? A_WIDTH : B_WIDTH;
-
-	input [A_WIDTH-1:0] A;
-	input [B_WIDTH-1:0] B;
-	output [Y_WIDTH-1:0] Y;
-
-	wire carry, carry_sign;
-	wire [WIDTH-1:0] A_buf, B_buf;
-	\$pos #(.A_SIGNED(A_SIGNED), .A_WIDTH(A_WIDTH), .Y_WIDTH(WIDTH)) A_conv (.A(A), .Y(A_buf));
-	\$pos #(.A_SIGNED(B_SIGNED), .A_WIDTH(B_WIDTH), .Y_WIDTH(WIDTH)) B_conv (.A(B), .Y(B_buf));
-
-	assign Y = |(A_buf ^ B_buf);
-endmodule
-
-
 // --------------------------------------------------------
 // Parallel Multiplexers
 // --------------------------------------------------------
-- 
cgit v1.2.3


From c64b1de11da8db9e912e0a293d5c9c8a9bc31096 Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Tue, 30 Dec 2014 11:41:24 +0100
Subject: Fixed build with SMALL=1

---
 techlibs/common/Makefile.inc | 2 ++
 1 file changed, 2 insertions(+)

(limited to 'techlibs/common')

diff --git a/techlibs/common/Makefile.inc b/techlibs/common/Makefile.inc
index 7c8cc2f66..0607ca1a1 100644
--- a/techlibs/common/Makefile.inc
+++ b/techlibs/common/Makefile.inc
@@ -1,5 +1,7 @@
 
+ifneq ($(SMALL),1)
 OBJS += techlibs/common/synth.o
+endif
 
 EXTRA_TARGETS += techlibs/common/blackbox.v
 
-- 
cgit v1.2.3


From ba43cf5807dadac970ff10afed4963d1ee329217 Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Tue, 30 Dec 2014 13:33:29 +0100
Subject: Fixed simlib entries for $memrd and $memwr

---
 techlibs/common/simlib.v | 2 ++
 1 file changed, 2 insertions(+)

(limited to 'techlibs/common')

diff --git a/techlibs/common/simlib.v b/techlibs/common/simlib.v
index e241cd3ce..bacf4a17e 100644
--- a/techlibs/common/simlib.v
+++ b/techlibs/common/simlib.v
@@ -1449,6 +1449,7 @@ parameter WIDTH = 8;
 
 parameter CLK_ENABLE = 0;
 parameter CLK_POLARITY = 0;
+parameter TRANSPARENT = 0;
 
 input CLK;
 input [ABITS-1:0] ADDR;
@@ -1473,6 +1474,7 @@ parameter WIDTH = 8;
 
 parameter CLK_ENABLE = 0;
 parameter CLK_POLARITY = 0;
+parameter PRIORITY = 0;
 
 input CLK;
 input [WIDTH-1:0] EN;
-- 
cgit v1.2.3


From 474831643c9e75bd3930f566bc746bb4e330bce9 Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Fri, 2 Jan 2015 17:11:31 +0100
Subject: New $mem simlib model

---
 techlibs/common/simlib.v | 131 +++++++++++++----------------------------------
 1 file changed, 36 insertions(+), 95 deletions(-)

(limited to 'techlibs/common')

diff --git a/techlibs/common/simlib.v b/techlibs/common/simlib.v
index bacf4a17e..ca4b1d36c 100644
--- a/techlibs/common/simlib.v
+++ b/techlibs/common/simlib.v
@@ -1518,107 +1518,48 @@ input [WR_PORTS*WIDTH-1:0] WR_EN;
 input [WR_PORTS*ABITS-1:0] WR_ADDR;
 input [WR_PORTS*WIDTH-1:0] WR_DATA;
 
-reg [WIDTH-1:0] data [SIZE-1:0];
-reg update_async_rd;
+reg [WIDTH-1:0] memory [SIZE-1:0];
 
-genvar i;
-generate
+integer i, j;
+reg [WR_PORTS-1:0] LAST_WR_CLK;
+reg [RD_PORTS-1:0] LAST_RD_CLK;
+
+function port_active;
+	input clk_enable;
+	input clk_polarity;
+	input last_clk;
+	input this_clk;
+	begin
+		casez ({clk_enable, clk_polarity, last_clk, this_clk})
+			4'b0???: port_active = 1;
+			4'b1101: port_active = 1;
+			4'b1010: port_active = 1;
+			default: port_active = 0;
+		endcase
+	end
+endfunction
 
-	for (i = 0; i < RD_PORTS; i = i+1) begin:rd
-		if (RD_CLK_ENABLE[i] == 0) begin:rd_noclk
-			always @(RD_ADDR or update_async_rd)
-				RD_DATA[i*WIDTH +: WIDTH] <= data[RD_ADDR[i*ABITS +: ABITS] - OFFSET];
-		end else
-		if (RD_TRANSPARENT[i] == 1) begin:rd_transparent
-			reg [ABITS-1:0] addr_buf;
-			if (RD_CLK_POLARITY[i] == 1) begin:rd_trans_posclk
-				always @(posedge RD_CLK[i])
-					addr_buf <= RD_ADDR[i*ABITS +: ABITS];
-			end else begin:rd_trans_negclk
-				always @(negedge RD_CLK[i])
-					addr_buf <= RD_ADDR[i*ABITS +: ABITS];
-			end
-			always @(addr_buf or update_async_rd)
-				RD_DATA[i*WIDTH +: WIDTH] <= data[addr_buf - OFFSET];
-		end else begin:rd_notransparent
-			if (RD_CLK_POLARITY[i] == 1) begin:rd_notrans_posclk
-				always @(posedge RD_CLK[i])
-					RD_DATA[i*WIDTH +: WIDTH] <= data[RD_ADDR[i*ABITS +: ABITS] - OFFSET];
-			end else begin:rd_notrans_negclk
-				always @(negedge RD_CLK[i])
-					RD_DATA[i*WIDTH +: WIDTH] <= data[RD_ADDR[i*ABITS +: ABITS] - OFFSET];
-			end
-		end
+always @* begin
+	for (i = 0; i < RD_PORTS; i = i+1) begin
+		if ((!RD_TRANSPARENT[i] && RD_CLK_ENABLE[i]) && port_active(RD_CLK_ENABLE[i], RD_CLK_POLARITY[i], LAST_RD_CLK[i], RD_CLK[i]))
+			RD_DATA[i*WIDTH +: WIDTH] <= memory[RD_ADDR[i*ABITS +: ABITS] - OFFSET];
 	end
 
-	for (i = 0; i < WR_PORTS; i = i+1) begin:wr
-		integer k, n;
-		reg found_collision, run_update;
-		if (WR_CLK_ENABLE[i] == 0) begin:wr_noclk
-			always @(WR_ADDR or WR_DATA or WR_EN) begin
-				run_update = 0;
-				for (n = 0; n < WIDTH; n = n+1) begin
-					if (WR_EN[i*WIDTH + n]) begin
-						found_collision = 0;
-						for (k = i+1; k < WR_PORTS; k = k+1)
-							if (WR_EN[k*WIDTH + n] && WR_ADDR[i*ABITS +: ABITS] == WR_ADDR[k*ABITS +: ABITS])
-								found_collision = 1;
-						if (!found_collision) begin
-							data[WR_ADDR[i*ABITS +: ABITS] - OFFSET][n] <= WR_DATA[i*WIDTH + n];
-							run_update = 1;
-						end
-					end
-				end
-				if (run_update) begin
-					update_async_rd <= 1;
-					update_async_rd <= 0;
-				end
-			end
-		end else
-		if (WR_CLK_POLARITY[i] == 1) begin:rd_posclk
-			always @(posedge WR_CLK[i]) begin
-				run_update = 0;
-				for (n = 0; n < WIDTH; n = n+1) begin
-					if (WR_EN[i*WIDTH + n]) begin
-						found_collision = 0;
-						for (k = i+1; k < WR_PORTS; k = k+1)
-							if (WR_EN[k*WIDTH + n] && WR_ADDR[i*ABITS +: ABITS] == WR_ADDR[k*ABITS +: ABITS])
-								found_collision = 1;
-						if (!found_collision) begin
-							data[WR_ADDR[i*ABITS +: ABITS] - OFFSET][n] <= WR_DATA[i*WIDTH + n];
-							run_update = 1;
-						end
-					end
-				end
-				if (run_update) begin
-					update_async_rd <= 1;
-					update_async_rd <= 0;
-				end
-			end
-		end else begin:rd_negclk
-			always @(negedge WR_CLK[i]) begin
-				run_update = 0;
-				for (n = 0; n < WIDTH; n = n+1) begin
-					if (WR_EN[i*WIDTH + n]) begin
-						found_collision = 0;
-						for (k = i+1; k < WR_PORTS; k = k+1)
-							if (WR_EN[k*WIDTH + n] && WR_ADDR[i*ABITS +: ABITS] == WR_ADDR[k*ABITS +: ABITS])
-								found_collision = 1;
-						if (!found_collision) begin
-							data[WR_ADDR[i*ABITS +: ABITS] - OFFSET][n] <= WR_DATA[i*WIDTH + n];
-							run_update = 1;
-						end
-					end
-				end
-				if (run_update) begin
-					update_async_rd <= 1;
-					update_async_rd <= 0;
-				end
-			end
-		end
+	for (i = 0; i < WR_PORTS; i = i+1) begin
+		if (port_active(WR_CLK_ENABLE[i], WR_CLK_POLARITY[i], LAST_WR_CLK[i], WR_CLK[i]))
+			for (j = 0; j < WIDTH; j = j+1)
+				if (WR_EN[i*WIDTH+j])
+					memory[WR_ADDR[i*ABITS +: ABITS] - OFFSET][j] = WR_DATA[i*WIDTH+j];
 	end
 
-endgenerate
+	for (i = 0; i < RD_PORTS; i = i+1) begin
+		if ((RD_TRANSPARENT[i] || !RD_CLK_ENABLE[i]) && port_active(RD_CLK_ENABLE[i], RD_CLK_POLARITY[i], LAST_RD_CLK[i], RD_CLK[i]))
+			RD_DATA[i*WIDTH +: WIDTH] <= memory[RD_ADDR[i*ABITS +: ABITS] - OFFSET];
+	end
+
+	LAST_RD_CLK <= RD_CLK;
+	LAST_WR_CLK <= WR_CLK;
+end
 
 endmodule
 
-- 
cgit v1.2.3


From 90f4017703a275c1a32cb347e4b60bd43873bbce Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Fri, 2 Jan 2015 22:45:26 +0100
Subject: Added proper clkpol support to memory_bram

---
 techlibs/common/simlib.v | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'techlibs/common')

diff --git a/techlibs/common/simlib.v b/techlibs/common/simlib.v
index ca4b1d36c..4680e209a 100644
--- a/techlibs/common/simlib.v
+++ b/techlibs/common/simlib.v
@@ -1539,7 +1539,7 @@ function port_active;
 	end
 endfunction
 
-always @* begin
+always @(RD_CLK, RD_ADDR, RD_DATA, WR_CLK, WR_EN, WR_ADDR, WR_DATA) begin
 	for (i = 0; i < RD_PORTS; i = i+1) begin
 		if ((!RD_TRANSPARENT[i] && RD_CLK_ENABLE[i]) && port_active(RD_CLK_ENABLE[i], RD_CLK_POLARITY[i], LAST_RD_CLK[i], RD_CLK[i]))
 			RD_DATA[i*WIDTH +: WIDTH] <= memory[RD_ADDR[i*ABITS +: ABITS] - OFFSET];
-- 
cgit v1.2.3


From a7e43ae3d97ef14c8d624d8fdfe938ae9f47ce84 Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Sat, 3 Jan 2015 10:57:01 +0100
Subject: Progress in memory_bram

---
 techlibs/common/simlib.v | 3 +++
 1 file changed, 3 insertions(+)

(limited to 'techlibs/common')

diff --git a/techlibs/common/simlib.v b/techlibs/common/simlib.v
index 4680e209a..f16bd6bd2 100644
--- a/techlibs/common/simlib.v
+++ b/techlibs/common/simlib.v
@@ -1540,6 +1540,9 @@ function port_active;
 endfunction
 
 always @(RD_CLK, RD_ADDR, RD_DATA, WR_CLK, WR_EN, WR_ADDR, WR_DATA) begin
+`ifdef SIMLIB_MEMDELAY
+	#`SIMLIB_MEMDELAY;
+`endif
 	for (i = 0; i < RD_PORTS; i = i+1) begin
 		if ((!RD_TRANSPARENT[i] && RD_CLK_ENABLE[i]) && port_active(RD_CLK_ENABLE[i], RD_CLK_POLARITY[i], LAST_RD_CLK[i], RD_CLK[i]))
 			RD_DATA[i*WIDTH +: WIDTH] <= memory[RD_ADDR[i*ABITS +: ABITS] - OFFSET];
-- 
cgit v1.2.3


From 1d96277f5d4c615ca4018d9a6e867c980db3b73a Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Thu, 8 Jan 2015 00:23:18 +0100
Subject: Added add_share_file Makefile macro

---
 techlibs/common/Makefile.inc | 31 ++++++-------------------------
 1 file changed, 6 insertions(+), 25 deletions(-)

(limited to 'techlibs/common')

diff --git a/techlibs/common/Makefile.inc b/techlibs/common/Makefile.inc
index 0607ca1a1..dc1e0ef66 100644
--- a/techlibs/common/Makefile.inc
+++ b/techlibs/common/Makefile.inc
@@ -9,29 +9,10 @@ techlibs/common/blackbox.v: techlibs/common/blackbox.sed techlibs/common/simlib.
 	$(P) cat techlibs/common/simlib.v techlibs/common/simcells.v | $(SED) -rf techlibs/common/blackbox.sed > techlibs/common/blackbox.v.new
 	$(Q) mv techlibs/common/blackbox.v.new techlibs/common/blackbox.v
 
-EXTRA_TARGETS += share/simlib.v share/simcells.v share/techmap.v share/blackbox.v share/pmux2mux.v share/adff2dff.v
-
-share/simlib.v: techlibs/common/simlib.v
-	$(P) mkdir -p share
-	$(Q) cp techlibs/common/simlib.v share/simlib.v
-
-share/simcells.v: techlibs/common/simcells.v
-	$(P) mkdir -p share
-	$(Q) cp techlibs/common/simcells.v share/simcells.v
-
-share/techmap.v: techlibs/common/techmap.v
-	$(P) mkdir -p share
-	$(Q) cp techlibs/common/techmap.v share/techmap.v
-
-share/blackbox.v: techlibs/common/blackbox.v
-	$(P) mkdir -p share
-	$(Q) cp techlibs/common/blackbox.v share/blackbox.v
-
-share/pmux2mux.v: techlibs/common/pmux2mux.v
-	$(P) mkdir -p share
-	$(Q) cp techlibs/common/pmux2mux.v share/pmux2mux.v
-
-share/adff2dff.v: techlibs/common/adff2dff.v
-	$(P) mkdir -p share
-	$(Q) cp techlibs/common/adff2dff.v share/adff2dff.v
+$(eval $(call add_share_file,share,techlibs/common/simlib.v))
+$(eval $(call add_share_file,share,techlibs/common/simcells.v))
+$(eval $(call add_share_file,share,techlibs/common/techmap.v))
+$(eval $(call add_share_file,share,techlibs/common/blackbox.v))
+$(eval $(call add_share_file,share,techlibs/common/pmux2mux.v))
+$(eval $(call add_share_file,share,techlibs/common/adff2dff.v))
 
-- 
cgit v1.2.3


From 3ed4e34380036c63d6177f41f43767b41201e4a8 Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Fri, 16 Jan 2015 15:50:42 +0100
Subject: Added cells.lib

---
 techlibs/common/Makefile.inc |   1 +
 techlibs/common/cells.lib    | 108 +++++++++++++++++++++++++++++++++++++++++++
 2 files changed, 109 insertions(+)
 create mode 100644 techlibs/common/cells.lib

(limited to 'techlibs/common')

diff --git a/techlibs/common/Makefile.inc b/techlibs/common/Makefile.inc
index dc1e0ef66..d2ce61cf6 100644
--- a/techlibs/common/Makefile.inc
+++ b/techlibs/common/Makefile.inc
@@ -15,4 +15,5 @@ $(eval $(call add_share_file,share,techlibs/common/techmap.v))
 $(eval $(call add_share_file,share,techlibs/common/blackbox.v))
 $(eval $(call add_share_file,share,techlibs/common/pmux2mux.v))
 $(eval $(call add_share_file,share,techlibs/common/adff2dff.v))
+$(eval $(call add_share_file,share,techlibs/common/cells.lib))
 
diff --git a/techlibs/common/cells.lib b/techlibs/common/cells.lib
new file mode 100644
index 000000000..eb89036d7
--- /dev/null
+++ b/techlibs/common/cells.lib
@@ -0,0 +1,108 @@
+library(yosys_cells) {
+	cell(DFF_N) {
+		ff(IQ, IQN) {
+			clocked_on: "!C";
+			next_state: "D";
+		}
+		pin(D) { direction: input; }
+		pin(C) { direction: input; clock: true; }
+		pin(Q) { direction: output; function: "IQ"; }
+	}
+	cell(DFF_P) {
+		ff(IQ, IQN) {
+			clocked_on: "C";
+			next_state: "D";
+		}
+		pin(D) { direction: input; }
+		pin(C) { direction: input; clock: true; }
+		pin(Q) { direction: output; function: "IQ"; }
+	}
+	cell(DFF_NN0) {
+		ff(IQ, IQN) {
+			clocked_on: "!C";
+			next_state: "D";
+			clear: "!R";
+		}
+		pin(D) { direction: input; }
+		pin(R) { direction: input; }
+		pin(C) { direction: input; clock: true; }
+		pin(Q) { direction: output; function: "IQ"; }
+	}
+	cell(DFF_NN1) {
+		ff(IQ, IQN) {
+			clocked_on: "!C";
+			next_state: "D";
+			preset: "!R";
+		}
+		pin(D) { direction: input; }
+		pin(R) { direction: input; }
+		pin(C) { direction: input; clock: true; }
+		pin(Q) { direction: output; function: "IQ"; }
+	}
+	cell(DFF_NP0) {
+		ff(IQ, IQN) {
+			clocked_on: "!C";
+			next_state: "D";
+			clear: "R";
+		}
+		pin(D) { direction: input; }
+		pin(R) { direction: input; }
+		pin(C) { direction: input; clock: true; }
+		pin(Q) { direction: output; function: "IQ"; }
+	}
+	cell(DFF_NP1) {
+		ff(IQ, IQN) {
+			clocked_on: "!C";
+			next_state: "D";
+			preset: "R";
+		}
+		pin(D) { direction: input; }
+		pin(R) { direction: input; }
+		pin(C) { direction: input; clock: true; }
+		pin(Q) { direction: output; function: "IQ"; }
+	}
+	cell(DFF_PN0) {
+		ff(IQ, IQN) {
+			clocked_on: "C";
+			next_state: "D";
+			clear: "!R";
+		}
+		pin(D) { direction: input; }
+		pin(R) { direction: input; }
+		pin(C) { direction: input; clock: true; }
+		pin(Q) { direction: output; function: "IQ"; }
+	}
+	cell(DFF_PN1) {
+		ff(IQ, IQN) {
+			clocked_on: "C";
+			next_state: "D";
+			preset: "!R";
+		}
+		pin(D) { direction: input; }
+		pin(R) { direction: input; }
+		pin(C) { direction: input; clock: true; }
+		pin(Q) { direction: output; function: "IQ"; }
+	}
+	cell(DFF_PP0) {
+		ff(IQ, IQN) {
+			clocked_on: "C";
+			next_state: "D";
+			clear: "R";
+		}
+		pin(D) { direction: input; }
+		pin(R) { direction: input; }
+		pin(C) { direction: input; clock: true; }
+		pin(Q) { direction: output; function: "IQ"; }
+	}
+	cell(DFF_PP1) {
+		ff(IQ, IQN) {
+			clocked_on: "C";
+			next_state: "D";
+			preset: "R";
+		}
+		pin(D) { direction: input; }
+		pin(R) { direction: input; }
+		pin(C) { direction: input; clock: true; }
+		pin(Q) { direction: output; function: "IQ"; }
+	}
+}
-- 
cgit v1.2.3


From e13a45ae61e05705d9ab6890da60737bd05eb24d Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Mon, 19 Jan 2015 11:55:05 +0100
Subject: Added $equiv cell type

---
 techlibs/common/simlib.v | 24 +++++++++++++++++++++++-
 1 file changed, 23 insertions(+), 1 deletion(-)

(limited to 'techlibs/common')

diff --git a/techlibs/common/simlib.v b/techlibs/common/simlib.v
index f16bd6bd2..d0feadd81 100644
--- a/techlibs/common/simlib.v
+++ b/techlibs/common/simlib.v
@@ -1160,12 +1160,34 @@ module \$assert (A, EN);
 
 input A, EN;
 
+`ifndef SIMLIB_NOCHECKS
 always @* begin
 	if (A !== 1'b1 && EN === 1'b1) begin
 		$display("Assertation failed!");
-		$finish;
+		$stop;
+	end
+end
+`endif
+
+endmodule
+
+// --------------------------------------------------------
+
+module \$equiv (A, B, Y);
+
+input A, B;
+output Y;
+
+assign Y = (A !== 1'bx && A !== B) ? 1'bx : A;
+
+`ifndef SIMLIB_NOCHECKS
+always @* begin
+	if (A !== 1'bx && A !== B) begin
+		$display("Equivalence failed!");
+		$stop;
 	end
 end
+`endif
 
 endmodule
 
-- 
cgit v1.2.3


From bedd46338fecd93c4c1c3b35017c26b080a990dc Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Fri, 30 Jan 2015 22:46:53 +0100
Subject: Added "fsm -encfile"

---
 techlibs/common/synth.cc | 11 +++++++++--
 1 file changed, 9 insertions(+), 2 deletions(-)

(limited to 'techlibs/common')

diff --git a/techlibs/common/synth.cc b/techlibs/common/synth.cc
index 211b5905a..5267344bb 100644
--- a/techlibs/common/synth.cc
+++ b/techlibs/common/synth.cc
@@ -52,6 +52,9 @@ struct SynthPass : public Pass {
 		log("    -top <module>\n");
 		log("        use the specified module as top module (default='top')\n");
 		log("\n");
+		log("    -encfile <file>\n");
+		log("        passed to 'fsm_recode' via 'fsm'\n");
+		log("\n");
 		log("    -run <from_label>[:<to_label>]\n");
 		log("        only run the commands between the labels (see below). an empty\n");
 		log("        from label is synonymous to 'begin', and empty to label is\n");
@@ -91,7 +94,7 @@ struct SynthPass : public Pass {
 	}
 	virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
 	{
-		std::string top_module;
+		std::string top_module, fsm_opts;
 		std::string run_from, run_to;
 
 		size_t argidx;
@@ -101,6 +104,10 @@ struct SynthPass : public Pass {
 				top_module = args[++argidx];
 				continue;
 			}
+			if (args[argidx] == "-encfile" && argidx+1 < args.size()) {
+				fsm_opts = " -encfile " + args[++argidx];
+				continue;
+			}
 			if (args[argidx] == "-run" && argidx+1 < args.size()) {
 				size_t pos = args[argidx+1].find(':');
 				if (pos == std::string::npos) {
@@ -140,7 +147,7 @@ struct SynthPass : public Pass {
 			Pass::call(design, "alumacc");
 			Pass::call(design, "share");
 			Pass::call(design, "opt");
-			Pass::call(design, "fsm");
+			Pass::call(design, "fsm" + fsm_opts);
 			Pass::call(design, "opt -fast");
 			Pass::call(design, "memory -nomap");
 			Pass::call(design, "opt_clean");
-- 
cgit v1.2.3


From 1df81f92ce171ba63cf0e4d10e6f203ca5f7f64e Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Sun, 1 Feb 2015 13:38:46 +0100
Subject: Added "make mklibyosys", some minor API changes

---
 techlibs/common/synth.cc | 10 +++++++++-
 1 file changed, 9 insertions(+), 1 deletion(-)

(limited to 'techlibs/common')

diff --git a/techlibs/common/synth.cc b/techlibs/common/synth.cc
index 5267344bb..69ef5bc55 100644
--- a/techlibs/common/synth.cc
+++ b/techlibs/common/synth.cc
@@ -55,6 +55,9 @@ struct SynthPass : public Pass {
 		log("    -encfile <file>\n");
 		log("        passed to 'fsm_recode' via 'fsm'\n");
 		log("\n");
+		log("    -noabc\n");
+		log("        do not run abc (as if yosys was compiled without ABC support)\n");
+		log("\n");
 		log("    -run <from_label>[:<to_label>]\n");
 		log("        only run the commands between the labels (see below). an empty\n");
 		log("        from label is synonymous to 'begin', and empty to label is\n");
@@ -96,6 +99,7 @@ struct SynthPass : public Pass {
 	{
 		std::string top_module, fsm_opts;
 		std::string run_from, run_to;
+		bool noabc = false;
 
 		size_t argidx;
 		for (argidx = 1; argidx < args.size(); argidx++)
@@ -119,6 +123,10 @@ struct SynthPass : public Pass {
 				}
 				continue;
 			}
+			if (args[argidx] == "-noabc") {
+				noabc = true;
+				continue;
+			}
 			break;
 		}
 		extra_args(args, argidx, design);
@@ -163,7 +171,7 @@ struct SynthPass : public Pass {
 		}
 
 	#ifdef YOSYS_ENABLE_ABC
-		if (check_label(active, run_from, run_to, "abc"))
+		if (check_label(active, run_from, run_to, "abc") && !noabc)
 		{
 			Pass::call(design, "abc -fast");
 			Pass::call(design, "opt -fast");
-- 
cgit v1.2.3


From d58c3eca3a6d4ab00021769fb31ee0279c2fcbab Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Thu, 12 Feb 2015 17:45:44 +0100
Subject: Some test related fixes

(incl. removal of three bad test cases)
---
 techlibs/common/simlib.v | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

(limited to 'techlibs/common')

diff --git a/techlibs/common/simlib.v b/techlibs/common/simlib.v
index d0feadd81..a73c6ee09 100644
--- a/techlibs/common/simlib.v
+++ b/techlibs/common/simlib.v
@@ -1328,7 +1328,7 @@ output reg [WIDTH-1:0] Q;
 
 always @* begin
 	if (EN == EN_POLARITY)
-		Q <= D;
+		Q = D;
 end
 
 endmodule
@@ -1356,11 +1356,11 @@ generate
 	for (i = 0; i < WIDTH; i = i+1) begin:bit
 		always @*
 			if (pos_clr[i])
-				Q[i] <= 0;
+				Q[i] = 0;
 			else if (pos_set[i])
-				Q[i] <= 1;
+				Q[i] = 1;
 			else if (pos_en)
-				Q[i] <= D[i];
+				Q[i] = D[i];
 	end
 endgenerate
 
-- 
cgit v1.2.3


From 04cb947d6a35b3773e694651971f28cbf83952e9 Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Fri, 13 Feb 2015 14:34:51 +0100
Subject: Added "check" command

---
 techlibs/common/synth.cc | 4 ++++
 1 file changed, 4 insertions(+)

(limited to 'techlibs/common')

diff --git a/techlibs/common/synth.cc b/techlibs/common/synth.cc
index 69ef5bc55..a50db53ee 100644
--- a/techlibs/common/synth.cc
+++ b/techlibs/common/synth.cc
@@ -71,6 +71,8 @@ struct SynthPass : public Pass {
 		log("\n");
 		log("    coarse:\n");
 		log("        proc\n");
+		log("        opt_clean\n");
+		log("        check\n");
 		log("        opt\n");
 		log("        wreduce\n");
 		log("        alumacc\n");
@@ -150,6 +152,8 @@ struct SynthPass : public Pass {
 		if (check_label(active, run_from, run_to, "coarse"))
 		{
 			Pass::call(design, "proc");
+			Pass::call(design, "opt_clean");
+			Pass::call(design, "check");
 			Pass::call(design, "opt");
 			Pass::call(design, "wreduce");
 			Pass::call(design, "alumacc");
-- 
cgit v1.2.3


From 910556560fbf26df4f2960b7d94039a1f399f1a1 Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Sat, 14 Feb 2015 10:23:03 +0100
Subject: Added $meminit cell type

---
 techlibs/common/simlib.v | 22 ++++++++++++++++++++++
 1 file changed, 22 insertions(+)

(limited to 'techlibs/common')

diff --git a/techlibs/common/simlib.v b/techlibs/common/simlib.v
index a73c6ee09..6707e190b 100644
--- a/techlibs/common/simlib.v
+++ b/techlibs/common/simlib.v
@@ -1514,6 +1514,28 @@ endmodule
 
 // --------------------------------------------------------
 
+module \$meminit (ADDR, DATA);
+
+parameter MEMID = "";
+parameter ABITS = 8;
+parameter WIDTH = 8;
+
+parameter PRIORITY = 0;
+
+input [ABITS-1:0] ADDR;
+input [WIDTH-1:0] DATA;
+
+initial begin
+	if (MEMID != "") begin
+		$display("ERROR: Found non-simulatable instance of $meminit!");
+		$finish;
+	end
+end
+
+endmodule
+
+// --------------------------------------------------------
+
 module \$mem (RD_CLK, RD_ADDR, RD_DATA, WR_CLK, WR_EN, WR_ADDR, WR_DATA);
 
 parameter MEMID = "";
-- 
cgit v1.2.3


From dcf2e242406d563254013ea7db4b29b55be96eff Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Sat, 14 Feb 2015 12:55:03 +0100
Subject: Added $meminit support to "memory" command

---
 techlibs/common/simlib.v | 18 +++++++++++++++---
 1 file changed, 15 insertions(+), 3 deletions(-)

(limited to 'techlibs/common')

diff --git a/techlibs/common/simlib.v b/techlibs/common/simlib.v
index 6707e190b..ee024051b 100644
--- a/techlibs/common/simlib.v
+++ b/techlibs/common/simlib.v
@@ -1543,6 +1543,7 @@ parameter SIZE = 256;
 parameter OFFSET = 0;
 parameter ABITS = 8;
 parameter WIDTH = 8;
+parameter signed INIT = 1'bx;
 
 parameter RD_PORTS = 1;
 parameter RD_CLK_ENABLE = 1'b1;
@@ -1583,25 +1584,36 @@ function port_active;
 	end
 endfunction
 
+initial begin
+	for (i = 0; i < SIZE; i = i+1)
+		memory[i] = INIT >>> (i*WIDTH);
+end
+
 always @(RD_CLK, RD_ADDR, RD_DATA, WR_CLK, WR_EN, WR_ADDR, WR_DATA) begin
 `ifdef SIMLIB_MEMDELAY
 	#`SIMLIB_MEMDELAY;
 `endif
 	for (i = 0; i < RD_PORTS; i = i+1) begin
-		if ((!RD_TRANSPARENT[i] && RD_CLK_ENABLE[i]) && port_active(RD_CLK_ENABLE[i], RD_CLK_POLARITY[i], LAST_RD_CLK[i], RD_CLK[i]))
+		if ((!RD_TRANSPARENT[i] && RD_CLK_ENABLE[i]) && port_active(RD_CLK_ENABLE[i], RD_CLK_POLARITY[i], LAST_RD_CLK[i], RD_CLK[i])) begin
+			// $display("Read from %s: addr=%b data=%b", MEMID, RD_ADDR[i*ABITS +: ABITS],  memory[RD_ADDR[i*ABITS +: ABITS] - OFFSET]);
 			RD_DATA[i*WIDTH +: WIDTH] <= memory[RD_ADDR[i*ABITS +: ABITS] - OFFSET];
+		end
 	end
 
 	for (i = 0; i < WR_PORTS; i = i+1) begin
 		if (port_active(WR_CLK_ENABLE[i], WR_CLK_POLARITY[i], LAST_WR_CLK[i], WR_CLK[i]))
 			for (j = 0; j < WIDTH; j = j+1)
-				if (WR_EN[i*WIDTH+j])
+				if (WR_EN[i*WIDTH+j]) begin
+					// $display("Write to %s: addr=%b data=%b", MEMID, WR_ADDR[i*ABITS +: ABITS], WR_DATA[i*WIDTH+j]);
 					memory[WR_ADDR[i*ABITS +: ABITS] - OFFSET][j] = WR_DATA[i*WIDTH+j];
+				end
 	end
 
 	for (i = 0; i < RD_PORTS; i = i+1) begin
-		if ((RD_TRANSPARENT[i] || !RD_CLK_ENABLE[i]) && port_active(RD_CLK_ENABLE[i], RD_CLK_POLARITY[i], LAST_RD_CLK[i], RD_CLK[i]))
+		if ((RD_TRANSPARENT[i] || !RD_CLK_ENABLE[i]) && port_active(RD_CLK_ENABLE[i], RD_CLK_POLARITY[i], LAST_RD_CLK[i], RD_CLK[i])) begin
+			// $display("Transparent read from %s: addr=%b data=%b", MEMID, RD_ADDR[i*ABITS +: ABITS],  memory[RD_ADDR[i*ABITS +: ABITS] - OFFSET]);
 			RD_DATA[i*WIDTH +: WIDTH] <= memory[RD_ADDR[i*ABITS +: ABITS] - OFFSET];
+		end
 	end
 
 	LAST_RD_CLK <= RD_CLK;
-- 
cgit v1.2.3


From ec05242c27754224c8dd5d8c60828a0b43ef8f4c Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Sun, 15 Feb 2015 00:20:05 +0100
Subject: Smaller default parameters in $mem simlib model

---
 techlibs/common/simlib.v | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

(limited to 'techlibs/common')

diff --git a/techlibs/common/simlib.v b/techlibs/common/simlib.v
index ee024051b..bc343c62d 100644
--- a/techlibs/common/simlib.v
+++ b/techlibs/common/simlib.v
@@ -1539,9 +1539,9 @@ endmodule
 module \$mem (RD_CLK, RD_ADDR, RD_DATA, WR_CLK, WR_EN, WR_ADDR, WR_DATA);
 
 parameter MEMID = "";
-parameter SIZE = 256;
+parameter SIZE = 4;
 parameter OFFSET = 0;
-parameter ABITS = 8;
+parameter ABITS = 2;
 parameter WIDTH = 8;
 parameter signed INIT = 1'bx;
 
-- 
cgit v1.2.3


From 881dcd8af988664b92a85daa5d82e90b1df29b51 Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Sun, 15 Feb 2015 13:00:00 +0100
Subject: Added final checks to "synth" and "synth_xilinx"

---
 techlibs/common/synth.cc | 21 ++++++++++++++-------
 1 file changed, 14 insertions(+), 7 deletions(-)

(limited to 'techlibs/common')

diff --git a/techlibs/common/synth.cc b/techlibs/common/synth.cc
index a50db53ee..56ab6eaff 100644
--- a/techlibs/common/synth.cc
+++ b/techlibs/common/synth.cc
@@ -90,12 +90,14 @@ struct SynthPass : public Pass {
 		log("        techmap\n");
 		log("        opt -fast\n");
 	#ifdef YOSYS_ENABLE_ABC
-		log("\n");
-		log("    abc:\n");
 		log("        abc -fast\n");
 		log("        opt -fast\n");
 	#endif
 		log("\n");
+		log("    check:\n");
+		log("        hierarchy -check\n");
+		log("        check\n");
+		log("\n");
 	}
 	virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
 	{
@@ -172,15 +174,20 @@ struct SynthPass : public Pass {
 			Pass::call(design, "opt -full");
 			Pass::call(design, "techmap");
 			Pass::call(design, "opt -fast");
+
+			if (!noabc) {
+		#ifdef YOSYS_ENABLE_ABC
+				Pass::call(design, "abc -fast");
+				Pass::call(design, "opt -fast");
+		#endif
+			}
 		}
 
-	#ifdef YOSYS_ENABLE_ABC
-		if (check_label(active, run_from, run_to, "abc") && !noabc)
+		if (check_label(active, run_from, run_to, "check"))
 		{
-			Pass::call(design, "abc -fast");
-			Pass::call(design, "opt -fast");
+			Pass::call(design, "hierarchy -check");
+			Pass::call(design, "check");
 		}
-	#endif
 
 		log_pop();
 	}
-- 
cgit v1.2.3


From 4d34d031f9c0b62cc4f669114c60ecdfdc555274 Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Sun, 15 Feb 2015 13:25:15 +0100
Subject: Added "stat" to "synth" and "synth_xilinx"

---
 techlibs/common/synth.cc | 2 ++
 1 file changed, 2 insertions(+)

(limited to 'techlibs/common')

diff --git a/techlibs/common/synth.cc b/techlibs/common/synth.cc
index 56ab6eaff..c3e7288db 100644
--- a/techlibs/common/synth.cc
+++ b/techlibs/common/synth.cc
@@ -96,6 +96,7 @@ struct SynthPass : public Pass {
 		log("\n");
 		log("    check:\n");
 		log("        hierarchy -check\n");
+		log("        stat\n");
 		log("        check\n");
 		log("\n");
 	}
@@ -186,6 +187,7 @@ struct SynthPass : public Pass {
 		if (check_label(active, run_from, run_to, "check"))
 		{
 			Pass::call(design, "hierarchy -check");
+			Pass::call(design, "stat");
 			Pass::call(design, "check");
 		}
 
-- 
cgit v1.2.3


From b005eedf369bc60ce5f7cba9a0db4694f22a360f Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Thu, 26 Feb 2015 18:04:10 +0100
Subject: Added $assume cell type

---
 techlibs/common/simlib.v | 19 ++++++++++++++++++-
 1 file changed, 18 insertions(+), 1 deletion(-)

(limited to 'techlibs/common')

diff --git a/techlibs/common/simlib.v b/techlibs/common/simlib.v
index bc343c62d..abd2af521 100644
--- a/techlibs/common/simlib.v
+++ b/techlibs/common/simlib.v
@@ -1163,7 +1163,24 @@ input A, EN;
 `ifndef SIMLIB_NOCHECKS
 always @* begin
 	if (A !== 1'b1 && EN === 1'b1) begin
-		$display("Assertation failed!");
+		$display("Assertation %m failed!");
+		$stop;
+	end
+end
+`endif
+
+endmodule
+
+// --------------------------------------------------------
+
+module \$assume (A, EN);
+
+input A, EN;
+
+`ifndef SIMLIB_NOCHECKS
+always @* begin
+	if (A !== 1'b1 && EN === 1'b1) begin
+		$display("Assumption %m failed!");
 		$stop;
 	end
 end
-- 
cgit v1.2.3