From b982ab4f59298946021186403e6415ba79e59200 Mon Sep 17 00:00:00 2001 From: Jannis Harder Date: Thu, 10 Nov 2022 16:17:54 +0100 Subject: satgen, simlib: Consistent x-propagation for `$pmux` cells This updates satgen and simlib to use a `$pmux` model where the output is fully X when the S input is not all zero or one-hot with no x bits. --- techlibs/common/simlib.v | 15 +++++++++++---- 1 file changed, 11 insertions(+), 4 deletions(-) (limited to 'techlibs/common') diff --git a/techlibs/common/simlib.v b/techlibs/common/simlib.v index e64697efb..b5e437d90 100644 --- a/techlibs/common/simlib.v +++ b/techlibs/common/simlib.v @@ -1331,10 +1331,17 @@ always @* begin Y = A; found_active_sel_bit = 0; for (i = 0; i < S_WIDTH; i = i+1) - if (S[i]) begin - Y = found_active_sel_bit ? 'bx : B >> (WIDTH*i); - found_active_sel_bit = 1; - end + case (S[i]) + 1'b1: begin + Y = found_active_sel_bit ? 'bx : B >> (WIDTH*i); + found_active_sel_bit = 1; + end + 1'b0: ; + 1'bx: begin + Y = 'bx; + found_active_sel_bit = 'bx; + end + endcase end endmodule -- cgit v1.2.3 From 39ac11340216eec2a040ace60feafd41f9cbb970 Mon Sep 17 00:00:00 2001 From: Jannis Harder Date: Fri, 11 Nov 2022 14:31:39 +0100 Subject: simlib: Fix wide $bmux and avoid iverilog warnings --- techlibs/common/simlib.v | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'techlibs/common') diff --git a/techlibs/common/simlib.v b/techlibs/common/simlib.v index b5e437d90..498cc27c2 100644 --- a/techlibs/common/simlib.v +++ b/techlibs/common/simlib.v @@ -1300,11 +1300,11 @@ wire [WIDTH-1:0] bm0_out, bm1_out; generate if (S_WIDTH > 1) begin:muxlogic - \$bmux #(.WIDTH(WIDTH), .S_WIDTH(S_WIDTH-1)) bm0 (.A(A), .S(S[S_WIDTH-2:0]), .Y(bm0_out)); + \$bmux #(.WIDTH(WIDTH), .S_WIDTH(S_WIDTH-1)) bm0 (.A(A[(WIDTH << (S_WIDTH - 1))-1:0]), .S(S[S_WIDTH-2:0]), .Y(bm0_out)); \$bmux #(.WIDTH(WIDTH), .S_WIDTH(S_WIDTH-1)) bm1 (.A(A[(WIDTH << S_WIDTH)-1:WIDTH << (S_WIDTH - 1)]), .S(S[S_WIDTH-2:0]), .Y(bm1_out)); assign Y = S[S_WIDTH-1] ? bm1_out : bm0_out; end else if (S_WIDTH == 1) begin:simple - assign Y = S ? A[1] : A[0]; + assign Y = S ? A[2*WIDTH-1:WIDTH] : A[WIDTH-1:0]; end else begin:passthru assign Y = A; end -- cgit v1.2.3 From 605d127517163f3d1113a6dbf19abcd55eb63dbb Mon Sep 17 00:00:00 2001 From: Jannis Harder Date: Thu, 10 Nov 2022 16:31:45 +0100 Subject: simlib: Silence iverilog warning for `$lut` iverilog complains about implicitly truncating LUT when connecting it to the `$bmux` A input. This explicitly truncates it to avoid that warning without changing the behaviour otherwise. --- techlibs/common/simlib.v | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'techlibs/common') diff --git a/techlibs/common/simlib.v b/techlibs/common/simlib.v index 498cc27c2..aca4d21a9 100644 --- a/techlibs/common/simlib.v +++ b/techlibs/common/simlib.v @@ -1377,7 +1377,7 @@ parameter LUT = 0; input [WIDTH-1:0] A; output Y; -\$bmux #(.WIDTH(1), .S_WIDTH(WIDTH)) mux(.A(LUT), .S(A), .Y(Y)); +\$bmux #(.WIDTH(1), .S_WIDTH(WIDTH)) mux(.A(LUT[(1< Date: Fri, 25 Nov 2022 17:40:50 +0100 Subject: simlib: Use optional SIMLIB_GLOBAL_CLOCK to define a global clock signal --- techlibs/common/simlib.v | 10 ++++++++-- 1 file changed, 8 insertions(+), 2 deletions(-) (limited to 'techlibs/common') diff --git a/techlibs/common/simlib.v b/techlibs/common/simlib.v index aca4d21a9..a22a3fd04 100644 --- a/techlibs/common/simlib.v +++ b/techlibs/common/simlib.v @@ -1700,6 +1700,9 @@ endmodule // -------------------------------------------------------- `ifdef SIMLIB_FF +`ifndef SIMLIB_GLOBAL_CLOCK +`define SIMLIB_GLOBAL_CLOCK $global_clk +`endif module \$anyinit (D, Q); parameter WIDTH = 0; @@ -1709,7 +1712,7 @@ output reg [WIDTH-1:0] Q; initial Q <= 'bx; -always @($global_clk) begin +always @(`SIMLIB_GLOBAL_CLOCK) begin Q <= D; end @@ -1790,6 +1793,9 @@ endmodule `endif // -------------------------------------------------------- `ifdef SIMLIB_FF +`ifndef SIMLIB_GLOBAL_CLOCK +`define SIMLIB_GLOBAL_CLOCK $global_clk +`endif module \$ff (D, Q); @@ -1798,7 +1804,7 @@ parameter WIDTH = 0; input [WIDTH-1:0] D; output reg [WIDTH-1:0] Q; -always @($global_clk) begin +always @(`SIMLIB_GLOBAL_CLOCK) begin Q <= D; end -- cgit v1.2.3 From 7203ba7bc1d83777bd2c2c347d45209d8e3d4b84 Mon Sep 17 00:00:00 2001 From: Jannis Harder Date: Wed, 2 Nov 2022 17:12:51 +0100 Subject: Add bitwise `$bweqx` and `$bwmux` cells The new bitwise case equality (`$bweqx`) and bitwise mux (`$bwmux`) cells enable compact encoding and decoding of 3-valued logic signals using multiple 2-valued signals. --- techlibs/common/simlib.v | 37 +++++++++++++++++++++++++++++++++++++ techlibs/common/techmap.v | 2 +- 2 files changed, 38 insertions(+), 1 deletion(-) (limited to 'techlibs/common') diff --git a/techlibs/common/simlib.v b/techlibs/common/simlib.v index a22a3fd04..9cb68e725 100644 --- a/techlibs/common/simlib.v +++ b/techlibs/common/simlib.v @@ -1601,6 +1601,43 @@ endmodule // -------------------------------------------------------- +module \$bweqx (A, B, Y); + +parameter WIDTH = 0; + +input [WIDTH-1:0] A, B; +output [WIDTH-1:0] Y; + +genvar i; +generate + for (i = 0; i < WIDTH; i = i + 1) begin:slices + assign Y[i] = A[i] === B[i]; + end +endgenerate + +endmodule + +// -------------------------------------------------------- + +module \$bwmux (A, B, S, Y); + +parameter WIDTH = 0; + +input [WIDTH-1:0] A, B; +input [WIDTH-1:0] S; +output [WIDTH-1:0] Y; + +genvar i; +generate + for (i = 0; i < WIDTH; i = i + 1) begin:slices + assign Y[i] = S[i] ? B[i] : A[i]; + end +endgenerate + +endmodule + +// -------------------------------------------------------- + module \$assert (A, EN); input A, EN; diff --git a/techlibs/common/techmap.v b/techlibs/common/techmap.v index 91d385b80..7fb8173b0 100644 --- a/techlibs/common/techmap.v +++ b/techlibs/common/techmap.v @@ -59,7 +59,7 @@ module _90_simplemap_compare_ops; endmodule (* techmap_simplemap *) -(* techmap_celltype = "$pos $slice $concat $mux $tribuf $bmux" *) +(* techmap_celltype = "$pos $slice $concat $mux $tribuf $bmux $bwmux $bweqx" *) module _90_simplemap_various; endmodule -- cgit v1.2.3