From 42f8e68e76a3717cf4ad29c36f0a9a801cde52c1 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Mon, 15 Jul 2019 14:45:47 -0700 Subject: OUT port to Y in generic DSP --- techlibs/common/mul2dsp.v | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'techlibs/common') diff --git a/techlibs/common/mul2dsp.v b/techlibs/common/mul2dsp.v index 0eec4cc82..0a87716d9 100644 --- a/techlibs/common/mul2dsp.v +++ b/techlibs/common/mul2dsp.v @@ -209,7 +209,7 @@ module \$__mul_gen (A, B, Y); `DSP_NAME _TECHMAP_REPLACE_ ( .A({ {{`DSP_A_MAXWIDTH-A_WIDTH}{Asign}}, A }), .B({ {{`DSP_B_MAXWIDTH-B_WIDTH}{Bsign}}, B }), - .OUT({dummy, out}) + .Y({dummy, out}) ); if (Y_WIDTH < A_WIDTH+B_WIDTH) assign Y = out[Y_WIDTH-1:0]; -- cgit v1.2.3