From eb67a7532bf1d8195216257a2d6d301c03980591 Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Fri, 23 Feb 2018 13:14:47 +0100
Subject: Add $allconst and $allseq cell types

Signed-off-by: Clifford Wolf <clifford@clifford.at>
---
 techlibs/common/simlib.v | 24 ++++++++++++++++++++++++
 1 file changed, 24 insertions(+)

(limited to 'techlibs/common')

diff --git a/techlibs/common/simlib.v b/techlibs/common/simlib.v
index 276503fe8..8e43fe058 100644
--- a/techlibs/common/simlib.v
+++ b/techlibs/common/simlib.v
@@ -1370,6 +1370,30 @@ endmodule
 
 // --------------------------------------------------------
 
+module \$allconst (Y);
+
+parameter WIDTH = 0;
+
+output [WIDTH-1:0] Y;
+
+assign Y = 'bx;
+
+endmodule
+
+// --------------------------------------------------------
+
+module \$allseq (Y);
+
+parameter WIDTH = 0;
+
+output [WIDTH-1:0] Y;
+
+assign Y = 'bx;
+
+endmodule
+
+// --------------------------------------------------------
+
 module \$equiv (A, B, Y);
 
 input A, B;
-- 
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