From f9a307a50b5ce67b67d2b53e8c1334ea23ffd997 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Sat, 27 Sep 2014 16:17:53 +0200 Subject: namespace Yosys --- techlibs/common/synth.cc | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) (limited to 'techlibs/common/synth.cc') diff --git a/techlibs/common/synth.cc b/techlibs/common/synth.cc index 4ccacd30b..8b41a003d 100644 --- a/techlibs/common/synth.cc +++ b/techlibs/common/synth.cc @@ -22,7 +22,10 @@ #include "kernel/rtlil.h" #include "kernel/log.h" -static bool check_label(bool &active, std::string run_from, std::string run_to, std::string label) +USING_YOSYS_NAMESPACE +PRIVATE_NAMESPACE_BEGIN + +bool check_label(bool &active, std::string run_from, std::string run_to, std::string label) { if (!run_from.empty() && run_from == run_to) { active = (label == run_from); @@ -154,3 +157,4 @@ struct SynthPass : public Pass { } } SynthPass; +PRIVATE_NAMESPACE_END -- cgit v1.2.3 From ab28491f271e3b02ba58dabb4b7033bcf17b6c25 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Fri, 31 Oct 2014 03:36:51 +0100 Subject: Added "opt -full" alias for all more aggressive optimizations --- techlibs/common/synth.cc | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) (limited to 'techlibs/common/synth.cc') diff --git a/techlibs/common/synth.cc b/techlibs/common/synth.cc index 8b41a003d..c76b002cc 100644 --- a/techlibs/common/synth.cc +++ b/techlibs/common/synth.cc @@ -76,9 +76,11 @@ struct SynthPass : public Pass { log(" opt_clean\n"); log("\n"); log(" fine:\n"); + log(" opt -fast -full\n"); log(" memory_map\n"); + log(" opt -full\n"); log(" techmap\n"); - log(" opt -fast\n"); + log(" opt -fast -full\n"); #ifdef YOSYS_ENABLE_ABC log(" abc -fast\n"); log(" opt_clean\n"); @@ -144,9 +146,11 @@ struct SynthPass : public Pass { if (check_label(active, run_from, run_to, "fine")) { + Pass::call(design, "opt -fast -full"); Pass::call(design, "memory_map"); + Pass::call(design, "opt -full"); Pass::call(design, "techmap"); - Pass::call(design, "opt -fast"); + Pass::call(design, "opt -fast -full"); #ifdef YOSYS_ENABLE_ABC Pass::call(design, "abc -fast"); Pass::call(design, "opt_clean"); -- cgit v1.2.3 From 74ef92b9c888fd05f03b4f679ecda6b04249e498 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Fri, 31 Oct 2014 03:46:27 +0100 Subject: Added "abc" label in synth script --- techlibs/common/synth.cc | 18 ++++++++++++------ 1 file changed, 12 insertions(+), 6 deletions(-) (limited to 'techlibs/common/synth.cc') diff --git a/techlibs/common/synth.cc b/techlibs/common/synth.cc index c76b002cc..211b5905a 100644 --- a/techlibs/common/synth.cc +++ b/techlibs/common/synth.cc @@ -80,10 +80,12 @@ struct SynthPass : public Pass { log(" memory_map\n"); log(" opt -full\n"); log(" techmap\n"); - log(" opt -fast -full\n"); + log(" opt -fast\n"); #ifdef YOSYS_ENABLE_ABC + log("\n"); + log(" abc:\n"); log(" abc -fast\n"); - log(" opt_clean\n"); + log(" opt -fast\n"); #endif log("\n"); } @@ -150,12 +152,16 @@ struct SynthPass : public Pass { Pass::call(design, "memory_map"); Pass::call(design, "opt -full"); Pass::call(design, "techmap"); - Pass::call(design, "opt -fast -full"); - #ifdef YOSYS_ENABLE_ABC + Pass::call(design, "opt -fast"); + } + + #ifdef YOSYS_ENABLE_ABC + if (check_label(active, run_from, run_to, "abc")) + { Pass::call(design, "abc -fast"); - Pass::call(design, "opt_clean"); - #endif + Pass::call(design, "opt -fast"); } + #endif log_pop(); } -- cgit v1.2.3 From bedd46338fecd93c4c1c3b35017c26b080a990dc Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Fri, 30 Jan 2015 22:46:53 +0100 Subject: Added "fsm -encfile" --- techlibs/common/synth.cc | 11 +++++++++-- 1 file changed, 9 insertions(+), 2 deletions(-) (limited to 'techlibs/common/synth.cc') diff --git a/techlibs/common/synth.cc b/techlibs/common/synth.cc index 211b5905a..5267344bb 100644 --- a/techlibs/common/synth.cc +++ b/techlibs/common/synth.cc @@ -52,6 +52,9 @@ struct SynthPass : public Pass { log(" -top \n"); log(" use the specified module as top module (default='top')\n"); log("\n"); + log(" -encfile \n"); + log(" passed to 'fsm_recode' via 'fsm'\n"); + log("\n"); log(" -run [:]\n"); log(" only run the commands between the labels (see below). an empty\n"); log(" from label is synonymous to 'begin', and empty to label is\n"); @@ -91,7 +94,7 @@ struct SynthPass : public Pass { } virtual void execute(std::vector args, RTLIL::Design *design) { - std::string top_module; + std::string top_module, fsm_opts; std::string run_from, run_to; size_t argidx; @@ -101,6 +104,10 @@ struct SynthPass : public Pass { top_module = args[++argidx]; continue; } + if (args[argidx] == "-encfile" && argidx+1 < args.size()) { + fsm_opts = " -encfile " + args[++argidx]; + continue; + } if (args[argidx] == "-run" && argidx+1 < args.size()) { size_t pos = args[argidx+1].find(':'); if (pos == std::string::npos) { @@ -140,7 +147,7 @@ struct SynthPass : public Pass { Pass::call(design, "alumacc"); Pass::call(design, "share"); Pass::call(design, "opt"); - Pass::call(design, "fsm"); + Pass::call(design, "fsm" + fsm_opts); Pass::call(design, "opt -fast"); Pass::call(design, "memory -nomap"); Pass::call(design, "opt_clean"); -- cgit v1.2.3 From 1df81f92ce171ba63cf0e4d10e6f203ca5f7f64e Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Sun, 1 Feb 2015 13:38:46 +0100 Subject: Added "make mklibyosys", some minor API changes --- techlibs/common/synth.cc | 10 +++++++++- 1 file changed, 9 insertions(+), 1 deletion(-) (limited to 'techlibs/common/synth.cc') diff --git a/techlibs/common/synth.cc b/techlibs/common/synth.cc index 5267344bb..69ef5bc55 100644 --- a/techlibs/common/synth.cc +++ b/techlibs/common/synth.cc @@ -55,6 +55,9 @@ struct SynthPass : public Pass { log(" -encfile \n"); log(" passed to 'fsm_recode' via 'fsm'\n"); log("\n"); + log(" -noabc\n"); + log(" do not run abc (as if yosys was compiled without ABC support)\n"); + log("\n"); log(" -run [:]\n"); log(" only run the commands between the labels (see below). an empty\n"); log(" from label is synonymous to 'begin', and empty to label is\n"); @@ -96,6 +99,7 @@ struct SynthPass : public Pass { { std::string top_module, fsm_opts; std::string run_from, run_to; + bool noabc = false; size_t argidx; for (argidx = 1; argidx < args.size(); argidx++) @@ -119,6 +123,10 @@ struct SynthPass : public Pass { } continue; } + if (args[argidx] == "-noabc") { + noabc = true; + continue; + } break; } extra_args(args, argidx, design); @@ -163,7 +171,7 @@ struct SynthPass : public Pass { } #ifdef YOSYS_ENABLE_ABC - if (check_label(active, run_from, run_to, "abc")) + if (check_label(active, run_from, run_to, "abc") && !noabc) { Pass::call(design, "abc -fast"); Pass::call(design, "opt -fast"); -- cgit v1.2.3 From 04cb947d6a35b3773e694651971f28cbf83952e9 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Fri, 13 Feb 2015 14:34:51 +0100 Subject: Added "check" command --- techlibs/common/synth.cc | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'techlibs/common/synth.cc') diff --git a/techlibs/common/synth.cc b/techlibs/common/synth.cc index 69ef5bc55..a50db53ee 100644 --- a/techlibs/common/synth.cc +++ b/techlibs/common/synth.cc @@ -71,6 +71,8 @@ struct SynthPass : public Pass { log("\n"); log(" coarse:\n"); log(" proc\n"); + log(" opt_clean\n"); + log(" check\n"); log(" opt\n"); log(" wreduce\n"); log(" alumacc\n"); @@ -150,6 +152,8 @@ struct SynthPass : public Pass { if (check_label(active, run_from, run_to, "coarse")) { Pass::call(design, "proc"); + Pass::call(design, "opt_clean"); + Pass::call(design, "check"); Pass::call(design, "opt"); Pass::call(design, "wreduce"); Pass::call(design, "alumacc"); -- cgit v1.2.3 From 881dcd8af988664b92a85daa5d82e90b1df29b51 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Sun, 15 Feb 2015 13:00:00 +0100 Subject: Added final checks to "synth" and "synth_xilinx" --- techlibs/common/synth.cc | 21 ++++++++++++++------- 1 file changed, 14 insertions(+), 7 deletions(-) (limited to 'techlibs/common/synth.cc') diff --git a/techlibs/common/synth.cc b/techlibs/common/synth.cc index a50db53ee..56ab6eaff 100644 --- a/techlibs/common/synth.cc +++ b/techlibs/common/synth.cc @@ -90,12 +90,14 @@ struct SynthPass : public Pass { log(" techmap\n"); log(" opt -fast\n"); #ifdef YOSYS_ENABLE_ABC - log("\n"); - log(" abc:\n"); log(" abc -fast\n"); log(" opt -fast\n"); #endif log("\n"); + log(" check:\n"); + log(" hierarchy -check\n"); + log(" check\n"); + log("\n"); } virtual void execute(std::vector args, RTLIL::Design *design) { @@ -172,15 +174,20 @@ struct SynthPass : public Pass { Pass::call(design, "opt -full"); Pass::call(design, "techmap"); Pass::call(design, "opt -fast"); + + if (!noabc) { + #ifdef YOSYS_ENABLE_ABC + Pass::call(design, "abc -fast"); + Pass::call(design, "opt -fast"); + #endif + } } - #ifdef YOSYS_ENABLE_ABC - if (check_label(active, run_from, run_to, "abc") && !noabc) + if (check_label(active, run_from, run_to, "check")) { - Pass::call(design, "abc -fast"); - Pass::call(design, "opt -fast"); + Pass::call(design, "hierarchy -check"); + Pass::call(design, "check"); } - #endif log_pop(); } -- cgit v1.2.3 From 4d34d031f9c0b62cc4f669114c60ecdfdc555274 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Sun, 15 Feb 2015 13:25:15 +0100 Subject: Added "stat" to "synth" and "synth_xilinx" --- techlibs/common/synth.cc | 2 ++ 1 file changed, 2 insertions(+) (limited to 'techlibs/common/synth.cc') diff --git a/techlibs/common/synth.cc b/techlibs/common/synth.cc index 56ab6eaff..c3e7288db 100644 --- a/techlibs/common/synth.cc +++ b/techlibs/common/synth.cc @@ -96,6 +96,7 @@ struct SynthPass : public Pass { log("\n"); log(" check:\n"); log(" hierarchy -check\n"); + log(" stat\n"); log(" check\n"); log("\n"); } @@ -186,6 +187,7 @@ struct SynthPass : public Pass { if (check_label(active, run_from, run_to, "check")) { Pass::call(design, "hierarchy -check"); + Pass::call(design, "stat"); Pass::call(design, "check"); } -- cgit v1.2.3