From 4a9e133fabe85847f4cdaafed0b8024691be5395 Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Sat, 18 Jan 2014 18:54:50 +0100
Subject: Fixed a type in $mem model in simlib.v

---
 techlibs/common/simlib.v | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'techlibs/common/simlib.v')

diff --git a/techlibs/common/simlib.v b/techlibs/common/simlib.v
index f3d652f0e..321119e37 100644
--- a/techlibs/common/simlib.v
+++ b/techlibs/common/simlib.v
@@ -1036,7 +1036,7 @@ generate
 				end
 			end
 		end else
-		if (RD_CLK_POLARITY[i] == 1) begin:rd_posclk
+		if (WR_CLK_POLARITY[i] == 1) begin:rd_posclk
 			always @(posedge WR_CLK[i])
 				if (WR_EN[i]) begin
 					data[ WR_ADDR[ (i+1)*ABITS-1 : i*ABITS ] - OFFSET ] <= WR_DATA[ (i+1)*WIDTH-1 : i*WIDTH ];
-- 
cgit v1.2.3


From 2fbaaaca7af79a6505679092251a80dc89cbc493 Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Sat, 18 Jan 2014 19:13:43 +0100
Subject: More changes to simlib to make it friendlier to a wider range of
 tools

---
 techlibs/common/simlib.v | 24 ++++++++++++++----------
 1 file changed, 14 insertions(+), 10 deletions(-)

(limited to 'techlibs/common/simlib.v')

diff --git a/techlibs/common/simlib.v b/techlibs/common/simlib.v
index 321119e37..e522e37c6 100644
--- a/techlibs/common/simlib.v
+++ b/techlibs/common/simlib.v
@@ -65,10 +65,10 @@ parameter Y_WIDTH = 0;
 output [Y_WIDTH-1:0] Y;
 
 generate
-	if (!A_SIGNED && 0 < A_WIDTH && A_WIDTH < Y_WIDTH) begin:A
+	if (!A_SIGNED && 0 < A_WIDTH && A_WIDTH < Y_WIDTH) begin:BLOCK1
 		assign Y[A_WIDTH-1:0] = A_BUF.val;
 		assign Y[Y_WIDTH-1:A_WIDTH] = 0;
-	end else begin:B
+	end else begin:BLOCK2
 		assign Y = +A_BUF.val;
 	end
 endgenerate
@@ -953,8 +953,10 @@ input [ABITS-1:0] ADDR;
 output [WIDTH-1:0] DATA;
 
 initial begin
-	$display("ERROR: Found non-simulatable instance of $memrd!");
-	$finish;
+	if (MEMID != "") begin
+		$display("ERROR: Found non-simulatable instance of $memrd!");
+		$finish;
+	end
 end
 
 endmodule
@@ -975,8 +977,10 @@ input [ABITS-1:0] ADDR;
 input [WIDTH-1:0] DATA;
 
 initial begin
-	$display("ERROR: Found non-simulatable instance of $memwr!");
-	$finish;
+	if (MEMID != "") begin
+		$display("ERROR: Found non-simulatable instance of $memwr!");
+		$finish;
+	end
 end
 
 endmodule
@@ -1008,7 +1012,7 @@ input [WR_PORTS*ABITS-1:0] WR_ADDR;
 input [WR_PORTS*WIDTH-1:0] WR_DATA;
 
 reg [WIDTH-1:0] data [SIZE-1:0];
-event update_async_rd;
+reg update_async_rd;
 
 genvar i;
 generate
@@ -1032,7 +1036,7 @@ generate
 			always @(WR_ADDR or WR_DATA or WR_EN) begin
 				if (WR_EN[i]) begin
 					data[ WR_ADDR[ (i+1)*ABITS-1 : i*ABITS ] - OFFSET ] <= WR_DATA[ (i+1)*WIDTH-1 : i*WIDTH ];
-					#1 -> update_async_rd;
+					update_async_rd <= 1; update_async_rd <= 0;
 				end
 			end
 		end else
@@ -1040,13 +1044,13 @@ generate
 			always @(posedge WR_CLK[i])
 				if (WR_EN[i]) begin
 					data[ WR_ADDR[ (i+1)*ABITS-1 : i*ABITS ] - OFFSET ] <= WR_DATA[ (i+1)*WIDTH-1 : i*WIDTH ];
-					#1 -> update_async_rd;
+					update_async_rd <= 1; update_async_rd <= 0;
 				end
 		end else begin:rd_negclk
 			always @(negedge WR_CLK[i])
 				if (WR_EN[i]) begin
 					data[ WR_ADDR[ (i+1)*ABITS-1 : i*ABITS ] - OFFSET ] <= WR_DATA[ (i+1)*WIDTH-1 : i*WIDTH ];
-					#1 -> update_async_rd;
+					update_async_rd <= 1; update_async_rd <= 0;
 				end
 		end
 	end
-- 
cgit v1.2.3


From 3d7a1491aac0849a2a9fae2a06242e125de883d0 Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Sat, 18 Jan 2014 19:27:16 +0100
Subject: Fixed $lut simlib model for a wider range of tools

---
 techlibs/common/simlib.v | 22 ++++++++++++----------
 1 file changed, 12 insertions(+), 10 deletions(-)

(limited to 'techlibs/common/simlib.v')

diff --git a/techlibs/common/simlib.v b/techlibs/common/simlib.v
index e522e37c6..0e041e12e 100644
--- a/techlibs/common/simlib.v
+++ b/techlibs/common/simlib.v
@@ -715,17 +715,19 @@ generate
 		\$lut #( .WIDTH(WIDTH-1), .LUT(LUT                  ) ) lut0 ( .I(I[WIDTH-2:0]), .O(lut0_out) );
 		\$lut #( .WIDTH(WIDTH-1), .LUT(LUT >> (2**(WIDTH-1))) ) lut1 ( .I(I[WIDTH-2:0]), .O(lut1_out) );
 	end
-endgenerate
 
-always @* begin
-	casez ({I[WIDTH-1], lut0_out, lut1_out})
-		3'b?11: O = 1'b1;
-		3'b?00: O = 1'b0;
-		3'b0??: O = lut0_out;
-		3'b1??: O = lut1_out;
-		default: O = 1'bx;
-	endcase
-end
+	if (WIDTH > 0) begin:lutlogic
+		always @* begin
+			casez ({I[WIDTH-1], lut0_out, lut1_out})
+				3'b?11: O = 1'b1;
+				3'b?00: O = 1'b0;
+				3'b0??: O = lut0_out;
+				3'b1??: O = lut1_out;
+				default: O = 1'bx;
+			endcase
+		end
+	end
+endgenerate
 
 endmodule
 
-- 
cgit v1.2.3


From 1e67099b77904802880ad7c53d2cac33c6df456f Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Sun, 19 Jan 2014 14:03:40 +0100
Subject: Added $assert cell

---
 techlibs/common/simlib.v | 15 +++++++++++++++
 1 file changed, 15 insertions(+)

(limited to 'techlibs/common/simlib.v')

diff --git a/techlibs/common/simlib.v b/techlibs/common/simlib.v
index 0e041e12e..8f354a63d 100644
--- a/techlibs/common/simlib.v
+++ b/techlibs/common/simlib.v
@@ -733,6 +733,21 @@ endmodule
 
 // --------------------------------------------------------
 
+module \$assert (A, EN);
+
+input A, EN;
+
+always @* begin
+	if (A !== 1'b1 && EN === 1'b1) begin
+		$display("Assertation failed!");
+		$finish;
+	end
+end
+
+endmodule
+
+// --------------------------------------------------------
+
 module \$sr (SET, CLR, Q);
 
 parameter WIDTH = 0;
-- 
cgit v1.2.3