From 83bce9f59c2ae54038f1cf2938fd095e7039c38a Mon Sep 17 00:00:00 2001 From: Miodrag Milanovic Date: Sat, 1 Dec 2018 18:28:54 +0100 Subject: Initial support for Anlogic FPGA --- techlibs/anlogic/synth_anlogic.cc | 205 ++++++++++++++++++++++++++++++++++++++ 1 file changed, 205 insertions(+) create mode 100644 techlibs/anlogic/synth_anlogic.cc (limited to 'techlibs/anlogic/synth_anlogic.cc') diff --git a/techlibs/anlogic/synth_anlogic.cc b/techlibs/anlogic/synth_anlogic.cc new file mode 100644 index 000000000..f4ef88770 --- /dev/null +++ b/techlibs/anlogic/synth_anlogic.cc @@ -0,0 +1,205 @@ +/* + * yosys -- Yosys Open SYnthesis Suite + * + * Copyright (C) 2018 Miodrag Milanovic + * Copyright (C) 2018 Clifford Wolf + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + * + */ + +#include "kernel/register.h" +#include "kernel/celltypes.h" +#include "kernel/rtlil.h" +#include "kernel/log.h" + +USING_YOSYS_NAMESPACE +PRIVATE_NAMESPACE_BEGIN + +struct SynthAnlogicPass : public ScriptPass +{ + SynthAnlogicPass() : ScriptPass("synth_anlogic", "synthesis for Anlogic FPGAs") { } + + void help() YS_OVERRIDE + { + // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| + log("\n"); + log(" synth_anlogic [options]\n"); + log("\n"); + log("This command runs synthesis for Anlogic FPGAs.\n"); + log("\n"); + log(" -top \n"); + log(" use the specified module as top module\n"); + log("\n"); + log(" -edif \n"); + log(" write the design to the specified EDIF file. writing of an output file\n"); + log(" is omitted if this parameter is not specified.\n"); + log("\n"); + log(" -json \n"); + log(" write the design to the specified JSON file. writing of an output file\n"); + log(" is omitted if this parameter is not specified.\n"); + log("\n"); + log(" -run :\n"); + log(" only run the commands between the labels (see below). an empty\n"); + log(" from label is synonymous to 'begin', and empty to label is\n"); + log(" synonymous to the end of the command list.\n"); + log("\n"); + log(" -noflatten\n"); + log(" do not flatten design before synthesis\n"); + log("\n"); + log(" -retime\n"); + log(" run 'abc' with -dff option\n"); + log("\n"); + log("\n"); + log("The following commands are executed by this synthesis command:\n"); + help_script(); + log("\n"); + } + + string top_opt, edif_file, json_file; + bool flatten, retime; + + void clear_flags() YS_OVERRIDE + { + top_opt = "-auto-top"; + edif_file = ""; + json_file = ""; + flatten = true; + retime = false; + } + + void execute(std::vector args, RTLIL::Design *design) YS_OVERRIDE + { + string run_from, run_to; + clear_flags(); + + size_t argidx; + for (argidx = 1; argidx < args.size(); argidx++) + { + if (args[argidx] == "-top" && argidx+1 < args.size()) { + top_opt = "-top " + args[++argidx]; + continue; + } + if (args[argidx] == "-edif" && argidx+1 < args.size()) { + edif_file = args[++argidx]; + continue; + } + if (args[argidx] == "-json" && argidx+1 < args.size()) { + json_file = args[++argidx]; + continue; + } + if (args[argidx] == "-run" && argidx+1 < args.size()) { + size_t pos = args[argidx+1].find(':'); + if (pos == std::string::npos) + break; + run_from = args[++argidx].substr(0, pos); + run_to = args[argidx].substr(pos+1); + continue; + } + if (args[argidx] == "-noflatten") { + flatten = false; + continue; + } + if (args[argidx] == "-retime") { + retime = true; + continue; + } + break; + } + extra_args(args, argidx, design); + + if (!design->full_selection()) + log_cmd_error("This comannd only operates on fully selected designs!\n"); + + log_header(design, "Executing SYNTH_ANLOGIC pass.\n"); + log_push(); + + run_script(design, run_from, run_to); + + log_pop(); + } + + void script() YS_OVERRIDE + { + if (check_label("begin")) + { + run("read_verilog -lib +/anlogic/cells_sim.v +/anlogic/eagle_bb.v"); + run(stringf("hierarchy -check %s", help_mode ? "-top " : top_opt.c_str())); + } + + if (flatten && check_label("flatten", "(unless -noflatten)")) + { + run("proc"); + run("flatten"); + run("tribuf -logic"); + run("deminout"); + } + + if (check_label("coarse")) + { + run("synth -run coarse"); + } + + if (check_label("fine")) + { + run("opt -fast -mux_undef -undriven -fine"); + run("memory_map"); + run("opt -undriven -fine"); + run("techmap -map +/techmap.v -map +/anlogic/arith_map.v"); + if (retime || help_mode) + run("abc -dff", "(only if -retime)"); + } + + if (check_label("map_ffs")) + { + run("dffsr2dff"); + run("techmap -D NO_LUT -map +/anlogic/cells_map.v"); + run("opt_expr -mux_undef"); + run("simplemap"); + } + + if (check_label("map_luts")) + { + run("abc -lut 6"); + run("clean"); + } + + if (check_label("map_cells")) + { + run("techmap -map +/anlogic/cells_map.v"); + run("clean"); + run("anlogic_eqn"); + } + + if (check_label("check")) + { + run("hierarchy -check"); + run("stat"); + run("check -noinit"); + } + + if (check_label("edif")) + { + if (!edif_file.empty() || help_mode) + run(stringf("write_edif %s", help_mode ? "" : edif_file.c_str())); + } + + if (check_label("json")) + { + if (!json_file.empty() || help_mode) + run(stringf("write_json %s", help_mode ? "" : json_file.c_str())); + } + } +} SynthAnlogicPass; + +PRIVATE_NAMESPACE_END -- cgit v1.2.3 From d53a2bd1d3ae3cfbc9ead0fc12999fe269628179 Mon Sep 17 00:00:00 2001 From: Icenowy Zheng Date: Fri, 14 Dec 2018 16:50:37 +0800 Subject: anlogic: add support for Eagle Distributed RAM The MSLICEs on the Eagle series of FPGA can be configured as Distributed RAM. Enable to synthesis to DRAM. As the Anlogic software suite doesn't support any 'bx to exist in the initializtion data of DRAM, do not enable the initialization support of the inferred DRAM. Signed-off-by: Icenowy Zheng --- techlibs/anlogic/synth_anlogic.cc | 6 ++++++ 1 file changed, 6 insertions(+) (limited to 'techlibs/anlogic/synth_anlogic.cc') diff --git a/techlibs/anlogic/synth_anlogic.cc b/techlibs/anlogic/synth_anlogic.cc index f4ef88770..a4eafeddf 100644 --- a/techlibs/anlogic/synth_anlogic.cc +++ b/techlibs/anlogic/synth_anlogic.cc @@ -150,6 +150,12 @@ struct SynthAnlogicPass : public ScriptPass run("synth -run coarse"); } + if (check_label("dram")) + { + run("memory_bram -rules +/anlogic/drams.txt"); + run("techmap -map +/anlogic/drams_map.v"); + } + if (check_label("fine")) { run("opt -fast -mux_undef -undriven -fine"); -- cgit v1.2.3 From 4bf8ac728cbebabf2333f2a15b9e52c6af8b806a Mon Sep 17 00:00:00 2001 From: Icenowy Zheng Date: Tue, 18 Dec 2018 15:39:02 +0800 Subject: anlogic: set the init value of DFFs As dffinit has already supported for different initialization strings for DFFs and check for re-initialization, initialization of Anlogic DFFs are now ready to go. Support for set the init values of Anlogic DFFs. Signed-off-by: Icenowy Zheng --- techlibs/anlogic/synth_anlogic.cc | 1 + 1 file changed, 1 insertion(+) (limited to 'techlibs/anlogic/synth_anlogic.cc') diff --git a/techlibs/anlogic/synth_anlogic.cc b/techlibs/anlogic/synth_anlogic.cc index a4eafeddf..492a830b9 100644 --- a/techlibs/anlogic/synth_anlogic.cc +++ b/techlibs/anlogic/synth_anlogic.cc @@ -170,6 +170,7 @@ struct SynthAnlogicPass : public ScriptPass { run("dffsr2dff"); run("techmap -D NO_LUT -map +/anlogic/cells_map.v"); + run("dffinit -strinit SET RESET -ff AL_MAP_SEQ q REGSET -noreinit"); run("opt_expr -mux_undef"); run("simplemap"); } -- cgit v1.2.3 From c9513c695a76124ef1155343e3c058767c418051 Mon Sep 17 00:00:00 2001 From: Icenowy Zheng Date: Wed, 19 Dec 2018 09:36:53 +0800 Subject: Anlogic: let LUT5/6 have more cost than LUT4- According to the datasheet of Anlogic Eagle FPGAs, The LUTs natively in an Anlogic FPGA is LUT4 (in MSLICEs) and "Enhanced LUT5" (in LSLICEs). An "Enhanced LUT5" can be divided into two LUT4s. So a LUT5 will cost around 2x resource of a LUT4, and a LUT6 will cost 2x resource of a LUT5. Change the -lut parameter passed to the abc command to pass this cost info to the ABC process. Signed-off-by: Icenowy Zheng --- techlibs/anlogic/synth_anlogic.cc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'techlibs/anlogic/synth_anlogic.cc') diff --git a/techlibs/anlogic/synth_anlogic.cc b/techlibs/anlogic/synth_anlogic.cc index a4eafeddf..9c44599ea 100644 --- a/techlibs/anlogic/synth_anlogic.cc +++ b/techlibs/anlogic/synth_anlogic.cc @@ -176,7 +176,7 @@ struct SynthAnlogicPass : public ScriptPass if (check_label("map_luts")) { - run("abc -lut 6"); + run("abc -lut 4:6"); run("clean"); } -- cgit v1.2.3 From 90d00182cfe358438d777f2ca7abacb4c6a2733c Mon Sep 17 00:00:00 2001 From: Icenowy Zheng Date: Wed, 19 Dec 2018 10:18:47 +0800 Subject: anlogic: implement DRAM initialization As the TD tool doesn't accept the DRAM cell to contain unknown values in the initial value, the initialzation support of DRAM is previously skipped. Now add the support by add a new pass to determine unknown values in the initial value. Signed-off-by: Icenowy Zheng --- techlibs/anlogic/synth_anlogic.cc | 1 + 1 file changed, 1 insertion(+) (limited to 'techlibs/anlogic/synth_anlogic.cc') diff --git a/techlibs/anlogic/synth_anlogic.cc b/techlibs/anlogic/synth_anlogic.cc index 9c44599ea..b34f4788f 100644 --- a/techlibs/anlogic/synth_anlogic.cc +++ b/techlibs/anlogic/synth_anlogic.cc @@ -154,6 +154,7 @@ struct SynthAnlogicPass : public ScriptPass { run("memory_bram -rules +/anlogic/drams.txt"); run("techmap -map +/anlogic/drams_map.v"); + run("anlogic_determine_init"); } if (check_label("fine")) -- cgit v1.2.3 From efa278e232d20ea080743801bd91d55ec62955cf Mon Sep 17 00:00:00 2001 From: whitequark Date: Fri, 7 Dec 2018 19:14:07 +0000 Subject: Fix typographical and grammatical errors and inconsistencies. The initial list of hits was generated with the codespell command below, and each hit was evaluated and fixed manually while taking context into consideration. DIRS="kernel/ frontends/ backends/ passes/ techlibs/" DIRS="${DIRS} libs/ezsat/ libs/subcircuit" codespell $DIRS -S *.o -L upto,iff,thru,synopsys,uint More hits were found by looking through comments and strings manually. --- techlibs/anlogic/synth_anlogic.cc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'techlibs/anlogic/synth_anlogic.cc') diff --git a/techlibs/anlogic/synth_anlogic.cc b/techlibs/anlogic/synth_anlogic.cc index 9c44599ea..68f4399d4 100644 --- a/techlibs/anlogic/synth_anlogic.cc +++ b/techlibs/anlogic/synth_anlogic.cc @@ -119,7 +119,7 @@ struct SynthAnlogicPass : public ScriptPass extra_args(args, argidx, design); if (!design->full_selection()) - log_cmd_error("This comannd only operates on fully selected designs!\n"); + log_cmd_error("This command only operates on fully selected designs!\n"); log_header(design, "Executing SYNTH_ANLOGIC pass.\n"); log_push(); -- cgit v1.2.3 From 5f561bdcb1d562d6f975b4a27beca1b8b7af908f Mon Sep 17 00:00:00 2001 From: Miodrag Milanovic Date: Mon, 12 Aug 2019 20:19:54 +0200 Subject: Proper arith for Anlogic and use standard pass --- techlibs/anlogic/synth_anlogic.cc | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) (limited to 'techlibs/anlogic/synth_anlogic.cc') diff --git a/techlibs/anlogic/synth_anlogic.cc b/techlibs/anlogic/synth_anlogic.cc index 620bf3965..b87fc8566 100644 --- a/techlibs/anlogic/synth_anlogic.cc +++ b/techlibs/anlogic/synth_anlogic.cc @@ -154,7 +154,7 @@ struct SynthAnlogicPass : public ScriptPass { run("memory_bram -rules +/anlogic/drams.txt"); run("techmap -map +/anlogic/drams_map.v"); - run("anlogic_determine_init"); + run("setundef -zero -params t:EG_LOGIC_DRAM16X4"); } if (check_label("fine")) @@ -186,6 +186,11 @@ struct SynthAnlogicPass : public ScriptPass { run("techmap -map +/anlogic/cells_map.v"); run("clean"); + } + + if (check_label("map_anlogic")) + { + run("anlogic_fixcarry"); run("anlogic_eqn"); } -- cgit v1.2.3