From 31b0002e8c0e1b7a8ad054e02b1200c03461b581 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Fri, 19 Jul 2019 13:20:45 -0700 Subject: Remove "top" from message --- passes/opt/wreduce.cc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'passes') diff --git a/passes/opt/wreduce.cc b/passes/opt/wreduce.cc index dff1c5370..23e14f7f5 100644 --- a/passes/opt/wreduce.cc +++ b/passes/opt/wreduce.cc @@ -395,7 +395,7 @@ struct WreduceWorker } if (bits_removed) { - log("Removed top %d bits (of %d) from port Y of cell %s.%s (%s).\n", + log("Removed %d bits (of %d) from port Y of cell %s.%s (%s).\n", bits_removed, GetSize(sig) + bits_removed, log_id(module), log_id(cell), log_id(cell->type)); cell->setPort("\\Y", sig); did_something = true; -- cgit v1.2.3 From 3a87dc35242598b6951fb70d4302ede60c2a96b2 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Fri, 19 Jul 2019 13:23:07 -0700 Subject: Wrap A and B in sigmap --- passes/opt/wreduce.cc | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'passes') diff --git a/passes/opt/wreduce.cc b/passes/opt/wreduce.cc index 23e14f7f5..294f0d57e 100644 --- a/passes/opt/wreduce.cc +++ b/passes/opt/wreduce.cc @@ -366,8 +366,8 @@ struct WreduceWorker } if (cell->type.in("$add", "$sub")) { - SigSpec A = cell->getPort("\\A"); - SigSpec B = cell->getPort("\\B"); + SigSpec A = mi.sigmap(cell->getPort("\\A")); + SigSpec B = mi.sigmap(cell->getPort("\\B")); bool sub = cell->type == "$sub"; int i; -- cgit v1.2.3 From cb0fd0521531a69632102f5fad8cdc9996ed4dee Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Fri, 19 Jul 2019 13:58:50 -0700 Subject: Do not access beyond bounds --- passes/opt/wreduce.cc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'passes') diff --git a/passes/opt/wreduce.cc b/passes/opt/wreduce.cc index 294f0d57e..908a85d5b 100644 --- a/passes/opt/wreduce.cc +++ b/passes/opt/wreduce.cc @@ -372,7 +372,7 @@ struct WreduceWorker int i; for (i = 0; i < GetSize(sig); i++) { - if (B[i] != S0 && (sub || A[i] != S0)) + if (B.at(i, Sx) != S0 && (sub || A.at(i, Sx) != S0)) break; if (B[i] == S0) module->connect(sig[i], A[i]); -- cgit v1.2.3