From dcc8a13e481c058f17b98ea900f9feb9192ea5ae Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Fri, 26 Apr 2019 15:32:02 -0700
Subject: Revert "Merge branch 'eddie/split_shiftx' into xc7mux"
This reverts commit 3042d5833041021bb45252b0cc862e9eff3d27d3, reversing
changes made to feff9764540cbf1152459cb377fc68d8e10c7153.
---
passes/opt/wreduce.cc | 2 ++
passes/pmgen/.gitignore | 2 +-
passes/pmgen/Makefile.inc | 13 +++----
passes/pmgen/README.md | 2 +-
passes/pmgen/split_shiftx.cc | 84 -------------------------------------------
passes/pmgen/split_shiftx.pmg | 59 ------------------------------
6 files changed, 9 insertions(+), 153 deletions(-)
delete mode 100644 passes/pmgen/split_shiftx.cc
delete mode 100644 passes/pmgen/split_shiftx.pmg
(limited to 'passes')
diff --git a/passes/opt/wreduce.cc b/passes/opt/wreduce.cc
index 68e077cf9..52245ce3e 100644
--- a/passes/opt/wreduce.cc
+++ b/passes/opt/wreduce.cc
@@ -462,10 +462,12 @@ struct WreduceWorker
SigSpec initsig = init_attr_sigmap(w);
int width = std::min(GetSize(initval), GetSize(initsig));
for (int i = 0; i < width; i++) {
+ log_dump(initsig[i], remove_init_bits.count(initsig[i]));
if (!remove_init_bits.count(initsig[i]))
new_initval[i] = initval[i];
}
w->attributes.at("\\init") = new_initval;
+ log_dump(w->name, initval, new_initval);
}
}
}
diff --git a/passes/pmgen/.gitignore b/passes/pmgen/.gitignore
index 52dfd93f3..c9263057e 100644
--- a/passes/pmgen/.gitignore
+++ b/passes/pmgen/.gitignore
@@ -1 +1 @@
-*_pm.h
+/ice40_dsp_pm.h
diff --git a/passes/pmgen/Makefile.inc b/passes/pmgen/Makefile.inc
index 5669bd3d1..e0609d9ba 100644
--- a/passes/pmgen/Makefile.inc
+++ b/passes/pmgen/Makefile.inc
@@ -1,11 +1,8 @@
-PMG_SRC = $(wildcard passes/pmgen/*.pmg)
-PMG_OBJS += $(patsubst %.pmg, %.o, $(PMG_SRC))
-OBJS += $(PMG_OBJS)
+OBJS += passes/pmgen/ice40_dsp.o
-$(PMG_OBJS): %.o: %_pm.h
+passes/pmgen/ice40_dsp.o: passes/pmgen/ice40_dsp_pm.h
+EXTRA_OBJS += passes/pmgen/ice40_dsp_pm.h
+.SECONDARY: passes/pmgen/ice40_dsp_pm.h
-EXTRA_OBJS += $(patsubst %.pmg, %_pm.h, $(PMG_SRC))
-.SECONDARY: $(EXTRA_OBJS)
-
-%_pm.h: passes/pmgen/pmgen.py %.pmg
+passes/pmgen/ice40_dsp_pm.h: passes/pmgen/pmgen.py passes/pmgen/ice40_dsp.pmg
$(P) mkdir -p passes/pmgen && python3 $^ $@
diff --git a/passes/pmgen/README.md b/passes/pmgen/README.md
index 320e95a77..7a46558b1 100644
--- a/passes/pmgen/README.md
+++ b/passes/pmgen/README.md
@@ -220,5 +220,5 @@ But in some cases it is more natural to utilize the implicit branch statement:
portAB = \B;
endcode
-There is an implicit `code..endcode` block at the end of each `.pmg` file
+There is an implicit `code..endcode` block at the end of each `.pgm` file
that just accepts everything that gets all the way there.
diff --git a/passes/pmgen/split_shiftx.cc b/passes/pmgen/split_shiftx.cc
deleted file mode 100644
index 3cbabcd76..000000000
--- a/passes/pmgen/split_shiftx.cc
+++ /dev/null
@@ -1,84 +0,0 @@
-/*
- * yosys -- Yosys Open SYnthesis Suite
- *
- * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
- *
- * Permission to use, copy, modify, and/or distribute this software for any
- * purpose with or without fee is hereby granted, provided that the above
- * copyright notice and this permission notice appear in all copies.
- *
- * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
- * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
- * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
- * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
- * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
- * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
- *
- */
-
-#include "kernel/yosys.h"
-#include "kernel/sigtools.h"
-#include "passes/pmgen/split_shiftx_pm.h"
-
-USING_YOSYS_NAMESPACE
-PRIVATE_NAMESPACE_BEGIN
-
-void create_split_shiftx(split_shiftx_pm &pm)
-{
- log_assert(pm.st.shiftx);
- if (pm.blacklist_cells.count(pm.st.shiftx))
- return;
- SigSpec A = pm.st.shiftx->getPort("\\A");
- SigSpec B = pm.st.shiftxB;
- log_assert(!B.empty());
- SigSpec Y = pm.st.shiftx->getPort("\\Y");
- const int A_WIDTH = pm.st.shiftx->getParam("\\A_WIDTH").as_int();
- const int B_WIDTH = GetSize(pm.st.shiftxB);
- const int Y_WIDTH = pm.st.shiftx->getParam("\\Y_WIDTH").as_int();
- int trailing_zeroes = 0;
- for (; B[trailing_zeroes] == RTLIL::S0; ++trailing_zeroes) ;
- const int WIDTH = trailing_zeroes > 0 ? 1 << trailing_zeroes : Y_WIDTH;
- std::vector<SigBit> bits;
- bits.resize(A_WIDTH / WIDTH);
- for (int i = 0; i < Y_WIDTH; ++i) {
- for (int j = 0; j < A_WIDTH/WIDTH; ++j)
- bits[j] = A[j*WIDTH + i];
- pm.module->addShiftx(NEW_ID, bits, B.extract(trailing_zeroes, B_WIDTH-trailing_zeroes), Y[i]);
- }
- pm.st.shiftx->unsetPort("\\Y");
-
- pm.autoremove(pm.st.shiftx);
- pm.autoremove(pm.st.macc);
-}
-
-struct BitblastShiftxPass : public Pass {
- BitblastShiftxPass() : Pass("split_shiftx", "Split up multi-bit $shiftx cells") { }
- void help() YS_OVERRIDE
- {
- // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
- log("\n");
- log(" split_shiftx [selection]\n");
- log("\n");
- log("Split up $shiftx cells where Y_WIDTH > 1, with consideration for any $macc\n");
- log("cells -- configured as a constant multiplier equal to Y_WIDTH -- that may be\n");
- log("driving their B inputs.\n");
- log("\n");
- }
- void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
- {
- log_header(design, "Executing SPLIT_SHIFTX pass.\n");
-
- size_t argidx;
- for (argidx = 1; argidx < args.size(); argidx++)
- {
- break;
- }
- extra_args(args, argidx, design);
-
- for (auto module : design->selected_modules())
- split_shiftx_pm(module, module->selected_cells()).run(create_split_shiftx);
- }
-} BitblastShiftxPass;
-
-PRIVATE_NAMESPACE_END
diff --git a/passes/pmgen/split_shiftx.pmg b/passes/pmgen/split_shiftx.pmg
deleted file mode 100644
index 3aafe1975..000000000
--- a/passes/pmgen/split_shiftx.pmg
+++ /dev/null
@@ -1,59 +0,0 @@
-state <SigSpec> shiftxB
-
-match shiftx
- select shiftx->type == $shiftx
- select param(shiftx, \Y_WIDTH).as_int() > 1
-endmatch
-
-match macc
- select macc->type == $macc
- select param(macc, \B_WIDTH).as_int() == 0
- optional
-endmatch
-
-code shiftxB
- shiftxB = port(shiftx, \B);
-
- if (macc) {
- const int b_width = param(shiftx, \B_WIDTH).as_int();
- if (param(shiftx, \B_SIGNED) != 0 && shiftxB[b_width-1] == RTLIL::S0)
- shiftxB = shiftxB.extract(0, b_width-1);
-
- if (port(macc, \Y) != shiftxB) {
- blacklist(shiftx);
- reject;
- }
-
- Const config = param(macc, \CONFIG);
- const int config_width = param(macc, \CONFIG_WIDTH).as_int();
- const int num_bits = config.extract(0, 4).as_int();
- const int num_ports = (config_width - 4) / (2 + 2*num_bits);
- if (num_ports != 1) {
- blacklist(shiftx);
- reject;
- }
- // IS_SIGNED?
- if (config[4] == 1) {
- blacklist(shiftx);
- reject;
- }
- // DO_SUBTRACT?
- if (config[5] == 1) {
- blacklist(shiftx);
- reject;
- }
- const int port_size_A = config.extract(6, num_bits).as_int();
- const int port_size_B = config.extract(6 + num_bits, num_bits).as_int();
- const SigSpec port_B = port(macc, \A).extract(port_size_A, port_size_B);
- if (!port_B.is_fully_const()) {
- blacklist(shiftx);
- reject;
- }
- const int multiply_factor = port_B.as_int();
- if (multiply_factor != param(shiftx, \Y_WIDTH).as_int()) {
- blacklist(shiftx);
- reject;
- }
- shiftxB = port(macc, \A).extract(0, port_size_A);
- }
-endcode
--
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